TW201521239A - Light emitting apparatus and manufacturing method thereof - Google Patents

Light emitting apparatus and manufacturing method thereof Download PDF

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TW201521239A
TW201521239A TW103139968A TW103139968A TW201521239A TW 201521239 A TW201521239 A TW 201521239A TW 103139968 A TW103139968 A TW 103139968A TW 103139968 A TW103139968 A TW 103139968A TW 201521239 A TW201521239 A TW 201521239A
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light
emitting
layer
emitting element
carrier
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TW103139968A
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TWI542045B (en
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Min-Hsun Hsieh
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Epistar Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46Reflective coating, e.g. dielectric Bragg reflector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0016Processes relating to electrodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)
  • Heating, Cooling, Or Curing Plastics Or The Like In General (AREA)

Abstract

The present disclosure provides a method for forming a light-emitting apparatus, comprising providing a first board having a plurality of first metal contacts, providing a substrate, forming a plurality of light-emitting stacks and trenches on the substrate, wherein the light-emitting stacks are apart from each other by the plurality of the trenches, bonding the light-emitting stacks to the first board, forming an encapsulating material commonly on the plurality of the light-emitting stacks, and cutting the first board and the encapsulating material to form a plurality of chip-scale LED units.

Description

發光裝置及其製作方法Light emitting device and manufacturing method thereof

【1】 本發明係一種發光元件及其製作方法以及一種發光元件陣列及其製作方法,特別是一種發光裝置及其製作方法。[1] The present invention relates to a light-emitting element, a method of fabricating the same, a light-emitting element array, and a method of fabricating the same, and more particularly to a light-emitting device and a method of fabricating the same.

【2】 習知發光二極體(LED)封裝技術係先在晶片座(sub-mount)上點膠,再將發光二極體晶片固定於晶片座上,進而形成一發光二極體元件,此步驟稱為固晶(Die Bonding)。固晶膠材主要為具導電性的銀膠或其他非導電性環氧樹脂。之後將發光二極體元件組合於電路板上。覆晶(flip chip)式的發光二極體係使二極體結構中的p型半導體導電層與n型半導體導電層,暴露於同一側,以能將陰、陽極電極製作於二極體結構的同一側上,因而可直接將設置有陰、陽極電極的發光二極體結構覆置於一錫料(solder)上。如此,能免除採用傳統金屬拉線(wire bonding)的需求。然而習知之覆晶式發光二極體仍需透過切割、固晶等封裝步驟,才能與電路板連結。因此,若覆晶式發光二極體的電極具有足夠大的接觸面積,便能夠省略習知之封裝步驟。 【3】 一般傳統LED的操作電流約為數十至數百個毫安培(mA),但亮度往往不足以應付一般照明所需。若組合大量的LED以提高亮度,則LED照明元件的體積將增加而導致市場上之競爭性降低。因此,提昇單顆LED之晶粒亮度,成為必然之趨勢。然而,當LED朝向高亮度發展時,單一LED的操作電流及功率增加為傳統LED的數倍至數百倍,例如,一個高亮度的LED的操作電流約為數百毫安培至數個安培,使得LED所產生的熱問題不容忽視。LED的性能會因為”熱”而降低,例如熱效應會影響LED的發光波長,半導體特性也因熱而產生亮度衰減,更嚴重時甚至造成元件損壞。因此,高功率LED如何散熱成為LED的重要議題。 【4】 美國專利申請號2004/0188696以及2004/023189(為2004/0188696之分割案)中分別揭示了一種使用表面黏著技術 (Surface Mount Technology, SMT)的LED封裝結構與方法,其中每一封裝結構含有一LED晶片。每一LED晶片先以覆晶的形式,藉由凸塊(bonding bump)黏著於在一晶片座(sub-mount)之前側(front side)上。在晶片座中具有預先鑿出之開孔陣列,並填以金屬以形成通道陣列(via array)。此晶片的電極可藉由此通道陣列連接至晶片座的具有錫料的後側(back side)。此通道陣列亦可作為LED晶片之散熱路徑。在每一LED晶片與次基板黏著之後,再將次基板切割,以進行後續之LED封裝。 【5】 然而,在美國專利申請號2004/0188696以及2004/023189中之晶片座,需鑿出填以金屬的通道陣列(via array),增加製程成本。此外,每一LED晶片黏著於晶片座的步驟,也會增加製作的複雜度。因此,若能具有一種發光二極體,不需晶片座,亦具有良好的散熱路徑,可在市場上具有優勢。[2] Conventional light-emitting diode (LED) packaging technology first dispenses on a sub-mount, and then fixes the light-emitting diode wafer on the wafer holder to form a light-emitting diode component. This step is called Die Bonding. The solid crystal glue is mainly made of conductive silver glue or other non-conductive epoxy resin. The LED components are then combined on a circuit board. A flip chip type light emitting diode system exposes a p-type semiconductor conductive layer and an n-type semiconductor conductive layer in a diode structure to the same side, so that the cathode and anode electrodes can be fabricated in a diode structure. On the same side, the light-emitting diode structure provided with the anode and cathode electrodes can be directly placed on a solder. In this way, the need for conventional metal wire bonding can be eliminated. However, conventional flip-chip light-emitting diodes still need to be packaged by cutting, solid-crystal, etc., in order to be connected to the circuit board. Therefore, if the electrode of the flip-chip type light-emitting diode has a sufficiently large contact area, the conventional packaging step can be omitted. [3] The operating current of conventional LEDs is about tens to hundreds of milliamps (mA), but the brightness is often insufficient to meet the general lighting needs. If a large number of LEDs are combined to increase the brightness, the volume of the LED lighting elements will increase and the competition in the market will decrease. Therefore, it is an inevitable trend to increase the grain brightness of a single LED. However, when the LED is developed toward high brightness, the operating current and power of a single LED increase by several times to several hundred times that of a conventional LED. For example, the operating current of a high-brightness LED is about several hundred milliamperes to several amps. The thermal problems caused by LEDs cannot be ignored. The performance of LEDs is reduced by "hot". For example, the thermal effect affects the wavelength of the LEDs. The characteristics of the semiconductors are also attenuated by the heat, and even worse, the components are damaged. Therefore, how to dissipate high-power LEDs becomes an important issue for LEDs. [4] U.S. Patent Application No. 2004/0188696 and 2004/023189 (division of 2004/0188696) respectively disclose an LED package structure and method using Surface Mount Technology (SMT), wherein each package The structure contains an LED wafer. Each LED wafer is first bonded in a flip chip form by bonding bumps on a front side of a sub-mount. An array of pre-cut apertures is provided in the wafer holder and filled with metal to form a via array. The electrodes of the wafer can be connected to the back side of the wafer holder by the array of channels. This channel array can also serve as a heat dissipation path for the LED chip. After each LED wafer is adhered to the sub-substrate, the sub-substrate is then diced for subsequent LED packaging. [5] However, in the wafer holders of U.S. Patent Application Nos. 2004/0188696 and 2004/023189, it is necessary to cut a via array filled with metal to increase the process cost. In addition, the step of attaching each LED chip to the wafer holder also increases the complexity of fabrication. Therefore, if it has a light-emitting diode, it does not require a wafer holder, and has a good heat dissipation path, which has an advantage in the market.

【6】 本發明揭示一種發光裝置的製作方法,其包含步驟:提供一第一載板,其具有複數第一金屬接觸;提供一基材;形成複數發光疊層以及複數溝槽於基材上,其中複數發光疊層藉由複數溝槽與彼此分離;連接複數發光疊層與第一載板;形成一封裝材料共同地位於複數發光疊層上;以及切割第一載板以及封裝材料以形成複數晶粒級的發光元件單元。 【7】 於本發明之一實施例中,發光裝置的製作方法更包含形成一第一波長轉換層於一第一發光疊層上,第一波長轉換層將第一發光疊層發出的光轉換為一第一光;形成一第二波長轉換層於一第二發光疊層上,第二波長轉換層將第二發光疊層發出的光轉換為一第二光;以及提供一個第三發光疊層,第三發光疊層之上方並未有任何波長轉換材料,其中第一發光疊層、第二發光疊層以及第三發光疊層發出的光為藍光,第一光為綠光且第二光為紅光。[6] The present invention discloses a method of fabricating a light-emitting device, comprising the steps of: providing a first carrier having a plurality of first metal contacts; providing a substrate; forming a plurality of light-emitting layers and a plurality of trenches on the substrate a plurality of light-emitting laminates separated from each other by a plurality of trenches; connecting the plurality of light-emitting laminates to the first carrier; forming a package material collectively on the plurality of light-emitting laminates; and cutting the first carrier and the encapsulating material to form A plurality of grain level light emitting element units. [7] In an embodiment of the invention, the method for fabricating the light emitting device further comprises: forming a first wavelength conversion layer on a first light emitting layer, wherein the first wavelength conversion layer converts light emitted by the first light emitting layer a first light; forming a second wavelength conversion layer on a second light emitting layer, the second wavelength converting layer converting light emitted by the second light emitting layer into a second light; and providing a third light emitting stack The layer does not have any wavelength conversion material above the third light emitting layer, wherein the light emitted by the first light emitting layer, the second light emitting layer, and the third light emitting layer is blue light, and the first light is green light and the second light The light is red.

【31】 為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。在圖式中,元件之形狀或厚度可擴大或縮小。需特別注意的是,圖中未繪示或描述之元件,可以是熟習此技藝之人士所知之形式。本發明所列舉之各實施例僅用以說明本發明,並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。 【32】 參照第1A第至第1E圖,係為依照本發明實施例之一種發光元件的製作方法流程各階段所對應之剖面圖。在第1A圖中,首先形成一發光結構100,其包含一基材11、一第一導電層102以做為一包覆層、一活性層104位於第一導電層102上以作為一發光層、一第二導電層106於此活性層104上以作為另一包覆層。較佳地,如第1A圖所示,一電極或接合墊(bonding pad)107a位於第一導電層102之暴露的部分上,另一電極或接合墊107b位在第二導電層106上。電極或接合墊107a與107b之材料(例如鋁)與製作方法應為習此技藝者所熟知,在此不加贅述。此外,在一實施例中,發光結構100更包含一保護層(passivation layer)120,以保護此發光結構100。此保護層120的材料(例如二氧化矽)與製作方法亦為習此技藝者所熟知,在此加不贅述。 【33】 在一實施例中,第一導電層102為一n型半導體導電層,而第二導電層106為一p型半導體導電層。n型半導體導電層102、p型半導體導電層106為任何習知或未來中可見者之半導體材料,較佳者為Ⅲ-Ⅴ(三/五)族化合物半導體,例如氮化鋁鎵銦(Alx Gay ln(1 -x-y) N)或磷化鋁鎵銦(Alx Gay In(1-x-y) P),其中0≦x≦1,0≦y≦1,0≦x+y≦1,並視情況進一步被p/n型摻質所摻雜。而活性層104亦可使用習知之半導體材料與結構,例如材料可為氮化鋁鎵銦(Alx Gay ln(1 -x-y) N)或磷化鋁鎵銦(Alx Gay ln(1 -x-y) P)等,而結構可為單量子井(Single Quantum Well, SQW)、多重量子井(Multiple Quantum Well, MQW)與雙異質(Double Heterosture, DH),其發光原理與機制係為習知之技術,在此不再贅述。此外,發光結構100可藉由有機金屬化學氣相沉積(MOCVD)、分子束磊晶成長(molecular beam epitaxy, MBE)製程、或氫化物氣相磊晶成長(hydride vapor phase epitaxy,HVPE)製程等製作。 【34】 接著,如第1B圖所示,形成一第一介電層122於此發光結構100上。較佳地,第一介電層122為一透明介電層,且其厚度D≦20μm,藉此有效地傳導發光結構100所產生之熱。第一介電層122的材料可為二氧化矽(SiO2 )、氮化矽(Si3 N4 )、或是其組合,而其可藉由MOCVD或是MBE製作。 【35】 之後,參見第1C圖,形成一第二介電層140於第一介電層122上。第二介電層140的材料可為二氧化矽、氮化矽、聚亞醯胺(polyimide)、 BCB(bisbenzocyclobutene)以及光阻劑(photoresist)中選擇其一。較佳地,第二介電層140之厚度約25μm,係藉由一印刷技術而形成。 【36】 參見第1D圖,在第二介電層140形成之後,形成金屬層160,金屬層160位於發光結構100上並電性接觸第一導電層102,且部分之金屬層160位於第一介電層122上;以及形成金屬層162,金屬層162位於發光結構100上並電性接觸第二導電層106,且部分之金屬層162位於第一介電層122上。其中,第一介電層122與第二介電層140隔絕金屬層160與金屬層162。金屬層160或金屬層162的材料可選自金(Au)、鋁(Al)、銀(Ag) 、其等之合金,或其他習知的金屬。較佳地,金屬層160與金屬層162係藉由一印刷技術或電鍍而共同形成。經由上述步驟,即完成發光元件10。 【37】 在一實施例中,第一介電層122為一透明介電層,而第一介電層122與金屬層160及/或金屬層162之接觸面供反射發光結構100發出之光,因而可有效提升發光元件10之光輸出強度。此外,金屬層160及/或金屬層162亦作為發光結構100之散熱路徑,當金屬層160及金屬層162具有較大的接觸面積A1、A2,也有助於有效且快速的散熱。 【38】 參見第1E圖,形成如同第1D圖所示之結構之後,發光元件的製作方法更包含一移除基材11之步驟,藉以暴露出第一導電層102。基材11可以例如是一藍寶石基材或是砷化鎵基材。當基材11為藍寶石基材,可藉由準分子雷射(excimer laser)移除基材11。準分子雷射可以為一具有能量為400毫焦耳/平方公分(mJ/cm2 )、波長為248奈米以及脈衝寬度(pulse width)為38奈秒(ns)的氟化氪(KrF)準分子雷射。在較高的溫度中,例如60℃,當準分子雷射照射在藍寶石基材上時,藍寶石基材被移除以暴露出第一導電層102。另外,當基材11為砷化鎵基材,一比例為1:35之氨水(NH4 OH)與過氧化氫(H2 O2 )的溶液或是一比例為5:3:5之磷酸(H3 PO4 )、過氧化氫(H2 O2 )與水的溶液可以用於移除砷化鎵基材,藉以暴露出第一導電層102。 【39】 移除基材11之後,發光元件的製作方法更包含粗化第一導電層102的表面102a。例如,當第一導電層102為一氮化鋁鎵銦(Alx Gay ln(1 -x-y ) N)層,其表面102a可以藉由蝕刻液粗化,蝕刻液可例如為氫氧化鉀(KOH)溶液。此外,當第一導電層102為一磷化鋁鎵銦(Alx Gay In(1-x-y) P)層,一鹽酸(HCl)以及磷酸的溶液可用於粗化第一導電層102的表面102a,粗化時間可例如為15秒。第一導電層102的粗化表面102a可降低發生全反射的可能性,藉以增加發光元件的光取出效率。 【40】 第1E圖所示之發光元件10以及第1D圖所示之發光元件10a、10b、10c提供足夠大的接觸面積(較佳為至少佔據發光元件10截面積之一半),發光元件10a、10b、10c係利用錫料(solder)12直接與電路載板13連接,而不需要固晶(Die Bonding)與金屬拉線(Wire Bonding)等過程。在一實施例中,發光元件10a發出紅光(R)、發光元件10b發出綠光(G)、發光元件10c發出藍光(B),三者分別與電路載板13連接以供影像顯示之用途。 【41】 參照第2A圖至第2D圖,係為依照本發明實施例之一種發光元件陣列的製作方法流程各階段所對應之剖面圖。在第2A圖中,首先提供一基材21,例如一藍寶石(Sapphire)基材、砷化鎵(GaAs)基材、或是其他習此技藝者所熟知之基材與其組合。接著,在基材21上形成複數個發光結構200a、200b、與200c。發光結構200a、200b、與200c的材料與製作方法可參考第1A圖至第1D圖的發光結構100。相似地,發光結構200a、200b、與200c可藉由有機金屬化學氣相沉積(MOCVD)製程、分子束磊晶成長(molecular beam epitaxy, MBE)製程、或氫化物氣相磊晶成長(hydride vapor phase epitaxy, HVPE)製程等製作。 【42】 接著,如第2B圖所示,形成一介電層222a於發光結構200a上、形成一介電層222b於發光結構200b上、形成一介電層222c於發光結構200c上。較佳地,如同第1B圖所示之介電層122,介電層222a、222b、222c為一透明介電層,且其厚度D≦20μm,藉此有效地傳導發光結構200a、200b、200c所產生之熱。介電層222a、222b、222c的材料可為二氧化矽、氮化矽或其等之組合,而其可藉由MOCVD或是MBE製作。 【43】 之後,參見第2C圖,形成介電層240a於介電層222a上、形成介電層240b於介電層222b上、形成介電層240c於介電層222c上。介電層240a、240b、240c的材料可為二氧化矽、氮化矽、聚亞醯胺(polyimide)、BCB(bisbenzocyclobutene)以及光阻劑(photoresist)中選擇其一。較佳地,如同第1C圖所示之介電層第二140,介電層240a、240b、240c之厚度分別約為25μm,且係藉由一印刷技術而形成。在一實施例中,在發光結構200a、200b、200c之間,更形成一介電層280,藉以電絕緣發光元件20a、20b、與20c(如第2D圖所示)。在此實施例中,介電層280之材料與介電層240a、240b、240c的材料相同,例如聚亞醯胺,並利用一製程(例如一印刷技術)與介電層240a、240b、240c共同形成。在另一實施例中,介電層280之材料不同於介電層240a、240b、240c的材料,且藉由不同製程形成。 【44】 參見第2D圖,形成金屬層260a、260b、260c;以及形成金屬層262a、262b、262c。金屬層260a、260b、260c、262a、262b、與262c的材料可選自金(Au)、鋁(Al)、銀(Ag)或其等之合金。較佳地,金屬層260a、260b、260c、262a、262b、與262c係藉由一印刷技術或是電鍍而共同形成。經由上述步驟,即完成具有發光元件20a、20b、與20c之發光元件陣列20。 【45】 如第2E圖至第2F圖所示,在一實施例中,發光元件20a、20b、與20c提供足夠大的接觸面積,以利用錫料(solder)22直接與電路載板23連接。再使基材21與發光元件陣列20分離,發光元件陣列20便可作為影像顯示之用。例如,利用錫料22直接連接發光元件20a、20b、與20c與電路載板23之後,發光元件的製作方法更包含一移除基材21之步驟。基材11可以例如是一藍寶石基材,且可藉由準分子雷射(excimer laser)移除。準分子雷射可以為一具有能量為400毫焦耳/平方公分(mJ/cm2 )、波長為248奈米以及脈衝寬度(pulse width)為38奈秒(ns)的氟化氪(KrF)準分子雷射。在較高的溫度中,例如60℃,當準分子雷射照射在藍寶石基材上時,藍寶石基材便被移除以暴露出第一導電層102。另外,當基材11為砷化鎵基材,一比例為1:35之氨水(NH4 OH)與過氧化氫(H2 O2 )的溶液或是一比例為5:3:5之磷酸(H3 PO4 )、過氧化氫(H2 O2 )與水的溶液可用於移除砷化鎵基材,藉以暴露出第一導電層102。 【46】 移除基材21之後,發光裝置的製作方法更包含粗化第一導電層102的表面102a。例如,當第一導電層102為一氮化鋁鎵銦(Alx Gay ln(1 -x-y ) N)層,其表面102a可以藉由蝕刻液粗化,蝕刻液可例如為氫氧化鉀(KOH)溶液。此外,當第一導電層102為一磷化鋁鎵銦(Alx Gay In1-x-y P)層,一鹽酸(HCl)以及磷酸的溶液可用於粗化第一導電層102的表面102a,粗化時間可例如為15秒。第一導電層102的粗化表面102a可降低發生全反射的可能性,藉以增加發光元件的光取出效率。一實施例中,如第2G圖所示,一透明封裝材料24係用於包覆包含發光元件20a、20b、與20c之發光元件陣列20且連接電路載板23,進而形成發光元件封裝25,其中透明封裝材料24可例如為環氧樹脂或是其他習知技藝者所熟知之適合的材料。 【47】 參照第3A圖至第3G圖,係為依照本發明實施例之一種發光裝置的製作方法流程各階段所對應之剖面圖。參見第3A圖,提供一基材21,其為單晶且包含藍寶石、砷化鎵、氮化鎵或矽;磊晶成長一第一導電層102於基材21上,第一導電層102係做為一包覆層;磊晶成長一包含多重量子井(Multiple Quantum Well, MQW)結構的活性層104於第一導電層102上,其中活性層104係作為一發光層;以及磊晶成長一第二導電層106於活性層104上,其中第二導電層106係做為另一包覆層。接著,蝕刻第一導電層102、活性層104以及第二導電層106以在基材21上形成複數藉由溝槽(圖未標)而彼此分離的發光疊層101,且每一發光疊層101中,一部分的第一導電層102是暴露的。接著,每一發光疊層101上形成有一保護層120,且保護層120覆蓋部分的第一導電層102、部分的第二導電層106以及發光疊層101的一側壁。接著,於每一第一導電層102的暴露的部位上設置一與第一導電層102電性連接的電極或接合墊107a,以及於每一第二導電層106上設置一與第二導電層106電性連接的電極或接合墊107b。<TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td></td></tr></TBODY></TABLE> 【48】 之後,參見第3B圖,於每一保護層120上設置一反射層221,以及於每一保護層120上形成一覆蓋反射層221之第一介電層122。對於發光疊層101發出的光,反射層221具有一等同於或是大於80%的反射率。反射層221之材料包含金屬,例如銀、銀合金、鋁或鋁合金。在一實施例中,反射層221的材料包含混有無機粒子的高分子,其中無機粒子由金屬氧化物組成或是由具有反射率等於或是大於1.8之材料組成,反射層221的材料例如為混有氧化鈦粒子的環氧樹脂。各反射層221係完全地被各自對應的保護層120以及第一介電層122覆蓋,藉以電絕緣各反射層221與各自對應的發光疊層101。於另一實施例中,保護層120是被省略的,且反射層221是直接形成於第二導電層106上且電性連接第二導電層106。之後,如第3C圖所示,於基材21上以及溝槽之間以及於每一發光疊層101上形成一第二介電層240,且各第二介電層240暴露各自對應的電極或接合墊107a以及電極或接合墊107b。之後,於每一第二介電層240之間以及於部分的對應之第一介電層122上形成一第一金屬層260以及一第二金屬層262。第一金屬層260以及第二金屬層262係分別形成於對應的電極或接合墊107a以及電極或接合墊107b上。第一金屬層260以及第二金屬層262之材料包含金、鋁、銀或其等之合金。於一實施例中,第一金屬層260以及第二金屬層262係藉由一印刷技術或是電鍍而共同形成。 【49】 如第3D圖所示,圖案化位於相鄰發光疊層101之間的第二介電層240藉以於第二介電層240裡形成凹槽,凹槽暴露一部分的基材21且將第二介電層240隔開以形成介電層240a,之後形成一不透光層290於凹槽中。於一實施例中,不透光層290作為一反射層或是一光吸收層,藉以反射或是吸收對應的發光疊層101發出的光且避免被鄰近的發光疊層101發出的光互相影響或產生串擾(crosstalk)。對於對應的發光疊層101發出的光,不透光層290具有一小於50%的穿透率(transmittance)。不透光層290的材料包含金屬或是包含混有無機粒子的高分子,其中無機粒子由金屬氧化物組成或是由具有反射率等於或是大於1.8之材料組成,反射層221的材料例如為混有氧化鈦粒子的環氧樹脂。至此,包含複數發光元件300的發光元件陣列30製作完成。如第3E圖所示,提供一電路載板23,其包含有複數位於電路載板23之上表面以及下表面的金屬接觸22以及包含有複數貫穿電路載板23的導電通道22a,其中導電通道22a可連接位於電路載板之上表面上的金屬接觸22以及位於電路載板之下表面上的金屬接觸22。於一實施例中,電路載板23包含錫料(solder)。電路載板23包含FR-4、BT (Bismaleimide-Triazine)樹脂、陶瓷或玻璃。電路載板23之厚度介於50至200微米之間以足夠支撐發光元件且依舊具有小體積。發光元件陣列30藉由對準各發光元件300的第一金屬層260與第二金屬層262至對應的金屬接觸22而直接以覆晶的形式與電路載板23連接。值得注意的是,發光元件陣列30與電路載板23之間金屬接觸22以外的區域可能形成有空隙。另外可選擇性地以填充材料填充於空隙裡以增進連結強度以及機械支撐。連接發光元件陣列30與電路載板23之後,移除發光元件陣列30的基材21。於一實施例中,基材包含藍寶石,發光疊層101包含氮化鎵,且移除基材21的方法包含於較高的溫度中,例如60℃,使用一準分子雷射照射在第一導電層102與基材21的介面,接著分離基材21與第一導電層102。準分子雷射可以為一具有能量為400毫焦耳/平方公分(mJ/cm2 )、波長為248奈米以及脈衝寬度(pulse width)為38奈秒(ns)的氟化氪(KrF)準分子雷射。於另一實施例中,當基材21為砷化鎵基材,移除基材21的方法包含使用一比例為1:35之氨水(NH4 OH)與過氧化氫(H2 O2 )的混和物或是一比例為5:3:5之磷酸(H3 PO4 )、過氧化氫(H2 O2 )與水的混和物藉以蝕刻至可以完全地移除基材21且暴露各發光元件300的第一導電層102、介電層240a以及不透光層290。 【50】 如第3F圖所示,移除基材21之後,發光裝置的製作方法更包括粗化第一導電層102之曓露的表面。於一實施例中,第一導電層102包含氮化鋁鎵銦(Alx Gay ln(1 -x-y) N,其中0≦x, y≦0),可使用氫氧化鉀(KOH)溶液蝕刻第一導電層102曓露的表面以形成一粗化表面102a。於另一實施例中,第一導電層102包含磷化鋁鎵銦(Alx Gay In(1 -x-y) P),可使用鹽酸(HCl)或是磷酸的溶液蝕刻第一導電層102曓露的表面以形成一粗化表面102a,粗化時間可例如為15秒。每一第一導電層102的粗化表面102a可降低各發光元件300內的光發生全反射的可能性,藉以增加發光元件的光取出效率。於粗化步驟之後,複數凹陷區域位於粗化表面102a且實質上被介電層240a環繞。於一實施例中,為了形成一用於顯示器的晶粒級的紅綠藍發光元件單元,本實施例之製作方法可選擇性地於發光元件300b上塗佈一第一波長轉換層294以轉換光,如第3F圖所示。例如,發光元件300b之發光疊層101,其發出之主要波長介於430奈米至470奈米之間的藍光,被轉換為第一轉換光,例如為一具有主要波長介於610奈米至690奈米之間的紅光。進一步的,一第二波長轉換層296可選擇性地塗佈在發光元件300c上藉以將發光元件300c所發出的光轉換為一第二轉換光,例如為一具有主要波長介於500奈米至570奈米之間的綠光。發光元件300a並未塗佈任何波長轉換材料,以直接自發光元件300a之粗化表面102a發出藍光。於一實施例中,第一或第二波長轉換層藉由聚集奈米級的量子點(quantum dot)或是奈米級的螢光粉以形成一具有厚度實質一致的膜,且藉由一黏結層(圖未示)連結至發光疊層101。於另一實施例中,第一或第二波長轉換層包含具有奈米級的量子點或是奈米級的螢光粉,其平均直徑或平均特徵長度介於10奈米至500奈米之間。每個奈米級的量子點或奈米級的螢光粉之長度或是特徵長度實質上小於1000奈米。奈米級的量子點包含半導體材料,例如一具有組成為Znx Cdy Mgl-x-y Se的II-ⅤI(二/六)族化合物半導體,其中x以及y可調變為使II-ⅤI(二/六)族化合物半導體光激發後發出綠或紅光。「特徵長度」定義為一螢光粉或是一量子點之任兩端點之間的最大距離。之後,將例如為環氧樹脂或是矽氧樹脂(silicone)的透明封裝材料24塗佈於發光元件陣列32之上表面以將波長轉換材料固定於發光疊層101,且作為發光元件陣列32之發光元件300a、300b、300c的光學透鏡。於另一實施例中,覆蓋發光元件300a、300b、300c的波長轉換層之材料是相同的。 【51】 第4A圖為如第3F圖所示之發光元件陣列32以覆晶的形式與電路載板23連接的俯視圖。發光元件陣列32以及電路載板23兩者為具有相同或類似尺寸的晶圓形式。發光元件陣列32包含於二維空間中交錯且連續設置的複數紅綠藍發光元件群組,且如圖中虛線圈起的部位所示,每一群組包含一個發光元件300a、一個發光元件300b以及一個發光元件300c。 【52】 最後,執行一切割(dicing)步驟同時切割發光元件陣列32以及電路載板23,形成如第3G圖所示之複數晶粒級的紅綠藍發光元件單元35,各晶粒級的紅綠藍發光元件單元35包含一發出藍光的藍色發光元件300a、一發出紅光的紅色發光元件300b以及一發出綠光的綠色發光元件300c。晶粒級的紅綠藍發光元件單元35是一種不含封裝且為一種表面黏著型的裝置,亦即,於切割步驟之後,不需要傳統的封裝步驟即可直接與一印刷電路載板黏接。透明封裝材料24係共同地覆蓋發光元件300a、300b以及300且不延伸至發光元件300a、300b以及300c之側壁。於一實施例中,切割(dicing)步驟同時切割發光元件陣列32以及電路載板23以形成複數晶粒級的紅綠藍發光元件單元,其中各晶粒級的紅綠藍發光元件單元包含複數紅綠藍發光元件群組。複數紅綠藍發光元件群組於一個紅綠藍發光元件單元中係以I*J陣列排列,其中I以及J是正整數,且I與J中至少一是大於1。I與J之比例較佳地是接近或是等於1/1、3/2、4/3或16/9。 【53】 參照第4B圖,係為晶粒級的紅綠藍發光元件單元35包含如第3G圖所示之紅綠藍發光元件群組。晶粒級的紅綠藍發光元件單元35是為具有一第一長邊以及一第一短邊的第一矩形,其中第一短邊具有一第一寬度S1且第一長邊具有一大於第一寬度S1的第一長度S2。每一發光疊層101為具有一第二長邊以及一第二短邊的第二矩形,其中第二短邊具有一第二寬度d1且第二長邊具有一大於第二寬度d1的第二長度d2。發光疊層101的第二短邊實質上設置於平行於晶粒級的紅綠藍發光元件單元35的第一長邊或實質上設置於垂直於晶粒級的紅綠藍發光元件單元35的第一短邊。於一實施例中,紅綠藍發光元件單元35可作為室內顯示平板的一個像素。為了使具有對角線為40吋且像素解析度為1024*768的電視顯示全部使用發光元件像素,每一像素的面積需小於約0.64平方毫米(mm2 )。因此,紅綠藍發光元件單元35的面積可例如為小於0.36 mm2 。第一長度S2以及第一寬度S1皆小於0.6毫米,且紅綠藍發光元件單元35的長寬比,亦即S2/S1,較佳地係小於2/1。根據本發明所揭露之實施例,第一金屬層260以及第二金屬層262之間的距離,亦即第一距離S3,受限於發光元件陣列以及電路載板於連接步驟中的對位控制。第一距離S3等於或是大於25微米(micron)且小於150微米,藉以確保製程容差且提供足夠做為導電用的接觸面積。紅綠藍發光元件單元35之其中一邊緣與紅綠藍發光元件單元35的其中一發光疊層101之間的距離,亦即第二距離S4,受限於切割步驟的容差。第二距離S4等於或是大於25微米且小於60微米,藉以確保切割步驟的容差以及維持小體積的優點。兩個相鄰發光元件之間的距離,亦即第三距離S5受限於微影蝕刻步驟,且小於50微米,或較佳地小於25微米,藉以於發光疊層101之間保留較多的面積。對於紅綠藍發光元件單元35中每一發光疊層101而言,第二寬度d1介於20至150微米之間且第二長度d2介於20至550微米之間。紅綠藍發光元件單元35的面積與發光疊層101的總面積之比例小於2或介於1.1至2之間,且較佳地係介於1.2至1.8之間。發光疊層101的面積取決於所需的亮度以及像素尺寸。值得注意的是,紅綠藍發光元件單元35的形狀亦可為四邊皆與第一寬度S1相同的正方形。於一實施例中,一像素包含兩個紅綠藍發光元件單元35,其中一個用於正常操作,另一個用於備用以防正常操作的紅綠藍發光元件單元35故障。第一寬度S1較佳地係小於0.3毫米,藉以使兩個紅綠藍發光元件單元35設置於一個像素內。本發明的優點在於,可以實現發光元件作為一平面電視的像素元件,且解析度更可以提升至像素解析度為1024*768的兩倍或是四倍。於另一實施例中,一紅綠藍發光元件單元35包含兩個紅綠藍發光元件群組,其中一個用於正常操作,另一個用於備用以防正常操作的紅綠藍發光元件群組故障。 【54】 參照第5A圖至第5C圖,係為依照本發明實施例之一種晶粒級的發光元件單元,其製造方法以及結構與第3A圖至第3G圖所示之實施例以及相關之揭示內容相似,不同的地方在於,於切割步驟之前,發光元件陣列34包含複數相同的發光元件300d,如第5A圖所示。每一發光元件300d係塗佈相同或不同的波長轉換層298,波長轉換層298用於轉換對應的發光元件300d之發光疊層101發出的光,例如,將主要波長介於430奈米至470奈米之間的藍光轉換為黃光、綠光或是從光的轉換光。參照第5B圖以及第5C圖,係為切割步驟後,包含單一發光元件的晶粒級的發光元件單元36之俯視圖以及剖面圖。晶粒級的發光元件單元36的尺寸與第4B圖所示之晶粒級的紅綠藍發光元件單元35的尺寸相似或相同。晶粒級的發光元件單元36為具有一第一長邊以及一第一短邊的第一矩形,其中第一長邊具有第一長度S1,且第一短邊具有小於第一長度S1的第一寬度S6。每一發光疊層101為具有一第二長邊以及一第二短邊的第二矩形,其中第二短邊具有一第二寬度d1且第二長邊具有一大於第二寬度d1的第二長度d2。發光疊層101的第二短邊實質上設置於平行於晶粒級的紅綠藍發光元件單元36的第一短邊或實質上設置於垂直於晶粒級的紅綠藍發光元件單元36的第一長邊。於一實施例中,紅綠藍發光元件單元36是用於一室內顯示平板的的像素之其中一部分。紅綠藍發光元件單元36的面積可例如為小於0.12mm2 。第一長度S1以及第一寬度S6皆小於0.2毫米,且紅綠藍發光元件單元36的長寬比,亦即S1/S6,較佳地係小於2/1。根據本發明,第一金屬層260以及第二金屬層262之間的距離,亦即第一距離S3,受限於發光元件陣列以及電路載板於連接步驟中的對位控制。第一距離S3等於或是大於25微米且小於150微米,以確保製程容差且提供足夠做為導電用的接觸面積。紅綠藍發光元件單元36之其中一邊緣與其發光疊層101之間的距離,亦即第二距離S4,受限於切割步驟的容差。第二距離S4等於或是大於25微米且小於60微米,藉以確保切割步驟的容差以及維持小體積的優點。對於晶粒級的紅綠藍發光元件單元36中的發光疊層101而言,第二寬度d1介於20至150微米之間且第二長度d2於20至550微米之間。晶粒級的紅綠藍發光元件單元36的面積與發光疊層101的總面積比例小於2或介於1.1至2之間,且較佳地係介於1.2至1.8之間。發光疊層101的面積取決於所需的亮度以及像素尺寸。值得注意的是,紅綠藍發光元件單元36的形狀亦可為四邊皆與第一寬度S6相同的正方形。相似的,發光疊層101的形狀亦可為四邊皆與第二寬度d1相同的正方形。於一實施例中,一像素包含至少三個晶粒級的紅綠藍發光元件單元36,藉以發出藍、紅以及綠光。 【55】 參照第5D圖至第5E圖,係為依照本發明實施例之一種晶粒級的發光元件單元,其製造方法以及結構與第5A圖至第5C圖所示之實施例以及相關之揭示內容相似,不同的地方在於,不透光層290可選擇性地省略。紅綠藍發光元件單元36’是直接表面黏著於一包含於一燈具的光板。發光疊層101之面積取決於所需的亮度以及光板或燈具的尺寸。對於例如小於0.3瓦之低功率的應用而言,紅綠藍發光元件單元36’的發光疊層101之面積係為100mil2 至200mil2 ,對於例如介於0.3至0.9瓦之間的中功率之應用而言,紅綠藍發光元件單元36’的發光疊層101之面積係為201 mil2 至900 mil2 ,對於例如高於0.9瓦的高功率之應用而言,紅綠藍發光元件單元36’的發光疊層101之面積係大於900 mil2 。環繞發光疊層101的介電層240a可作為將光取出晶粒級的發光元件單元36’的耦合透鏡(coupling lens)。晶粒級的發光元件單元36’的面積與發光疊層101的面積之比例等於或大於9,且較佳地係等於或大於15,藉以具有較佳的光取出效率以及光分散性。於本發明中,第一金屬層260以及第二金屬層262之間的距離,亦即第一距離S3’,受限於發光元件陣列以及電路載板於連接步驟中的對位控制。第一距離S3’等於或是大於25微米且小於150微米,藉以確保製程容差且提供足夠做為導電用的接觸面積。值得注意的是,晶粒級的發光元件單元36’的形狀亦可為四邊皆與第一寬度S6’相同的正方形。同樣的,發光疊層101的形狀亦可為四邊皆與第二寬度d1’相同的正方形。第一寬度S6’與第二寬度d1’相同或是大於第二寬度d1’的三倍,較佳地,第一寬度S6’與第二寬度d1’相同或是大於第二寬度d1’的四倍,以使晶粒級的發光元件單元36’具有較佳的光取出效率。於一實例中,介電層於發光疊層101的側壁具有不相同的厚度,因此第一寬度S6’與第二寬度d1’的第一比例(S6’/ d1’)不同於第一長度S1’與第二長度d2’的第二比例(S1’/ d2’),以達到於操作時,俯視晶粒級的發光元件單元36’,其具有不對稱的光場的特性。此外,第一比例至少為第二比例的兩倍,或較佳地係為第二比例的四倍。 【56】 參照第6A圖,係為依照本發明實施例之一晶粒級的紅綠藍發光元件單元65的剖面圖,其製造方法以及結構與第3A圖至第3G圖所示之實施例以及相關之揭示內容相似,不同的地方在於,一填充材料680係填充於包含發光元件300a’、300b’以及300c’的發光元件陣列32’以及電路載板23之間的空隙,藉以提高兩者的連接強度以及提供電路載板以及發光元件之間的電流路徑。填充材料680包含異方導電膠(anisotropic conductive film,ACF),其具有在發光元件陣列32’與電路載板23之間以垂直路徑傳導電流以及在發光元件陣列32’ 與電路載板23之間以平行於發光元件陣列32’或電路載板的橫向路徑絕緣電流的能力。填充材料680係於連接發光元件陣列至電路載板23之前塗佈於電路載板23上。於一實施例中,第一金屬層260’以及第二金屬層262’皆未接觸電路載板23的金屬接觸22。填充材料680係位於第一金屬層260’、第二金屬層262’ 與金屬接觸22之間,藉以在第一金屬層260’、第二金屬層262’ 以及金屬接觸22之間傳導電流。第一金屬層260’以及第二金屬層262’係經圖案化,因此在面對金屬接觸22的表面為一具有複數凹部以及凸部的粗化表面。故,發光元件陣列與電路載板的接觸面積增加,發光元件陣列與電路載板的連接強度亦提升。複數凹部以及凸部具有規則形狀或是不規則形狀,且表面粗糙度(Ra)係介於0.5至5微米之間。使用異方導電膠作為填充材料的的優點在於第一金屬層260’與第二金屬層262’之間的距離,即如第4B圖所示之第一距離S3,可小於25微米。 【57】 第6B圖係為第6A圖所示之發光元件陣列32’中的單顆發光元件300d’ 之示意圖。填充材料680以及第一金屬層260’與第二金屬層262’之圖案化的表面亦可以應用於如第5A圖至第5C圖所示之實施例,藉以形成如第6B圖所示之結構。填充材料680係填充於發光元件300d’以及電路載板23之間的空隙,以提高兩者的連接強度以及提供電路載板與發光元件之間的電流路徑。填充材料680包含異方導電膠(anisotropic conductive film,ACF),其具有在發光元件300d’與電路載板23之間以垂直路徑傳導電流以及在發光元件300d’與電路載板23之間以平行於發光元件300d’或電路載板的橫向路徑絕緣電流的能力。填充材料680係於連接發光元件陣列至電路載板23之前塗佈於電路載板23上。於一實施例中,第一金屬層260’以及第二金屬層262’皆未接觸電路載板23的金屬接觸22。填充材料680係位於第一金屬層260’、第二金屬層262’ 與金屬接觸22之間,藉以在第一金屬層260’ 、第二金屬層262’以及金屬接觸22之間傳導電流。第一金屬層260’以及第二金屬層262’係經圖案化,因此在面對金屬接觸22的表面上有複數凹部以及凸部。故,發光元件與電路載板的接觸面積增加,發光元件與電路載板的連接強度亦提升。複數凹部以及凸部具有規則形狀或是不規則形狀,且表面粗糙度(Ra)係介於0.5至5微米之間。同樣地,填充材料680以及第一金屬層260’與第二金屬層262’之圖案化的表面亦可以應用於上述如第5E圖所示之實施例,以形成如第6C圖所示之結構。 【58】 參照第7A圖至第7G圖,係為依照本發明實施例之一種發光裝置的製作方法流程各階段所對應之剖面圖,其中第7A圖至第7D圖之步驟以及結構與第2A圖至第2D圖所示之實施例以及相關之揭示內容相似,第7F圖至第7G圖之步驟以及結構與第3E圖至第3F圖所示之實施例以及相關之揭示內容相似,不同的地方在於,如第7C圖所示,介電層240a、240b、240c、280係為一光阻劑,例如為正光阻劑或是負光阻劑;如第7D圖至第7E圖所示,於形成金屬層260a、260b、260c以及形成金屬層262a、262b、262c之後,所述的製作方法更包含移除介電層240a、240b、240c、280,因此形成空隙於兩相鄰的發光元件之間以及單一發光元件之金屬層之間;如第7F圖至第7G圖所示,移除基材21之後,兩相鄰的發光元件藉由空隙以彼此分離,且所述的製作方法更包括粗化第一導電層102曓露的表面以形成一粗化表面102a,粗化的方法如前所述,在此便不再贅述。於一實施例中,為了形成一用於顯示或照明的晶粒級(chip-scale)的紅綠藍發光元件,其製作方法可選擇性地於發光元件300b上塗佈一第一波長轉換層294,如第7G圖所示,以將發光元件300b所發出的光轉換為一第一轉換光。進一步的,一第二波長轉換層296可選擇性地塗佈在發光元件300c上藉以將發光元件300c所發出的光轉換為一第二轉換光。發光元件300a並未塗佈任何波長轉換材料,以直接自發光元件300a之粗化表面102a發出藍光。各轉換層的形成方式以及材料如前所述,在此不再贅述。第7H圖係為依照本發明實施例之晶粒級的紅綠藍發光元件單元包含如第7G圖所示之紅綠藍發光元件群組之俯視圖,紅綠藍發光元件單元37之第一寬度S1、第一長度S2、第二長度d2、第一距離S3、第二距離S4、第二寬度d1、第三距離S5如第4B圖所示之實施例以及相關之揭示內容所述,在此不再贅述,不同的地方在於,發光疊層101並未被介電層240a以及不透光層290環繞。於形成第一波長轉換層294以及第二波長轉換層296之後,不需塗佈前述實施例之透明封裝材料24,直接執行切割(dicing)步驟以直接切割電路載板23而不需經由切割發光元件陣列32,形成複數晶粒級的紅綠藍發光元件單元。參照第7I圖以及第7J圖,係為切割步驟後,包含單一發光元件的晶粒級的發光元件單元37之剖面圖以及俯視圖。晶粒級的發光元件單元37之第一長度S1、第一寬度S6、第二寬度d1、第二長度d2、第一距離S3以及第二距離S4如圖5B所示之實施例以及相關之揭示內容所述,在此不再贅述,不同的地方在於,發光疊層101、第一金屬層260以及第二金屬層262之的側壁並未有介電層240a以及不透光層290;此外,波長轉換層298上並未有透明封裝材料24。 【59】 參照第8A圖,係為依照本發明實施例之一種顯示模組76,其包含複數位於第二電路載板73上的晶粒級的紅綠藍發光元件單元65。例如,任兩個相鄰的晶粒級的紅綠藍發光元件單元65是由一間距彼此分離或是無縫地設置而使兩者互相接觸。第二電路載板73包含電路72,電路72是與紅綠藍發光元件單元65之各發光元件電性連接,藉以獨立控制每一紅綠藍發光元件單元65中的藍、紅以及綠色發光元件。於一實施例中,顯示模組76包含M列以及N行的晶粒級的紅綠藍發光元件單元65以用於一具有X*Y像素解析度的顯示器,其中M/N = 1/1、3/2、4/3或16/9,X=a*M,Y=b*N,且a以及b皆為等於或大於2的正整數。顯示模組76於一平方英吋之面積中,包含超過500個的紅綠藍發光元件單元65。也就是說,顯示模組76於一平方英吋之面積中,包含超過1500個發光疊層101。於另一實施例中,每一晶粒級的紅綠藍發光元件單元包含複數紅綠藍發光元件群組,且每一群組如之前所述,包含一藍色發光元件、一紅色發光元件以及一綠色發光元件。複數紅綠藍發光元件群組於一個晶粒級的紅綠藍發光元件單元中係以I*J陣列排列,其中I以及J是正整數,且I與J中至少一是大於1。I與J之比例較佳地是接近或是等於1/1、3/2、4/3或16/9。於一晶粒級的紅綠藍發光元件單元中,分別來自於兩相鄰的紅綠藍發光元件群組的兩相鄰的發光疊層之間的距離,實質上等於分別來自於兩相鄰的晶粒級的紅綠藍發光元件單元之兩相鄰的發光疊層之間的距離。顯示模組76包含M列以及N行的晶粒級的紅綠藍發光元件單元65以用於一具有X*Y像素解析度的顯示器,其中M /N = 1/1、3/2、4/3或16/9,X=a*M*I,Y=b*N*J,且a以及b皆為等於或大於2的正整數。顯示模組76於一平方英吋之面積中,包含超過500個的紅綠藍發光元件群組。也就是說,顯示模組76於一平方英吋之面積中,包含超過1500個發光疊層101。每一紅綠藍發光元件單元以及紅綠藍發光元件單元中的每一發光元件皆可藉由電路載板23以及第二電路載板73上形成的電路獨立驅動。第二電路載板73的材料班還FR-4、BT (Bismaleimide-Triazine) 樹脂、陶瓷或是玻璃。第8B圖係為依照本發明實施例之一種照明模組78的示意圖。照明模組78包括複數位於第二電路載板73上的晶粒級的發光元件單元66。依據施加的驅動電壓,晶粒級的發光元件單元66可藉由第二電路載板73上的電路以串聯或是並聯方式連接。於一實施例中,照明模組78係被設置於一如第9所示之燈泡80內。燈泡80進一步包含一覆蓋照明模組78的光學透鏡82,一具有一連接表面且照明模組78是位於連接表面的散熱槽85,一與散熱槽85連接的連結部87,以及一與連結部87連接且與照明模組78電性連接的電連接器88。 【60】 以上所述之實施例僅係為說明本發明之技術思想及特點,其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施,當不能以之限定本發明之專利範圍,即大凡依本發明所揭示之精神所作之均等變化或修飾,仍應涵蓋在本發明之專利範圍內。[31] The above described features and advantages of the present invention will be more apparent from the following description of the embodiments. In the drawings, the shape or thickness of the elements may be enlarged or reduced. It is to be noted that elements not shown or described in the figures may be in a form known to those skilled in the art. The examples of the invention are intended to be illustrative only and not to limit the scope of the invention. Any changes or modifications of the present invention to those skilled in the art will be made without departing from the spirit and scope of the invention. [32] Referring to FIGS. 1A to 1E, there are shown cross-sectional views corresponding to respective stages of a flow of a method for fabricating a light-emitting element according to an embodiment of the present invention. In FIG. 1A, a light emitting structure 100 is formed, which comprises a substrate 11 and a first conductive layer 102 as a cladding layer, and an active layer 104 is disposed on the first conductive layer 102 as a light emitting layer. A second conductive layer 106 is disposed on the active layer 104 as another cladding layer. Preferably, as shown in FIG. 1A, an electrode or bonding pad 107a is located on the exposed portion of the first conductive layer 102, and the other electrode or bonding pad 107b is positioned on the second conductive layer 106. The materials of the electrodes or pads 107a and 107b (e.g., aluminum) and methods of fabrication are well known to those skilled in the art and will not be further described herein. In addition, in an embodiment, the light emitting structure 100 further includes a passivation layer 120 to protect the light emitting structure 100. The material of the protective layer 120 (e.g., cerium oxide) and the method of fabrication are also well known to those skilled in the art and will not be described herein. In one embodiment, the first conductive layer 102 is an n-type semiconductor conductive layer, and the second conductive layer 106 is a p-type semiconductor conductive layer. The n-type semiconductor conductive layer 102 and the p-type semiconductor conductive layer 106 are semiconductor materials of any conventional or future visible, preferably a III-V (three/five) group compound semiconductor, such as aluminum gallium indium nitride (Al).x Gay Ln(1 -x-y) N) or aluminum gallium indium phosphide (Alx Gay In(1-xy) P), where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1, and is further doped by the p/n type dopant as appropriate. The active layer 104 can also use conventional semiconductor materials and structures. For example, the material can be aluminum gallium indium nitride (Al).x Gay Ln(1 -x-y) N) or aluminum gallium indium phosphide (Alx Gay Ln(1 -x-y) P), etc., and the structure may be Single Quantum Well (SQW), Multiple Quantum Well (MQW) and Double Heterosture (DH), and the principle and mechanism of illumination are conventional techniques. I will not repeat them here. In addition, the light emitting structure 100 can be subjected to a metalorganic chemical vapor deposition (MOCVD), a molecular beam epitaxy (MBE) process, or a hydride vapor phase epitaxy (HVPE) process. Production. [34] Next, as shown in FIG. 1B, a first dielectric layer 122 is formed on the light emitting structure 100. Preferably, the first dielectric layer 122 is a transparent dielectric layer and has a thickness of D ≦ 20 μm, thereby effectively conducting heat generated by the light emitting structure 100. The material of the first dielectric layer 122 may be cerium oxide (SiO2 ), tantalum nitride (Si3 N4 ), or a combination thereof, which can be made by MOCVD or MBE. [35] Thereafter, referring to FIG. 1C, a second dielectric layer 140 is formed on the first dielectric layer 122. The material of the second dielectric layer 140 may be one selected from the group consisting of cerium oxide, cerium nitride, polyimide, BCB (bisbenzocyclobutene), and photoresist. Preferably, the thickness of the second dielectric layer 140 is about 25 μm, which is formed by a printing technique. [36] Referring to FIG. 1D, after the second dielectric layer 140 is formed, a metal layer 160 is formed, the metal layer 160 is located on the light emitting structure 100 and electrically contacts the first conductive layer 102, and a portion of the metal layer 160 is located at the first On the dielectric layer 122; and forming a metal layer 162, the metal layer 162 is located on the light emitting structure 100 and electrically contacts the second conductive layer 106, and a portion of the metal layer 162 is located on the first dielectric layer 122. The first dielectric layer 122 and the second dielectric layer 140 are separated from the metal layer 160 and the metal layer 162 . The material of the metal layer 160 or the metal layer 162 may be selected from gold (Au), aluminum (Al), silver (Ag), alloys thereof, or the like, or other conventional metals. Preferably, the metal layer 160 and the metal layer 162 are formed together by a printing technique or electroplating. Through the above steps, the light-emitting element 10 is completed. In one embodiment, the first dielectric layer 122 is a transparent dielectric layer, and the contact surface of the first dielectric layer 122 and the metal layer 160 and/or the metal layer 162 is used to reflect the light emitted by the light emitting structure 100. Therefore, the light output intensity of the light-emitting element 10 can be effectively improved. In addition, the metal layer 160 and/or the metal layer 162 also serves as a heat dissipation path of the light emitting structure 100. When the metal layer 160 and the metal layer 162 have large contact areas A1 and A2, it also contributes to efficient and rapid heat dissipation. [38] Referring to FIG. 1E, after forming the structure as shown in FIG. 1D, the method of fabricating the light-emitting element further includes a step of removing the substrate 11, thereby exposing the first conductive layer 102. The substrate 11 can be, for example, a sapphire substrate or a gallium arsenide substrate. When the substrate 11 is a sapphire substrate, the substrate 11 can be removed by an excimer laser. The excimer laser can have an energy of 400 mJ/cm 2 (mJ/cm)2 A krypton fluoride (KrF) excimer laser having a wavelength of 248 nm and a pulse width of 38 nanoseconds (ns). At higher temperatures, such as 60 ° C, when the excimer laser is illuminated on the sapphire substrate, the sapphire substrate is removed to expose the first conductive layer 102. In addition, when the substrate 11 is a gallium arsenide substrate, a ratio of 1:35 ammonia water (NH)4 OH) and hydrogen peroxide (H2 O2 a solution or a ratio of 5:3:5 phosphoric acid (H)3 PO4 ), hydrogen peroxide (H2 O2 The solution with water can be used to remove the gallium arsenide substrate, thereby exposing the first conductive layer 102. [39] After the substrate 11 is removed, the method of fabricating the light-emitting element further includes roughening the surface 102a of the first conductive layer 102. For example, when the first conductive layer 102 is an aluminum gallium nitride (Al)x Gay Ln(1 -x-y ) The N) layer, the surface 102a thereof may be roughened by an etching solution, which may be, for example, a potassium hydroxide (KOH) solution. In addition, when the first conductive layer 102 is an aluminum gallium indium phosphide (Alx Gay In(1-xy) The P) layer, a solution of hydrochloric acid (HCl) and phosphoric acid, can be used to roughen the surface 102a of the first conductive layer 102, and the roughening time can be, for example, 15 seconds. The roughened surface 102a of the first conductive layer 102 can reduce the possibility of occurrence of total reflection, thereby increasing the light extraction efficiency of the light emitting element. [40] The light-emitting element 10 shown in FIG. 1E and the light-emitting elements 10a, 10b, and 10c shown in FIG. 1D provide a sufficiently large contact area (preferably occupying at least one half of the cross-sectional area of the light-emitting element 10), and the light-emitting element 10a The 10b and 10c are directly connected to the circuit carrier 13 by a solder 12, and do not require processes such as die bonding and wire bonding. In one embodiment, the light-emitting element 10a emits red light (R), the light-emitting element 10b emits green light (G), and the light-emitting element 10c emits blue light (B), and the three are respectively connected to the circuit carrier 13 for image display. . Referring to FIGS. 2A to 2D, there are shown cross-sectional views corresponding to various stages of the flow of the method for fabricating a light-emitting element array according to an embodiment of the present invention. In Figure 2A, a substrate 21 is first provided, such as a sapphire substrate, a gallium arsenide (GaAs) substrate, or other combination of substrates well known to those skilled in the art. Next, a plurality of light emitting structures 200a, 200b, and 200c are formed on the substrate 21. For the materials and manufacturing methods of the light-emitting structures 200a, 200b, and 200c, reference may be made to the light-emitting structures 100 of FIGS. 1A to 1D. Similarly, the light-emitting structures 200a, 200b, and 200c may be subjected to a metalorganic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, or a hydride vapor phase epitaxial growth process. Phase epitaxy, HVPE) process and other production. [42] Next, as shown in FIG. 2B, a dielectric layer 222a is formed on the light emitting structure 200a to form a dielectric layer 222b on the light emitting structure 200b, and a dielectric layer 222c is formed on the light emitting structure 200c. Preferably, as in the dielectric layer 122 shown in FIG. 1B, the dielectric layers 222a, 222b, and 222c are a transparent dielectric layer and have a thickness of D ≦ 20 μm, thereby effectively conducting the light emitting structures 200a, 200b, and 200c. The heat generated. The material of the dielectric layers 222a, 222b, and 222c may be a combination of cerium oxide, tantalum nitride, or the like, which may be fabricated by MOCVD or MBE. [43] Thereafter, referring to FIG. 2C, a dielectric layer 240a is formed on the dielectric layer 222a, a dielectric layer 240b is formed on the dielectric layer 222b, and a dielectric layer 240c is formed on the dielectric layer 222c. The material of the dielectric layers 240a, 240b, 240c may be one selected from the group consisting of cerium oxide, cerium nitride, polyimide, BCB (bisbenzocyclobutene), and photoresist. Preferably, as in the dielectric layer second 140 shown in FIG. 1C, the dielectric layers 240a, 240b, 240c each have a thickness of about 25 μm and are formed by a printing technique. In one embodiment, a dielectric layer 280 is formed between the light emitting structures 200a, 200b, 200c to electrically insulate the light emitting elements 20a, 20b, and 20c (as shown in FIG. 2D). In this embodiment, the material of the dielectric layer 280 is the same as that of the dielectric layers 240a, 240b, 240c, such as polyamidene, and utilizes a process (eg, a printing technique) and dielectric layers 240a, 240b, 240c. Formed together. In another embodiment, the material of the dielectric layer 280 is different from the material of the dielectric layers 240a, 240b, 240c and is formed by different processes. [44] Referring to FIG. 2D, metal layers 260a, 260b, 260c are formed; and metal layers 262a, 262b, 262c are formed. The material of the metal layers 260a, 260b, 260c, 262a, 262b, and 262c may be selected from alloys of gold (Au), aluminum (Al), silver (Ag), or the like. Preferably, the metal layers 260a, 260b, 260c, 262a, 262b, and 262c are formed by a printing technique or electroplating. Through the above steps, the light-emitting element array 20 having the light-emitting elements 20a, 20b, and 20c is completed. [45] As shown in FIGS. 2E to 2F, in an embodiment, the light-emitting elements 20a, 20b, and 20c provide a sufficiently large contact area to directly connect to the circuit carrier 23 using a solder 22 . . Further, the substrate 21 is separated from the light-emitting element array 20, and the light-emitting element array 20 can be used for image display. For example, after the solder material 20 is directly connected to the light-emitting elements 20a, 20b, and 20c and the circuit carrier 23, the method of fabricating the light-emitting element further includes a step of removing the substrate 21. Substrate 11 can be, for example, a sapphire substrate and can be removed by an excimer laser. The excimer laser can have an energy of 400 mJ/cm 2 (mJ/cm)2 A krypton fluoride (KrF) excimer laser having a wavelength of 248 nm and a pulse width of 38 nanoseconds (ns). At higher temperatures, such as 60 ° C, when the excimer laser is illuminated on the sapphire substrate, the sapphire substrate is removed to expose the first conductive layer 102. In addition, when the substrate 11 is a gallium arsenide substrate, a ratio of 1:35 ammonia water (NH)4 OH) and hydrogen peroxide (H2 O2 a solution or a ratio of 5:3:5 phosphoric acid (H)3 PO4 ), hydrogen peroxide (H2 O2 The solution with water can be used to remove the gallium arsenide substrate, thereby exposing the first conductive layer 102. [46] After the substrate 21 is removed, the method of fabricating the light-emitting device further includes roughening the surface 102a of the first conductive layer 102. For example, when the first conductive layer 102 is an aluminum gallium nitride (Al)x Gay Ln(1 -x-y ) The N) layer, the surface 102a thereof may be roughened by an etching solution, which may be, for example, a potassium hydroxide (KOH) solution. In addition, when the first conductive layer 102 is an aluminum gallium indium phosphide (Alx Gay In1-xy The P) layer, a solution of hydrochloric acid (HCl) and phosphoric acid, can be used to roughen the surface 102a of the first conductive layer 102, and the roughening time can be, for example, 15 seconds. The roughened surface 102a of the first conductive layer 102 can reduce the possibility of occurrence of total reflection, thereby increasing the light extraction efficiency of the light emitting element. In one embodiment, as shown in FIG. 2G, a transparent encapsulating material 24 is used to cover the light emitting device array 20 including the light emitting elements 20a, 20b, and 20c and to connect the circuit carrier 23, thereby forming the light emitting device package 25. The transparent encapsulating material 24 can be, for example, an epoxy resin or other suitable material well known to those skilled in the art. [47] Referring to FIGS. 3A to 3G, there are shown cross-sectional views corresponding to various stages of a method of fabricating a light-emitting device according to an embodiment of the present invention. Referring to FIG. 3A, a substrate 21 is provided which is single crystal and comprises sapphire, gallium arsenide, gallium nitride or germanium; epitaxial growth of a first conductive layer 102 on the substrate 21, and a first conductive layer 102 As a cladding layer; epitaxial growth of an active layer 104 comprising a multiple quantum well ( MQW) structure on the first conductive layer 102, wherein the active layer 104 serves as a light-emitting layer; and epitaxial growth The second conductive layer 106 is on the active layer 104, wherein the second conductive layer 106 serves as another cladding layer. Next, the first conductive layer 102, the active layer 104, and the second conductive layer 106 are etched to form a plurality of light-emitting stacks 101 separated from each other by trenches (not shown) on the substrate 21, and each of the light-emitting stacks In 101, a portion of the first conductive layer 102 is exposed. Next, a protective layer 120 is formed on each of the light emitting laminates 101, and the protective layer 120 covers a portion of the first conductive layer 102, a portion of the second conductive layer 106, and a sidewall of the light emitting laminate 101. Next, an electrode or bonding pad 107a electrically connected to the first conductive layer 102 is disposed on the exposed portion of each of the first conductive layers 102, and a second conductive layer is disposed on each of the second conductive layers 106. 106 electrically connected electrodes or bond pads 107b. <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td></td></tr></TBODY></TABLE> [48] Thereafter, referring to FIG. 3B, a reflective layer 221 is disposed on each of the protective layers 120, and a first dielectric layer 122 covering the reflective layer 221 is formed on each of the protective layers 120. For the light emitted by the light-emitting layer 101, the reflective layer 221 has a reflectance equal to or greater than 80%. The material of the reflective layer 221 comprises a metal such as silver, a silver alloy, aluminum or an aluminum alloy. In one embodiment, the material of the reflective layer 221 comprises a polymer mixed with inorganic particles, wherein the inorganic particles are composed of a metal oxide or a material having a reflectance equal to or greater than 1.8, and the material of the reflective layer 221 is, for example, An epoxy resin mixed with titanium oxide particles. Each of the reflective layers 221 is completely covered by the corresponding protective layer 120 and the first dielectric layer 122, thereby electrically insulating the respective reflective layers 221 and the corresponding light-emitting stacks 101. In another embodiment, the protective layer 120 is omitted, and the reflective layer 221 is directly formed on the second conductive layer 106 and electrically connected to the second conductive layer 106. Then, as shown in FIG. 3C, a second dielectric layer 240 is formed on the substrate 21 and between the trenches and on each of the light emitting stacks 101, and each of the second dielectric layers 240 exposes the corresponding electrode. Or bond pad 107a and electrode or bond pad 107b. Thereafter, a first metal layer 260 and a second metal layer 262 are formed between each of the second dielectric layers 240 and a portion of the corresponding first dielectric layer 122. The first metal layer 260 and the second metal layer 262 are formed on the corresponding electrode or bonding pad 107a and the electrode or bonding pad 107b, respectively. The material of the first metal layer 260 and the second metal layer 262 comprises an alloy of gold, aluminum, silver or the like. In one embodiment, the first metal layer 260 and the second metal layer 262 are formed by a printing technique or electroplating. [00] As shown in FIG. 3D, the second dielectric layer 240 patterned between the adjacent light-emitting layers 101 is formed with a recess in the second dielectric layer 240, and the recess exposes a portion of the substrate 21 and The second dielectric layer 240 is spaced apart to form a dielectric layer 240a, after which an opaque layer 290 is formed in the recess. In one embodiment, the opaque layer 290 acts as a reflective layer or a light absorbing layer to reflect or absorb the light emitted by the corresponding luminescent layer 101 and to avoid the mutual influence of the light emitted by the adjacent luminescent layer 101. Or generate crosstalk. For the light emitted by the corresponding light-emitting stack 101, the opaque layer 290 has a transmittance of less than 50%. The material of the opaque layer 290 comprises a metal or a polymer containing inorganic particles, wherein the inorganic particles are composed of a metal oxide or a material having a reflectance equal to or greater than 1.8, and the material of the reflective layer 221 is, for example, An epoxy resin mixed with titanium oxide particles. Thus far, the light-emitting element array 30 including the plurality of light-emitting elements 300 is completed. As shown in FIG. 3E, a circuit carrier 23 is provided which includes a plurality of metal contacts 22 on the upper surface and the lower surface of the circuit carrier 23 and a conductive via 22a including a plurality of through circuit carriers 23, wherein the conductive vias 22a can connect metal contacts 22 on the upper surface of the circuit carrier and metal contacts 22 on the lower surface of the circuit carrier. In one embodiment, the circuit carrier 23 contains a solder. The circuit carrier 23 contains FR-4, BT (Bismaleimide-Triazine) resin, ceramic or glass. The thickness of the circuit carrier 23 is between 50 and 200 microns to adequately support the light-emitting elements and still have a small volume. The light emitting element array 30 is directly connected to the circuit carrier 23 in a flip chip form by aligning the first metal layer 260 and the second metal layer 262 of each of the light emitting elements 300 to the corresponding metal contacts 22. It is to be noted that a region other than the metal contact 22 between the light emitting element array 30 and the circuit carrier 23 may be formed with a void. Alternatively, the filler material may be selectively filled in the void to enhance the joint strength and mechanical support. After the light emitting element array 30 and the circuit carrier 23 are connected, the substrate 21 of the light emitting element array 30 is removed. In one embodiment, the substrate comprises sapphire, the light-emitting stack 101 comprises gallium nitride, and the method of removing the substrate 21 is included in a higher temperature, such as 60 ° C, using a quasi-laser laser at the first The interface between the conductive layer 102 and the substrate 21 is followed by separation of the substrate 21 from the first conductive layer 102. The excimer laser can have an energy of 400 mJ/cm 2 (mJ/cm)2 A krypton fluoride (KrF) excimer laser having a wavelength of 248 nm and a pulse width of 38 nanoseconds (ns). In another embodiment, when the substrate 21 is a gallium arsenide substrate, the method of removing the substrate 21 comprises using a 1:35 ratio of ammonia (NH).4 OH) and hydrogen peroxide (H2 O2 a mixture or a ratio of 5:3:5 phosphoric acid (H)3 PO4 ), hydrogen peroxide (H2 O2 The mixture with water is etched to completely remove the substrate 21 and expose the first conductive layer 102, the dielectric layer 240a, and the opaque layer 290 of each of the light-emitting elements 300. [50] As shown in FIG. 3F, after the substrate 21 is removed, the method of fabricating the light-emitting device further includes roughening the exposed surface of the first conductive layer 102. In an embodiment, the first conductive layer 102 comprises aluminum gallium indium nitride (Al)x Gay Ln(1 -x-y) N, where 0 ≦ x, y ≦ 0), the exposed surface of the first conductive layer 102 may be etched using a potassium hydroxide (KOH) solution to form a roughened surface 102a. In another embodiment, the first conductive layer 102 comprises aluminum gallium phosphide (Al)x Gay In(1 -x-y) P), the exposed surface of the first conductive layer 102 may be etched using a solution of hydrochloric acid (HCl) or phosphoric acid to form a roughened surface 102a, which may be, for example, 15 seconds. The roughened surface 102a of each of the first conductive layers 102 can reduce the possibility of total reflection of light in each of the light-emitting elements 300, thereby increasing the light extraction efficiency of the light-emitting elements. After the roughening step, the plurality of recessed regions are located on the roughened surface 102a and are substantially surrounded by the dielectric layer 240a. In one embodiment, in order to form a die-level red, green, and blue light-emitting element unit for a display, the fabrication method of the embodiment can selectively apply a first wavelength conversion layer 294 to the light-emitting element 300b for conversion. Light, as shown in Figure 3F. For example, the light-emitting layer 101 of the light-emitting element 300b emits blue light having a dominant wavelength between 430 nm and 470 nm, and is converted into a first converted light, for example, having a main wavelength of 610 nm to Red light between 690 nm. Further, a second wavelength conversion layer 296 can be selectively coated on the light-emitting element 300c to convert the light emitted by the light-emitting element 300c into a second converted light, for example, having a dominant wavelength of 500 nm to Green light between 570 nm. The light-emitting element 300a is not coated with any wavelength converting material to directly emit blue light from the roughened surface 102a of the light-emitting element 300a. In one embodiment, the first or second wavelength conversion layer forms a film having a substantially uniform thickness by collecting a nanometer quantum dot or a nanometer phosphor powder, and by using a film A bonding layer (not shown) is attached to the light emitting laminate 101. In another embodiment, the first or second wavelength conversion layer comprises a nanometer-sized quantum dot or a nano-scale phosphor powder having an average diameter or an average characteristic length of between 10 nm and 500 nm. between. The length or characteristic length of each nano-scale quantum dot or nano-scale phosphor is substantially less than 1000 nm. Nano-scale quantum dots comprise a semiconductor material, such as a composition having Znx Cdy MgLxy A II-VI (di/hexa) compound semiconductor of Se in which x and y are tuned to cause green light or red light after photo-excitation of a II-VI (di/hexa) compound semiconductor. "Feature length" is defined as the maximum distance between a phosphor powder or a point at either end of a quantum dot. Thereafter, a transparent encapsulating material 24 such as an epoxy resin or a silicone is applied to the upper surface of the light emitting element array 32 to fix the wavelength converting material to the light emitting layer 101, and as the light emitting element array 32 Optical lenses of light-emitting elements 300a, 300b, 300c. In another embodiment, the materials of the wavelength conversion layer covering the light-emitting elements 300a, 300b, 300c are the same. Fig. 4A is a plan view showing the light-emitting element array 32 as shown in Fig. 3F connected to the circuit carrier 23 in a flip chip form. Both the light emitting element array 32 and the circuit carrier 23 are in the form of wafers having the same or similar dimensions. The light-emitting element array 32 includes a plurality of red, green, and blue light-emitting element groups that are staggered and continuously disposed in a two-dimensional space, and each group includes one light-emitting element 300a and one light-emitting element 300b as shown by the dotted circle in the figure. And a light emitting element 300c. [52] Finally, a dicing step is performed to simultaneously cut the light-emitting element array 32 and the circuit carrier 23 to form a plurality of grain-level red, green and blue light-emitting element units 35 as shown in FIG. 3G, each of the grain level The red-green-blue light-emitting element unit 35 includes a blue light-emitting element 300a that emits blue light, a red light-emitting element 300b that emits red light, and a green light-emitting element 300c that emits green light. The grain-level red, green and blue light-emitting element unit 35 is a device that is package-free and is a surface-adhesive type, that is, after the cutting step, it can be directly bonded to a printed circuit carrier without a conventional packaging step. . The transparent encapsulating material 24 collectively covers the light emitting elements 300a, 300b, and 300 and does not extend to the side walls of the light emitting elements 300a, 300b, and 300c. In one embodiment, the dicing step simultaneously cuts the light emitting element array 32 and the circuit carrier 23 to form a plurality of grain level red, green and blue light emitting element units, wherein the red, green and blue light emitting element units of each grain level comprise a plurality of Red, green and blue light-emitting component groups. The plurality of red, green and blue light emitting elements are arranged in an I*J array in a red, green and blue light emitting element unit, wherein I and J are positive integers, and at least one of I and J is greater than one. The ratio of I to J is preferably close to or equal to 1/1, 3/2, 4/3 or 16/9. Referring to FIG. 4B, the red-green-blue light-emitting element unit 35 of the grain level includes a red-green-blue light-emitting element group as shown in FIG. 3G. The grain-level red-green-blue light-emitting element unit 35 is a first rectangle having a first long side and a first short side, wherein the first short side has a first width S1 and the first long side has a larger than the first A first length S2 of width S1. Each of the light emitting laminates 101 is a second rectangle having a second long side and a second short side, wherein the second short side has a second width d1 and the second long side has a second larger than the second width d1 Length d2. The second short side of the light-emitting layer 101 is substantially disposed on the first long side of the red-green-blue light-emitting element unit 35 parallel to the grain level or substantially disposed on the red-green-blue light-emitting element unit 35 perpendicular to the grain level. The first short side. In an embodiment, the red, green and blue light emitting element unit 35 can be used as one pixel of the indoor display panel. In order to make the television display having a diagonal of 40 吋 and a pixel resolution of 1024*768 all use the light-emitting element pixels, the area of each pixel needs to be less than about 0.64 square millimeters (mm).2 ). Therefore, the area of the red-green-blue light-emitting element unit 35 can be, for example, less than 0.36 mm.2 . The first length S2 and the first width S1 are both less than 0.6 mm, and the aspect ratio of the red, green and blue light-emitting element unit 35, that is, S2/S1, is preferably less than 2/1. According to the embodiment of the present invention, the distance between the first metal layer 260 and the second metal layer 262, that is, the first distance S3, is limited by the alignment control of the light emitting element array and the circuit carrier in the connecting step. . The first distance S3 is equal to or greater than 25 microns (micron) and less than 150 microns to ensure process tolerance and provide sufficient contact area for electrical conduction. The distance between one of the edges of the red-green-blue light-emitting element unit 35 and one of the light-emitting stacks 101 of the red-green-blue light-emitting element unit 35, that is, the second distance S4, is limited by the tolerance of the cutting step. The second distance S4 is equal to or greater than 25 microns and less than 60 microns to ensure tolerance of the cutting step and to maintain the advantages of a small volume. The distance between two adjacent illuminating elements, that is, the third distance S5 is limited to the lithography etching step, and is less than 50 microns, or preferably less than 25 microns, whereby more remains between the luminescent stacks 101. area. For each of the light-emitting stacks 101 in the red-green-blue light-emitting element unit 35, the second width d1 is between 20 and 150 microns and the second length d2 is between 20 and 550 microns. The ratio of the area of the red-green-blue light-emitting element unit 35 to the total area of the light-emitting stack 101 is less than 2 or between 1.1 and 2, and preferably between 1.2 and 1.8. The area of the light-emitting stack 101 depends on the desired brightness and pixel size. It should be noted that the shape of the red, green and blue light emitting element unit 35 may also be a square whose four sides are the same as the first width S1. In one embodiment, a pixel includes two red, green and blue light emitting element units 35, one for normal operation and the other for standby to prevent malfunction of the normally operating red, green and blue light emitting element unit 35. The first width S1 is preferably less than 0.3 mm, whereby the two red, green and blue light emitting element units 35 are disposed within one pixel. The invention has the advantages that the light-emitting element can be realized as a pixel element of a flat-panel television, and the resolution can be further improved to twice or four times the pixel resolution of 1024*768. In another embodiment, a red, green, and blue light emitting element unit 35 includes two red, green, and blue light emitting element groups, one for normal operation and the other for standby to prevent normal operation of the red, green, and blue light emitting element groups. malfunction. [54] Referring to FIGS. 5A to 5C, there is shown a crystal-level light-emitting element unit according to an embodiment of the present invention, a manufacturing method and structure thereof, and an embodiment shown in FIGS. 3A to 3G and related thereto. The disclosure is similar, except that prior to the cutting step, the array of light-emitting elements 34 comprises a plurality of identical light-emitting elements 300d, as shown in Figure 5A. Each of the light-emitting elements 300d is coated with the same or different wavelength conversion layer 298, and the wavelength conversion layer 298 is used to convert the light emitted by the light-emitting layer 101 of the corresponding light-emitting element 300d, for example, the main wavelength is between 430 nm and 470. The blue light between the nanometers is converted into yellow light, green light or converted light from light. Referring to FIGS. 5B and 5C, a plan view and a cross-sectional view of the light-emitting element unit 36 including the die-level of a single light-emitting element after the dicing step. The size of the grain-level light-emitting element unit 36 is similar to or the same as the size of the grain-level red-green-blue light-emitting element unit 35 shown in FIG. 4B. The grain-level light-emitting element unit 36 is a first rectangle having a first long side and a first short side, wherein the first long side has a first length S1 and the first short side has a smaller than the first length S1 A width S6. Each of the light emitting laminates 101 is a second rectangle having a second long side and a second short side, wherein the second short side has a second width d1 and the second long side has a second larger than the second width d1 Length d2. The second short side of the light emitting stack 101 is substantially disposed on the first short side of the red, green and blue light emitting element unit 36 parallel to the grain level or substantially disposed in the red, green and blue light emitting element unit 36 perpendicular to the grain level. The first long side. In one embodiment, the red, green, and blue light emitting element unit 36 is a portion of a pixel for an indoor display panel. The area of the red-green-blue light-emitting element unit 36 may be, for example, less than 0.12 mm.2 . The first length S1 and the first width S6 are both less than 0.2 mm, and the aspect ratio of the red, green and blue light-emitting element unit 36, that is, S1/S6, is preferably less than 2/1. According to the present invention, the distance between the first metal layer 260 and the second metal layer 262, that is, the first distance S3, is limited by the alignment control of the light-emitting element array and the circuit carrier in the connecting step. The first distance S3 is equal to or greater than 25 microns and less than 150 microns to ensure process tolerance and provide sufficient contact area for electrical conduction. The distance between one of the edges of the red, green and blue light-emitting element unit 36 and its light-emitting stack 101, that is, the second distance S4, is limited by the tolerance of the cutting step. The second distance S4 is equal to or greater than 25 microns and less than 60 microns to ensure tolerance of the cutting step and to maintain the advantages of a small volume. For the light-emitting stack 101 in the grain-level red, green, and blue light-emitting element unit 36, the second width d1 is between 20 and 150 microns and the second length d2 is between 20 and 550 microns. The ratio of the area of the grain-level red-green-blue light-emitting element unit 36 to the total area of the light-emitting stack 101 is less than 2 or between 1.1 and 2, and preferably between 1.2 and 1.8. The area of the light-emitting stack 101 depends on the desired brightness and pixel size. It should be noted that the shape of the red, green and blue light emitting element unit 36 may also be a square whose four sides are the same as the first width S6. Similarly, the shape of the light emitting laminate 101 may also be a square having the same width as the second width d1. In one embodiment, a pixel includes at least three grain level red, green, and blue light emitting element units 36 to emit blue, red, and green light. [55] Referring to FIGS. 5D to 5E, there is shown a crystal-level light-emitting element unit according to an embodiment of the present invention, a manufacturing method and structure thereof, and an embodiment shown in FIGS. 5A to 5C and related thereto. The disclosure is similar, except that the opaque layer 290 can be selectively omitted. The red, green and blue light-emitting element unit 36' is directly surface-attached to a light panel contained in a light fixture. The area of the light-emitting stack 101 depends on the desired brightness and the size of the light panel or luminaire. For applications such as low power of less than 0.3 watts, the area of the light-emitting stack 101 of the red-green-blue light-emitting element unit 36' is 100 mils.2 Up to 200mil2 For applications such as medium power between 0.3 and 0.9 watts, the area of the light-emitting stack 101 of the red-green-blue light-emitting element unit 36' is 201 mils.2 To 900 mil2 For applications such as high power above 0.9 watts, the area of the light-emitting stack 101 of the red-green-blue light-emitting element unit 36' is greater than 900 mils.2 . The dielectric layer 240a surrounding the light-emitting layer stack 101 serves as a coupling lens for taking out the light-emitting element unit 36' of the grain level. The ratio of the area of the crystal-level light-emitting element unit 36' to the area of the light-emitting layer 101 is equal to or greater than 9, and preferably equal to or greater than 15, thereby having better light extraction efficiency and light dispersibility. In the present invention, the distance between the first metal layer 260 and the second metal layer 262, that is, the first distance S3', is limited by the alignment control of the light-emitting element array and the circuit carrier in the connecting step. The first distance S3' is equal to or greater than 25 microns and less than 150 microns to ensure process tolerance and provide sufficient contact area for electrical conduction. It is to be noted that the shape of the light-emitting element unit 36' of the grain level may also be a square having the same width as the first width S6'. Similarly, the shape of the light-emitting laminate 101 may be a square having the same width as the second width d1'. The first width S6' is the same as the second width d1' or three times larger than the second width d1'. Preferably, the first width S6' is the same as the second width d1' or is greater than the second width d1'. In order to make the light-emitting element unit 36' of the grain level have better light extraction efficiency. In one example, the dielectric layer has a different thickness on the sidewall of the light emitting laminate 101, and thus the first ratio (S6'/d1') of the first width S6' and the second width d1' is different from the first length S1. A second ratio (S1'/d2') to the second length d2', in order to achieve operation, looks at the grain level light-emitting element unit 36' which has an asymmetrical light field characteristic. Furthermore, the first ratio is at least twice the second ratio, or preferably four times the second ratio. Referring to FIG. 6A, there is shown a cross-sectional view of a grain-level red, green and blue light-emitting element unit 65 according to an embodiment of the present invention, a manufacturing method and structure thereof, and an embodiment shown in FIGS. 3A to 3G. And the related disclosure is similar, except that a filling material 680 is filled in the gap between the light-emitting element array 32' including the light-emitting elements 300a', 300b' and 300c' and the circuit carrier 23, thereby improving both The strength of the connection and the current path between the circuit carrier and the light-emitting elements. The filling material 680 includes an anisotropic conductive film (ACF) having a current in a vertical path between the light emitting element array 32' and the circuit carrier 23 and between the light emitting element array 32' and the circuit carrier 23. The ability to insulate current in parallel with the lateral path of the array of light-emitting elements 32' or the circuit carrier. The filling material 680 is applied to the circuit carrier 23 before connecting the array of light emitting elements to the circuit carrier 23. In one embodiment, neither the first metal layer 260' nor the second metal layer 262' contact the metal contacts 22 of the circuit carrier 23. Filler material 680 is positioned between first metal layer 260', second metal layer 262' and metal contact 22 to conduct electrical current between first metal layer 260', second metal layer 262', and metal contact 22. The first metal layer 260' and the second metal layer 262' are patterned so that the surface facing the metal contact 22 is a roughened surface having a plurality of recesses and protrusions. Therefore, the contact area between the array of the light-emitting elements and the circuit carrier is increased, and the connection strength between the array of the light-emitting elements and the circuit carrier is also improved. The plurality of concave portions and the convex portions have a regular shape or an irregular shape, and the surface roughness (Ra) is between 0.5 and 5 μm. An advantage of using the isotropic conductive paste as the filling material is that the distance between the first metal layer 260' and the second metal layer 262', i.e., the first distance S3 as shown in Fig. 4B, may be less than 25 microns. Fig. 6B is a schematic view showing a single light-emitting element 300d' in the light-emitting element array 32' shown in Fig. 6A. The filling material 680 and the patterned surface of the first metal layer 260' and the second metal layer 262' can also be applied to the embodiments as shown in FIGS. 5A-5C, thereby forming a structure as shown in FIG. 6B. . The filling material 680 is filled in the gap between the light-emitting element 300d' and the circuit carrier 23 to improve the connection strength between the two and to provide a current path between the circuit carrier and the light-emitting element. The filling material 680 includes an anisotropic conductive film (ACF) having a current in a vertical path between the light emitting element 300d' and the circuit carrier 23 and parallel between the light emitting element 300d' and the circuit carrier 23. The ability to insulate current in the lateral path of light-emitting element 300d' or circuit carrier. The filling material 680 is applied to the circuit carrier 23 before connecting the array of light emitting elements to the circuit carrier 23. In one embodiment, neither the first metal layer 260' nor the second metal layer 262' contact the metal contacts 22 of the circuit carrier 23. Filler material 680 is positioned between first metal layer 260', second metal layer 262' and metal contact 22 to conduct current between first metal layer 260', second metal layer 262', and metal contact 22. The first metal layer 260' and the second metal layer 262' are patterned so that there are a plurality of recesses and protrusions on the surface facing the metal contacts 22. Therefore, the contact area between the light-emitting element and the circuit carrier is increased, and the connection strength between the light-emitting element and the circuit carrier is also improved. The plurality of concave portions and the convex portions have a regular shape or an irregular shape, and the surface roughness (Ra) is between 0.5 and 5 μm. Similarly, the filling material 680 and the patterned surface of the first metal layer 260' and the second metal layer 262' can also be applied to the above-described embodiment as shown in FIG. 5E to form a structure as shown in FIG. 6C. . [58] Referring to FIGS. 7A to 7G, there are cross-sectional views corresponding to various stages of the flow of a method for fabricating a light-emitting device according to an embodiment of the present invention, wherein steps 7A and 7D and structure and 2A are used. The embodiment shown in FIG. 2D and the related disclosure are similar, and the steps and structures of FIGS. 7F to 7G are similar to the embodiments shown in FIGS. 3E to 3F and related disclosures, and are different. Wherein, as shown in FIG. 7C, the dielectric layers 240a, 240b, 240c, and 280 are a photoresist, such as a positive photoresist or a negative photoresist; as shown in FIGS. 7D to 7E, After forming the metal layers 260a, 260b, 260c and forming the metal layers 262a, 262b, 262c, the fabrication method further comprises removing the dielectric layers 240a, 240b, 240c, 280, thereby forming a void in two adjacent light-emitting elements. Between and between the metal layers of the single light-emitting element; as shown in FIGS. 7F to 7G, after the substrate 21 is removed, the two adjacent light-emitting elements are separated from each other by the gap, and the manufacturing method is further Including roughening the exposed surface of the first conductive layer 102 to form a thick Surface 102a, roughening methods described above, will be omitted here. In one embodiment, in order to form a chip-scale red, green and blue light-emitting element for display or illumination, a method of fabricating a first wavelength conversion layer on the light-emitting element 300b is selectively applied. 294, as shown in FIG. 7G, converts light emitted by the light-emitting element 300b into a first converted light. Further, a second wavelength conversion layer 296 can be selectively coated on the light-emitting element 300c to convert the light emitted by the light-emitting element 300c into a second converted light. The light-emitting element 300a is not coated with any wavelength converting material to directly emit blue light from the roughened surface 102a of the light-emitting element 300a. The formation manner and material of each conversion layer are as described above, and will not be described herein. 7H is a plan view of a red, green and blue light-emitting element unit of a grain level according to an embodiment of the present invention, including a red, green and blue light-emitting element group as shown in FIG. 7G, and a first width of the red-green-blue light-emitting element unit 37. S1, the first length S2, the second length d2, the first distance S3, the second distance S4, the second width d1, and the third distance S5 are as described in the embodiment shown in FIG. 4B and related disclosures. No longer, the difference is that the light-emitting layer 101 is not surrounded by the dielectric layer 240a and the opaque layer 290. After forming the first wavelength conversion layer 294 and the second wavelength conversion layer 296, the dicing step is directly performed without directly coating the transparent encapsulation material 24 of the foregoing embodiment to directly cut the circuit carrier 23 without cutting light. The element array 32 forms a plurality of grain-level red, green and blue light-emitting element units. Referring to FIGS. 7I and 7J, there are a cross-sectional view and a plan view of a light-emitting element unit 37 including a single-level light-emitting element after the dicing step. The first length S1, the first width S6, the second width d1, the second length d2, the first distance S3, and the second distance S4 of the grain-level light-emitting element unit 37 are as shown in the embodiment of FIG. 5B and related disclosure The details are not described here. The difference is that the sidewalls of the light-emitting layer 101, the first metal layer 260, and the second metal layer 262 do not have the dielectric layer 240a and the opaque layer 290; There is no transparent encapsulation material 24 on the wavelength conversion layer 298. Referring to FIG. 8A, a display module 76 according to an embodiment of the present invention includes a plurality of die-level red, green and blue light-emitting element units 65 on a second circuit carrier 73. For example, any two adjacent grain-level red, green, and blue light-emitting element units 65 are separated from each other by a pitch or seamlessly disposed to bring them into contact with each other. The second circuit carrier 73 includes a circuit 72 electrically connected to the respective light-emitting elements of the red-green-blue light-emitting element unit 65, thereby independently controlling the blue, red and green light-emitting elements in each of the red-green-blue light-emitting element units 65. . In one embodiment, the display module 76 includes M columns and N rows of grain level red, green and blue light emitting element units 65 for a display having X*Y pixel resolution, where M/N = 1/1 , 3/2, 4/3 or 16/9, X=a*M, Y=b*N, and both a and b are positive integers equal to or greater than 2. The display module 76 includes more than 500 red, green and blue light emitting element units 65 in an area of one square inch. That is, display module 76 includes more than 1500 light-emitting stacks 101 in an area of one square inch. In another embodiment, each of the die-level red, green, and blue light emitting element units includes a plurality of red, green, and blue light emitting element groups, and each group includes a blue light emitting element and a red light emitting element as previously described. And a green light-emitting element. The plurality of red, green and blue light-emitting elements are arranged in an I*J array in a grain-level red, green and blue light-emitting element unit, wherein I and J are positive integers, and at least one of I and J is greater than one. The ratio of I to J is preferably close to or equal to 1/1, 3/2, 4/3 or 16/9. In a grain-level red, green and blue light-emitting element unit, the distance between two adjacent light-emitting stacks respectively from two adjacent red-green-blue light-emitting element groups is substantially equal to respectively from two adjacent The distance between two adjacent light-emitting stacks of the grain-level red, green and blue light-emitting element units. The display module 76 includes M columns and N rows of grain level red, green and blue light emitting element units 65 for a display having X*Y pixel resolution, where M /N = 1/1, 3/2, 4 /3 or 16/9, X=a*M*I, Y=b*N*J, and both a and b are positive integers equal to or greater than 2. The display module 76 contains more than 500 red, green and blue light-emitting component groups in an area of one square inch. That is, display module 76 includes more than 1500 light-emitting stacks 101 in an area of one square inch. Each of the red, green and blue light emitting element units and the red, green and blue light emitting element units can be independently driven by the circuit formed on the circuit carrier 23 and the second circuit carrier 73. The material of the second circuit carrier 73 is also FR-4, BT (Bismaleimide-Triazine) resin, ceramic or glass. Figure 8B is a schematic illustration of a lighting module 78 in accordance with an embodiment of the present invention. The lighting module 78 includes a plurality of grain level light emitting element units 66 on the second circuit carrier 73. Depending on the applied driving voltage, the chip level light emitting element units 66 can be connected in series or in parallel by circuitry on the second circuit carrier 73. In one embodiment, the illumination module 78 is disposed within the bulb 80 as shown in FIG. The light bulb 80 further includes an optical lens 82 covering the illumination module 78, a connection surface and the illumination module 78 is a heat dissipation groove 85 on the connection surface, a connection portion 87 connected to the heat dissipation groove 85, and a connection portion. An electrical connector 88 that is coupled to and electrically coupled to the lighting module 78. The embodiment described above is only for explaining the technical idea and the features of the present invention, and the object of the present invention is to enable those skilled in the art to understand the contents of the present invention and implement it according to the present invention. The scope of the patent, i.e., the equivalent variations or modifications made by the spirit of the invention, should be covered by the scope of the invention.

【61】100、200a、200b、與200c‧‧‧發光結構
【62】11、21‧‧‧基材
【63】102‧‧‧第一導電層
【64】104‧‧‧活性層
【65】106‧‧‧第二導電層
【66】107a、107b‧‧‧電極或接合墊
【67】120‧‧‧保護層
【68】122‧‧‧第一介電層
【69】140、240‧‧‧第二介電層
【70】222a、222b、222c、240a、240b、240c、280‧‧‧介電層
【71】160、260a、260b、260c、162、262a、262b、262c‧‧‧金屬層
【72】20、30、32、32’‧‧‧發光元件陣列
【73】21‧‧‧基材
【74】22‧‧‧錫料
【75】13、23‧‧‧電路載板
【76】24‧‧‧透明封裝材料
【77】25‧‧‧發光元件封裝
【78】10、10a、10b、10c、20a、20b、20c、300、300a、300b、300c、300d、300a’、300b’、300c’、300d’‧‧‧發光元件
【79】102a‧‧‧表面
【80】101‧‧‧發光疊層
【81】221‧‧‧反射層
【82】260、260’‧‧‧第一金屬層
【83】262、262’‧‧‧第二金屬層
【84】290‧‧‧不透光層
【86】22a‧‧‧導電通道
【87】294‧‧‧第一波長轉換層
【88】296‧‧‧第二波長轉換層
【89】35、36、36’、65、66、37‧‧‧紅綠藍發光元件單元
【90】S1、S6’‧‧‧第一寬度
【91】S2‧‧‧第一長度
【92】d1、d1’‧‧‧第二寬度
【93】d2‧‧‧第二長度
【94】S3、S3’‧‧‧第一距離
【95】S4‧‧‧第二距離
【96】S5‧‧‧第三距離
【97】298‧‧‧波長轉換層
【98】S1‧‧‧第一長度
【99】S6‧‧‧第一寬度
【100】680‧‧‧填充材料
【101】76‧‧‧顯示模組
【102】73‧‧‧第二電路載板
【103】72‧‧‧電路
【104】78‧‧‧照明模組
【105】80‧‧‧燈泡
【106】82‧‧‧光學透鏡
【107】85‧‧‧散熱槽
【108】87‧‧‧連結部
【109】88‧‧‧電連接器
[61] 100, 200a, 200b, and 200c‧‧ ‧ luminescent structure [62] 11, 21 ‧ ‧ substrate [63] 102 ‧ ‧ first conductive layer [64] 104 ‧ ‧ active layer [65] 106‧‧‧Second conductive layer [66]107a, 107b‧‧‧electrode or bonding pad [67]120‧‧‧Protective layer [68]122‧‧‧First dielectric layer [69]140, 240‧ ‧Second dielectric layer [70] 222a, 222b, 222c, 240a, 240b, 240c, 280‧‧ dielectric layer [71] 160, 260a, 260b, 260c, 162, 262a, 262b, 262c‧ ‧ metal Layer [72] 20, 30, 32, 32'‧‧‧ illuminating element array [73] 21‧‧‧ substrate [74] 22‧‧‧ tin material [75] 13, 23‧‧‧ circuit carrier board [76 】24‧‧‧Transparent encapsulation material [77]25‧‧‧Light-emitting device package [78]10, 10a, 10b, 10c, 20a, 20b, 20c, 300, 300a, 300b, 300c, 300d, 300a', 300b' , 300c', 300d'‧‧ ‧ illuminating elements [79] 102a ‧ ‧ surface [80] 101 ‧ ‧ luminous stacking [81] 221 ‧ ‧ reflective layer [82] 260, 260' ‧ ‧ first Metal layer [83] 262, 262'‧‧‧ second metal [84] 290‧‧‧ opaque layer [86] 22a‧‧‧ Conductive channel [87] 294‧‧‧ first wavelength conversion layer [88] 296‧‧‧ second wavelength conversion layer [89] 35, 36 , 36', 65, 66, 37‧‧‧ red, green and blue light-emitting element units [90] S1, S6'‧‧‧ first width [91] S2‧‧‧ first length [92] d1, d1'‧‧ ‧Second width [93]d2‧‧‧Second length [94]S3, S3'‧‧‧First distance [95]S4‧‧‧Second distance [96]S5‧‧‧ Third distance [97] 298‧‧‧wavelength conversion layer [98]S1‧‧‧first length [99]S6‧‧‧first width [100]680‧‧‧filling material [101]76‧‧‧ display module [102]73 ‧‧‧Second circuit carrier [103]72‧‧‧Circuit [104]78‧‧‧Lighting module [105]80‧‧‧Light bulb [106]82‧‧‧ Optical lens [107]85‧‧‧ Heat sink [108]87‧‧‧Connecting Department [109]88‧‧‧Electrical connector

【8】 第1A圖至第1D圖係為依照本發明實施例之發光二極體製作方法的示意圖; 【9】 第1E圖係為本發明實施例之發光二極體之應用示意圖; 【10】 第2A圖至第2D圖係為依照本發明實施例之發光二極體陣列製作方法的示意圖; 【11】 第2E圖係為依照本發明實施例之發光二極體陣列與電路板連結之示意圖; 【12】 第2F圖係為依照本發明實施例之發光二極體陣列之封裝示意圖; 【13】 第3A圖至第3G圖係為依照本發明實施例之發光裝置的製作方法流程各階段所對應之剖面圖; 【14】 第4A圖係為如第3F圖所示之發光元件陣列以覆晶的形式與電路載板連接的俯視圖; 【15】 第4B圖係為依照本發明實施例之晶粒級的紅綠藍發光元件單元包含如第3G圖所示之紅綠藍發光元件群組之俯視圖; 【16】 第5A圖係為依照本發明實施例之發光元件陣列以覆晶的形式與電路載板連接的俯視圖; 【17】 第5B圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之俯視圖; 【18】 第5C圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之剖面圖; 【19】 第5D圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之俯視圖; 【20】 第5E圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之剖面圖; 【21】 第6A圖係為依照本發明實施例之晶粒級的紅綠藍發光元件單元的剖面圖 【22】 第6B圖係為第6A圖所示之發光元件陣列中的單顆發光元件之示意圖; 【23】 第6C圖係為依照本發明實施例之發光元件陣列中的單顆發光元件之示意圖; 【24】 第7A圖至第7G圖係為依照本發明實施例之一種發光裝置的製作方法流程各階段所對應之剖面圖; 【25】 第7H圖係為依照本發明實施例之晶粒級的紅綠藍發光元件單元包含如圖7G所示之紅綠藍發光元件群組之俯視圖; 【26】 第7I圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之剖面圖; 【27】 第7J圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之俯視圖; 【28】 第8A圖係為依照本發明實施例之顯示模組之示意圖; 【29】 第8B圖係為依照本發明實施例之顯示模組之示意圖;以及 【30】 第9圖係為依照本發明實施例之燈泡元件分解圖。[8] FIG. 1A to FIG. 1D are schematic diagrams showing a method for fabricating a light-emitting diode according to an embodiment of the present invention; [9] FIG. 1E is a schematic diagram of application of a light-emitting diode according to an embodiment of the present invention; 2A to 2D are schematic diagrams showing a method for fabricating an LED array according to an embodiment of the invention; [11] FIG. 2E is a diagram of an LED array and a circuit board according to an embodiment of the invention. FIG. 2F is a schematic diagram of a package of a light emitting diode array according to an embodiment of the present invention; [13] FIGS. 3A to 3G are flowcharts showing a method for fabricating a light emitting device according to an embodiment of the present invention. A cross-sectional view corresponding to the stage; [14] FIG. 4A is a plan view of the light-emitting element array as shown in FIG. 3F connected to the circuit carrier in a flip chip form; [15] FIG. 4B is a diagram in accordance with the present invention. A grain-level red, green and blue light-emitting element unit comprises a top view of a red-green-blue light-emitting element group as shown in FIG. 3G; [16] FIG. 5A is a light-emitting element array in accordance with an embodiment of the present invention for flip chip Form connected to the circuit board FIG. 5B is a plan view of a light-emitting element unit of a grain level of a single light-emitting element according to an embodiment of the present invention; [18] FIG. 5C is a crystal of a single light-emitting element according to an embodiment of the present invention. A cross-sectional view of a light-emitting element unit of a granular level; [19] FIG. 5D is a plan view of a light-emitting element unit of a grain level of a single light-emitting element according to an embodiment of the present invention; [20] FIG. 5E is a diagram in accordance with the present invention. FIG. 6A is a cross-sectional view of a grain-level red, green and blue light-emitting element unit according to an embodiment of the invention [22] FIG. 6B A schematic diagram of a single light-emitting element in the array of light-emitting elements shown in FIG. 6A; [23] FIG. 6C is a schematic diagram of a single light-emitting element in an array of light-emitting elements according to an embodiment of the invention; [24] 7A to 7G are cross-sectional views corresponding to various stages of the manufacturing method of a light-emitting device according to an embodiment of the present invention; [25] FIG. 7H is a red, green and blue grain level according to an embodiment of the present invention. hair The optical element unit includes a top view of a group of red, green and blue light-emitting elements as shown in FIG. 7G; [26] FIG. 7I is a cross-sectional view of a light-emitting element unit of a grain level of a single light-emitting element according to an embodiment of the present invention; 27] FIG. 7J is a plan view of a light-emitting element unit of a grain level of a single light-emitting element according to an embodiment of the present invention; [28] FIG. 8A is a schematic view of a display module according to an embodiment of the present invention; [29] Figure 8B is a schematic view of a display module in accordance with an embodiment of the present invention; and [30] Figure 9 is an exploded view of a light bulb component in accordance with an embodiment of the present invention.

32‧‧‧發光元件陣列 32‧‧‧Lighting element array

300a、300b、300c‧‧‧發光元件 300a, 300b, 300c‧‧‧Lighting elements

102a‧‧‧表面 102a‧‧‧ surface

240a‧‧‧介電層 240a‧‧‧ dielectric layer

290‧‧‧不透光層 290‧‧‧ opaque layer

294‧‧‧第一波長轉換層 294‧‧‧First wavelength conversion layer

296‧‧‧第二波長轉換層 296‧‧‧second wavelength conversion layer

23‧‧‧電路載板 23‧‧‧Circuit carrier board

22a‧‧‧導電通道 22a‧‧‧ conductive path

22‧‧‧金屬接觸 22‧‧‧Metal contact

102‧‧‧第一導電層 102‧‧‧First conductive layer

24‧‧‧透明封裝材料 24‧‧‧Transparent packaging materials

Claims (20)

一種發光裝置的製作方法,包含步驟: 提供一第一載板,其具有複數第一金屬接觸; 提供一基材; 形成複數發光疊層以及複數溝槽於該基材上,其中該等發光疊層藉由該等溝槽與彼此分離; 連接該等發光疊層與該第一載板; 形成一封裝材料共同地位於該等發光疊層上;以及 切割該第一載板以及該封裝材料以形成複數晶粒級的發光元件單元。A method of fabricating a light-emitting device, comprising the steps of: providing a first carrier having a plurality of first metal contacts; providing a substrate; forming a plurality of light-emitting layers and a plurality of grooves on the substrate, wherein the light-emitting stack The layers are separated from each other by the trenches; the light emitting laminates are connected to the first carrier; a packaging material is formed on the light emitting laminates; and the first carrier and the packaging material are cut A plurality of light-emitting element units of a plurality of grain levels are formed. 如請求項1所述之方法,於該形成該封裝材料之前,其更包含移除該基材。The method of claim 1, further comprising removing the substrate prior to forming the encapsulating material. 如請求項1所述之方法,其更包含於該等發光疊層上形成複數金屬層以與該等第一金屬接觸連接。The method of claim 1, further comprising forming a plurality of metal layers on the light-emitting stack to be in contact with the first metal. 如請求項1所述之方法,其更包含形成一不透光層於該等溝槽中且環繞該等發光疊層,藉以避免相鄰的發光疊層發出的光互相影響或串擾(crosstalk)。The method of claim 1, further comprising forming an opaque layer in the trenches and surrounding the light emitting stacks to avoid mutual influence or crosstalk of light emitted by adjacent light emitting stacks. . 如請求項1所述之方法,其更包含形成一第一波長轉換層於一第一發光疊層上,該第一波長轉換層將該第一發光疊層發出的光轉換為一第一光,其中該第一發光疊層為該等發光疊層之其中之一。The method of claim 1, further comprising forming a first wavelength conversion layer on a first light-emitting layer, the first wavelength conversion layer converting the light emitted by the first light-emitting layer into a first light Wherein the first luminescent laminate is one of the luminescent laminates. 如請求項5所述之方法,其更包含形成一第二波長轉換層於一第二發光疊層上,該第二波長轉換層將該第二發光疊層發出的光轉換為一第二光,其中該第二發光疊層為該等發光疊層之其中之一。The method of claim 5, further comprising forming a second wavelength conversion layer on a second light-emitting layer, the second wavelength conversion layer converting the light emitted by the second light-emitting layer into a second light Wherein the second light emitting laminate is one of the light emitting laminates. 如請求項6所述之方法,其中該等發光疊層包含一第三發光疊層,該第三發光疊層之上方並未有任何波長轉換材料,其中該第一發光疊層、該第二發光疊層以及該第三發光疊層發出的光為藍光,該第一光為綠光且該第二光為紅光。The method of claim 6, wherein the light-emitting laminate comprises a third light-emitting layer, the wavelength-free material is not above the third light-emitting layer, wherein the first light-emitting layer, the second layer The light emitted by the light-emitting layer and the third light-emitting layer is blue light, the first light is green light and the second light is red light. 如請求項1所述之方法,其更包含形成一不透光層於該等溝槽中,其中該封裝材料是位於該等溝槽以及該不透光層之上。The method of claim 1, further comprising forming an opaque layer in the trenches, wherein the encapsulating material is over the trenches and the opaque layer. 如請求項6所述之方法,其更包含形成一介電層於該等溝槽中且於該不透光層以及該等發光疊層之間。The method of claim 6 further comprising forming a dielectric layer in the trenches between the opaque layer and the luminescent stacks. 如請求項3所述之方法,其更包含圖案化該等金屬層以使該等金屬層的表面形成粗化表面。The method of claim 3, further comprising patterning the metal layers such that the surfaces of the metal layers form a roughened surface. 如請求項1所述之方法,於該連接該等發光疊層與該第一載板之後,其更包含移除該基材以暴露該等發光疊層之一曝露表面以及包含粗化該等發光疊層之該曝露表面。The method of claim 1, after the connecting the light-emitting laminate and the first carrier, further comprising removing the substrate to expose an exposed surface of the light-emitting laminates and including roughening the same The exposed surface of the luminescent stack. 如請求項1所述之方法,其更包含形成一反射層於該等發光疊層以及該第一載板之間。The method of claim 1, further comprising forming a reflective layer between the light emitting stacks and the first carrier. 如請求項1所述之方法,於該連接該等發光疊層與該第一載板之該等第一金屬接觸之前,其更包含形成一填充材料,該填充材料實質上是形成於該第一載板之一表面的上方。The method of claim 1, before the connecting the light-emitting laminates to the first metal of the first carrier, further comprising forming a filling material, wherein the filling material is substantially formed in the first Above the surface of one of the plates. 如請求項13所述之方法,其中該填充材料是導電的,且該等發光疊層是藉由該填充材料與該第一載板電性連接。The method of claim 13, wherein the filling material is electrically conductive, and the light emitting laminates are electrically connected to the first carrier by the filling material. 如請求項1所述之方法,其中該等第一金屬接觸自該第一載板之一頂面延伸至該第一載板之底面。The method of claim 1, wherein the first metal contacts extend from a top surface of the first carrier to a bottom surface of the first carrier. 如請求項1所述之方法,其更包含提供一具有複數第二金屬接觸的第二載板,以及連接該等晶粒級的發光元件單元與該第二載板的該等第二金屬接觸。The method of claim 1, further comprising providing a second carrier having a plurality of second metal contacts, and contacting the light-emitting component units connecting the die levels with the second metal of the second carrier . 如請求項1所述之方法,其中該等發光疊層是以一小於25微米的間距彼此分離。The method of claim 1, wherein the light-emitting laminates are separated from one another by a pitch of less than 25 microns. 如請求項1所述之方法,其中該等晶粒級的發光元件單元的其中之一具有一小於0.36平方毫米(mm2 )的面積。The method of claim 1, wherein one of the grain level light emitting element units has an area of less than 0.36 square millimeters (mm 2 ). 如請求項1所述之方法,其中該等晶粒級的發光元件單元的其中之一包含單個發光疊層,且該晶粒級的發光元件單元的面積與該單個發光疊層的面積之比例是等於或是大於9。The method of claim 1, wherein one of the light-emitting element units of the grain level comprises a single light-emitting stack, and an area of the area of the light-emitting element unit of the grain level is proportional to an area of the single light-emitting layer Is equal to or greater than 9. 如請求項1所述之方法,其中該等晶粒級的發光元件單元的其中之一包含複數發光疊層,且該晶粒級的發光元件單元的面積與該等發光疊層之總面積的比例是小於2。The method of claim 1, wherein one of the light-emitting element units of the grain level comprises a plurality of light-emitting laminates, and an area of the light-emitting element units of the grain level and a total area of the light-emitting laminates The ratio is less than 2.
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