TW201513350A - MOSFET in three-dimensional structure and manufacturing method thereof - Google Patents

Abstract

One of the subjects to be solved by the present invention is to provide a fundamental electronic element which may substantially achieve the element performance based on the dimensional design even with extremely small dimensions and an integrated semiconductor device composed by integration of the fundamental electronic elements. The solution of the present invention relates to a MOSFET in three-dimensional structure, which comprises a channel area with a plurality of different crystalline surfaces, a gate electrode disposed facing the plurality of crystalline surfaces of the channel area, a gate insulation film disposed between the gate electrode and the channel area, and a first and a second silicide area disposed facing the current direction flowing through the channel area and separated from the channel area.

Description

Three-dimensional structure MOSFET and manufacturing method thereof

The present invention relates to a three-dimensional structure MOSFET and a method of fabricating the same.

The development history of semiconductor devices such as IC (collective circuit) and LSI (large-scale collective circuit) has progressed almost due to miniaturization and high integration.

One of the constituent elements of the semiconductor device, for example, the size of a basic electronic component such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (especially the gate length) is reduced as a whole, and the miniaturization of the basic electronic component is in accordance with the so-called ratio. The evolution of the law of the law. Moreover, the maintenance of the high performance due to the ratio can also be achieved.

However, every time the micro-generation of basic electronic components moves forward, various problems arise. Although there are solutions to this problem, on the one hand, the original characteristics of basic electrons are ensured, and on the other hand, micro-leveling is improved to improve integration. The two-dimensional structure (planar structure) of the basic electronic component and the two-dimensional array are perceived as limits.

Recently, the multi-layered three-dimensional discharge structure by the multilayer wiring technique has been used to further improve the degree of integration, or the basic electronic components such as the three-dimensional structure of the FinFET have been used, thereby preventing the deterioration of the characteristics of the micro-reduced components and further achieving the fineness. Chemicalization, high integration, and high performance.

On the other hand, if the basic electronic component of the transistor, for example in the case of a MOS transistor, the electrical contact with the source, the drain region and the corresponding electrode is ideally an ohmic contact. Therefore, the technique of deuteration is generally employed.

In the case of a basic electronic component of a FinFET, the structure of the source and drain regions is composed of a polycrystalline face and is composed of a plurality of different crystal faces. Although electrodes are attached to each of the different crystal faces, a telluride region is provided between the electrodes and the source and drain regions. In each of the different crystallized telluride regions, the resistance of the path of the current flowing through the electrode, the germanide region, the source region, and the electrode, the germanide region, and the drain region is minimized to increase the formed transistor The goal of the characteristics.

In the case where the size of the basic electronic component is as large as the current size, the resistance of the current path does not have to care about the problem of the process, but as the integration of the miniaturization increases, the size of the basic electronic component is reduced, and the current is The resistance problem of the path is obvious.

The resistance of the current path is roughly divided into the contact resistance between the electrode and the germanide region, the germanide region and the source region, and the drain region, and the internal resistance of the germanide region and the source region and the drain region.

In the case of using a germanium wafer or an SOI substrate on a semiconductor substrate In the source and drain regions, for example, impurities such as boron (B) or phosphorus (P) are formed at a high concentration to form a high concentration region of the Si layer, and the germanide region is the high concentration region and appropriate. The metal produces a region formed by the oximation reaction.

Reducing the internal resistance of the source region and the drain region is accomplished by appropriately selecting the material of the impurity to be infiltrated and optimizing the amount of the dopant. Reducing the contact resistance is achieved by selecting the appropriate metal and appropriate deuteration treatment.

This device design protocol is also applicable to a semiconductor device including a basic electronic component group having a source region and a drain region, which is composed of a plurality of different crystal faces of a FinFET.

Moreover, up to now, even in the case of a basic electronic component having a source region or a drain region formed of a plurality of different crystal faces such as a FinFET, a source region and a drain region are formed on one crystal face. In the case of the basic electronic component of the two-dimensional structure, the telluride region is not formed in the same manner as the crystal face.

However, as a result of intensive research by the inventors of the present invention, if the size of the basic electronic component is a certain level or less, the crystal surface dependency in the telluride region is conspicuous, and the basic electronic component is increased in refinement, and the crystal plane dependency is obtained. With the improvement, the miniaturization is further improved, and it is known that the performance of basic electronic components is improved in the conventional method as described above or its extended method. In order to obtain high performance of a highly integrated semiconductor device including a plurality of basic electronic components, it is difficult to obtain high performance.

One of the problems to be solved by the present invention is to provide a basic electronic component which is designed according to the size even if the size is smaller, and which has essentially the component performance and an integrated semiconductor device which is integrated with the basic electronic component.

Another object of the present invention is to provide a basic electronic component which can be designed according to the size even if the size is smaller, and a method of manufacturing the integrated semiconductor device including the basic electronic component.

Still another object of the present invention is to provide a basic electronic component having a structure of a source region and a drain region composed of a plurality of different crystal faces, and an integrated semiconductor device including the basic electronic component.

These problems are achieved by forming a telluride region in the most appropriate component arrangement.

One aspect of the three-dimensional structure MOS-FET of the present invention is characterized in that: a channel region having a plurality of different crystal faces, a gate electrode provided to face a plurality of crystal faces of the channel region, and a gate electrode are provided a gate insulating film between the gate electrode and the channel region, and first and second germanium regions disposed in a direction facing a current flowing through the channel region and interposed between the channel regions ("the present invention" The first 3-dimensional structure of MOS- FET").

Another aspect of the three-dimensional structure MOS-FET of the present invention is characterized in that the MOS-FET of the first three-dimensional structure is characterized by a high concentration region having semiconductor impurities between the germanide region and the channel region ( The "second three-dimensional structure MOS-FET" of the present invention).

Hereinafter, in the present invention, the term "semiconductor device" means both or both of the basic electronic component and the integrated semiconductor device including the basic electronic component.

According to the present invention, one of the problems to be solved is to provide a basic electronic component which is designed according to the size even if the size is smaller, and which has essentially the component performance and an integrated semiconductor device which is integrated with the basic electronic component.

Other features and advantages of the present invention will be apparent from the description and appended claims. In the drawings, the same or similar components are denoted by the same reference numerals.

100‧‧‧FET

101‧‧‧矽 substrate

102‧‧‧BOX layer

201‧‧‧SOI layer area

202‧‧‧ source area

203‧‧‧Bungee area

204‧‧‧ Telluride area

205‧‧‧ source electrode

206‧‧‧汲electrode

207‧‧‧ gate insulating film area

208‧‧‧ gate electrode layer area

209‧‧‧ side wall

400‧‧‧ base

401‧‧‧SOI layer

402‧‧‧SOI layer area a

403‧‧‧ gate insulating film area a

404‧‧‧gate electrode layer

405‧‧‧Source area layer

406‧‧ ‧ bungee zone

407‧‧‧Top wall

501‧‧‧Source area layer a

502‧‧ ‧ bungee zone a

503‧‧‧Metal layer for telluride formation

504‧‧‧Metal layer for connection formation

The accompanying drawings, which are incorporated in the claims

Fig. 1 is a schematic perspective view showing one of typical examples of the three-dimensional structure MOSFET 100 of the present invention.

Fig. 2 is a schematic cross-sectional view taken along line AA shown in Fig. 1.

Fig. 3 is a schematic cross-sectional view taken along line BB shown in Fig. 2.

Fig. 4 is a schematic view showing the first mode of the project before the construction example of the specific example of the MOS-FET of the three-dimensional structure of the present invention.

Fig. 5 is a schematic view showing the second mode of the project after the engineering example of the specific example of the MOS-FET of the three-dimensional structure of the present invention.

Hereinafter, the present invention will be specifically described, but the present invention is not limited to the examples.

One of the typical examples of the three-dimensional structure MOSFET 100 of the present invention is shown in Figs. 1, 2, and 3. Fig. 1 is a perspective view of a mode, Fig. 2 is a schematic cross-sectional view taken along line AA shown in Fig. 1, and Fig. 3 is a schematic cross-sectional view taken along line BB of Fig. 2.

The MOSFET 100 is an SOI layer region 201 in which a channel region (not shown) is formed, and an outer germanide of the SOI layer region 201, and a source region (n ⁺ region) 202 and a drain region (n ⁺ region) 203 are respectively provided. .

A gate insulating film region 207 and a gate electrode layer region 208 are provided on the upper surface of the SOI layer region 201, respectively.

Telluride regions 204a and 204b are provided on the respective outer sides of the source region 202 and the drain region 203, respectively.

A source electrode 205 is provided in the telluride region 204a in a state of direct electrical contact, and a drain electrode 206 is provided in the drain region 204b.

Each of the gate insulating film region 207 and the gate electrode layer region 208 is not only the upper surface of the SOI layer region 201 but also extends in a flow direction of current flowing in a channel region formed in the SOI layer region 201. The side of the aforementioned SOI layer region 201. That is, each of the foregoing gate insulating film regions 207 and the gate electrode layer region 208 is disposed to surround the SOI layer region 201 in the SOI layer region along a current flowing direction flowing through the SOI layer region 201. Three of the outside of 201.

The telluride regions 204a and 204b are respectively disposed on the side faces of the SOI layer region 201 in a state of being electrically in direct contact with two sides perpendicular or slightly perpendicular to a flow direction of a current flowing through the SOI layer region 201. The entire area of the side corresponding to the middle or the entire area.

Thus, the channel region formed in the SOI layer region 201 can be formed in the approximate or substantially entire region of the SOI layer region 201 by providing the germanide regions 204a and 204b.

[Example 1]

Fig. 4 is a view showing the first mode of the previous stage of the engineering example of the specific example of the MOS-FET of the three-dimensional structure of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 5 is a schematic explanatory view showing a second mode of engineering of the latter stage. Fig. 4 is a view for explaining the process until the formation of the telluride region 204, and Fig. 5 is mainly for explaining the process of forming the germanide region 204.

First, a base 400 for forming a three-dimensional structure MOS-FET of the present invention is prepared, and an SOI layer 401 is formed thereon ("Project (4a)" in Fig. 4). The base 400 is constituted by a ruthenium substrate 101 and a BOX layer 102 provided thereon.

Next, the removed portion of the SOI layer 401 is etched by dry etching or the like to form an SOI layer region a402 ("Project (4b)" in Fig. 4).

Then, the gate insulating film region a403 is formed on the SOI layer region a402 by an insulating material such as SiO ₂ by film formation by sputtering or general patterning. The gate electrode layer 404 is formed thereon by using Poly-Si or the like ("Project (4c)" in Fig. 4).

Then, photoresist coating, pattern exposure, etching, cleaning, or the like is performed to perform patterning, thereby forming a gate insulating film region 207 and a gate electrode layer region 208 ("Project (4d)" in Fig. 4).

In the source and drain formation regions of the SOI layer region a402, impurities such as boron (B) are ion-implanted at a high concentration to form a source region layer 405 and a drain region layer 406 of a high concentration n ⁺ region (fourth) Figure "Project (4e)").

Next, an insulating material such as SiO _{2 is} deposited by a sputtering method or the like, and then anisotropic etching is performed by a dry etching method to form side walls 209a and 209b and an upper surface 407 as shown in the figure (Fig. 4 "Engineering ( 4f)").

Then, leaving the width portions of the sidewalls 209a and 209b, removing the unnecessary portions of the source region layer 405 and the drain region layer 406 by etching, respectively forming the source region layer a501 and the drain region layer a502 (Fig. 5) Engineering (5g)").

In the work (5h) of Fig. 5, the metal layer 503 for forming a telluride is provided by a vapor deposition method as shown in the figure.

Then, heat treatment is performed to form the telluride regions 204a and 204b in the respective interface regions of the metal layer 503 and the source region layer a501 and the drain region layer a502 ("engineering (5i)" in Fig. 5). At the same time, a source region 202 and a drain region 203 are formed, respectively. In the work (5i) of Fig. 5, the entire region of the source region layer a501 and the drain region layer a502 may be mashed.

Next, the unnecessary portion of the metal layer 503 for forming a telluride is removed ("engineering (5j)" in Fig. 5).

Then, a metal for forming an electrical connection is formed by vapor deposition, a metal layer 504 for forming a connection is formed, and then a portion of the metal layer 504 is removed by patterning to form a source electrode 205 and a drain electrode 206 (5th) Figure "Project (5k), (5l)"). At the same time, the upper wall 407 can also be removed as needed.

The outline of the production conditions of the main projects using the above-described production method will be described below.

(1) Formation of side wall 209

‧ Film type: 矽 nitride film

‧ film formation method: sputtering CVD

‧ Film formation conditions

Microwave power: 2000W

Pressure: 13mTorr

Workbench (for base setting) Temperature: 400 °C

Gas flow

Ar gas: 20sccm

N ₂ gas: 75sccm

H ₂ gas: 15sccm

SiH ₄ gas: 0.5sccm

(2) removing the unnecessary portions of the n ⁺ region layers 405, 406 by dry etching using the sidewall 209 as a mask

The side wall surface after etching is a (100) plane.

Dry etching conditions / Ar: 160 sccm, HBr: 270 sccm, 0.67 Pa (5 mTorr), RF power: 30 W

(3) Film formation of metal (Er) layer 503 for telluride formation

Er sputtering film formation conditions / Ar: 20sccm, 0.67Pa (5mTorr), side wall (100) surface is 5nm

(4) Deuteration

Lamp annealing conditions / 600 ° C, 2 min

(5) Removal of unreacted metal layer domain

SPM (H ₂ SO ₄ : H ₂ O ₂ = 4:1) 30 sec

(6) Formation of a metal (tungsten: W) layer 504 for connection formation

W sputtering film formation conditions / Ar: 20sccm, 1.33Pa (10mTorr), film thickness: 100nm

(7) Dry etching removes unnecessary portions of the metal (tungsten: W) layer 504 for connection formation

Dry etching conditions of W/Ar: 100 sccm, SF ₆ : 20 sccm, 1.33 Pa (10 mTorr), RF power: 30 W

The present invention is not limited to the embodiments described above, and various changes and modifications may be made without departing from the spirit and scope of the invention.

101‧‧‧矽 substrate

102‧‧‧BOX layer

201‧‧‧SOI layer area

202‧‧‧ source area

203‧‧‧Bungee area

204a, 204b‧‧‧ Telluride area

205‧‧‧ source electrode

206‧‧‧汲electrode

207‧‧‧ gate insulating film area

208‧‧‧ gate electrode layer area

209a, 209b‧‧‧ side wall

Claims (2)

A MOS-FET having a three-dimensional structure, comprising: a channel region having a plurality of different crystal faces; a gate electrode provided to face a plurality of crystal faces of the channel region; and the gate electrode and the foregoing a gate insulating film between the channel regions, and first and second germanide regions disposed to face the direction of current flowing through the channel region and interposed between the channel regions. A three-dimensional structure MOS-FET according to claim 1, wherein a high concentration region of semiconductor impurities is provided between the germanide region and the channel region.