WO2014009990A1 - Mosfet having 3d-structure and manufacturing method for same - Google Patents

Mosfet having 3d-structure and manufacturing method for same Download PDF

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WO2014009990A1
WO2014009990A1 PCT/JP2012/004427 JP2012004427W WO2014009990A1 WO 2014009990 A1 WO2014009990 A1 WO 2014009990A1 JP 2012004427 W JP2012004427 W JP 2012004427W WO 2014009990 A1 WO2014009990 A1 WO 2014009990A1
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region
channel region
layer
basic electronic
silicide
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PCT/JP2012/004427
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Japanese (ja)
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智之 諏訪
田中　宏明
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国立大学法人東北大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to a MOSFET having a three-dimensional structure and a manufacturing method thereof.
  • MOSFETs Metal Oxide Semiconductors Field Effects Transistors
  • miniaturization is achieved while securing the original characteristics of basic electronic elements.
  • the limit has begun to appear in the two-dimensional structure (planar structure) and two-dimensional arrangement of basic electronic elements.
  • the degree of integration has been further increased by adopting a three-dimensional array structure by multilayering by multilayer wiring technology, or by the use of a three-dimensional basic electronic device represented by FinFET, which has led to a reduction in device characteristics. Further miniaturization, higher integration, and higher performance are being attempted through prevention.
  • the electrical contact between the source / drain region and each corresponding electrode is an ohmic contact.
  • a silicidation technique is generally employed.
  • the structure of the source / drain region is a polycrystal structure, and is composed of a plurality of different crystal faces.
  • An electrode is attached to each of the different crystal planes, and a silicide region is provided between the electrode and the source / drain region.
  • the silicide regions provided on each of the different crystal planes serve to reduce the electric resistance of the current path flowing through the electrode / silicide region / source region and the electrode / silicide region / drain region as much as possible and enhance the characteristics of the formed transistor. Bear.
  • the electric resistance of the current path does not have to be considered as a problem, but the degree of integration is improved by miniaturization.
  • the size of the basic electronic device decreases and the size of the basic electronic device decreases, the problem of the electrical resistance of the current path has become apparent.
  • the electric resistance of the current path is roughly classified into contact resistance between the electrode and the silicide region, between the silicide region and the source region / drain region, and internal resistance of the silicide region, source region / drain region.
  • the source / drain regions are high concentration regions formed by doping impurities such as boron (B) or phosphorus (P) in the Si layer at a high concentration.
  • the silicide region is a region formed by silicidation reaction between this high concentration region and an appropriate metal.
  • the internal resistance of the source region / drain region is reduced by optimizing the doping amount by appropriately selecting the material of the impurity to be doped.
  • the reduction in contact resistance is achieved by proper metal selection and proper silicidation.
  • This element design protocol has also been applied to the case of a semiconductor device composed of a basic electronic element group having a source region and a drain region composed of a plurality of different crystal planes such as FinFET.
  • the source / drain regions are formed on one crystal plane.
  • the silicide region is uniformly formed regardless of the crystal plane.
  • the conventional method as described above or a method that is an extension of the conventional method improves the performance of the basic electronic element, such as a highly integrated semiconductor device configured by integrating a large number of basic electronic elements. We obtained the knowledge that it is difficult to achieve high performance.
  • One of the problems to be solved by the present invention is to provide a basic electronic element having essential element performance based on the size design even when the size is smaller, and an integrated semiconductor device configured by integrating the basic electronic elements. Is to provide.
  • Another object of the present invention is to provide a basic electronic element having essential element performance based on the size design even when the size is further reduced, and a method of manufacturing an integrated semiconductor device configured by integrating the basic electronic elements. That is.
  • Still another object of the present invention is to provide a basic electronic device having a structure having a source region and a drain region composed of a plurality of different crystal planes, and an integrated semiconductor device configured by integrating the basic electronic devices. That is.
  • MOS-FET of the present invention includes a channel region having a plurality of different crystal planes, a gate electrode provided facing the plurality of crystal planes of the channel region, and the gate electrode And a gate insulating film provided between the channel region, and first and second silicide regions provided so as to face the channel region in a direction in which current flows and sandwich the channel region. (“First three-dimensional MOS-FET” of the present invention).
  • Another aspect of the three-dimensional structure MOS-FET of the present invention is that the first three-dimensional structure MOS-FET has a high concentration region of semiconductor impurities between the silicide region and the channel region. Characteristic (“second three-dimensional structure MOS-FET" of the present invention).
  • semiconductor device means either or both of the basic electronic element and the integrated semiconductor device formed by integrating the basic electronic element. It shall be.
  • the present invention it is possible to obtain a basic electronic element having essential element performance based on the size design even if the size is further reduced, and an integrated semiconductor device configured by integrating the basic electronic elements.
  • FIG. 1 is a schematic perspective view showing one of typical examples of a MOSFET 100 having a three-dimensional structure according to the present invention.
  • FIG. 2 is a schematic cross-sectional view taken along line AA shown in FIG.
  • FIG. 3 is a schematic cross-sectional view taken along line BB shown in FIG.
  • FIG. 4 is a first schematic process schematic explanatory view showing a pre-process of a process example of a specific manufacturing method of one example of the three-dimensional structure MOS-FET of the present invention.
  • FIG. 5 is a second schematic process schematic explanatory view showing a post-process of a process example of a specific manufacturing method of one example of the three-dimensional structure MOS-FET of the present invention.
  • FIGS. 1, 2 and 3 show one of typical examples of the MOSFET 100 having a three-dimensional structure according to the present invention.
  • FIG. 1 is a schematic perspective view
  • FIG. 2 is a schematic sectional view taken along line AA shown in FIG. 1
  • FIG. 3 is a schematic sectional view taken along line BB shown in FIG.
  • the MOSFET 100 includes an SOI layer region 201 in which a channel region (not shown) is formed, and a source region (n + region) 202 and a drain region (n + region) 203 on the outer side of the SOI layer region 201, respectively. Is provided.
  • a gate insulating film region 207 and a gate electrode layer region 208 are provided on the upper surface of the SOI layer region 201, respectively.
  • Silicide regions 204a and 204b are provided outside the source region 202 and the drain region 203, respectively.
  • the source electrode 205 is provided in the silicide region 204a and the drain electrode 206 is provided in direct contact with the silicide region 204b.
  • Each of the gate insulating film region 207 and the gate electrode layer region 208 includes not only the upper surface of the SOI layer region 201 but also the SOI layer along the flow direction of the current flowing in the channel region formed in the SOI layer region 201. It also extends to the side surface of the region 201. That is, each of the gate insulating film region 207 and the gate electrode layer region 208 includes the SOI layer region on three surfaces of the outer surface of the SOI layer region 201 along the flow direction of the current flowing in the SOI layer region 201. It is provided so as to surround 201.
  • the silicide regions 204a and 204b are side surfaces of the SOI layer region 201, and correspond to two side surfaces that are perpendicular or substantially perpendicular to the flow direction of the current flowing in the SOI layer region 201. It is provided in a state of being in direct electrical contact with the entire side surface or substantially the entire region.
  • a channel region formed in the SOI layer region 201 can be formed substantially or substantially in the entire region of the SOI layer region 201.
  • FIG. 4 is a first schematic process schematic explanatory diagram showing a pre-process of a process example of a specific manufacturing method of one example of a three-dimensional structure MOS-FET of the present invention
  • FIG. 5 is a second schematic process showing a post-process. It is a typical process schematic explanatory drawing.
  • FIG. 4 illustrates a process before the formation of the silicide region 204
  • FIG. 5 mainly illustrates a process of forming the silicide region 204.
  • a substrate 400 for forming a three-dimensional structure MOS-FET of the present invention is prepared, and an SOI layer 401 is formed thereon (“Step (4a)” in FIG. 4).
  • the base 400 includes a silicon substrate 101 and a BOX layer 102 provided thereon.
  • step (4b) the removed portion of the SOI layer 401 is etched by dry etching or the like to form an SOI layer region a402 (“step (4b)” in FIG. 4).
  • a gate insulating film region a403 is formed of an insulating material such as SiO 2 on the SOI layer region a402 by film formation by sputtering and normal patterning.
  • a gate electrode layer 404 is formed thereon using Poly-Si or the like (“Step (4c)” in FIG. 4).
  • step (4d) in FIG. 4).
  • Impurities such as boron (B) are ion-implanted at a high concentration in the source / drain formation region of the SOI layer region a402, thereby forming a source region layer 405 and a drain region layer 406 which are high-concentration n + regions.
  • Step (4e) in FIG. 4).
  • anisotropic etching is performed by a dry etching method to form side walls 209a and 209b and an upper surface wall 407 as shown in FIG. “Step (4f)”).
  • a metal layer 503 for forming a silicide is provided by an evaporation method as illustrated.
  • Step (5i) heat treatment is performed to form silicide regions 204a and 204b in respective interface regions between the metal layer 503, the source region layer a501 and the drain region layer a502 (“Step (5i)” in FIG. 5).
  • a source region 202 and a drain region 203 are formed.
  • the entire region of the source region layer a501 and the drain region layer a502 may be silicided.
  • Step (5j) unnecessary portions of the metal layer 503 for forming the silicide are removed (“Step (5j)” in FIG. 5).
  • a metal for electrical contact formation is deposited to form a metal layer 504 for contact formation, and then unnecessary portions of the metal layer 504 are removed by patterning to form a source electrode 205 and a drain electrode 206.
  • Step (5k), (5l) in FIG. 5
  • the top wall 407 may be removed as necessary.

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Abstract

One of the problems to be solved by the present invention is the provision of a basic electronic element that, even when the element size is reduced, exhibits intrinsic essential element performance that is commensurate to the element design, and an integrated semiconductor device that is configured by integrating the basic electronic element. The solution provided by the present invention is a MOS-FET having a 3D structure, the MOS-FET being provided with: a channel region that includes a plurality of different crystalline surfaces; a gate electrode that is provided facing the plurality of crystalline surfaces of the channel region; a gate insulating film that is provided between the gate electrode and the channel region; and first and second silicide regions that are provided facing each other in the direction of the flow of the channel region current so as to sandwich the channel region therebetween.

Description

３次元構造のＭＯＳＦＥＴ及びその製造方法MOSFET having three-dimensional structure and manufacturing method thereof
　本発明は、３次元構造のＭＯＳＦＥＴ及びその製造方法に関するものである。 The present invention relates to a MOSFET having a three-dimensional structure and a manufacturing method thereof.
　ＩＣ（集積回路）やＬＳＩ（大規模集積回路）のような半導体装置の開発の歴史の殆どは、微細化と高集積化によって進展してきた。 Most of the development history of semiconductor devices such as IC (Integrated Circuit) and LSI (Large Scale Integrated Circuit) has progressed with miniaturization and higher integration.
　半導体装置の構成要素の一つである、例えばＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）のような基本電子素子の寸法（特にゲート長）は縮小の一途を辿り、所謂、スケーリング則に沿う形で基本電子素子の微細化が進められてきている。しかも、スケーリングによる高性能化の維持も図られていている。 The dimensions (especially the gate length) of basic electronic elements such as MOSFETs (Metal Oxide Semiconductors Field Effects Transistors), one of the components of semiconductor devices, are steadily shrinking, and are based on the so-called scaling law. Electronic devices have been miniaturized. In addition, high performance is maintained by scaling.
　しかし、基本電子素子の微細化の世代が進むごとに種々の課題が生じ、その都度、解決策が施されてきているが、基本電子素子の本来の特性を確保しながら微細化を図って集積度を高めるのに基本電子素子の２次元構造（プレナー構造）・２次元配列では、その限界が見え始めてきている。 However, every time the generation of miniaturization of basic electronic elements progresses, various problems arise, and solutions are being taken each time. However, miniaturization is achieved while securing the original characteristics of basic electronic elements. In order to increase the degree, the limit has begun to appear in the two-dimensional structure (planar structure) and two-dimensional arrangement of basic electronic elements.
　最近は、多層配線技術による多層化による３次元配列構造の採用で集積度を更に高め、或いは、ＦｉｎＦＥＴに代表されるような立体構造の基本電子素子の採用で、微細化による素子の特性低下の阻止を図ってより一層の微細化・高集積化・高性能化が図られようとしている。 Recently, the degree of integration has been further increased by adopting a three-dimensional array structure by multilayering by multilayer wiring technology, or by the use of a three-dimensional basic electronic device represented by FinFET, which has led to a reduction in device characteristics. Further miniaturization, higher integration, and higher performance are being attempted through prevention.
　他方、トランジスタのような基本電子素子、例えばＭＯＳトランジスタの場合でいえば、ソース・ドレイン領域と対応の各電極との間の電気的接触がオーミックコンタクトであることが理想とされる。そのために、一般的にはシリサイド化の技術が採用されている。 On the other hand, in the case of a basic electronic element such as a transistor, for example, a MOS transistor, it is ideal that the electrical contact between the source / drain region and each corresponding electrode is an ohmic contact. For this purpose, a silicidation technique is generally employed.
　ＦｉｎＦＥＴのような基本電子素子の場合、ソース・ドレイン領域の構造は、多結晶面構成であり、複数の異なる結晶面で構成されたものとされている。この異なる結晶面のそれぞれに電極が付設されるが、この電極とソース・ドレイン領域との間にはシリサイド領域が設けられる。異なる結晶面のそれぞれにおいて設けられるシリサイド領域は、電極・シリサイド領域・ソース領域及び電極・シリサイド領域・ドレイン領域を流れる電流のパスの電気抵抗をできるだけ小さくし、形成されるトランジスタの特性を高める役目を担う。 In the case of a basic electronic device such as a FinFET, the structure of the source / drain region is a polycrystal structure, and is composed of a plurality of different crystal faces. An electrode is attached to each of the different crystal planes, and a silicide region is provided between the electrode and the source / drain region. The silicide regions provided on each of the different crystal planes serve to reduce the electric resistance of the current path flowing through the electrode / silicide region / source region and the electrode / silicide region / drain region as much as possible and enhance the characteristics of the formed transistor. Bear.
　基本電子素子のサイズがこれまでのようにある程度の大きさを有している場合は、前記の電流のパスの電気抵抗はそれ程問題視される必要はなかったが、微細化による集積度の向上が高まり、基本電子素子のサイズが小さくなるにつれ、前記の電流のパスの電気抵抗の問題が顕在化してきた。 When the basic electronic device has a certain size as before, the electric resistance of the current path does not have to be considered as a problem, but the degree of integration is improved by miniaturization. As the size of the basic electronic device decreases and the size of the basic electronic device decreases, the problem of the electrical resistance of the current path has become apparent.
　電流パスの電気抵抗は、電極とシリサイド領域の間、シリサイド領域とソース領域・ドレイン領域との間の接触抵抗と、シリサイド領域及びソース領域・ドレイン領域の内部抵抗とに大別される。 The electric resistance of the current path is roughly classified into contact resistance between the electrode and the silicide region, between the silicide region and the source region / drain region, and internal resistance of the silicide region, source region / drain region.
　半導体基板にシリコンウェハー若しくはＳＯＩ基板を利用する場合、ソース・ドレイン領域は、例えばボロン（Ｂ）若しくはリン（Ｐ）などの不純物をＳｉ層に高濃度にドープして形成された高濃度領域であり、シリサイド領域は、この高濃度領域と適当な金属とをシリサイド化反応させて形成した領域である。 When a silicon wafer or SOI substrate is used as the semiconductor substrate, the source / drain regions are high concentration regions formed by doping impurities such as boron (B) or phosphorus (P) in the Si layer at a high concentration. The silicide region is a region formed by silicidation reaction between this high concentration region and an appropriate metal.
　ソース領域・ドレイン領域の内部抵抗の低減は、ドープする不純物の材料選択を適切にしてそのドープ量を最適化することでなされる。接触抵抗の低減は、金属の適切な選択と適切なシリサイド化処理によって実現される。 The internal resistance of the source region / drain region is reduced by optimizing the doping amount by appropriately selecting the material of the impurity to be doped. The reduction in contact resistance is achieved by proper metal selection and proper silicidation.
　この素子設計プロトコールは、ＦｉｎＦＥＴのような複数の異なる結晶面で構成されているソース領域・ドレイン領域を有する基本電子素子群で構成されている半導体装置の場合にも適用されてきている。 This element design protocol has also been applied to the case of a semiconductor device composed of a basic electronic element group having a source region and a drain region composed of a plurality of different crystal planes such as FinFET.
　しかも、これまでは、ＦｉｎＦＥＴのような複数の異なる結晶面で構成されているソース領域・ドレイン領域を有する基本電子素子の場合であっても、ソース領域・ドレイン領域が一つの結晶面に形成されている２次元構造の基本電子素子の場合と同様に、結晶面によらず一様にシリサイド領域を形成していた。 In addition, until now, even in the case of a basic electronic device having source / drain regions composed of a plurality of different crystal planes such as FinFET, the source / drain regions are formed on one crystal plane. As in the case of the basic electronic device having a two-dimensional structure, the silicide region is uniformly formed regardless of the crystal plane.
　しかしながら、本発明者等が鋭意研究した結果、基本電子素子のサイズがある程度以下になるとシリサイド領域には結晶面依存性が顕在化し、基本電子素子の微細化が高まるに連れその結晶面依存性も高まり、微細化をより高めるには上記のような従来法若しくはその延長にある方法では、基本電子素子の性能向上、如いては多数の基本電子素子を集積して構成する高集積化半導体装置の高性能化を図ることが難しいという知見を得た。 However, as a result of diligent research by the present inventors, when the size of the basic electronic device becomes below a certain level, the crystal surface dependency becomes obvious in the silicide region, and the crystal surface dependency also increases as the miniaturization of the basic electronic device increases. In order to further increase the miniaturization, the conventional method as described above or a method that is an extension of the conventional method improves the performance of the basic electronic element, such as a highly integrated semiconductor device configured by integrating a large number of basic electronic elements. We obtained the knowledge that it is difficult to achieve high performance.
　本発明の解決しようとする課題の一つは、サイズがより小さくなってもそのサイズ設計に基づく本質的素子性能を有する基本電子素子及びその基本電子素子を集積して構成した集積化半導体装置を提供することである。 One of the problems to be solved by the present invention is to provide a basic electronic element having essential element performance based on the size design even when the size is smaller, and an integrated semiconductor device configured by integrating the basic electronic elements. Is to provide.
　本発明の他の課題は、サイズがより小さくなってもそのサイズ設計に基づく本質的素子性能を有する基本電子素子及びその基本電子素子を集積して構成する集積化半導体装置の製造法を提供することである。 Another object of the present invention is to provide a basic electronic element having essential element performance based on the size design even when the size is further reduced, and a method of manufacturing an integrated semiconductor device configured by integrating the basic electronic elements. That is.
　本発明の更にもう一つの課題は、複数の異なる結晶面で構成されているソース領域・ドレイン領域を有する構造の基本電子素子及びその基本電子素子を集積して構成した集積化半導体装置を提供することである。 Still another object of the present invention is to provide a basic electronic device having a structure having a source region and a drain region composed of a plurality of different crystal planes, and an integrated semiconductor device configured by integrating the basic electronic devices. That is.
　これらの課題は、最適な素子配置にシリサイド領域を形成することによって達成される。 These problems are achieved by forming a silicide region in an optimum element arrangement.
　本発明の３次元構造のＭＯＳ－ＦＥＴの一つの側面は、異なる複数の結晶面を有するチャネル領域と、該チャネル領域の複数の結晶面に対面して設けられているゲート電極と、該ゲート電極と前記チャネル領域の間に設けてあるゲート絶縁膜と、前記チャネル領域の電流を流す方向に対面し該チャネル領域を挟むように設けられた第一、第二のシリサイド領域と、を備えたことを特徴とする（本発明の「第一の３次元構造のＭＯＳ－ＦＥＴ」）。 One aspect of the three-dimensional structure MOS-FET of the present invention includes a channel region having a plurality of different crystal planes, a gate electrode provided facing the plurality of crystal planes of the channel region, and the gate electrode And a gate insulating film provided between the channel region, and first and second silicide regions provided so as to face the channel region in a direction in which current flows and sandwich the channel region. (“First three-dimensional MOS-FET” of the present invention).
　本発明の３次元構造のＭＯＳ－ＦＥＴのもう一つの側面は、前記第一の３次元構造のＭＯＳ－ＦＥＴにおいて、前記シリサイド領域と前記チャネル領域の間に半導体不純物の高濃度領域を有することを特徴とする（本発明の「第二の３次元構造のＭＯＳ－ＦＥＴ」）。 Another aspect of the three-dimensional structure MOS-FET of the present invention is that the first three-dimensional structure MOS-FET has a high concentration region of semiconductor impurities between the silicide region and the channel region. Characteristic ("second three-dimensional structure MOS-FET" of the present invention).
　以後、本願においては、特別に断ることなければ、「半導体装置」の語は、上記の基本電子素子及びその基本電子素子を集積して構成した集積化半導体装置の両者若しくは何れか一つを意味するものとする。 Hereinafter, unless otherwise specified, in this application, the term “semiconductor device” means either or both of the basic electronic element and the integrated semiconductor device formed by integrating the basic electronic element. It shall be.
　本発明によれば、サイズがより小さくなってもそのサイズ設計に基づく本質的素子性能を有する基本電子素子及びその基本電子素子を集積して構成した集積化半導体装置を得ることができる。 According to the present invention, it is possible to obtain a basic electronic element having essential element performance based on the size design even if the size is further reduced, and an integrated semiconductor device configured by integrating the basic electronic elements.
　本発明のその他の特徴及び利点は、添付図面を参照とした以下の説明により明らかになるであろう。なお、添付図面においては、同じ若しくは同様の構成には、同じ参照番号を付す。 Other features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings. In the accompanying drawings, the same or similar components are denoted by the same reference numerals.
　添付図面は明細書に含まれ、その一部を構成し、本発明の実施の形態を示し、その記述と共に本発明の原理を説明するために用いられる。
図１は、本発明の３次元構造のＭＯＳＦＥＴ１００の典型例の一つを示す模式的斜視図である。 図２は、図１に示す線ＡＡでの模式的切断面図である。 図３は、図２に示す線ＢＢでの模式的切断面図である。 図４は、本発明の３次元構造のＭＯＳ－ＦＥＴの一つの例の具体的製法の工程例の前工程を示す第一の模式的工程概略説明図である。 図５は、本発明の３次元構造のＭＯＳ－ＦＥＴの一つの例の具体的製法の工程例の後工程を示す第二の模式的工程概略説明図である。 The accompanying drawings are included in the specification, constitute a part thereof, show an embodiment of the present invention, and are used to explain the principle of the present invention together with the description.
FIG. 1 is a schematic perspective view showing one of typical examples of a MOSFET 100 having a three-dimensional structure according to the present invention. FIG. 2 is a schematic cross-sectional view taken along line AA shown in FIG. FIG. 3 is a schematic cross-sectional view taken along line BB shown in FIG. FIG. 4 is a first schematic process schematic explanatory view showing a pre-process of a process example of a specific manufacturing method of one example of the three-dimensional structure MOS-FET of the present invention. FIG. 5 is a second schematic process schematic explanatory view showing a post-process of a process example of a specific manufacturing method of one example of the three-dimensional structure MOS-FET of the present invention.
　以下、本発明を具体的に説明するが、本発明はそれらの例に限定されるものでない。 Hereinafter, the present invention will be specifically described, but the present invention is not limited to these examples.
　図１，２，３に本発明の３次元構造のＭＯＳＦＥＴ１００の典型例の一つが示される。図１は、その模式的斜視図、図２は、図１に示す線ＡＡでの模式的切断面図、図３は、図２に示す線ＢＢでの模式的切断面図である。 FIGS. 1, 2 and 3 show one of typical examples of the MOSFET 100 having a three-dimensional structure according to the present invention. FIG. 1 is a schematic perspective view, FIG. 2 is a schematic sectional view taken along line AA shown in FIG. 1, and FIG. 3 is a schematic sectional view taken along line BB shown in FIG.
　ＭＯＳＦＥＴ１００は、チャネル領域（図示されてない）が形成されるＳＯＩ層領域２０１、該ＳＯＩ層領域２０１の外側サイドには、ソース領域（ｎ＋領域）２０２、ドレイン領域（ｎ＋領域）２０３がそれぞれ設けられている。 The MOSFET 100 includes an SOI layer region 201 in which a channel region (not shown) is formed, and a source region (n + region) 202 and a drain region (n + region) 203 on the outer side of the SOI layer region 201, respectively. Is provided.
　前記ＳＯＩ層領域２０１の上面にはゲート絶縁膜領域２０７、ゲート電極層領域２０８がそれぞれ設けられている。 A gate insulating film region 207 and a gate electrode layer region 208 are provided on the upper surface of the SOI layer region 201, respectively.
　前記ソース領域２０２、前記ドレイン領域２０３の外側のそれぞれには、シリサイド領域２０４ａ，２０４ｂがそれぞれ設けてある。 Silicide regions 204a and 204b are provided outside the source region 202 and the drain region 203, respectively.
　前記シリサイド領域２０４ａには、ソース電極２０５が、前記シリサイド領域２０４ｂには、ドレイン電極２０６が、それぞれ電気的に直接接触する状態に設けてある。 The source electrode 205 is provided in the silicide region 204a and the drain electrode 206 is provided in direct contact with the silicide region 204b.
　前記ゲート絶縁膜領域２０７、前記ゲート電極層領域２０８のそれぞれは、前記ＳＯＩ層領域２０１の上面だけでなく前記ＳＯＩ層領域２０１に形成されるチャネル領域内を流れる電流の流れ方向に沿う前記ＳＯＩ層領域２０１の側面にも延在して設けてある。即ち、前記ゲート絶縁膜領域２０７、前記ゲート電極層領域２０８のそれぞれは、前記ＳＯＩ層領域２０１内を流れる電流の流れ方向に沿う前記ＳＯＩ層領域２０１の外面の中の３面に前記ＳＯＩ層領域２０１を囲うように設けられている。 Each of the gate insulating film region 207 and the gate electrode layer region 208 includes not only the upper surface of the SOI layer region 201 but also the SOI layer along the flow direction of the current flowing in the channel region formed in the SOI layer region 201. It also extends to the side surface of the region 201. That is, each of the gate insulating film region 207 and the gate electrode layer region 208 includes the SOI layer region on three surfaces of the outer surface of the SOI layer region 201 along the flow direction of the current flowing in the SOI layer region 201. It is provided so as to surround 201.
　前記シリサイド領域２０４ａ，２０４ｂは、それぞれ、前記ＳＯＩ層領域２０１の側面であって、前記ＳＯＩ層領域２０１内を流れる電流の流れ方向に対して垂直乃至は略垂直な２つの側面の中の対応する側面の全域若しくは実質上の全域に、電気的に直接接触する状態で設けられてある。 The silicide regions 204a and 204b are side surfaces of the SOI layer region 201, and correspond to two side surfaces that are perpendicular or substantially perpendicular to the flow direction of the current flowing in the SOI layer region 201. It is provided in a state of being in direct electrical contact with the entire side surface or substantially the entire region.
　このように前記シリサイド領域２０４ａ，２０４ｂを設けることにより、前記ＳＯＩ層領域２０１に形成されるチャネル領域を前記ＳＯＩ層領域２０１の略あるいは実質上の全域に形成することが出来る。 As described above, by providing the silicide regions 204a and 204b, a channel region formed in the SOI layer region 201 can be formed substantially or substantially in the entire region of the SOI layer region 201.
　図４は、本発明の３次元構造のＭＯＳ－ＦＥＴの一つの例の具体的製法の工程例の前工程を示す第一の模式的工程概略説明図、図５は、その後工程を示す第二の模式的工程概略説明図である。図４には、シリサイド領域２０４を形成する前までの工程を、図５は、主にシリサイド領域２０４を形成する工程を説明するものである。 FIG. 4 is a first schematic process schematic explanatory diagram showing a pre-process of a process example of a specific manufacturing method of one example of a three-dimensional structure MOS-FET of the present invention, and FIG. 5 is a second schematic process showing a post-process. It is a typical process schematic explanatory drawing. FIG. 4 illustrates a process before the formation of the silicide region 204, and FIG. 5 mainly illustrates a process of forming the silicide region 204.
　先ず、本発明の３次元構造のＭＯＳ－ＦＥＴを形成するための基体４００を用意し、その上にＳＯＩ層４０１を形成する（図４の「工程（４ａ）」）。基体４００は、シリコン基板１０１とその上に設けたＢＯＸ層１０２とで構成されている。 First, a substrate 400 for forming a three-dimensional structure MOS-FET of the present invention is prepared, and an SOI layer 401 is formed thereon (“Step (4a)” in FIG. 4). The base 400 includes a silicon substrate 101 and a BOX layer 102 provided thereon.
　次いで、ドライエッチングなどでＳＯＩ層４０１の除去部分をエッチングしＳＯＩ層領域ａ４０２を形成する（図４の「工程（４ｂ）」）。 Next, the removed portion of the SOI layer 401 is etched by dry etching or the like to form an SOI layer region a402 (“step (4b)” in FIG. 4).
　その後、スパッター法での成膜、通常のパターニングにより前記ＳＯＩ層領域ａ４０２上にＳｉＯ２などの絶縁材料でゲート絶縁膜領域ａ４０３を形成する。その上にＰｏｌｙ－Ｓｉなどでゲート電極層４０４を形成する（図４の「工程（４ｃ）」）。 Thereafter, a gate insulating film region a403 is formed of an insulating material such as SiO 2 on the SOI layer region a402 by film formation by sputtering and normal patterning. A gate electrode layer 404 is formed thereon using Poly-Si or the like (“Step (4c)” in FIG. 4).
　その後、レジスト塗布、パターン露光、エッチング、洗浄などを施すことでパターニングして、ゲート絶縁膜領域２０７、ゲート電極層領域２０８を形成する（図４の「工程（４ｄ）」）。 Then, patterning is performed by applying resist, pattern exposure, etching, cleaning, and the like, thereby forming the gate insulating film region 207 and the gate electrode layer region 208 (“step (4d)” in FIG. 4).
　ＳＯＩ層領域ａ４０２のソース・ドレインの形成領域に、ボロン（Ｂ）などの不純物を高濃度にイオン注入することで、高濃度のｎ＋領域であるソース領域層４０５、ドレイン領域層４０６を形成する（図４の「工程（４ｅ）」）。 Impurities such as boron (B) are ion-implanted at a high concentration in the source / drain formation region of the SOI layer region a402, thereby forming a source region layer 405 and a drain region layer 406 which are high-concentration n + regions. ("Step (4e)" in FIG. 4).
　次に、ＳｉＯ２などの絶縁材料をスパッター法などで堆積させた後、ドライエッチング法で異方性エッチングし、サイドウォール２０９ａ、２０９ｂ、上面ウォール４０７をそれぞれ図示のように形成する（図４の「工程（４ｆ）」）。 Next, after depositing an insulating material such as SiO 2 by a sputtering method or the like, anisotropic etching is performed by a dry etching method to form side walls 209a and 209b and an upper surface wall 407 as shown in FIG. “Step (4f)”).
　その後、サイドウォール２０９ａ、２０９ｂの幅分を残してソース領域層４０５、ドレイン領域層４０６の不要部分をエッチングにより除去し、ソース領域層ａ５０１、ドレイン領域層ａ５０２をそれぞれ形成する（図５の「工程（５ｇ）」）。 After that, unnecessary portions of the source region layer 405 and the drain region layer 406 are removed by etching, leaving the width of the sidewalls 209a and 209b, thereby forming the source region layer a501 and the drain region layer a502 (see “Step” in FIG. 5). (5g) ").
　図５の工程（５ｈ）においては、シリサイド形成用の金属層５０３を蒸着法により図示のごとく設ける。 In the step (5h) of FIG. 5, a metal layer 503 for forming a silicide is provided by an evaporation method as illustrated.
　その後、熱処理して、金属層５０３とソース領域層ａ５０１およびドレイン領域層ａ５０２との各界面領域にシリサイド領域２０４ａ，２０４ｂをそれぞれ形成する（図５の「工程（５ｉ）」）。同時に、ソース領域２０２、ドレイン領域２０３がそれぞれ形成される。図５の工程（５ｉ）においては、ソース領域層ａ５０１およびドレイン領域層ａ５０２の全領域をシリサイド化しても良い。 Thereafter, heat treatment is performed to form silicide regions 204a and 204b in respective interface regions between the metal layer 503, the source region layer a501 and the drain region layer a502 (“Step (5i)” in FIG. 5). At the same time, a source region 202 and a drain region 203 are formed. In step (5i) of FIG. 5, the entire region of the source region layer a501 and the drain region layer a502 may be silicided.
　次いで、シリサイド形成用の金属層５０３の不要な部分を除去する（図５の「工程（５ｊ）」）。 Next, unnecessary portions of the metal layer 503 for forming the silicide are removed (“Step (5j)” in FIG. 5).
　その後、電気的コンタクト形成用の金属を蒸着してコンタクト形成用の金属層５０４を形成し、次いで、パターニングにより金属層５０４の不要な部分を除去して、ソース電極２０５、ドレイン電極２０６を形成する（図５の「工程（５ｋ），（５ｌ）」）。同時に、上面ウォール４０７を必要に応じて除去しても良い。 Thereafter, a metal for electrical contact formation is deposited to form a metal layer 504 for contact formation, and then unnecessary portions of the metal layer 504 are removed by patterning to form a source electrode 205 and a drain electrode 206. ("Step (5k), (5l)" in FIG. 5). At the same time, the top wall 407 may be removed as necessary.
　以下に上記製法における主だった工程での製法条件の概略を記す。 The following outlines the manufacturing conditions in the main steps of the above manufacturing method.
（１）　サイドウォール２０９の形成
・膜種：シリコン窒化膜
・成膜方法：プラズマＣＶＤ
・成膜条件
　　マイクロ波パワー：２０００Ｗ
　　圧力：１３ mTorr
　　ステージ（基体設置用）温度：４００℃
　　ガス流量
　　　　Ａｒガス：２０ sccm
　　　　Ｎ２ガス：７５ sccm
　　　　Ｈ２ガス：１５ sccm
　　　　ＳｉＨ４ガス：０．５ sccm (1) Formation of sidewall 209 / film type: silicon nitride film / film formation method: plasma CVD
・ Film formation conditions Microwave power: 2000W
Pressure: 13 mTorr
Stage (for substrate installation) temperature: 400 ° C
Gas flow rate Ar gas: 20 sccm
N 2 gas: 75 sccm
H 2 gas: 15 sccm
SiH 4 gas: 0.5 sccm
（２）　サイドウォール２０９をマスクにして、ｎ＋領域層４０５，４０６の不要部分のドライエッチング除去
　　　　エッチング後の側壁面は（１００）面である。
　　　　ドライエッチング条件／Ａｒ：１６０ sccm、
　　　　　　　　　　　　　　　ＨＢｒ：２７０ sccm、
　　　　　　　　　　　　　　　０．６７Ｐａ（５ mTorr）、
　　　　　　　　　　　　　　　ＲＦパワー：３０Ｗ (2) Dry etching removal of unnecessary portions of n + region layers 405 and 406 using sidewall 209 as a mask The side wall surface after etching is a (100) plane.
Dry etching conditions / Ar: 160 sccm,
HBr: 270 sccm,
0.67 Pa (5 mTorr),
RF power: 30W
（３）　シリサイド形成用の金属（Ｅｒ）層５０３の成膜
　　　　Ｅｒスパッタ成膜条件／Ａｒ：２０ sccm、
　　　　　　　　　　　　　　　０．６７Ｐａ（５ mTorr）、
　　　　　　　　　　　　　　　側壁（１００）面に５ nm (3) Film formation of metal (Er) layer 503 for forming silicide Er sputtering film formation conditions / Ar: 20 sccm,
0.67 Pa (5 mTorr),
5 nm on the side wall (100)
（４）　シリサイド化
　　　　ランプアニール条件／６００℃、２ min (4) Silicidation Lamp annealing conditions / 600 ° C, 2 min
（５）　未反応金属層領域の除去
　　　ＳＰＭ（Ｈ２ＳＯ４：Ｈ２Ｏ２＝４：１）　３０ sec (5) Removal of unreacted metal layer region SPM (H 2 SO 4 : H 2 O 2 = 4: 1) 30 sec
（６）　コンタクト形成用の金属（タングステン：Ｗ）層５０４の形成
　　　　Ｗスパッタ成膜条件／Ａｒ：２０ sccm、
　　　　　　　　　　　　　　１．３３Ｐａ（１０ mTorr）、
　　　　　　　　　　　　　　膜厚：１００ nm (6) Formation of contact forming metal (tungsten: W) layer 504 W sputter deposition conditions / Ar: 20 sccm,
1.33 Pa (10 mTorr),
Film thickness: 100 nm
（７）　コンタクト形成用の金属（タングステン：Ｗ）層５０４の不要部分のドライエッチング除去
　　　　Ｗのドライエッチング条件／Ａｒ：１００ sccm、
　　　　　　　　　　　　　　　　　ＳＦ６：２０ sccm、
　　　　　　　　　　　　　　　　　１．３３Ｐａ（１０ mTorr）、
　　　　　　　　　　　　　　　　　ＲＦパワー：３０Ｗ (7) Dry etching removal of unnecessary portion of metal (tungsten: W) layer 504 for contact formation Dry etching conditions for W / Ar: 100 sccm,
SF 6 : 20 sccm,
1.33 Pa (10 mTorr),
RF power: 30W
　本発明は上記実施の形態に制限されるものではなく、本発明の精神及び範囲から離脱することなく、様々な変更及び変形が可能である。従って、本発明の範囲を公にするために、以下の請求項を添付する。 The present invention is not limited to the above embodiment, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, in order to make the scope of the present invention public, the following claims are attached.
　１００　　ＦＥＴ
　１０１　　シリコン基板
　１０２　　ＢＯＸ層
　２０１　　ＳＯＩ層領域
　２０２　　ソース領域
　２０３　　ドレイン領域
　２０４　　シリサイド領域
　２０５　　ソース電極
　２０６　　ドレイン電極
　２０７　　ゲート絶縁膜領域
　２０８　　ゲート電極層領域
　２０９　　サイドウォール
　４００　　基体
　４０１　　ＳＯＩ層
　４０２　　ＳＯＩ層領域ａ
　４０３　　ゲート絶縁膜領域ａ
　４０４　　ゲート電極層
　４０５　　ソース領域層
　４０６　　ドレイン領域層
　４０７　　上面ウォール
　５０１　　ソース領域層ａ
　５０２　　ドレイン領域層ａ
　５０３　　シリサイド形成用の金属層
　５０４　　コンタクト形成用の金属層 100 FET
101 Silicon substrate 102 BOX layer 201 SOI layer region 202 Source region 203 Drain region 204 Silicide region 205 Source electrode 206 Drain electrode 207 Gate insulating film region 208 Gate electrode layer region 209 Side wall 400 Base body 401 SOI layer 402 SOI layer region a
403 Gate insulating film region a
404 Gate electrode layer 405 Source region layer 406 Drain region layer 407 Upper surface wall 501 Source region layer a
502 Drain region layer a
503 Metal layer for forming silicide 504 Metal layer for forming contact

Claims (2)

  1. 　異なる複数の結晶面を有するチャネル領域と、該チャネル領域の複数の結晶面に対面して設けられているゲート電極と、該ゲート電極と前記チャネル領域の間に設けてあるゲート絶縁膜と、前記チャネル領域の電流を流す方向に対面し該チャネル領域を挟むように設けられた第一、第二のシリサイド領域と、を備えたことを特徴とする３次元構造のＭＯＳ－ＦＥＴ。 A channel region having a plurality of different crystal planes; a gate electrode provided facing the plurality of crystal planes of the channel region; a gate insulating film provided between the gate electrode and the channel region; A MOS-FET having a three-dimensional structure, comprising: first and second silicide regions facing each other in a direction in which a channel region current flows and sandwiching the channel region.
  2. 　前記シリサイド領域と前記チャネル領域の間に半導体不純物の高濃度領域を有する請求項１に記載の３次元構造のＭＯＳ－ＦＥＴ。 The MOS-FET having a three-dimensional structure according to claim 1, wherein a high concentration region of semiconductor impurities is provided between the silicide region and the channel region.
PCT/JP2012/004427 2012-07-09 2012-07-09 Mosfet having 3d-structure and manufacturing method for same WO2014009990A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02228041A (en) * 1989-03-01 1990-09-11 Agency Of Ind Science & Technol Manufacture of semiconductor device
WO2005036651A1 (en) * 2003-10-09 2005-04-21 Nec Corporation Semiconductor device and production method therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02228041A (en) * 1989-03-01 1990-09-11 Agency Of Ind Science & Technol Manufacture of semiconductor device
WO2005036651A1 (en) * 2003-10-09 2005-04-21 Nec Corporation Semiconductor device and production method therefor

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