TW201513351A - Three-dimensional structure of MOSFET and manufacturing method thereof - Google Patents

Abstract

To provide a basic electronic device having a substantially device performance and an integrated semiconductor device having the integration of the basic electronic component, which can be designed according to a specific size even if the size is extremely small. A MOSFET of a three-dimensional structure comprises a channel region having a plurality of different crystalline faces, a gate electrode facing the plurality of crystalline faces of the channel region, a gate insulating film disposed between the gate electrode and the channel region, and a first and a second silicide regions disposed in such a way that they face toward the direction of current flowing through the channel region and isolated by the channel region.

Description

Three-dimensional structure MOSFET and manufacturing method thereof

The present invention relates to a three-dimensional structure MOSFET and a method of fabricating the same.

The development history of semiconductor devices such as IC (collective circuit) and LSI (large-scale collective circuit) has progressed almost due to miniaturization and high integration.

One of the constituent elements of the semiconductor device, for example, the size of a basic electronic component such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (especially the gate length) is reduced as a whole, and the miniaturization of the basic electronic component is in accordance with the so-called ratio. The evolution of the law of the law. Moreover, the maintenance of the high performance due to the ratio can also be achieved.

However, every time the micro-generation of basic electronic components moves forward, various problems arise. Although there are solutions to this problem, on the one hand, the original characteristics of basic electronic components are ensured, and on the other hand, micro-leveling is improved to improve integration. The two-dimensional structure (planar structure) of the basic electronic component and the two-dimensional array are perceived as limits.

Recently used multi-layered 3D with multilayer wiring technology In order to further improve the degree of integration, or to use a basic electronic component such as a three-dimensional structure representing a FinFET, the resistance characteristics of the element due to the miniaturization are reduced, and further miniaturization and integration are achieved.

On the other hand, if the basic electronic component of the transistor, for example in the case of a MOS transistor, the electrical contact with the source, the drain region and the corresponding electrode is ideally an ohmic contact. Therefore, the technique of deuteration is generally employed.

Further, while further miniaturizing, it is possible to achieve a high function due to a decrease in the characteristics of the device due to miniaturization. For example, in the case of a basic electronic component of a FinFET, the structure of the source and the drain region is composed of a polycrystalline face, in plural. A different crystal face is formed. Although electrodes are attached to each of the different crystal faces, a telluride region is provided between the electrodes and the source and drain regions.

In each of the different crystallized telluride regions, the resistance of the path of the current flowing through the electrode, the germanide region, the source region, and the electrode, the germanide region, and the drain region is minimized to increase the formed transistor The goal of the characteristics.

In the case where the size of the basic electronic component is as large as the current size, the resistance of the current path does not have to care about the problem of the process, but as the integration of the miniaturization increases, the size of the basic electronic component is reduced, and the current is The resistance problem of the path is obvious.

The resistance of the current path is roughly divided into: contact resistance between the electrode and the germanide region, between the germanide region and the source region, and the drain region, and internalization of the germanide region and the source region and the drain region. Resistance.

In the case where the semiconductor substrate uses a germanium wafer or an SOI substrate, the source and drain regions are, for example, impurities such as boron (B) or phosphorus (P) are formed at a high concentration to form a high concentration region of the Si layer. The telluride region is a region formed by the high concentration region and a suitable metal to produce a ruthenium formation reaction. Reducing the internal resistance of the source region and the drain region is accomplished by appropriately selecting the material of the impurity to be infiltrated and optimizing the amount of the dopant. Reducing the contact resistance is achieved by selecting the appropriate metal and appropriate deuteration treatment.

This device design protocol is also applicable to a semiconductor device including a basic electronic component group having a source region and a drain region, which is composed of a plurality of different crystal faces of a FinFET.

Moreover, up to now, even in the case of a basic electronic component having a source region or a drain region formed of a plurality of different crystal faces such as a FinFET, a source region and a drain region are formed on one crystal face. In the case of the basic electronic component of the two-dimensional structure, the telluride region is not formed in the same manner as the crystal face.

However, as a result of intensive research by the inventors of the present invention, if the size of the basic electronic component is a certain level or less, the crystal surface dependency in the telluride region is conspicuous, and the basic electronic component is increased in refinement, and the crystal plane dependency is obtained. Also improve, the micro-refinement is improved, and it is known that In the above-described conventional method or the method of extending the same, the performance of the basic electronic component is improved, and it is difficult to obtain high performance of a highly integrated semiconductor device including a plurality of basic electronic components.

One of the problems to be solved by the present invention is to provide a basic electronic component which is designed according to the size even if the size is smaller, and which has essentially the component performance and an integrated semiconductor device which is integrated with the basic electronic component.

Another object of the present invention is to provide a basic electronic component which can be designed according to the size even if the size is smaller, and a method of manufacturing the integrated semiconductor device including the basic electronic component.

Still another object of the present invention is to provide a basic electronic component having a structure of a source region and a drain region composed of a plurality of different crystal faces, and an integrated semiconductor device including the basic electronic component.

These problems are achieved by forming the most appropriate telluride region on each crystal plane.

In one aspect of the semiconductor device of the present invention, the basic electronic component is a three-dimensional MOS-FET having electrodes and a germanide region, and having a source region formed by a plurality of different crystal faces. The structure of the polar region, the layer thickness of the germanium region of the source region and the drain region varies depending on different crystal faces (the first half of the present invention) Conductor device").

Another aspect of the semiconductor device of the present invention is characterized in that the basic electronic component is a three-dimensional MOS-FET having a channel region having a plurality of different crystal faces and a plurality of crystal faces facing the channel region. a gate electrode, a gate insulating film disposed between the gate electrode and the channel region, and first and second regions disposed to face a direction of current flowing through the channel region and interposed between the channel regions a high concentration region of semiconductor impurities, each high concentration region having a plurality of different crystal faces and a telluride region directly disposed on each crystal face, the layer thickness of the germanide region being different depending on different crystal faces (The present invention "Second semiconductor device").

Hereinafter, in the present invention, the term "semiconductor device" means both or both of the basic electronic component and the integrated semiconductor device including the basic electronic component.

According to the present invention, one of the problems to be solved is to provide a basic electronic component which is designed according to the size even if the size is smaller, and which has essentially the component performance and an integrated semiconductor device which is integrated with the basic electronic component.

Other features and advantages of the present invention will be apparent from the description and appended claims. In the drawings, the same or similar components are denoted by the same reference numerals.

100‧‧‧FET

101‧‧‧矽 substrate

102‧‧‧BOX layer

201‧‧‧SOI layer area

202‧‧‧ source area

203‧‧‧Bungee area

204‧‧‧ Telluride area

205‧‧‧ source electrode

206‧‧‧汲electrode

207‧‧‧ gate insulating film area

208‧‧‧ gate electrode layer area

209‧‧‧ side wall

400‧‧‧ base

401‧‧‧SOI layer

402‧‧‧SOI layer area a

403‧‧‧ gate insulating film area a

404‧‧‧gate electrode layer

405‧‧‧Source area layer

406‧‧ ‧ bungee zone

407‧‧‧Top wall

701‧‧‧(551)

702‧‧‧(100)

703‧‧‧Photoresist film

704‧‧‧metal layer a (metal layer for telluride formation)

705‧‧‧metal layer b (metal layer for telluride formation)

706‧‧‧Deuterated area

707‧‧‧Do not (unreacted) metal layer

708‧‧‧ Telluride area a

709‧‧‧ Telluride area

801‧‧‧(551)

802‧‧‧(100)

803‧‧‧Deuterated area

804‧‧‧ Telluride area a

805‧‧‧ Telluride area

806‧‧‧Do not (unreacted) metal layer

901‧‧‧ Telluride field

The accompanying drawings, which are incorporated in the claims

Fig. 1 is a schematic perspective view showing one of typical examples of a three-dimensional structure MOSFET of the present invention.

Fig. 2 is a schematic cross-sectional view taken along line AA shown in Fig. 1.

Fig. 3 is a schematic cross-sectional view taken along line BB shown in Fig. 2.

Fig. 4 is a schematic view showing the first mode of the project before the construction example of the specific example of the MOS-FET of the three-dimensional structure of the present invention.

Fig. 5 is a schematic view showing the second mode of the project after the engineering example of the specific example of the MOS-FET of the three-dimensional structure of the present invention.

Fig. 6 is a schematic view showing a third mode of engineering after the engineering example of a specific example of the MOS-FET of the three-dimensional structure of the present invention.

Fig. 7 is a view showing a mode for explaining one of typical examples of forming a telluride region according to the present invention.

Fig. 8 is a view showing a pattern for explaining another typical example of forming a telluride region according to the present invention.

Fig. 9 is a schematic cross-sectional view showing another typical example of the MOSFET of the three-dimensional structure of the present invention.

Hereinafter, the present invention will be specifically described, but the present invention is not limited to the examples.

One of the typical examples of the three-dimensional structure MOSFET 100 of the present invention is shown in Figs. 1, 2, and 3. Fig. 1 is a perspective view of a mode, Fig. 2 is a schematic cross-sectional view taken along line AA shown in Fig. 1, and Fig. 3 is a schematic cross-sectional view taken along line BB of Fig. 2.

The MOSFET 100 is an SOI layer region 201 in which a channel region (not shown) is formed, and an outer germanide of the SOI layer region 201, and a source region (n ⁺ region) 202 and a drain region (n ⁺ region) 203 are respectively provided. .

A gate insulating film region 207 and a gate electrode layer region 208 are provided on the upper surface of the SOI layer region 201, respectively.

Telluride regions 204a and 204b are provided on the respective outer sides of the source region 202 and the drain region 203, respectively.

A source electrode 205 is provided in the telluride region 204a in a state of direct electrical contact, and a drain electrode 206 is provided in the drain region 204b.

Each of the gate insulating film region 207 and the gate electrode layer region 208 is not only the upper surface of the SOI layer region 201 but also extends in a flow direction of current flowing in a channel region formed in the SOI layer region 201. The side of the aforementioned SOI layer region 201. That is, each of the foregoing gate insulating film regions 207 and the gate electrode layer region 208 is disposed to surround the SOI layer region 201 in the SOI layer region along a current flowing direction flowing through the SOI layer region 201. Outside of 201 Three sides in the face.

The telluride regions 204a and 204b are respectively disposed on the side faces of the SOI layer region 201 in a state of electrical direct contact between two sides perpendicular or slightly perpendicular to a flow direction of a current flowing through the SOI layer region 201. The entire area of the corresponding side or the entire area.

Thus, the channel region formed in the SOI layer region 201 can be formed in the approximate or substantially entire region of the SOI layer region 201 by providing the germanide regions 204a and 204b.

[Example 1]

Fig. 4 is a schematic view showing a first mode of the first stage of the engineering example of the specific example of the MOS-FET of the three-dimensional structure of the present invention, and Fig. 5 is a schematic view showing the second mode of the middle section engineering. The explanatory diagram, Fig. 5 is a schematic explanatory diagram showing the third mode engineering of the subsequent stage engineering. Figures 4, 5, and 6 illustrate the work up to the formation of the telluride region 204. Further, a preferred example of forming the telluride region 204 on each predetermined crystal plane is shown in Figs.

First, a base 400 for forming a three-dimensional structure MOS-FET of the present invention is prepared, and an SOI layer 401 is formed thereon ("Project (4a)" in Fig. 4). The base 400 is constituted by a ruthenium substrate 101 and a BOX layer 102 provided thereon.

Next, the removed portion of the SOI layer 401 is etched by dry etching or the like to form an SOI layer region a402 ("Project (4b)" in Fig. 4).

Then, a gate insulating film (not shown) and a gate electrode layer 404 are formed on the SOI layer region a402 by an insulating material such as SiO2 by film formation by sputtering and general patterning. The gate electrode layer 404 is made of, for example, Poly-Si or the like ("Project (5c)" in Fig. 5).

Then, photoresist coating, pattern exposure, etching, cleaning, or the like is performed to perform patterning, thereby forming a gate insulating film region 403 and a gate electrode layer region 208 ("Project (5d)" in Fig. 5).

In the source and drain formation regions of the SOI layer region a402, impurities such as boron (B) are ion-implanted at a high concentration to form a source region layer 405 and a drain region layer 406 of a high concentration n ⁺ region (6th) Figure "Engineering (6e)").

Then, an insulating material such as SiO2 is deposited by a sputtering method or the like, and then anisotropic etching is performed by a dry etching method, and sidewalls 209a and 209b are formed as shown in the figure ("Project (6f)" in Fig. 6).

The points of the above-described project (Figs. 4 to 5) are described below.

Prepare Engineering (4a) SOI Wafer

. The film thickness of the SOI layer is adjusted as intended.

Engineering (4b) SOI layer component separation

. Forming the pattern of the element separation portion by dry etching

Engineering (5c) formation of gate insulating film, film formation of gate electrode

. A gate insulating film is formed using an insulating material such as SiO 2 .

. Deposition of Poly-Si for Gate Electrode

Engineering (5d) etching of gate electrode and etching of gate insulating film

. The gate electrode is dry etched with Poly-Si (gate electrode layer 404) to form a gate electrode layer region 208.

. The gate insulating film is subjected to etching (dry etching or wet etching) treatment to form a gate insulating film region a403.

Engineering (6e) ion implantation source and drain region layer

. A semiconductor impurity such as boron (B) or phosphorus (P) is ion-implanted into the source and drain regions to form a high-concentration region layer (source region layer 405 and drain region layer 406) of impurities.

Engineering (6f) forms sidewall 209

. Deposition of a film for sidewall formation

. Dry etching (non-isotropic etching) processing film for sidewall formation

[Formation Example 1 of Telluride Region]

Next, an illustration of setting a telluride region will be described based on Fig. 7. In the work (7c) or (7e) of Fig. 7, the metal layer b705 for forming a telluride is placed twice by a vapor deposition method as shown in the figure. At this time, the vapor deposition conditions were selected so that the layer thickness of the optimum telluride region was vapor-deposited on each crystal face.

In the case of the legend, the layer thickness of the metal layer b705 on the (100) plane 702 is relatively thicker than the layer thickness of the metal layer b705 on the (551) plane 701. Therefore, the layer thickness of the germanide region formed by the subsequent bismuth chemical treatment is also relatively thick on the (100) plane 702.

In the present invention, the layer thickness of the telluride region a708 formed on the (551) plane 701 is a metal used for bismuthation, but in the case of, for example, erbium (Er), it is preferably 4 nm or less.

Then, heat treatment is performed to form the telluride regions 204a and 708b in the respective interface regions of the metal layer 705 and the source region layer a501 and the drain region layer a502 ("engineering (7i)" in Fig. 7). At the same time, the source region 202 and the drain region 203 are formed separately (see FIG. 2).

Next, the undeposited metal layers 707a and 707b (unreacted metal layers) of the undeuterated material are removed by the above-described bismuth chemical treatment ("engineering (7g)" in Fig. 7).

Then, a metal for forming an electrical connection is formed by vapor deposition to form a metal layer for connection formation, and then unnecessary portions of the metal layer are removed by patterning to form a source electrode 205 and a drain electrode 206 (see FIG. 2). .

In the following description, an example of the formation conditions of the points of the telluride region is formed in the above-described process.

(a) Forming a source and a drain region of a three-dimensional structure (item 7a of Fig. 7).

(b) The photoresist is applied by a spin coating method (Item 7b of Fig. 7).

(c) Metal film formation is performed to form the metal layer a704 (item 7c of Fig. 7).

. The sputtering method is used to form Er (铕).

. Sputtering conditions: Ar gas flow. . . 20sccm, pressure. . . 133Pa (1 Torr), film thickness. . . 8nm

(d) Removal of the photoresist and the metal layer on the photoresist (Work 7d of Figure 7).

For example, the metal layer is peeled off while the photoresist is removed by an organic solvent.

(e) Metal film formation is performed to form metal layer b704 (Project 7e of Fig. 7).

. The sputtering method is used to form Er (铕).

. Sputtering conditions: Ar gas flow. . . 20sccm, pressure. . . 133Pa (1 Torr), film thickness. . . 2nm

(f) Deuteration treatment (Project 7f of Fig. 7).

The lamp was annealed at 600 ° C for 2 min.

(g) Removal of unreacted metal (engineer 7g of Fig. 7).

SPM (H2SO4: H2O2 = 4:1) uses 30sec time.

[Formation Example 2 of Telluride Region]

Next, another example of setting the telluride region will be described based on Fig. 8. In order to avoid complexity, the following is recorded.

(a) Forming a source and a drain region of a three-dimensional structure (item 7a of Fig. 8).

(b) Under the following conditions, the substrate was tilted, and an anisotropic film formation was performed to form a metal film, and a metal layer was formed as in the case of Fig. 7 (item 8b of Fig. 8).

. The Er film was formed by sputtering.

. Sputtering conditions: Ar gas flow. . . 20sccm, pressure. . . 0.67Pa (5mTorr),

. An Er film was formed by having 5 nm on the (100) plane and 1 nm on the (551) plane.

(c) Under the following conditions, the substrate was tilted, and an anisotropic film formation was performed to form a metal film, and a metal layer was formed as in the case of Fig. 7 (item 8c of Fig. 8).

. Sputtering conditions: Ar gas flow. . . 20sccm, pressure. . . 0.67Pa (5mTorr),

. An Er film was formed by having 5 nm on the (100) plane and 1 nm on the (551) plane.

With this two-time film formation, an Er film was formed by 10 nm on the (100) plane and 2 nm on the (551) plane.

(d) Deuteration treatment

The lamp was annealed at 600 ° C for 2 min.

(e) removal of unreacted metal

SPM (H2SO4: H2O2 = 4:1) uses 30sec time.

An example of the case where the source electrode 205 and the drain electrode 206 are formed will be described below.

(1) A metal (tungsten: W) layer for forming a connection is formed.

. A tungsten (W) film is formed by sputtering.

. Sputtering conditions: flow of Ar gas. . . . 20sccm, pressure. . . . 1.33Pa (10mTorr), film thickness. . . . 100nm

(2) The unnecessary portion of the metal (tungsten: W) layer for connection formation is removed by dry etching.

. Dry etching conditions of W: Ar gas flow. . . . 100sccm, SF6 gas flow. . . . 20sccm, pressure. . . . 1.33Pa (10mTorr), RF power. . . . 30W

Fig. 9 shows an example in which the germanide region is provided on the four faces of the source and drain regions of the three-dimensional structure. The illustration of Fig. 9 is an example of the modification of Fig. 2 . That is, in the case illustrated in Fig. 2, the telluride regions are provided on three faces, but in the case of the exemplified in Fig. 9, the telluride regions 901a and 901b are provided, respectively. As such a structure, the securing of the current path is more reliable.

The present invention is not limited to the embodiments described above, and various changes and modifications may be made without departing from the spirit and scope of the invention.

101‧‧‧矽 substrate

102‧‧‧BOX layer

201‧‧‧SOI layer area

202‧‧‧ source area

203‧‧‧Bungee area

204a, 204b‧‧‧ Telluride area

205‧‧‧ source electrode

206‧‧‧汲electrode

207‧‧‧ gate insulating film area

208‧‧‧ gate electrode layer area

209a, 209b‧‧‧ side wall

Claims (2)

A semiconductor device is a MOS-FET having a three-dimensional structure in which a basic electronic component has an electrode and a germanide region, and has a structure in which a source region and a drain region are formed by a plurality of different crystal faces. The layer thickness of the telluride region in the source region and the drain region varies depending on different crystal faces. A semiconductor device belonging to a MOS-FET having a three-dimensional structure of basic electronic components, comprising: a channel region having a plurality of different crystal faces; and a gate electrode provided to face a plurality of crystal faces of the channel region a gate insulating film disposed between the gate electrode and the channel region, and a high concentration of first and second semiconductor impurities disposed in a direction facing a current flowing through the channel region and interposed between the channel regions The region, each of the high concentration regions, has a plurality of different crystal faces and has a telluride region directly disposed on each crystal face, and the layer thickness of the telluride region varies depending on different crystal faces.