TW201443850A - Pull-up circuit, shift register and gate driving module - Google Patents

Abstract

A pull-up circuit has a first switch, a second switch and a third switch. The first switch determines whether or not transmitting a first voltage signal to a second node according to a first driving signal. In addition, the second switch determines whether or not transmitting a pull-up signal to the first node according to a second driving signal. A period of the second driving signal enabled and a period of the pull-up signal enabled are overlap, and the period of the second driving signal enabled and a period of the first driving signal enabled are not overlap. Furthermore, a frequency of the pull-up signal is higher than or equal to that of the second driving signal. Additionally, the third switch determines whether or not transmitting a clock signal to an output terminal according to the status of the first node.

Description

Voltage pull-up circuit, shift register and gate drive module

The present invention relates to a shift register and, more particularly, to a shift register for a gate drive module for use in a display.

1A is a block diagram of a conventional gate drive array, and FIG. 1B is a timing diagram of the gate drive signals of FIG. 1A. Referring to FIG. 1A and FIG. 1B together, the conventional gate drive array 100 can be applied to a display device including a plurality of shift registers, such as 102, 104, 106, 108, 110, and 112, and each The shift registers 102, 104, 106, 108, 110, and 112 each output corresponding gate signals G1, G2, G3, G4, G5, and G6 according to a start signal (for example, ST1) and a clock signal CLK. Each column in the display device is given to activate the pixels in each column.

However, in recent years, stereoscopic image display devices have begun to flourish. Since the stereoscopic image display device needs to display the left-eye image and the right-eye image in one frame period, a faster driving frequency is required. As a result, the conventional driving circuit cannot be applied to the stereoscopic image display device.

Therefore, the present invention provides a gate driving module that can be applied to a stereoscopic image display device.

The invention also provides a shift register, which can constitute the above-mentioned gate drive module.

In addition, the present invention further provides a potential pull-up circuit that can be applied to the shift register described above such that the shift register provides a larger driving force.

The invention provides a potential pull-up circuit comprising a first switch, a second switch and a third switch. The first switch can determine whether to transmit a first voltage signal to a second node according to the first driving signal. In addition, the second switch determines whether to send a voltage boost signal to the first node according to a second driving signal, and the time when the second driving signal is enabled is overlapped with the time when the voltage boosting signal is enabled, and The time when the second driving signal is enabled does not overlap with the time when the first driving signal is enabled. In addition, the frequency of the voltage boosting signal may be greater than or equal to the frequency of the second driving signal. In addition, the third switch determines to transmit a clock signal to an output according to the state of the first node.

From another point of view, the present invention provides a shift register having the above-described potential pull-up circuit. In addition, the shift register of the present invention further includes a pull-up control circuit, a pull-down control circuit, a pull-down circuit, and a main pull-down circuit. The pull-up control circuit transmits the first driving signal to the first node according to a first start signal, so that the third switch can decide whether to send the second clock signal to the shift temporary storage according to the state of the first driving signal. The output of the device. The pull-down control circuit determines to output the first voltage signal to the pull-down circuit according to the state of the first node. The pull-down circuit is coupled to the pull-down control circuit, the first node and the output of the shift register to stabilize the potential of the output of the first node and the shift register according to the output of the pull-down control circuit. In addition, the main pull-down circuit is coupled to a second voltage signal and a third switch to pull down the potential of the output of the first node and the shift register by controlling the operation of the third switch.

From another point of view, the present invention further provides a gate driving module having a plurality of the above-described shift registers and sequentially arranged. Wherein, the first switch in each shift register is based on the gate signal outputted by the prior shift register A drive signal. In addition, the second switch in each shift register is used as the second driving signal according to the gate signal outputted by the shift register arranged in front or rear.

Since the second pull-up circuit is disposed in the shift register of the present invention, the potential of the first node can be pulled up to a higher level through the potential pull-up of the second node to enhance the third The potential of the gate voltage of the switch. In this way, the driving force of the shift register can be increased.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

100‧‧‧Gate drive array

102, 104, 106, 108, 110, 112, SR1, SR2, SR3, SR4, SR5..., SRn‧‧ ‧ shift register: shift register

200‧‧ ‧ gate drive module

402‧‧‧Second pull-up circuit

404‧‧‧ Pull-up control circuit

406‧‧‧First pull-down control circuit

408‧‧‧Second pull-down control circuit

410‧‧‧First pull-down circuit

412‧‧‧Second pull-down circuit

414‧‧‧Main pull-down circuit

416‧‧‧First pull-up circuit

422, 424, 426‧ ‧ switch

428‧‧‧ Capacitance

602‧‧‧voltage dotted line

604‧‧‧voltage solid line

5t1, 5t2, 5t3‧‧

Qn‧‧‧ first node

An‧‧‧second node

G1, G2, G3, G4, G5, G6, G(n-4), Gn, G(n+1) ‧ ‧ gate signal

CLK, HC1, HC2, HC3, HC4, HC5, HC6, HC7, HC8, HCn‧‧‧ clock signals

LC1, LC2‧‧‧ control signals

ST1, STn, ST(n-4), ST(n+4), ST5, ST9‧‧‧ start signal

T11, T12, T21, T22, T23, T31, T32, T33, T34, T35, T41, T42, T43, T51, T52, T53, T54, T61, T62, T63, T64‧‧‧ transistors

VSS1‧‧‧First voltage signal

VSS2‧‧‧second voltage signal

FIG. 1A is a block diagram of a conventional gate drive array.

FIG. 1B is a timing diagram of the driving signals of the gate stages in FIG. 1A.

2 is a circuit block diagram of a gate driving module for use in a display device in accordance with a preferred embodiment of the present invention.

FIG. 3 is a timing diagram of a clock signal of a display device in a stereoscopic image mode according to an embodiment of the invention.

4 is a diagram showing an internal circuit of a shift register in accordance with an embodiment of the present invention.

FIG. 5 is a timing diagram of the internal signal of the shift register of FIG. 4 according to a preferred embodiment of the present invention.

FIG. 6 is a voltage diagram of the node Qn in FIG. 4.

2 is a circuit block diagram of a gate driving module for use in a display device in accordance with a preferred embodiment of the present invention. Please refer to FIG. 2, the gate provided by this embodiment The driving module 200 includes a plurality of shift registers SR1, SR2, SR3, SR4, SR5, ..., SRn arranged in order. Each of the shift registers outputs a gate signal G1, G2, G3, G4, G5, . . . , Gn to scan corresponding gate lines in the display device. In addition, in this embodiment, each shift register is coupled to a clock signal, such as HC1, HC2, HC3, HC4, HC5, .

FIG. 3 is a timing diagram of a clock signal of a display device in a stereoscopic image mode according to an embodiment of the invention. Referring to FIG. 2 and FIG. 3 together, when the display device displays the stereo image (that is, works in the 3D mode), since the left eye signal and the right eye signal need to be displayed in a frame, the frequency of the clock signal is Need to speed up. In this embodiment, the phase of each clock signal relative to the odd gate line is the same as the phase of the clock signal corresponding to the next gate line. For example, the clock signal HC1 relative to the first gate line has the same phase as the clock signal HC2 with respect to the second gate line; the clock signal HC3 relative to the third gate line is opposite to the fourth gate The phase pulse signal HC4 has the same phase; the clock signal HC5 with respect to the fifth gate line has the same phase as the clock signal HC6 with respect to the sixth gate line; and the clock with respect to the seventh gate line The signal HC7 has the same phase as the clock signal HC8 with respect to the eighth gate line. In addition, the period in which each of the clock signals with respect to the odd gate line is enabled may partially overlap with the period in which the clock signal with respect to the next odd gate line is enabled. For example, a portion of the time when the clock signal HC1 is enabled relative to the first gate line overlaps with a time when the clock signal HC3 of the third gate line is enabled.

In addition, the time when the gate signal output by each shift register is enabled may overlap with the time when the corresponding clock signal is enabled. For example, the time when the gate signal G5 outputted by the shift register SR5 is enabled may overlap with the time when the corresponding clock signal HC5 is enabled.

4 is a diagram showing an internal circuit of a shift register in accordance with an embodiment of the present invention. Referring to FIG. 4, the circuit of the shift register provided by the embodiment is suitable. Used in the shift register in the gate drive module 200 of FIG. The circuit of the shift register provided by this embodiment includes a second pull-up circuit 402, a pull-up control circuit 404, a first pull-down control circuit 406, a second pull-down control circuit 408, a first pull-down circuit 410, The second pull-down circuit 412, the main pull-down circuit 414, and the first pull-up circuit 416.

With continued reference to FIG. 4, the first pull up circuit 416 includes a switch 426. In the present embodiment, the switch 426 can be completed with a transistor T21. In the first pull-up circuit 416 of the embodiment, the gate terminal of the transistor T21 is coupled to the first node Qn, and the first node Qn is coupled to the second node An via the capacitor 428. The first source/汲 terminal of the transistor T21 is coupled to the clock signal corresponding to the same gate line, and the second source/汲 terminal is coupled to the output terminal of the shift register to output the gate. Signal Gn. The shift register disclosed in this embodiment is a shift register corresponding to the fifth gate line (n=5), so the first source/汲 terminal of the transistor T21 is coupled to the clock signal. HC5.

With continued reference to FIG. 4, the second pull-up circuit 402 includes switches 422, 424 and a capacitor 428. In the present embodiment, switches 422 and 424 can be completed with transistors T22 and T23, respectively. In this embodiment, the gate terminal of the transistor T22 arranged in the nth shift register is the gate signal G(n-4) outputted by the n-4th shift register. Be the first drive signal. In addition, the first source/汲 terminal of the transistor T22 is coupled to the first voltage signal VSS1, and the second source/汲 terminal thereof is coupled to the second node An. In this embodiment, the polarity of the voltage signal VSS1 is negative polarity.

In addition, the gate terminal of the transistor T23 is coupled to the gate signal outputted by the shift register stored in the front or the rear as the second driving signal. In this embodiment, if the shift register is arranged in an odd column, the gate terminal of the transistor T23 is coupled to the gate signal outputted by the next stage (n+1th stage) shift register. Make the second drive signal. In contrast, in the shift register arranged in the even column, the gate terminal of the transistor T23 is coupled to the gate signal outputted by the shift register of the upper stage (n-1th stage) as the first Second drive signal. The shift register provided in this embodiment is arranged in an odd column, so the transistor T23 The gate terminal receives the gate signal G(n+1) outputted by the n+1th stage shift register as the second driving signal. In addition, the first source/汲 terminal of the transistor T23 is coupled to a voltage boosting signal. In this embodiment, the first source/汲 terminal of the transistor T23 is coupled to the gate terminal, and the gate signal G(n+1) is used as the voltage boosting signal. The second source/汲 terminal of the transistor T23 is coupled to the second node An. In some other embodiments, the first source/deuterium terminal of the transistor T23 can also be directly coupled to the clock signal of the next stage.

Further, in the present embodiment, the pull-up control circuit 404 includes transistors T11 and T12. The gate terminal of the transistor T11 is coupled to the start signal outputted by the prior arrangement shift register, for example, coupled to the start signal ST(n-4). In addition, the first source/汲 terminal of the transistor T11 and the gate terminal of the transistor T22 together receive the first driving signal (eg, G(n-4)), and the second source/汲 terminal of the transistor T11 is coupled. The first node Qn. On the other hand, the first source/汲 terminal and the gate terminal of the transistor T12 are respectively coupled to the first source/汲 terminal and the gate terminal of the transistor T21, and the second source/汲 terminal of the transistor T12 can also output a corresponding Start signal STn.

The first pull-down control circuit 406 then includes transistors T51, T52, T53, and T54. The gate terminal of the transistor T51 and the first source/deuterium terminal are coupled together with the first source/turn terminal of the control signal LC1 and the transistor T53. The gate terminal of the transistor T53 is coupled to the second source/汲 terminal of the transistors T51 and T52, and the second source/汲 terminal of the transistor T53 is coupled to the second source/汲 terminal of the transistor T54. In addition, the first source/汲 terminal of the transistors T52 and T54 are coupled to the first voltage signal VSS1, and the gate terminals are commonly coupled to the first node Qn.

Cooperating with the first pull-down control circuit 406 is a first pull-down circuit 410. In the present embodiment, the first pull-down circuit 410 includes transistors T32, T34, and T42. The first source/汲 terminal and the second source/汲 terminal of the transistor T42 are respectively coupled to the second source/汲 terminal and the gate terminal of the transistor T12, and the gate terminal of the transistor T42 is connected to the gates of the transistors T32 and T34. Extremely coupled to the second source/汲 terminal of transistor T53. In addition, the first source/汲 terminal of the transistor T32 is coupled to the second voltage signal VSS2, and the second source/汲 terminal is coupled to the shift. The output of the register, wherein the potential of the second voltage signal VSS2 is lower than the first voltage signal VSS1. On the other hand, the first source/汲 terminal of the transistor T34 is coupled to the first voltage signal VSS1, and the second source/汲 terminal is coupled to the second source/pole terminal of the transistor T12.

Similarly, the second pull-down control circuit 408 includes transistors T61, T62, T63, and T64. The gate terminal of the transistor T61 and the first source/deuterium terminal are commonly coupled to the first source/deuterium terminal of the control signal LC2 and the transistor T63. The gate terminal of the transistor T63 is coupled to the second source/汲 terminal of the transistors T61 and T62, and the second source/汲 terminal of the transistor T63 is coupled to the second source/汲 terminal of the transistor T64. In addition, the first source/tb terminals of the transistors T62 and T64 are respectively coupled to the first voltage signal VSS1, and the gate terminals are commonly coupled to the first node Qn.

The second pull-down circuit 412, which cooperates with the second pull-down control circuit 408, also includes transistors T33, T35 and T43. The first source/汲 terminal and the second source/汲 terminal of the transistor T43 are respectively coupled to the first source/汲 terminal and the second source/汲 terminal of the transistor T42, and the gate terminal of the transistor T43 is coupled to the transistor T33. And the gate terminal of T35 is coupled to the second source/汲 terminal of transistor T63. In addition, the first source/deuterium terminal and the second source/deuterium terminal of the transistors T33 and T35 are respectively coupled to the first source/deuterium terminal and the second source/deuterium terminal of the transistors T32 and 34, respectively.

The main pull-down circuit 414 includes transistors T31 and T41. The gate terminals and the first source/drain terminals of the transistors T31 and T41 are coupled to each other. In this embodiment, the gate terminals of the transistors T31 and T41 are coupled to the start signal ST(n+4), and the first source/汲 terminals of the transistors T41 and T31 are coupled to the second voltage signal VSS2. In addition, the second source/汲 terminal of the transistor T31 is coupled to the first node Qn, and the second source/汲 terminal of the transistor T31 is coupled to the output of the shift register.

FIG. 5 is a timing diagram of the internal signal of the shift register of FIG. 4 according to a preferred embodiment of the present invention. In this embodiment, the fifth shift register (n=5) is arranged as an example, and those skilled in the art can push other shifts by themselves. The operating principle of the memory. Referring to FIG. 4 and FIG. 5 together, at 5t1, both the clock signal HC1 and the gate signal G1 are enabled, and thus the transistors T11 and T22 are turned on. Therefore, the transistor T11 transfers the gate signal G1 to the node Q5 and pulls the potential of the node Q5 to a first potential. At this time, the transistors T12 and T21 are turned on. Since the clock signal HC5 is at a low potential at 5t1, the start signal ST5 and the gate signal G5 are both low.

At 5t2, the clock signal HC5 is enabled and pulled up to a high potential. Since the start signal ST9 is still at a low level at this time, the transistors T41 and T31 are continuously turned off. In addition, the transistors T12 and T21 are maintained in an open state. In this way, the transistor T21 turns on the high-potential clock signal HC5 to the output terminal of the shift register, so that the shift register outputs the high-potential gate signal G5, and the voltage of the node Q5 is The first potential is pulled up to a higher second potential. In addition, the start signal ST5 is also pulled up to a high level.

On the other hand, since the gate signals G6 and G5 have the same phase, the transistor T23 is turned on. Therefore, the transistor T23 turns on the gate signal G6 to the node A5, and the voltage of the node A5 is coupled to the node Q5 via the capacitor 428, thereby pulling up the potential of the node Q5. As a result, the gate terminal of the transistor T21 is applied with a higher voltage, so that the current flowing through the transistor T21 is increased, and the driving ability of the bit register is improved.

In some embodiments, the first source/tb terminal of the transistor T23 can be directly coupled to the clock signal HC6 of the next stage, and since the waveform of the clock signal HC6 is better than the waveform quality of the gate signal G6, Therefore, the driving force of the shift register can be increased.

Next, at 5t3, since the start signal ST9 is enabled, the transistors T41 and T31 are turned on. Therefore, the second voltage signal VSS2 is applied to the gate terminal of the transistor T21, turning off the transistor T21, and pulling the node Q5 down to a low potential. In addition, the second voltage signal VSS2 is also applied to the output of the shift register, so that the gate signal G5 is pulled down to a low potential.

On the other hand, transistors T62 and T64 are turned off because node Q5 is pulled low. In contrast, the transistor T61 is turned on because the control signal LC2 is maintained at a high potential, so that the transistor T63 is also turned on, and the high-potential control signal LC2 is applied to the transistors T43, T33, and T35. As a result, the transistors T43, T33 and T35 are turned on, so that the node Q5, the gate signal G5 and the start signal ST5 are all stabilized at a low potential.

Similarly, during the next frame, the control signal LC1 is switched to the high potential, and the control signal LC2 is pulled down to the low potential, the voltage stabilization circuit 410 acts like the voltage stabilization circuit 412 to stabilize the node Q5 and the gate. The potential of the pole signal G5 and the start signal ST5.

FIG. 6 is a voltage diagram of the node Qn in FIG. 4. Referring to FIG. 4 and FIG. 6, the voltage change of the node Qn when the voltage is pulled up without using the transistors T22 and T23 is indicated by a broken line 602, and the voltage change of the node Qn when the transistors T22 and T23 are arranged is used. The solid line 604 is indicated. As is apparent from Fig. 6, since the present invention is configured with transistors T22 and T23, the potential of the node Qn at the high level is higher than the potential of the node Qn at the high level when the transistors T22 and T23 are not disposed. high. In this way, the driving force of the shift register can be increased.

Referring back to FIG. 3 and FIG. 4, when the display device displays a two-dimensional image (that is, operates in the 2D mode), the frequency of the clock signals HC1, HC2, ... can be lowered. In other words, the time at which the clock signals HC1, HC2, ... are enabled does not overlap each other. As a result, the gate signals (G1, G2, ...) output by each stage of the shift register are not overlapped. Therefore, when the display device operates in the 2D mode and the HC5 is enabled, since the gate signal G6 is maintained at the low level, the transistor T23 maintains the off state. Therefore, the potential of the node Qn is not pulled up to a higher level, and flows through The current of the transistor T21 does not increase. In other words, when the display device is operated in the 2D mode, no additional power is consumed.

In summary, since the present invention utilizes the transistors T22 and T23 to pull up the potential of the node Qn, the shift register can be made to have a large driving force. On the other hand, the present invention does not consume additional power when the display device operates in the 2D mode.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

402‧‧‧Second pull-up circuit

404‧‧‧ Pull-up control circuit

406‧‧‧First pull-down control circuit

408‧‧‧Second pull-down control circuit

410‧‧‧First pull-down circuit

412‧‧‧Second pull-down circuit

414‧‧‧Main pull-down circuit

416‧‧‧First pull-up circuit

422, 424, 426‧ ‧ switch

428‧‧‧ Capacitance

Qn‧‧‧ first node

An‧‧‧second node

G(n-4), Gn, G(n+1)‧‧‧ gate signal

HCn‧‧‧ clock signal

LC1, LC2‧‧‧ control signals

STn, ST(n-4), ST(n+4)‧‧‧ start signal

T11, T12, T21, T22, T23, T31, T32, T33, T34, T35, T41, T42, T43, T51, T52, T53, T54, T61, T62, T63, T64‧‧‧ transistors

VSS1‧‧‧First voltage signal

VSS2‧‧‧second voltage signal

Claims (10)

A potential pull-up circuit includes: a first switch, determining whether to transmit a first voltage signal to a second node according to a first driving signal; and a second switch determining whether to be based on a second driving signal A voltage boosting signal is sent to the first node, wherein the time when the second driving signal is enabled is overlapped with the time when the voltage boosting signal is enabled, and the frequency of the voltage boosting signal is greater than or equal to the second driving signal. Frequency, the time when the second driving signal is enabled does not overlap with the time when the first driving signal is enabled; and a third switch determines to transmit a clock signal to the state of the first node according to the state of the first node An output. The potential pull-up circuit of claim 1, wherein the second drive signal and the voltage boost signal are the same signal. The potential pull-up circuit of claim 1, further comprising a capacitor, the first end of which is coupled to the second node, and the second end of which is coupled to the third switch through a first node, The third switch is configured to transmit the clock signal to the output according to the state of the first node. A shift register having a potential pull-up circuit according to any one of claims 1-3, wherein the shift register further comprises: a pull-up control circuit, according to a first control signal Sending the first driving signal to the third switch, so that the third switch determines to send the clock signal to the output terminal according to the driving signal; a pull-down control circuit determines to output the first voltage signal according to the state of the first node; a pull-down circuit is coupled to the pull-down control circuit and the output terminal to stabilize the output end according to the output of the pull-down control circuit And a main pull-down circuit coupled to the second voltage signal and the third switch to pull down the potential of the output terminal by controlling the actuation of the third switch. A gate driving module is applicable to a display and has a plurality of shift registers, and each of the shift registers has an output terminal for outputting a corresponding gate signal, and each shift register is temporarily stored. The device further includes: a first switch, determining whether to transmit a first voltage signal to a second node according to a state of the gate signal outputted by the previous shift register; and a second switch The gate signal outputted by the pre-arranged or rear-shifted register is used as a second driving signal to determine whether to send a voltage boosting signal to the first node, wherein the second driving signal is caused The time of the voltage is overlapped with the enable time of the voltage boosting signal, and the frequency of the voltage boosting signal is greater than or equal to the frequency of the second driving signal, and the time when the second driving signal is enabled and the first driving signal The time of being enabled does not overlap; a third switch determines to transmit a clock signal to an output according to the state of the first node; a pull-up control circuit, the first according to a first control signal Drive signal The third switch is configured to cause the third switch to send the clock signal to the output terminal according to the driving signal; the pull-down control circuit determines to output the first voltage signal according to the state of the first node; And a pull-down circuit, coupled to the pull-down control circuit and the output terminal, according to the pull-down control The output of the circuit stabilizes the potential of the output; a main pull-down circuit is coupled to a second voltage signal and the third switch to control the operation of the third switch, and pull down the potential of the output, wherein the mth stage shift The gate signal output by the bit buffer is in phase with the gate signal output by the m+1th stage shift register, and m is an odd number. The gate drive module of claim 5, wherein the second switch in each of the odd-numbered shift registers is based on the gate signal output by the next-stage shift register. Second drive signal. The gate driving module of claim 5, wherein the second switch in each of the even-numbered shift registers is based on the gate signal outputted by the shift register of the previous stage as the first Second drive signal. The gate drive module of claim 5, wherein each of the shift registers receives the gate signal output by the next stage shift register as the second control of the second switch thereof. Drive signal. The gate driving module of claim 5, wherein the second driving signal and the voltage boosting signal are the same signal. The gate drive module of claim 5, wherein each of the shift registers further includes a capacitor, the first end of which is coupled to the second node, and the second end of which is coupled to the first The node is coupled to the third switch, so that the third switch can transmit the clock signal to the output according to the state of the first node.