TWI743984B - Driving method and displat device - Google Patents

Driving method and displat device Download PDF

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TWI743984B
TWI743984B TW109131178A TW109131178A TWI743984B TW I743984 B TWI743984 B TW I743984B TW 109131178 A TW109131178 A TW 109131178A TW 109131178 A TW109131178 A TW 109131178A TW I743984 B TWI743984 B TW I743984B
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node
logic level
circuit
pull
stage
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TW109131178A
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TW202211191A (en
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林煒力
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友達光電股份有限公司
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Logic Circuits (AREA)

Abstract

A diving method is adapted to a display device. The display device includes an output circuit and a voltage regulator and reset circuit. The output circuit includes a first node, a first output end and a second output end. The voltage regulator and reset circuit is coupled to the output circuit and includes a first pull-down circuit, a first control circuit, a second pull-down circuit and a second control circuit. The diving method includes: adjusting the first node to a first logic level according to a trigger signal at a first stage; discharging inner nodes of the first control circuit and the second control circuit according to a pull-down signal and the first logic level of the first node at the first stage; discharging the first output end and the second output end according to a pull-up signal and the first logic level of the first node at a second stage; and controlling first pull-down circuit so as to discharge the first node according to a reset signal at a third stage.

Description

驅動方法及顯示裝置Driving method and display device

本案涉及一種電子方法及裝置。詳細而言，本案涉及一種顯示裝置及驅動方法。This case involves an electronic method and device. In detail, this case relates to a display device and a driving method.

現有斷電系統並無針對面板左右兩側的閘極驅動電路內部進行重置的動作，使閘極驅動電路內部殘存電荷，於下次啟動面板時，將產生漏電流，啟動過電流保護機制使系統關機，因此上述技術尚存諸多缺陷，而有待本領域從業人員研發出其餘適合的驅動方式。The existing power-off system does not reset the internal gate drive circuits on the left and right sides of the panel, so that the residual charge in the gate drive circuit will generate leakage current when the panel is activated next time, and the overcurrent protection mechanism will be activated. The system shuts down, so the above-mentioned technology still has many defects, and it is necessary for practitioners in the field to develop other suitable driving methods.

本案的一面向涉及一種驅動方法適用於顯示裝置。顯示裝置包含輸出電路及穩壓與重置電路。輸出電路包含第一節點、第一輸出端及第二輸出端。穩壓與重置電路耦接於輸出電路並包含第一下拉電路、第一控制電路、第二下拉電路及第二控制電路。驅動方法包含以下步驟:於第一階段根據觸發訊號將第一節點調整至第一邏輯準位；於第一階段根據下拉訊號及第一節點之第一邏輯準位對第一控制電路及第二控制電路內部之複數個節點進行放電；於第二階段根據上拉訊號及第一節點之第一邏輯準位對第一輸出端及第二輸出端進行放電；以及於第三階段根據重置訊號控制第一下拉電路以對第一節點進行放電。One aspect of this case relates to a driving method suitable for a display device. The display device includes an output circuit and a voltage stabilization and reset circuit. The output circuit includes a first node, a first output terminal, and a second output terminal. The voltage stabilization and reset circuit is coupled to the output circuit and includes a first pull-down circuit, a first control circuit, a second pull-down circuit, and a second control circuit. The driving method includes the following steps: in the first stage, the first node is adjusted to the first logic level according to the trigger signal; in the first stage, the first control circuit and the second control circuit are adjusted according to the pull-down signal and the first logic level of the first node. A plurality of nodes in the control circuit are discharged; in the second stage, the first output terminal and the second output terminal are discharged according to the pull-up signal and the first logic level of the first node; and in the third stage according to the reset signal The first pull-down circuit is controlled to discharge the first node.

本案的另一面向涉及一種顯示裝置。顯示裝置包含輸出電路及穩壓與重置電路。輸出電路包含第一節點、第一輸出端及第二輸出端。穩壓與重置電路耦接於輸出電路並包含第一下拉電路、第一控制電路、第二下拉電路及第二控制電路。輸出電路用以於第一階段根據觸發訊號將第一節點調整至第一邏輯準位。第一控制電路及第二控制電路用以於第一階段根據下拉訊號及第一節點之第一邏輯準位對第一控制電路及第二控制電路內部之複數個節點進行放電。輸出電路用以於第二階段根據上拉訊號及第一節點之第一邏輯準位對第一輸出端及第二輸出端進行放電。第一下拉電路用以於第三階段根重置訊號對第一節點進行放電。Another aspect of this case involves a display device. The display device includes an output circuit and a voltage stabilization and reset circuit. The output circuit includes a first node, a first output terminal, and a second output terminal. The voltage stabilization and reset circuit is coupled to the output circuit and includes a first pull-down circuit, a first control circuit, a second pull-down circuit, and a second control circuit. The output circuit is used for adjusting the first node to the first logic level according to the trigger signal in the first stage. The first control circuit and the second control circuit are used for discharging a plurality of nodes in the first control circuit and the second control circuit according to the pull-down signal and the first logic level of the first node in the first stage. The output circuit is used for discharging the first output terminal and the second output terminal according to the pull-up signal and the first logic level of the first node in the second stage. The first pull-down circuit is used for discharging the first node by the reset signal in the third stage.

以下將以圖式及詳細敘述清楚說明本案之精神，任何所屬技術領域中具有通常知識者在瞭解本案之實施例後，當可由本案所教示之技術，加以改變及修飾，其並不脫離本案之精神與範圍。The following will clearly illustrate the spirit of this case with diagrams and detailed descriptions. Anyone with ordinary knowledge in the technical field who understands the embodiments of this case can change and modify the technology taught in this case without departing from the scope of this case. Spirit and scope.

本文之用語只為描述特定實施例，而無意為本案之限制。單數形式如“一”、“這”、“此”、“本”以及“該”，如本文所用，同樣也包含複數形式。The terms used herein are only to describe specific embodiments, and are not intended to limit the present application. Singular forms such as "a", "this", "this", "本" and "this", as used herein, also include plural forms.

關於本文中所使用之『包含』、『包括』、『具有』、『含有』等等，均為開放性的用語，即意指包含但不限於。Regarding the "include", "include", "have", "contain", etc. used in this article, they are all open terms, which means including but not limited to.

關於本文中所使用之用詞（terms），除有特別註明外，通常具有每個用詞使用在此領域中、在本案之內容中與特殊內容中的平常意義。某些用以描述本案之用詞將於下或在此說明書的別處討論，以提供本領域技術人員在有關本案之描述上額外的引導。Regarding the terms used in this article, unless otherwise specified, each term usually has the usual meaning when used in this field, in the content of the case, and in the special content. Some terms used to describe the case will be discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance on the description of the case.

第1圖為根據本案一些實施例繪示的驅動裝置之部分電路方塊圖。在一些實施例中，驅動裝置100包含輸出電路110及穩壓與重置電路120。在一些實施例中，輸出電路110包含第一節點N1、第一輸出端O1及第二輸出端O2。穩壓與重置電路120耦接於輸出電路110並包含第一下拉電路121、第一控制電路123、第二下拉電路125及第二控制電路127。FIG. 1 is a partial circuit block diagram of a driving device according to some embodiments of the present application. In some embodiments, the driving device 100 includes an output circuit 110 and a voltage stabilization and reset circuit 120. In some embodiments, the output circuit 110 includes a first node N1, a first output terminal O1, and a second output terminal O2. The voltage stabilization and reset circuit 120 is coupled to the output circuit 110 and includes a first pull-down circuit 121, a first control circuit 123, a second pull-down circuit 125 and a second control circuit 127.

在一些實施例中，輸出電路110包含電晶體M1~M3、電容C1、第一節點N1、第一輸出端O1及第二輸出端O2。電晶體M1接收第一電壓VGH。在一些實施例中，第一輸出端O1輸出訊號至複數個畫素(圖中未示)。In some embodiments, the output circuit 110 includes transistors M1 to M3, a capacitor C1, a first node N1, a first output terminal O1, and a second output terminal O2. The transistor M1 receives the first voltage VGH. In some embodiments, the first output terminal O1 outputs signals to a plurality of pixels (not shown in the figure).

在一些實施例中，第一控制電路123耦接於第一下拉電路121，第二控制電路127耦接於第二下拉電路125，第一下拉電路121及第二下拉電路125耦接於輸出電路110之第一節點N1、第一輸出端O1及第二輸出端O2。In some embodiments, the first control circuit 123 is coupled to the first pull-down circuit 121, the second control circuit 127 is coupled to the second pull-down circuit 125, and the first pull-down circuit 121 and the second pull-down circuit 125 are coupled to The first node N1, the first output terminal O1, and the second output terminal O2 of the output circuit 110.

在一些實施例中，第一下拉電路121、第一控制電路123、第二下拉電路125及第二控制電路127接收第二電壓VQ。In some embodiments, the first pull-down circuit 121, the first control circuit 123, the second pull-down circuit 125, and the second control circuit 127 receive the second voltage VQ.

在一些實施例中，第一下拉電路121及第二下拉電路125接收第三電壓VG。In some embodiments, the first pull-down circuit 121 and the second pull-down circuit 125 receive the third voltage VG.

在一些實施例中，第一下拉電路121包含電晶體M4~M8，第一控制電路123包含電晶體M9~M14、第二節點N2及第三節點N3。第一下拉電路121耦接於第一控制電路123之第二節點N2並根據第二節點N2之電位驅動。電晶體M9之第二端耦接於第二節點N2，且電晶體M9之控制端耦接於第三節點N3。 In some embodiments, the first pull-down circuit 121 includes transistors M4 to M8, and the first control circuit 123 includes transistors M9 to M14, a second node N2, and a third node N3. The first pull-down circuit 121 is coupled to the second node N2 of the first control circuit 123 and is driven according to the potential of the second node N2. The second end of the transistor M9 is coupled to the second node N2, and the control end of the transistor M9 is coupled to the third node N3.

在一些實施例中，第二下拉電路125包含電晶體M15~M17，第二控制電路127包含電晶體M18~M23、第四節點N4及第五節點N5。第二下拉電路125耦接於第二控制電路127之第四節點N4並根據第四節點N4電位驅動。電晶體M18之第二端耦接於第四節點N4，且電晶體M18之控制端耦接於五節點N5。 In some embodiments, the second pull-down circuit 125 includes transistors M15 to M17, and the second control circuit 127 includes transistors M18 to M23, a fourth node N4, and a fifth node N5. The second pull-down circuit 125 is coupled to the fourth node N4 of the second control circuit 127 and is driven according to the potential of the fourth node N4. The second end of the transistor M18 is coupled to the fourth node N4, and the control end of the transistor M18 is coupled to the five node N5.

在一些實施例中，為使第1圖之驅動裝置100的操作易於理解，請一併參閱第2圖，第2圖為根據本案一些實施例繪示的驅動方法之訊號時序圖。須說明的是，每個訊號自上方由下的三條虛線，分別代表第一邏輯準位、第二邏輯準位及第三邏輯準位。在一些實施例中，第一邏輯準位為高邏輯準位(logic high level)、第二邏輯準位為接地準位及第三邏輯準位為負邏輯準位(logic low level)。 In some embodiments, in order to make the operation of the driving device 100 in FIG. 1 easier to understand, please refer to FIG. 2 together. FIG. 2 is a signal timing diagram of the driving method according to some embodiments of the present application. It should be noted that the three dashed lines from the top to the bottom of each signal represent the first logic level, the second logic level, and the third logic level. In some embodiments, the first logic level is a logic high level, the second logic level is a ground level, and the third logic level is a negative logic level (logic low level).

接著，輸出電路110用以於第一階段T1根據觸發訊號ST將第一節點N1調整至第一邏輯準位。第一控制電路123及第二控制電路127用以於第一階段T1根據下拉訊號(LC1及LC2)及第一節點N1之第一邏輯準位對第一控制電路123及第二控制電路127內部之複數個節點進行放電。輸出電路110用以於第二階段T2根據上拉訊號HC及第一節點N1之第一邏輯準位對第一輸出端O1及第二輸出端O2進行放電。第一下拉電路121用以於第三階段根據重置訊號RST對第一節點N1進行放電。Then, the output circuit 110 is used to adjust the first node N1 to the first logic level according to the trigger signal ST in the first stage T1. The first control circuit 123 and the second control circuit 127 are used to control the interior of the first control circuit 123 and the second control circuit 127 according to the pull-down signal (LC1 and LC2) and the first logic level of the first node N1 in the first stage T1 The multiple nodes are discharged. The output circuit 110 is used for discharging the first output terminal O1 and the second output terminal O2 according to the pull-up signal HC and the first logic level of the first node N1 in the second stage T2. The first pull-down circuit 121 is used for discharging the first node N1 according to the reset signal RST in the third stage.

第3圖為根據本案一些實施例繪示的驅動方法之步驟流程圖。在一些實施例中，此驅動方法300可由第1圖所示的驅動裝置100所執行。為使第3圖之驅動方法300的操作易於理解，請一併參閱第3圖至第7圖。第4圖至第7圖為根據本案一些實施例繪示的驅動裝置之狀態示意圖，係對應第1圖之驅動裝置100。FIG. 3 is a flowchart of the steps of the driving method according to some embodiments of the present application. In some embodiments, the driving method 300 can be executed by the driving device 100 shown in FIG. 1. In order to make the operation of the driving method 300 in FIG. 3 easy to understand, please refer to FIGS. 3 to 7 together. FIGS. 4 to 7 are schematic diagrams showing the states of the driving device according to some embodiments of the present application, corresponding to the driving device 100 in FIG. 1.

於步驟310中，於第一階段根據觸發訊號將輸出電路之第一節點調整至第一邏輯準位。In step 310, the first node of the output circuit is adjusted to the first logic level according to the trigger signal in the first stage.

在一些實施例中，請參閱第2圖、第3圖及第4圖，於第一階段T1，觸發訊號ST及第一電壓VGH為第一邏輯準位，此時第一電壓VGH透過電晶體M1對第一節點N1調整至第一邏輯準位(例如，高邏輯準位)。同時，電晶體M2~M3根據第一節點N1之第一邏輯準位，將第一邏輯準位之上拉訊號HC提供至第一輸出端O1及第二輸出端O2，此時，上拉訊號HC、第一輸出端O1及第二輸出端O2均為第一邏輯準位。In some embodiments, please refer to FIG. 2, FIG. 3, and FIG. 4. In the first stage T1, the trigger signal ST and the first voltage VGH are at the first logic level. At this time, the first voltage VGH passes through the transistor M1 adjusts the first node N1 to a first logic level (for example, a high logic level). At the same time, the transistors M2~M3 provide the first logic level pull-up signal HC to the first output terminal O1 and the second output terminal O2 according to the first logic level of the first node N1. At this time, the pull-up signal HC, the first output terminal O1, and the second output terminal O2 are all at the first logic level.

於步驟320中，於第一階段根據下拉訊號及第一節點之第一邏輯準位對第一控制電路及第二控制電路內部之複數個節點進行放電。In step 320, a plurality of nodes in the first control circuit and the second control circuit are discharged according to the pull-down signal and the first logic level of the first node in the first stage.

在一些實施例中，請參閱第2圖、第3圖及第4圖，於第一階段T1，第二電壓VQ及下拉訊號(LC1及LC2)為第二邏輯準位(例如，接地準位)，第一控制電路123之電晶體M14根據下拉訊號(LC1)不導通，電晶體M10~M13根據第一節點N1之第一邏輯準位(例如，高邏輯準位)導通，此時，第二節點N2之電位經過電晶體M10及M12調整至第二電壓VQ的第二邏輯準位，第三節點N3之電位藉由電晶體M11及M13調整至第二電壓VQ的第二邏輯準位。因此，第一下拉電路121之電晶體M6~M8根據第二節點N2之電位不導通。須說明的是，第一下拉電路121之電晶體M4根據觸發訊號ST導通及第一下拉電路121之電晶體M5根據重置訊號RST不導通。In some embodiments, referring to Figures 2, 3, and 4, in the first stage T1, the second voltage VQ and the pull-down signal (LC1 and LC2) are at the second logic level (for example, the ground level) ), the transistor M14 of the first control circuit 123 is not turned on according to the pull-down signal (LC1), and the transistors M10~M13 are turned on according to the first logic level (for example, the high logic level) of the first node N1. At this time, the first The potential of the two nodes N2 is adjusted to the second logic level of the second voltage VQ by the transistors M10 and M12, and the potential of the third node N3 is adjusted to the second logic level of the second voltage VQ by the transistors M11 and M13. Therefore, the transistors M6 to M8 of the first pull-down circuit 121 are not turned on according to the potential of the second node N2. It should be noted that the transistor M4 of the first pull-down circuit 121 is turned on according to the trigger signal ST and the transistor M5 of the first pull-down circuit 121 is not turned on according to the reset signal RST.

此外，第二控制電路127之電晶體M23根據下拉訊號(LC2)不導通，電晶體M19~M22根據第一節點N1之第一邏輯準位導通，此時，第四節點N4之電位藉由電晶體M19及M21調整至第二電壓VQ的第二邏輯準位，第五節點N5之電位經過電晶體M20及M22調整至第二電壓VQ的第二邏輯準位。因此，第二下拉電路125根據第四節點N4之電位不導通。In addition, the transistor M23 of the second control circuit 127 is not turned on according to the pull-down signal (LC2), and the transistors M19~M22 are turned on according to the first logic level of the first node N1. At this time, the potential of the fourth node N4 is The transistors M19 and M21 are adjusted to the second logic level of the second voltage VQ, and the potential of the fifth node N5 is adjusted to the second logic level of the second voltage VQ through the transistors M20 and M22. Therefore, the second pull-down circuit 125 is non-conductive according to the potential of the fourth node N4.

於步驟330中，於第二階段根據上拉訊號及第一節點之第一邏輯準位對輸出電路的第一輸出端及第二輸出端進行放電。In step 330, the first output terminal and the second output terminal of the output circuit are discharged according to the pull-up signal and the first logic level of the first node in the second stage.

在一些實施例中，請參閱第2圖、第3圖及第5圖，於第二階段T2，第一節點N1之第一邏輯準位維持第一邏輯準位(例如，高邏輯準位)，輸出電路110之電晶體M2及M3導通，此時將上拉訊號HC的第一邏輯準位調整至第二邏輯準位(例如，接地準位)，輸出電路110之第一輸出端O1及第二輸出端O2也隨著上拉訊號HC調整至第二邏輯準位。須說明的是，第一控制電路123之第二節點N2及第三節點N3維持上述步驟320之狀態。第二控制電路127之第四節點N4及第五節點N5維持上述步驟320之狀態。In some embodiments, referring to FIGS. 2, 3, and 5, in the second stage T2, the first logic level of the first node N1 maintains the first logic level (for example, a high logic level) , The transistors M2 and M3 of the output circuit 110 are turned on. At this time, the first logic level of the pull-up signal HC is adjusted to the second logic level (for example, the ground level), and the first output terminals O1 and The second output terminal O2 is also adjusted to the second logic level according to the pull-up signal HC. It should be noted that the second node N2 and the third node N3 of the first control circuit 123 maintain the state of step 320 described above. The fourth node N4 and the fifth node N5 of the second control circuit 127 maintain the state of step 320 described above.

此外，第三電壓VG於第二階段T2調整至第二邏輯準位。In addition, the third voltage VG is adjusted to the second logic level in the second stage T2.

於步驟340中，於第三階段根據重置訊號控制第一下拉電路以對第一節點進行放電。In step 340, the first pull-down circuit is controlled according to the reset signal in the third stage to discharge the first node.

在一些實施例中，請參閱第2圖、第3圖及第6圖，於第三階段T3，觸發訊號ST及第一電壓VGH調整至第二邏輯準位(例如，接地準位)，輸出電路110之電晶體M2及M3不導通，此時，將穩壓與重置電路120之電晶體M5的重置訊號RST從第三邏輯準位(例如，負邏輯準位)調整至第一邏輯準位(例如，高邏輯準位)，使得輸出電路110之第一節點N1之第一邏輯準位透過穩壓與重置電路120之電晶體M5調整至第二電壓VQ的第二邏輯準位。在一些實施例中，第一邏輯準位為正邏輯準位，第二邏輯準位為接地準位及第三邏輯準位為負邏輯準位。In some embodiments, referring to Figures 2, 3, and 6, in the third stage T3, the trigger signal ST and the first voltage VGH are adjusted to the second logic level (for example, the ground level), and output The transistors M2 and M3 of the circuit 110 are not conducting. At this time, the reset signal RST of the transistor M5 of the voltage stabilization and reset circuit 120 is adjusted from the third logic level (for example, the negative logic level) to the first logic level Level (for example, high logic level), so that the first logic level of the first node N1 of the output circuit 110 is adjusted to the second logic level of the second voltage VQ through the transistor M5 of the voltage stabilizing and reset circuit 120 . In some embodiments, the first logic level is a positive logic level, the second logic level is a ground level, and the third logic level is a negative logic level.

此外，第一控制電路123之電晶體M10~M13及第二控制電路127之電晶體M19~M22根據第一節點N1之第二邏輯準位不導通。In addition, the transistors M10 to M13 of the first control circuit 123 and the transistors M19 to M22 of the second control circuit 127 are not turned on according to the second logic level of the first node N1.

在一些實施例中，請參閱第2圖、第3圖及第7圖，將穩壓與重置電路120之電晶體M5的重置訊號RST從第一邏輯準位(例如，高邏輯準位)調整至第二邏輯準位(例如，接地準位)，使得驅動裝置100內部的電荷清除完畢。In some embodiments, referring to FIGS. 2, 3, and 7, the reset signal RST of the transistor M5 of the voltage stabilization and reset circuit 120 is changed from a first logic level (for example, a high logic level). ) Is adjusted to the second logic level (for example, the ground level), so that the charge inside the driving device 100 is completely cleared.

在一些實施例中，請參閱第1圖，驅動裝置100可為移位暫存器。In some embodiments, referring to FIG. 1, the driving device 100 may be a shift register.

依據前述實施例，本案提供一種驅動方法及顯示裝置，藉以改善顯示裝置內部電路殘存電荷，使得顯示裝置啟動面板時將不會有過大的漏電流。According to the foregoing embodiment, the present application provides a driving method and a display device, so as to improve the residual electric charge in the internal circuit of the display device, so that there will be no excessive leakage current when the display device activates the panel.

雖然本案以詳細之實施例揭露如上，然而本案並不排除其他可行之實施態樣。因此，本案之保護範圍當視後附之申請專利範圍所界定者為準，而非受於前述實施例之限制。Although this case is disclosed as above with detailed embodiments, this case does not exclude other feasible implementation aspects. Therefore, the scope of protection of this case shall be determined by the scope of the attached patent application, and shall not be restricted by the foregoing embodiments.

對本領域技術人員而言，在不脫離本案之精神和範圍內，當可對本案作各種之更動與潤飾。基於前述實施例，所有對本案所作的更動與潤飾，亦涵蓋於本案之保護範圍內。For those skilled in the art, without departing from the spirit and scope of the case, various changes and modifications can be made to the case. Based on the foregoing embodiment, all changes and modifications made to this case are also covered by the scope of protection of this case.

100:顯示裝置 110:輸出電路 N1:第一節點 O1:第一輸出端 O2:第二輸出端 M1~M3:電晶體 C1:電容 VGH:第一電壓 VQ:第二電壓 VG:第三電壓 120:穩壓與重置電路 M4~M23:電晶體 ST:觸發訊號 RST:重置訊號 HC:上拉訊號 LC1~LC2:下拉訊號 300:方法 310~340:步驟 100: display device 110: output circuit N1: the first node O1: The first output terminal O2: second output M1~M3: Transistor C1: Capacitance VGH: first voltage VQ: second voltage VG: third voltage 120: Voltage stabilization and reset circuit M4~M23: Transistor ST: trigger signal RST: reset signal HC: pull up signal LC1~LC2: pull-down signal 300: method 310~340: Step

參照後續段落中的實施方式以及下列圖式，當可更佳地理解本案的內容： 第1圖為根據本案一些實施例繪示的驅動裝置之部分電路方塊圖； 第2圖為根據本案一些實施例繪示的驅動方法之訊號時序圖； 第3圖為根據本案一些實施例繪示的驅動方法之步驟流程圖； 第4圖為根據本案一些實施例繪示的驅動裝置之狀態示意圖； 第5圖為根據本案一些實施例繪示的驅動裝置之狀態示意圖； 第6圖為根據本案一些實施例繪示的驅動裝置之狀態示意圖；以及 第7圖為根據本案一些實施例繪示的驅動裝置之狀態示意圖。 With reference to the implementation in the subsequent paragraphs and the following diagrams, you can better understand the content of this case: Figure 1 is a partial circuit block diagram of a driving device according to some embodiments of the present invention; Figure 2 is a signal timing diagram of the driving method according to some embodiments of the present case; Figure 3 is a flowchart of the steps of the driving method according to some embodiments of the present case; Figure 4 is a schematic diagram of the state of the driving device according to some embodiments of the present case; Figure 5 is a schematic diagram showing the state of the driving device according to some embodiments of the present case; Figure 6 is a schematic diagram showing the state of the driving device according to some embodiments of the present case; and Fig. 7 is a schematic diagram showing the state of the driving device according to some embodiments of the present application.

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300:方法 300: method

310~340:步驟 310~340: Step

Claims (10)

一種驅動方法，適用於一顯示裝置，其中該顯示裝置包含一輸出電路及一穩壓與重置電路，其中該輸出電路包含一第一節點、一第一輸出端及一第二輸出端，其中該穩壓與重置電路耦接於該輸出電路並包含一第一下拉電路、一第一控制電路、一第二下拉電路及一第二控制電路，其中該驅動方法包含: 於一第一階段根據一觸發訊號將該輸出電路的該第一節點調整至一第一邏輯準位； 於該第一階段根據一下拉訊號及該第一節點之該第一邏輯準位對該第一控制電路及該第二控制電路內部之複數個節點進行放電； 於一第二階段根據一上拉訊號及該第一節點之該第一邏輯準位對該輸出電路的該第一輸出端及該第二輸出端進行放電；以及 於一第三階段根據一重置訊號控制該第一下拉電路以對該第一節點進行放電。 A driving method suitable for a display device, wherein the display device includes an output circuit and a voltage stabilization and reset circuit, wherein the output circuit includes a first node, a first output terminal and a second output terminal, wherein The voltage stabilization and reset circuit is coupled to the output circuit and includes a first pull-down circuit, a first control circuit, a second pull-down circuit, and a second control circuit, wherein the driving method includes: Adjusting the first node of the output circuit to a first logic level according to a trigger signal in a first stage; Discharging the first control circuit and the plurality of nodes in the second control circuit according to the pull-down signal and the first logic level of the first node in the first stage; Discharging the first output terminal and the second output terminal of the output circuit according to a pull-up signal and the first logic level of the first node in a second stage; and In a third stage, the first pull-down circuit is controlled according to a reset signal to discharge the first node. 如請求項1所述之驅動方法，其中於該第一階段根據該觸發訊號將該輸出電路之該第一節點調整至該第一邏輯準位之步驟包含： 根據該上拉訊號及該第一節點之該第一邏輯準位對該第一輸出端及該第二輸出端調整至該第一邏輯準位。 The driving method according to claim 1, wherein the step of adjusting the first node of the output circuit to the first logic level according to the trigger signal in the first stage includes: The first output terminal and the second output terminal are adjusted to the first logic level according to the pull-up signal and the first logic level of the first node. 如請求項1所述之驅動方法，其中於該第一階段根據該下拉訊號及該第一節點之該第一邏輯準位對該第一控制電路及該第二控制電路內部之該些節點進行放電之步驟包含: 於該第一階段根據該下拉訊號及該第一節點之該第一邏輯準位對該第一控制電路內部之一第二節點及一第三節點調整至一第二邏輯準位；以及 於該第一階段根據該下拉訊號及該第一節點之該第一邏輯準位對該第二控制電路內部之一第四節點及一第五節點調整至該第二邏輯準位。 The driving method according to claim 1, wherein in the first stage, the nodes in the first control circuit and the second control circuit are performed according to the pull-down signal and the first logic level of the first node The steps of discharging include: Adjusting a second node and a third node in the first control circuit to a second logic level according to the pull-down signal and the first logic level of the first node in the first stage; and In the first stage, a fourth node and a fifth node in the second control circuit are adjusted to the second logic level according to the pull-down signal and the first logic level of the first node. 如請求項3所述之驅動方法，其中於該第二階段藉根據該上拉訊號及該第一節點之該第一邏輯準位對該第一輸出端及該第二輸出端進行放電之步驟包含: 於該第二階段根據該上拉訊號及該第一節點之該第一邏輯準位將該第一輸出端及該第二輸出端調整至該第二邏輯準位。 The driving method according to claim 3, wherein in the second stage, the first output terminal and the second output terminal are discharged according to the pull-up signal and the first logic level of the first node Include: In the second stage, the first output terminal and the second output terminal are adjusted to the second logic level according to the pull-up signal and the first logic level of the first node. 如請求項4所述之驅動方法，其中於該第三階段根據該重置訊號控制該第一下拉電路以對該第一節點進行放電之步驟包含: 於該第三階段據該重置訊號控制該第一下拉電路以對該第一節點調整至該第二邏輯準位。 The driving method according to claim 4, wherein the step of controlling the first pull-down circuit to discharge the first node according to the reset signal in the third stage includes: In the third stage, the first pull-down circuit is controlled according to the reset signal to adjust the first node to the second logic level. 一種顯示裝置，包含: 一輸出電路，包含一第一節點、一第一輸出端及第二輸出端；以及 一穩壓與重置電路，耦接於該輸出電路並包含一第一下拉電路、一第一控制電路、一第二下拉電路及一第二控制電路； 其中該輸出電路用以於一第一階段根據一觸發訊號將該第一節點調整至一第一邏輯準位；其中該第一控制電路及該第二控制電路用以於該第一階段根據一下拉訊號及該第一節點之該第一邏輯準位對該第一控制電路及該第二控制電路內部之複數個節點進行放電；其中該輸出電路用以於一第二階段根據一上拉訊號及該第一節點之該第一邏輯準位對該第一輸出端及該第二輸出端進行放電；其中該第一下拉電路用以於該第三階段根據一重置訊號對該第一節點進行放電。 A display device comprising: An output circuit including a first node, a first output terminal and a second output terminal; and A voltage stabilization and reset circuit, coupled to the output circuit and including a first pull-down circuit, a first control circuit, a second pull-down circuit, and a second control circuit; The output circuit is used to adjust the first node to a first logic level according to a trigger signal in a first stage; wherein the first control circuit and the second control circuit are used to adjust the first node to a first logic level in the first stage according to the following The pull signal and the first logic level of the first node discharge the first control circuit and the plurality of nodes in the second control circuit; wherein the output circuit is used for a pull-up signal in a second stage And the first logic level of the first node to discharge the first output terminal and the second output terminal; wherein the first pull-down circuit is used to discharge the first output terminal and the second output terminal in the third stage according to a reset signal The node is discharged. 如請求項6所述之顯示裝置，其中該輸出電路用以於該第一階段根據該上拉訊號及該第一節點之該第一邏輯準位將該第一輸出端及該第二輸出端調整至該第一邏輯準位。The display device according to claim 6, wherein the output circuit is used for the first output terminal and the second output terminal according to the pull-up signal and the first logic level of the first node in the first stage Adjust to the first logic level. 如請求項7所述之顯示裝置，其中該第一控制電路包含一第二節點及一第三節點，並用以於該第一階段根據該下拉訊號及該第一節點之該第一邏輯準位對該第二節點及第三節點調整至一第二邏輯準位，其中該第二控制電路包含一第四節點及一第五節點，並用以於該第一階段根據該下拉訊號及該第一節點之該第一邏輯準位對該第四節點及該第五節點調整至該第二邏輯準位。The display device according to claim 7, wherein the first control circuit includes a second node and a third node, and is used in the first stage according to the pull-down signal and the first logic level of the first node The second node and the third node are adjusted to a second logic level, wherein the second control circuit includes a fourth node and a fifth node, and is used in the first stage according to the pull-down signal and the first The first logic level of the node is adjusted to the second logic level for the fourth node and the fifth node. 如請求項8所述之顯示裝置，其中該輸出電路用以於該第二階段根據該上拉訊號及該第一節點之該第一邏輯準位對該第一輸出端及該第二輸出端調整至該第二邏輯準位。The display device according to claim 8, wherein the output circuit is used for the first output terminal and the second output terminal according to the pull-up signal and the first logic level of the first node in the second stage Adjust to the second logic level. 如請求項9所述之顯示裝置，其中該第一下拉電路用以於該第三階段據該重置訊號對該第一節點調整至該第二邏輯準位。The display device according to claim 9, wherein the first pull-down circuit is used to adjust the first node to the second logic level according to the reset signal in the third stage.
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TWI625711B (en) * 2017-08-29 2018-06-01 友達光電股份有限公司 Gate driving circuit
TWI699744B (en) * 2019-07-16 2020-07-21 友達光電股份有限公司 Driving method, shift register, and display device using the same
CN111312184A (en) * 2019-07-30 2020-06-19 友达光电股份有限公司 Shift register and related display device

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