TW201438198A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device includes a plurality of lower electrodes which are arranged along a first direction parallel to a surface of a semiconductor substrate and a second direction perpendicular to the first direction and which extend in a third direction perpendicular to the surface of the semiconductor substrate; a first support film disposed at upper end portions of the lower electrodes and having a plurality of first openings; a second support film disposed at intermediate portions of the lower electrodes with respect to the third direction and having a plurality of second openings; a capacitor insulating film covering surfaces of the lower electrodes; and an upper electrode covering the surface of the capacitor insulating film. The first and the second openings have the same pattern, are matched in position in plan view, and are arranged at positions overlapping in the third direction. Among the lower electrodes, four lower electrodes adjacent to one another in the second direction are grouped into a unit lower electrode group. Each of the first and the second openings are arranged so that parts of eight lower electrodes contained in two unit lower electrode groups adjacent to each other in the first direction are collectively positioned in the opening.

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of manufacturing the same, and, in particular, to a semiconductor device having a structure supporting a lower electrode of a crown-shaped capacitor by a plurality of support films, and a method of manufacturing the same.

The related semiconductor device has a plurality of insulating beams, and the manufacturing method thereof is to sequentially form a plurality of insulating beams from the lower layer side (for example, refer to Patent Document 1).

Specifically, a first insulating beam film is formed on the first sacrificial insulating film, and the formed first insulating beam film is selectively etched to form a first insulator beam having a desired pattern. Next, a second sacrificial insulating film and a second insulating beam film are sequentially formed on the first insulator beam and the exposed first sacrificial insulating film. Next, similarly to the case of the first insulating beam film, the second insulating beam film is selectively etched as the second insulator beam having a desired pattern.

Thereafter, a through hole penetrating through the second insulator beam, the second sacrificial insulating film, and the first insulator beam and the first sacrificial insulating film is formed to be coated A conductive film that becomes an electrode at the lower portion of the capacitor is formed on the inner surface of the through hole. The formed conductive film is connected to the second insulator beam and the first insulator beam exposed in the through hole.

Thereafter, even if the second sacrificial insulating film and the first sacrificial insulating film are removed, the lower electrode is supported by the second insulator beam and the first insulator beam. Thereby, a crown-type capacitor having a higher aspect ratio can be formed by preventing collapse of the lower electrode or the like.

[Previous Technical Literature] [Patent Document]

Patent Document 1: Japanese Patent Laid-Open Publication No. 2003-142605

A method of manufacturing a related semiconductor device is to form a plurality of insulator beams from each of the lower layers, and then form a through hole. Here, when there is an offset between the pattern position of the plurality of insulator beams and the formation position of the through holes, the lower electrode formed in the through holes generates any or all of the insulator beams that are not connected to the plurality of insulator beams. problem.

Further, even if the plurality of lower electrodes are connected to the insulator beam as a whole, and the thickness of the lower electrode must be thinned by the miniaturization of the semiconductor device, the mechanical strength of the lower electrode itself is lowered, and the insulator beam has The pressure is caused by the distortion of the lower electrode and the short circuit of the adjacent lower electrode.

Further, when the diameter of the through-hole itself is reduced by the miniaturization of the semiconductor device, the coverage of the lower electrode is remarkably found, and the through-hole is closed by the lower electrode itself formed in the opening of the through-hole. Therefore, the capacitor insulating film or the upper electrode cannot be formed inside the through hole, and there is a problem that the capacitor cannot be formed.

The present invention is intended to provide a semiconductor device and a method of manufacturing the same that avoids the occurrence of the above problems.

A semiconductor device according to an embodiment of the present invention includes: being arranged on the semiconductor substrate along a first direction parallel to a surface of the semiconductor substrate and a second direction perpendicular to the first direction, and extending in a direction perpendicular to the foregoing a plurality of lower electrodes in the third direction on the surface of the semiconductor substrate, and a first support film having a plurality of first openings disposed at positions corresponding to the upper ends of the plurality of lower electrodes, and arranged in the third direction a second support film having a plurality of second openings, a capacitor insulating film covering the surface of the plurality of lower electrodes, and a top electrode covering the surface of the capacitor insulating film at a position corresponding to a middle portion of the lower plurality of electrodes, the plural The first opening and the second plurality of openings are planarly integrated in the same pattern, and are disposed at positions overlapping the third direction, and each of the plurality of first openings and the plurality of second openings Among the plurality of lower electrode portions, four lower electrodes adjacent to the second direction are adjacent to the front portion as a unit lower electrode group 8 lower electrodes included in the first direction of the lower electrode group of 2 units Each of the portions is configured to be positioned within the first opening and the second opening.

A semiconductor device according to another aspect of the present invention includes: a plurality of lower electrodes extending in a third direction perpendicular to a surface of the semiconductor substrate; and a first electrode having a rectangular shape disposed at a position corresponding to an upper end portion of the lower plurality of electrodes a first support film having an opening, a second support film having a rectangular second opening, and a capacitive insulating film covering the surface of the plurality of lower electrodes, at a position intermediate the third direction of the plurality of lower electrodes; And covering the upper surface of the surface of the capacitor insulating film, the plurality of lower electrodes, the capacitor insulating film and the upper electrode forming a capacitor group, wherein the capacitor group is disposed in a plane view and disposed on a side of the first opening One of the outer peripheral side surfaces of the lower electrode is connected to the first capacitor of the first support film, and the other one of the outer peripheral side surfaces of the lower electrode that is not exposed in the first opening is connected to the first support film. a second capacitor having a top surface of the lower electrode constituting the first capacitor and the first support film Becomes the upper surface of the first flattened, and is compared with the second low above the top of the first.

A semiconductor device according to still another aspect of the present invention includes a lower electrode extending over a contact plug disposed on a semiconductor substrate and extending in a third direction perpendicular to a surface of the semiconductor substrate, and a top electrode connected to the lower electrode a first support film on the outer circumference of the portion, a second support film connected to the outer periphery of the intermediate portion in the third direction of the lower electrode, and a capacitor insulating film covering the surface of the lower electrode, and covering the capacitor a lower electrode on the surface of the edge film, the lower electrode, the capacitor insulating film and the upper electrode forming a capacitor, wherein the capacitor includes a lower capacitor positioned between the contact plug upper surface and the second support film, and a position of the capacitor The upper capacitor between the lower surface of the second support film and the upper surface of the first support film has a thickness of the lower electrode at a position close to the first support film of the upper capacitor as T1a, and is close to The film thickness of the lower electrode at the position of the second support film of the upper capacitor is T2a, and the film thickness of the lower electrode at a position close to the second support film of the lower capacitor is T3, which is close to The film thickness of the lower electrode at the position of the contact plug of the lower capacitor is T4, and the above T2a is the smallest.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes sequentially forming a stop tantalum nitride film, a first sacrificial film, a first insulating film, a second sacrificial film, and a second insulating film on a semiconductor substrate. And a process of forming the second insulating film, the second sacrificial film, the first insulating film, the first sacrificial film, and the cylinder hole for stopping the tantalum nitride film, and the process of widening the cylinder bore. And a process of forming a film of the lower electrode material integrally formed on the inner surface of the cylinder bore, and a process of forming a protective film on the film of the lower electrode material, and forming at least a portion of the protective film to form the cylinder bore a first opening pattern in which the surface of the second insulating film on one surface of the surface is connected to the lower electrode material film, and a first opening is formed in the second insulating film as a mask to form a first support Engineering of the film, and the process of removing the second sacrificial film by the first opening, and passing through the front The first support film is formed as a second support having the same pattern as the first opening in the first insulating film as an isotropic dry etching of the mask, and the second support film is formed and removed from the first support film. a lower electrode material film is formed in the cylinder bore to form an outer peripheral surface of the first support film and the lower electrode of the second support film, and the first sacrificial film is completely removed by the second opening. The process of forming the second opening is performed by excavating the upper surface of the first support film and the upper surface of the lower electrode while retracting the upper surface of the lower electrode.

According to the present invention, among the plurality of lower electrodes arranged in a first direction parallel to the surface of the semiconductor substrate and in the second direction perpendicular to the first direction, four lower portions adjacent to the second direction are formed. The electrode is arranged in the first direction and is adjacent to the two unit lower electrode groups as the unit lower electrode group, and the opening pattern is formed to be exposed, so that the pressure of the support film itself can be relaxed and the distortion of the lower electrode can be avoided. And to prevent the problem of short circuit between the adjacent lower electrodes.

Further, since the film thickness of the lower electrode of the upper portion of the capacitor on the first support film is set to be the thinnest at the position close to the first support film, the side surface and the upper surface of the lower electrode of the upper capacitor are retracted, and the film thickness can be enlarged. The diameter of the opening of the lower electrode can be avoided by blocking the capacitor.

1‧‧‧Semiconductor substrate

2‧‧‧ buried gate electrode

3‧‧‧Gap insulation film

4‧‧‧ impurity diffusion layer

5‧‧‧1st interlayer insulating film

6‧‧‧Contact plug

7‧‧‧ peripheral circuits

8‧‧‧Stop the tantalum nitride film

9‧‧‧1st sacrificial film

10‧‧‧2nd support film

10a‧‧‧1st insulating film

10b‧‧‧The top of the 2nd support film (1st insulating film)

10c‧‧‧ below the second support film (first insulating film)

11‧‧‧1st photomask

12‧‧‧2nd opening

13‧‧‧2nd sacrificial film

14‧‧‧1st support film

14a‧‧‧2nd insulating film

14b‧‧‧Top of the first support film (second insulation film) after etch back

14c‧‧‧Under the first support film (second insulation film)

14d‧‧‧Top of the first support film (second insulation film) before eclipse

15‧‧‧hard mask film

15a‧‧‧Amorphous film

15b‧‧‧Oxide film

15c‧‧‧Amorphous carbon film

16‧‧‧hard mask film

17‧‧‧Anti-reflection film

18‧‧‧Organic mask film

19‧‧‧ cylinder hole pattern

20‧‧‧ cylinder bore

21a, 21b‧‧‧ lower electrode material film

21‧‧‧ lower electrode

21c, 21d, 21e‧‧‧ lower electrode section

21cc, 21dd‧‧‧ above the lower electrode

22,22a‧‧‧Protective film

23‧‧‧Photomask

24‧‧‧1st opening

24a‧‧‧ peripheral openings

OP11~OP61‧‧‧1st opening

OP12~OP62‧‧‧2nd opening

C2, F2‧‧‧ lower electrode

C2a, F2a‧‧‧ Part 1

C2b, F2b‧‧‧ Part 2

C2aa‧‧‧1st top

C2bb‧‧‧2nd top

25‧‧‧Capacitive insulation film

26‧‧‧Upper electrode

27‧‧‧Second interlayer insulating film

28‧‧‧through hole plug

29‧‧‧Upper wiring

30a‧‧‧1st hole

30b‧‧‧2nd hole

1A is a cross-sectional view showing a main configuration of a semiconductor device according to a first embodiment of the present invention.

Fig. 1B is a plan view showing the layout of a semiconductor device according to a first embodiment of the present invention.

Figure 1C is an enlarged cross-sectional view of the range MC shown in the cross-sectional view of Figure 1A.

Figure 1D is an enlarged cross-sectional view of the range MD shown in the cross-sectional view of Figure 1A.

Figure 1E is an enlarged cross-sectional view of capacitor C2 shown in the cross-sectional view of Figure 1A.

Fig. 1F is an enlarged cross-sectional view of the capacitor F2 shown in the cross-sectional view of Fig. 1A.

Fig. 2A is a cross-sectional view showing the construction of the semiconductor device according to the first embodiment of the present invention shown in Fig. 1 in the middle of the line A-A' shown in Fig. 2B.

Figure 2B is a plan view corresponding to the cross-sectional view of Figure 2A.

Figure 3 is a cross-sectional view of the position corresponding to the line A-A' in Figure 2B for the purpose of illustrating the drawing continuing through the process of Figure 2A.

Fig. 4A is a cross-sectional view of the position of Fig. 2B corresponding to the line A-A' for explaining the drawing continuing the process of Fig. 3.

Fig. 4B is a view in which the range MD of Fig. 4A is enlarged.

Figure 5A is a diagram for illustrating the operation of Figure 4A, in Figure 5B A-A' line profile.

Figure 5B is a plan view corresponding to the cross-sectional view of Figure 4A.

Fig. 5C is a diagram in which the range MC of Fig. 5A is enlarged.

Fig. 5D is a diagram in which the range MD of Fig. 5A is enlarged.

Fig. 6A is a cross-sectional view taken at a position corresponding to the line A-A' in Fig. 5B for the purpose of explaining the drawing continuing the process of Fig. 5A.

Fig. 6B is a diagram in which the range MC of Fig. 6A is enlarged.

Fig. 7A is a cross-sectional view taken along line A-A' of Fig. 7B for the purpose of explaining the drawing of the process continued from Fig. 6A.

Figure 7B is a plan view corresponding to the cross-sectional view of Figure 7A.

Fig. 7C is a diagram in which the range MC of Fig. 7A is enlarged.

Fig. 8A is a cross-sectional view of the position corresponding to the line A-A' in Fig. 7B for the purpose of explaining the drawing continuing the process of Fig. 7A.

Fig. 8B is a view in which the range MC of Fig. 8A is enlarged.

Figure 9A is a cross-sectional view of the position corresponding to the line A-A' in Figure 7B for the purpose of illustrating the drawing continuing through the process of Figure 8A.

Fig. 9B is a view in which the range MC of Fig. 9A is enlarged.

Fig. 9C is a diagram in which the range MD of Fig. 9A is enlarged.

Figure 10 is a cross-sectional view of the position corresponding to the line A-A' in Figure 7B for the purpose of illustrating the drawing continuing through the process of Figure 9A.

Fig. 11 is a sectional view showing the construction of an experimental example reviewed by the inventors.

Figure 12 is a cross-sectional view of the work for continuing the construction of Figure 11.

Figure 13 is a cross-sectional view of the construction for illustrating the work continued in Figure 12.

Figure 14 is a cross-sectional view of the engineering for continuing the construction of Figure 13.

Figure 15A is a cross-sectional view of the work for continuing the construction of Figure 14.

Fig. 15B is an enlarged view of the range MD shown in Fig. 15A.

Figure 16 is a cross-sectional view of the work for continuing the construction of Figure 15A.

Figure 17 is a cross-sectional view of the work for continuing the construction of Figure 16.

Figure 18 is a cross-sectional view of the engineering for continuing the construction of Figure 17.

Figure 19A is a cross-sectional view of the work for continuing the construction of Figure 18.

Fig. 19B is an enlarged view of the range MD shown in Fig. 19A.

Figure 20 is a cross-sectional view of the work for continuing the construction of Figure 19A.

Figure 21 is a cross-sectional view of the work for continuing the construction of Figure 20.

Figure 22 is a cross-sectional view of the engineering for continuing the construction of Figure 21.

Fig. 23 is an enlarged view of the range MD shown in Fig. 21.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, in order to make the understanding of the present invention easy, an experimental example of a method of manufacturing a capacitor implemented by the inventors will be described with reference to FIGS. 11 to 23 .

(Experimental example)

Fig. 11 shows an in-transit process of a method of manufacturing a semiconductor device constituting a DRAM (Dynamic Random Access Memory). The DRAM has a memory cell range MCA in which a plurality of capacitors are formed and a peripheral circuit range PCA.

On the surface of the semiconductor substrate 1 of the memory cell range MA, a plurality of buried gate electrodes 2 and a gap insulating film 3 covering the upper surface of the buried gate electrode 2 are formed. The semiconductor substrate 1 adjacent to the gap insulating film 3 is formed with an impurity diffusion layer (hereinafter, a diffusion layer) 4 serving as a source or a drain. The first interlayer insulating film 5 formed on the semiconductor substrate 1 is formed and connected to a plurality of (capacitor) contact plugs 6 of the diffusion layer 4. A bit line (not shown) is formed inside the first interlayer insulating film 5. A peripheral circuit 7 is formed on the first interlayer insulating film 5 of the peripheral circuit range PA. The first interlayer insulating film 5 is covered, the contact plug 6 is formed, and the tantalum nitride film 8 is formed (stopped) in the peripheral circuit 7. The first sacrificial film 9 and the first insulating film 10a are formed on the tantalum nitride film 8. The first photomask film 11 having the pattern of the second opening 12 is formed on the first insulating film 10a via the first photolithography process.

Next, as shown in FIG. 12, the first insulating film 10a is etched using the first photomask film 11 as a mask, and the second support film 10 having the second opening 12 is formed.

Next, as shown in FIG. 13, the second sacrificial film 13, the second insulating film 14a, the first hard mask film 15, and the second hard mask are formed so as to cover the second support film 10 and the first sacrificial film 9. Film 16, anti-reflection film 17. The second photomask film 18 having the cylinder hole pattern 19 is formed on the anti-reflection film 17 via the second photolithography process.

Next, as shown in FIG. 14, the second mask film 18 is used as a mask, and the anti-reflection film 17, the second hard mask film 16, the first hard mask film 15, and the second insulating film 14a are sequentially etched. The cylinder hole pattern 19 is transferred to the second insulating film 14a. After the hard mask films 15 and 16 remaining on the second insulating film 14a are removed, the second insulating film 14a having the cylinder hole pattern 19 is formed as a mask, and the second sacrificial film 13 is sequentially etched, and the second supporting film is etched. 10. The first sacrificial film 9, the tantalum nitride film 8, forms a cylinder bore 20 that reaches the contact plug 6.

Next, as shown in FIG. 15A, the lower electrode material film 21a is formed integrally in the cylinder bore 20. Fig. 15D is a configuration in which the opening range MD of one of the cylinder bores 20 of Fig. 15A is enlarged. The minimum processing dimension F defined by the resolution limit of the photolithography technique is such that, in the DRAM of the F25 nm generation of 25 nm, the cylinder hole 20 is formed to have a diameter L1 of 50 nm and a depth H1 of 1500 nm. Claim. In the case where the lower electrode material film 21a is formed in the cylinder bore 20, when a specific film thickness T2 is to be formed on the inner surface of the cylinder bore 20, it is formed to have an end portion which is easily formed into a film. The film material film 21a is formed under the film thickness T7. On the upper surface of the second insulating film 14a, a portion of the lower electrode material film 21a having a thickness smaller than T7 is formed. That is, it is difficult for the cylinder hole 20 having a high aspect ratio (~30) to have a good coating property. Therefore, in the subsequent process, when the capacitor insulating film is formed on the lower electrode 21, the upper end opening portion is closed, and the upper portion cannot be opened. The electrode is formed in the cylinder bore 20. That is, there is a problem that a capacitor cannot be formed. This problem is not caused when the diameter of the cylinder bore 20 is relatively large, but it is remarkable in the semiconductor device of the generation in which the diameter of the cylinder bore 20 which is miniaturized is reduced.

Next, as shown in FIG. 16, the lower electrode material film 21a is covered, and the protective film 22a is formed to close the opening. The mask film 23 having the pattern of the first opening 24 and the peripheral opening 24a is formed on the protective film 22a via the third photolithography process.

Next, as shown in FIG. 17, the mask film 23 is used as a mask, and the protective film 22a exposed in the first opening 24 and the peripheral opening 24a is etched. Thereby, the protective film 22 which has a 1st opening pattern is formed. Further, the upper and lower electrode material films 21a are exposed by etching, and the second insulating film 14a is exposed in the first opening 24 and the peripheral opening 24a.

Next, as shown in FIG. 18, the second insulating film 14a exposed in the first opening 24 and the peripheral opening 24a is etched. In this etching, the protective film 22 is also etched and destroyed. As a result, the upper surface of the second sacrificial film 13 is exposed in the first opening 24 and in the peripheral opening 24a. Further, the lower electrode material film 21b is exposed in a range other than the first opening 24 and the peripheral opening 24a. Further, the first support film 14 that connects the upper end portions of the lower electrode (21) is formed.

Next, as shown in FIG. 19A, the lower electrode material film 21b is formed on the lower surface of the first support film 14 in a range other than the first opening 24 and the peripheral opening 24a. Thereby, the lower electrode 21 is formed independently of the inner cylinder hole 20. Lower electrode formed in a range other than the first opening 24 The 21 series includes lower electrode portions 21c and 21d which are in contact with the first support film 14 and which are flattened on the upper surface of the first support film 14. Further, a portion of the lower electrode 21 formed in the first opening 24 includes the lower electrode portion 21c which is in contact with the first support film 14 and which is flattened on the upper surface of the first support film 14, and is not in contact with the first electrode 21 The support film 14 has an upper surface lower electrode portion 21e at a position lower than the upper surface of the first support film 14.

Fig. 19B is a configuration in which the opening range MD of one cylinder bore 20 in the range other than the first opening 24 in Fig. 19A is enlarged. At the stage of Fig. 15D, the lower electrode material film 21a formed on the upper surface of the second insulating film 14a is removed, and the upper surface 14b of the first support film 14 and the upper surfaces 21cc and 21dd of the lower electrode are each flattened. At this time, the upper electrode side portions 21c, 21d having a film thickness T2 thicker than the film thickness T2 are formed on the upper end side surface of the first support film 14 in the cylinder bore 20.

Next, as shown in FIG. 20, the etching solution is diffused from the first opening 24 and the peripheral opening 24a, and the second sacrificial film 13 and the first sacrificial film 9 are completely removed. Thereby, the upper surface 14b and the lower surface 14c of the first support film 14 that connects the upper end portions of the lower electrodes 21 are exposed, and the upper surface 10b and the lower surface 10c of the second support film 10 that connects the intermediate portions of the lower electrodes 21 are exposed. . Further, the upper surface of the tantalum nitride film 8 is exposed. As a result, a continuous first cavity 30a is formed on the outer side of the plurality of lower electrodes 21 between the first support film 14 and the second support film 10, and the second support film 10 and the tantalum nitride are positioned. A continuous second cavity 30b is formed on the outer side of the plurality of lower electrodes 21 between the films 8. And each The inner and outer surfaces of the lower electrode 21 that are not in contact with the first support film 14 and the second support film 10 are exposed to the voids 30a and 30b.

Next, as shown in FIG. 21, a capacitive insulating film is formed on the surface of the structure formed by the first support film 14 and the second support film 10 on the lower electrode 21, that is, the entire surface including the voids 30a and 30b (Fig. 23, 25). . Next, the upper electrode 26 is formed to cover the surface of the capacitor insulating film.

Next, as shown in FIG. 22, the second interlayer insulating film 27, the via plug 28, and the upper wiring 29 are formed. As described above, a capacitor having the crown-shaped lower electrode 21 is formed.

In the present experimental example, the problems described below were generated.

First, the formation of the pattern of the second opening 12 and the formation of the cylinder bore pattern 19 are formed using individual photolithography. Therefore, the positional adjustment offset of each pattern occurs, and in the extreme case, the cylinder hole 20 is formed at a position shifted from the second opening 12, and the lower electrode 21 is not connected to the second support film 10. In this case, the second support film 10 does not function as a support, and the lower electrode 21 is twisted.

Second, the opening of the cylinder bore is closed and there is a problem that the capacitor cannot be formed. Fig. 23 is an enlarged view showing the range MD at the stage of Fig. 21. On the upper end side surface of the first support film 14, a lower electrode portion 21c, 21d having a thickness T7 is formed, and an opening portion of the cylinder hole 20 is narrowed. When the capacitor insulating film 25 is formed, the opening portion is closed, and the upper electrode 26 is not provided. A state formed in the cylinder bore 20. The inside of the cavities 30a and 30b positioned on the outer side of the cylinder bore 20 functions as a capacitor because the capacitor insulating film 25 and the upper electrode 26 are formed. But for the internal system of the cylinder bore 20 Only the capacitor insulating film 25 is formed, and the upper electrode 26 is not formed, and does not function as a capacitor. It is impossible to maintain a capacitor necessary for DRAM operation and becomes a poor capacitor.

(First embodiment of the present invention)

Hereinafter, a first embodiment of the present invention will be described with reference to Figs. 1A to 10 .

(semiconductor device)

The configuration of the semiconductor device of the present embodiment will be described with reference to Figs. 1A to 1F. The semiconductor device of this embodiment constitutes a DRAM.

Fig. 1A is a cross-sectional view taken along the line A-A' of the plan view shown in Fig. 1B which will be described later. Similarly to the above-described experimental example, the DRAM has a memory cell range MCA in which a plurality of capacitors are formed and a peripheral circuit range PCA. A plurality of buried gate electrodes 2 and a gap insulating film 3 covering the upper surface of the buried gate electrode 2 are disposed on the surface of the semiconductor substrate 1 positioned on the memory cell range MCA. The semiconductor substrate 1 adjacent to the gap insulating film 3 is provided with an impurity diffusion layer (hereinafter, a diffusion layer) 4 serving as a source or a drain of the transistor. The first interlayer insulating film 5 penetrating through the semiconductor substrate 1 is disposed, and is connected to a plurality of contact plugs 6 of the diffusion layer 4. A bit line (not shown) is formed inside the first interlayer insulating film 5. A peripheral circuit 7 is disposed on the first interlayer insulating film 5 of the peripheral circuit range PCA. The first interlayer insulating film 5 is covered, the contact plug 6 is placed, and the tantalum nitride film 8 is stopped in the peripheral circuit 7. Through stop nitriding The ruthenium film 8 is formed by a specific arrangement pitch from eight lower electrodes 21 of A2 to H2 connected to the upper surfaces of the respective contact plugs 6 in the Y direction (first direction) parallel to the surface of the semiconductor substrate 1. Configuration. However, in the following description, the symbols A2 to H2 described as the lower electrode 21 are described as the symbols of the corresponding capacitors. Further, there are cases in which the symbols A2 to H2 are described as the lower electrodes.

The upper end portions of the lower electrodes 21 are connected to each other by the first support film 14. In addition, the second support film 10 is disposed in the middle in the Z direction (third direction) which is a direction perpendicular to the surface of the semiconductor substrate 1 of each lower electrode 21, and the lower electrodes 21 are connected to each other. The second support film 10 is formed in the same pattern as the first support film 14 and has a film thickness thinner than that of the first support film 14. The film thickness of the second support film 10 is set to be in the range of 1/10 to 1/2 of the film thickness of the first support film 14. For example, when the film thickness of the first support film 14 is 100 nm, the film thickness of the second support film 10 can be 10 to 50 nm. Further, the second support film 10 is higher than half the height of the lower electrode 21, and is disposed at a position lower than 1/4 from the upper end. For example, when the height H1 of the lower electrode 21 is 1600 nm, it is disposed deeper than 400 nm from the upper end and shallower than 800 nm.

The first support film 14 has first openings OP21 and OP51. In addition, the second support film 10 has the same pattern as the first openings OP21 and OP51, and has the second openings OP22 and OP52 at positions where the positions are integrated in the Z direction and overlap. Lower electrode C2, D2, G2, H2 A part of the upper portion is formed to be exposed in the first openings OP21 and OP51. For example, when focusing on the lower electrode C2, in the plan view from the Z direction, the first portion C2a having the upper surface in the first opening OP21 is not positioned, and the upper portion is located in the first opening OP21. Part 2 C2b. The outer portion of the first portion C2a is connected to the first support film 14 and the upper surface is flattened to the upper surface of the first support film 14, but the second portion C2b is not connected to the first support film 14, and the upper surface is The upper surface 14b of the first support film 14 is low and is higher than the lower surface 14c. In this manner, a capacitor having a second upper lower electrode which is lower than the upper surface of the first upper support film 14 and the upper surface of the first support film 14 is formed as a first capacitor. The lower electrode constituting the first capacitor has a ring-shaped upper surface in a plan view, and the first upper surface of the lower electrode is a portion of the lower electrode located outside the first opening, and the second upper surface is the upper surface of the lower electrode. It is positioned on the other part of the lower electrode in the first opening.

On the other hand, the upper surfaces of the lower electrodes A2, B2, E2, and F2 are in plan view, and are formed not in the openings OP21 and OP51. For example, when focusing on the lower electrode F2, the portion F2a and the portion F2b each having no upper surface in the opening OP51 are included. The upper end portion of the lower electrode in the OP 51 is not connected to the opening OP21. The upper end portion of the lower electrode in the OP 51 is connected to the first support film 14 over the entire circumference, and the upper surface is formed to be flattened with the upper surface of the first support film 14. A capacitor having the lower electrode as described above is used as the second capacitor. That is, the memory cell of the present embodiment is configured by a first capacitor and a second capacitor.

Each of the lower electrodes is formed of a crown structure, and the inner and outer surfaces of the lower electrodes, the upper and lower surfaces of the first support film 14, the upper and lower surfaces of the second support film 10, and the upper surface of the tantalum nitride film 8 are stopped. The capacitor insulating film is coated, and the surface of the capacitor insulating film is covered with the upper electrode 26. The second interlayer insulating film 27 is disposed to cover the upper electrode 26. The second interlayer insulating film 27 is inserted through the via plug 28 that is also connected to the upper electrode 26, and the upper layer wiring 29 is connected to the upper surface of the via plug 28 to form a DRAM. The lower electrode 21 of the capacitor constituting the crown structure of the present embodiment is constituted by a cylinder having a bottom surface, and the upper end surface has a ring shape in plan view.

Next, reference is made to the plan view of Fig. 1B. Fig. 1B is a view showing a portion of the memory cell range MCA and the peripheral circuit range PCA taken out for convenience of explanation. Fig. 1B is a plan view showing a state in which the upper surface of the first support film 14 is exposed. The memory cell range MCA is provided with a capacitor lower electrode (shown in a circle) corresponding to a plurality of X-directions (second directions) arranged in the Y direction and perpendicular to the Y direction. For example, the lower electrodes of A1 to A8 are arranged for the X1 row, and the lower electrodes of A2 to H2 shown in FIG. 1A are arranged for the Y2 row. FIG. 1B shows the arrangement layout of the first openings OP11, OP21, OP31, OP41, OP51, and OP61. The second opening is the same as the first opening and has the same layout, and the description thereof will be omitted. However, the following description is the same for the second opening (OP12, OP22, OP32, OP42, OP52, OP62). By.

In plan view, each first opening is parallel to half The surface of the conductor substrate has a long side in the X direction, and is formed in a rectangular shape having a short side in the Y direction perpendicular to the X direction. When focusing on the Y2 column corresponding to the cross-sectional view of FIG. 1A, the upper lower electrode A2, B2, E2, F2 is not located in the first opening, and the lower electrode C2 is provided in the upper portion of the first opening. , D2, G2, and H2 are regularly arranged in the Y direction. For example, when focusing on the first opening OP21, the patterns of the first openings OP21 are arranged on a straight line, and are arranged at equal intervals in a plurality of lower electrodes in the Y direction and the X direction, and are adjacent to the lower four portions in the X direction. The electrodes are arranged in the Y direction as a unit lower electrode group, and one of the upper portions of the two unit lower electrode groups adjacent to each other is formed so as to be positioned in the first opening. That is, one of the upper portions of the first unit lower electrode group formed by the four lower electrodes C1, C2, C3, and C4 adjacent to the X direction, and the four lower electrodes D1, D2, and D3 adjacent to each other in the Y direction. One of the upper portions of the second unit lower electrode group formed by D4 has a configuration in which the total position is in the first opening.

Then, in the first opening, four lower electrodes including the position on the long side of the first opening and two in the diameter direction, and having 1/2 of the upper surface of the lower electrode of the planar view ring shape, and the position are included. At the corner of the first opening, four lower electrodes having a quarter of the upper surface of the annular lower electrode are planarly viewed. In other words, C2, C3, D2, and D3 are located at 1/2 of the upper surface of the ring-shaped lower electrode, and are located in the first opening OP21. Similarly, C1, C4, D1, and D4 are 1/1 of the upper electrode of the ring shape. 4 is formed in the first opening OP21.

In the plane view, when the diameter of each lower electrode is taken as W3, when the distance between the two adjacent lower electrodes is W4, the arrangement pitch of the lower electrodes is defined by W3+W4, and the width of the first opening in the X direction, that is, the width W1 of the long side is equal to the lower electrode. Configure the spacing by 3 times. Further, the width in the Y direction, that is, the width W2 of the short side is equal to W3 + W4, that is, the lower electrode arrangement pitch. The interval between the first openings adjacent to the X direction is also equal to the arrangement pitch W2 of the lower electrodes. The interval between the first openings arranged adjacent to the Y direction is also equal to the arrangement pitch W2 of the lower electrodes. However, the first opening system adjacent to the plural in the Y direction is not arranged on the straight line, but is arranged in a zigzag manner of 2/3 (two times the lower electrode arrangement pitch) of the offset W1 in the X direction. For example, in the first opening OP51, the first opening OP41 adjacent to the Y direction is disposed at a position twice the offset W2 in the X direction. Further, the first opening OP31 adjacent to the Y direction is shifted by 2 times in the X direction by W2. When the viewpoint is changed, the first openings arranged in the Y direction at one position are arranged in a straight line and arranged. The center line of the first opening in the X direction is not intersected with the first opening that is adjacent to the first direction in the Y direction, and is configured to coincide with the center line of the first opening disposed in the Y direction at one position in the X direction.

As described above, the first support film 14 and the second support film 10 of the present embodiment are not separated into a linear shape, and constitute a continuous beam that is connected to all of the lower electrodes disposed in the range of one memory cell. .

The inventors have reviewed the first openings other than the first opening shape and the layout formed by the above-described configuration, but in a combination of different pattern shapes or an irregular layout other than FIG. 1B, It is difficult to increase the manufacturing yield of the capacitor, and the present invention has been considered.

Next, reference is made to Fig. 1C. Fig. 1C is a cross-sectional view showing a range MC in which the upper end portion of the lower electrode C2 shown in Fig. 1A is enlarged. The lower electrode C2 constituting the first capacitor has a first portion C2a in which the first upper surface C2aa is not located in the first opening OP21, and a second portion C2b in which the second upper surface C2bb is located in the first opening OP21. The upper end portion of the side portion of the first portion C2a is connected to the first support film 14, and the first upper surface C2aa is formed to be flattened with the upper surface 14b of the first support film 14. On the other hand, the upper end portion of the second portion C2b is not connected to the first support film 14, and the second upper surface C2bb is disposed at a position lower than the upper surface 14b of the first support film 14 and higher than the lower surface 14c.

The lower electrode C2 constituting the first capacitor has a first upper surface C2aa that is leveled with the upper surface 14b of the first support film 14, and a second upper surface C2bb that is lower than the upper surface 14b of the first support film 14. Accordingly, since the position of the upper end portion of the first portion C2a and the second portion C2b is high or low, the proximity of the first portion C2a and the second portion C2b can be avoided, and even if the capacitor insulating film 25 is provided, the upper electrode 26 There was also no problem of occlusion. The two lower electrode layers facing the Y direction in one first opening have a configuration in which the second upper and lower electrodes are opposed to each other. For example, in the first opening OP21, the lower electrodes C2 and D2 are opposed to the Y direction, and among the lower electrodes, the second portion C2b of the second upper surface C2bb and the other second portion having the second upper surface D2aa are provided. D2a is the opposite of each other.

Next, reference is made to FIG. 1D. Fig. 1D is a cross-sectional view showing a range MD of an upper end portion of the lower electrode F2 shown in Fig. 1A. Each of the lower electrode F2 constituting the second capacitor has a first portion F2a and a second portion F2b having the upper surface F2aa and F2bb not positioned in the first opening. The upper end portions of the first portion F2a and the second portion F2b are connected to the first support film 14, and the upper surface F2aa and F2bb are formed to be flattened with the upper surface 14b of the first support film 14. In this case, as in the above-described experimental example, the upper end portion of the first portion F2a and the upper end portion of the second portion F2b are close to each other. However, in the present embodiment, as will be described later, the first support film 14 which has been retracted to the Z direction and the first portion F2a and the second portion F2b which are retracted to the Y direction and the Z direction constitute the lower electrode F2, and thus the suppression is suppressed. The first portion F2a is close to the second portion F2b to ensure an interval. In the case of the second capacitor, the upper electrode 26 can be disposed on the inner surface of the lower electrode F2 by clogging through the arrangement of the capacitor insulating film 25 to constitute a capacitor.

Next, reference is made to FIG. 1E. Fig. 1E is a cross-sectional view showing an enlarged view of the entire lower electrode C2 of the first capacitor.

The lower electrode C2 constituting the first capacitor extends in the Z direction perpendicular to the surface of the semiconductor substrate, and the second support film 10 is connected to the outer peripheral side surface of the lower electrode positioned in the middle of the Z direction. Further, the first support film 14 is connected to a portion of the side surface of the lower electrode located at the upper end portion in the Z direction. The upper surface of the lower electrode constituting the first capacitor is constituted by a first upper surface C2aa which is leveled with the upper surface 14b of the first support film 14, and a second upper surface C2bb which is lower than the upper surface 14b of the first support film 14. The bottom surface of the lower electrode C2 is connected Above the contact plug 6.

The capacitor C2 having the lower electrode C2 as a constituent element is a lower capacitor 21B positioned between the upper surface of the contact plug 6 and the lower surface 10c of the second support film 10, and a lower surface 10c of the second support film 10 and the first support. The upper capacitor 21A between the upper faces 14b of the film 14 is constructed. The film thickness of the lower electrode at a position close to the first support film 14 of the upper capacitor 21A is referred to as T1a, and the film thickness of the lower electrode at a position close to the second support film 10 is referred to as T2a. Further, the film thickness of the lower electrode at a position close to the second support film 10 of the lower capacitor 21B is referred to as T3, and the film thickness of the lower electrode at a position close to the contact plug 6 is referred to as T4. In the present embodiment, among T1a, T2a, T3, and T4, T2a is configured to be the thinnest.

In Fig. 1E, the dotted line 14d shows the position of the upper surface of the first support film 14 before retraction. Further, the dotted line 21a is displayed at a position above the point at which the lower electrode material film is formed. At the time of forming the lower electrode material film, the thickness of the first support film 14 is T5, and the thickness of the widened portion 40 of the lower electrode material film 21a positioned on the side surface of the first support film 14 is T7. Further, the film thickness T1 of the upper portion C2a, C2b constituting the lower electrode C2 of the upper capacitor 21A, and the film thickness T2 of the lower portion constitute the portion C2c of the lower electrode of the lower capacitor 21B, and the film thickness T3 of the upper portion of the C2d, The lower film thickness is T4. In the point of forming the lower electrode material film 21a, T1>T2>T3≧T4. In the above experimental example, the lower electrode C2 is constituted by maintaining this relationship. In the present embodiment, the film thickness of the first support film 14 is retracted from T5 to T5a. That is, under The upper surface C2aa of the portion electrode C2a is retracted to a position that is level with the upper surface 14b of the first support film 14. Further, the upper capacitor 21A is T1a when T1 is formed, and T2 is also retracted to the Y direction when it is T2a. As a result, the film thickness relationship of each portion of the lower electrode C2 of the present embodiment is T1a ≧ T3 ≧ T4 > T2a. However, the scale of the graph is not correct.

The lower electrode of the present embodiment has a diameter (outer diameter) L1 constituting the lower electrode of the upper capacitor 21A, and a diameter L2 close to the position of the second support film 10 constituting the lower electrode of the lower capacitor 21B and is close to The diameter L3 at which the tantalum nitride film 8 is stopped, and the diameter L4 defined by the diameter of the contact hole provided to stop the tantalum nitride film 8 are stopped. The magnitude relationship of these diameters is such that L2>L1>L3>L4, and the diameter of the lower electrode constituting the upper portion of the lower capacitor 21B below the second support film 10 becomes the largest size. However, in the above description, the close position refers to a position which means 50 nm isolation. For example, a position close to the second support film 10 among the lower electrodes constituting the lower capacitor 21B means that it is isolated from the lower surface 10c of the second support film 10 to a position at 50 nm. In addition, the scale of the figure is not correct.

Next, reference is made to FIG. 1F. Fig. 1F is a cross-sectional view showing the expansion of the entire lower electrode F2 of the second capacitor.

The configuration in which the first support film 14 corresponding to the second capacitor lower electrode F2 is lower than the first capacitor lower electrode C2 is the same as that of the first capacitor lower electrode C2. The different points do not have a position above the lower electrode in the first opening OP. Followed by the lower part The upper end portion of the outer peripheral side surface of the electrode F2 is connected to the side surface of the first support film 14 over the entire circumference. In the above-described experimental example, the opening width W5 of the cylinder hole at the time when the lower electrode is formed by the dotted line 21a is maintained. At the stage of forming the capacitor insulating film, the opening is closed, and the upper electrode cannot be formed. In the cylinder bore. However, in the present embodiment, as described with reference to Fig. 1E, since the lower electrode of the upper capacitor 21A is retracted to the Z direction and the Y direction, it can be used as a component for widening the opening width of the cylinder bore to W6. . As a result, even if the capacitor insulating film is formed, the opening of the cylinder bore can be avoided, and the upper electrode can be disposed in the cylinder bore to constitute a capacitor. However, in the second capacitor, similarly to the first capacitor, the relationship between T1a ≧ T3 ≧ T4 > T2a and the relationship of L2 > L1 > L0 > L3 > L4 are maintained. For example, when T1a is used as a film thickness of 100%, the T3 system is 97%, the T4 system is 94%, and the T2a system is about 85%. Further, when L0 is made 100% wide, L1 is 110%, L2 is 120%, L3 is 80%, and L4 is 70%.

(Method of Manufacturing Semiconductor Device)

Next, a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described in detail with reference to FIGS. 2 to 10. Here, a DRAM (Dynamic Random Access Memory) is exemplified as an example of a semiconductor device. However, the present invention is also applicable to a semiconductor device other than a DRAM that supports a structure having a high aspect ratio with a plurality of support films.

DRAM has a memory configured with a plurality of memory cells The body unit range MCA and the peripheral circuit range PCA for driving the memory unit. Each of FIG. 2 and FIG. 10 is a portion showing the periphery of the boundary portion between the memory cell range MCA of the DRAM and the peripheral circuit range PCA in the middle of manufacturing.

First, as shown in FIG. 2A, FIG. 2B and FIG. 3, a cylinder hole forming process is performed.

When it is described in detail, as shown in FIG. 2A and FIG. 2B, the buried gate electrode 2, the gap insulating film 3, the impurity diffusion layer 4, and the like are formed in the memory cell range MCA of the semiconductor substrate 1. Further, a first interlayer insulating film 5 is formed on the semiconductor substrate 1, and a contact plug 6 penetrating therethrough is formed. A peripheral circuit 7 or the like is formed in the peripheral circuit range PCA. Further, a tantalum nitride film 8 having a thickness of, for example, 50 nm is formed, and a first cylinder interlaminar film (first sacrificial film) 9 having a thickness of, for example, 900 nm is formed, and a tantalum nitride having a thickness of, for example, 30 nm is formed. The first insulating film 10a is formed to have a thickness of, for example, a second cylinder interlaminar film (second sacrificial film) 13 of 500 nm, and a second insulating film 14a made of tantalum nitride having a thickness of, for example, 150 nm, and a hard mask. Film 15, organic photomask film 18. The hard mask film 15 is composed of a laminated film of an amorphous tantalum film 15a, a tantalum oxide film 15b, and an amorphous carbon film 15c.

The first sacrificial film 9 and the second sacrificial film 13 are formed by dividing the first insulating film 10a as a boundary. The first sacrificial film 9 is formed of a first sacrificial film having a thickness of, for example, 500 nm below the first sacrificial film and a relative wet etching rate, and a thickness of, for example, 400 nm above the first sacrificial film. The lower first sacrificial film and the upper first sacrificial film system contain boron (B) and phosphorus (P), and can be used. A ruthenium oxide film (BPSG film: Boron-doped Phospho-Silicate Grass film) formed by a CVD (Chemical Vapor Deposition) method. In the lower first sacrificial film B, the P concentration is high, and the upper first sacrificial film B is formed at a low P concentration. B, the higher the P concentration, the faster the wet etching speed. Further, an undoped yttrium oxide film is used for the second sacrificial film 13 formed on the first insulating film 10a. As a result, the wet etching rate of the lower first sacrificial film is the fastest, and the etching rate is slow in the order of the upper first sacrificial film and the undoped yttrium oxide film. However, a well-known technique can be used for the film formation system of each layer mentioned above.

After the uppermost organic photomask film 18 is formed, a plurality of cylinder bore patterns 19 are formed in the organic photomask film 18 positioned in the memory cell range MCA via the first photolithography process. Here, the diameter W3 of the cylinder bore pattern 19 is made, for example, as 50 nm. Further, the interval W4 is made, for example, at 30 nm.

In the present embodiment, unlike the above-described experimental example, no patterning process is performed on any of the first insulating film 10a and the second insulating film 14a, and the second sacrificial film 13 and the hard surface are formed on each of the above. Photomask film 15.

The semiconductor substrate 1 is, for example, a p-type single crystal germanium substrate. The semiconductor substrate 1 is electrically separated into a memory cell range MCA and a peripheral circuit range PCA via an element isolation range (not shown). The buried gate electrode 2 and the diffusion layer 4 formed in the memory cell range MCA constitute a transistor. Further, the buried gate electrode 2 also functions as a word line. The contact plug 6 is connected to the diffusion layer 4 at the same time The project is connected to the lower electrode of the capacitor. However, a bit line (not shown) is formed in the first interlayer insulating film 5. The stop tantalum nitride film 8 is formed on the entire surface of the semiconductor substrate 1 by, for example, a CVD method. The first insulating film 10a is formed, for example, by a CVD method. The first insulating film 10a may be formed by a sputtering method or an HDP (High Density Plasma) method. The film formed by the sputtering method or the HDP method has high density, and can be reduced in etching speed through the solution than the film formed by the CVD method. Further, unlike the method of manufacturing the related semiconductor device, the patterning of the first insulating film 10a is not performed at this time.

The second insulating film 14a is formed in the same manner as the first insulating film 10a. The second insulating film 14a is also not patterned at this point. The amorphous tantalum film 15a is formed to have a thickness of, for example, 1000 nm by a CVD method. The hafnium oxide film 15b is formed, for example, by a CVD method to a thickness of 50 nm. The amorphous carbon film 15c is formed, for example, by a plasma CVD method to a thickness of 500 nm.

The organic photomask film 18 is formed of a photoresist and a laminated film containing an antireflection film or the like. Each of the openings constituting the cylinder hole pattern 19 corresponds to a capacitor forming position. The diameter of the opening is 40 to 80 nm, and the closest spacing between the adjacent openings can be 20 to 40 nm. In the most dense pattern in which such a large number of openings are disposed, the interval between the adjacent openings, that is, the interval between the capacitors is narrow, and in the method of manufacturing the related semiconductor device, the linear beam is repeatedly disposed in the X direction, Y The situation in the direction is difficult. In the present embodiment, the opening is formed in the support film as will be described later, and the structure is supported by the surface instead of the beam.

Next, as shown in FIG. 3, the organic photomask film 18 is used as a photomask, and the amorphous carbon film 15c is etched by an isotropic dry etching method using a plasma containing oxygen. Further, the arsenic oxide film 15b containing fluorine is used for dry etching, and the cylinder hole pattern 19 is transferred to the ruthenium oxide film 15b. Thereafter, the organic photomask film 18 and the amorphous carbon film 15c are removed. Next, the amorphous tantalum film 15a is subjected to an isotropic dry etching using the tantalum oxide film 15b as a mask, and the cylinder hole pattern 19 is transferred to the amorphous tantalum film 15a.

Then, the second insulating film 14a, the second sacrificial film 13, the first insulating film 10a, and the first sacrificial film are sequentially etched by an isotropic dry etching method using the yttrium oxide film 15b and the amorphous ruthenium film 15a as a mask. 9. The tantalum nitride film 8 is stopped to form the cylinder bore 20. Upon this etching, the ruthenium oxide film 15b and the amorphous ruthenium film 15a are destroyed, and the upper surface of the second support film 14a is exposed. At this stage, the film thickness T5 of the second support film was 130 nm. Further, the upper surface of the contact plug 6 is exposed on the bottom surface of the cylinder bore 20.

Next, the wet cleaning by removing the residue by dry etching is performed, and the wet processing by the hydrofluoric acid (HF)-containing solution which is washed before the formation of the lower electrode material film is performed. The second sacrificial film 13 and the first sacrificial film 9 exposed in the cylinder bore 20 by the wet treatment are etched in the Y direction to widen the cylinder bore 20.

Here, reference is made to FIG. 1F described above. The cylinder bore 20 is formed with an upper capacitor 21A upper portion hole 20A between the first insulating film 10a and the second insulating film 14a, and a lower portion of the lower capacitor 21B is formed lower than the first insulating film 10a. The hole 20B is constructed. The upper hole 20A includes the uppermost layer formed on the second insulating film 14a. Electric hole. Further, the lower hole 20B includes the lowermost hole formed in the stop tantalum nitride film 8. The uppermost hole has a diameter L0 formed in the second insulating film 14a formed by the tantalum nitride film. The upper hole 20A has a diameter L1 of the second sacrificial film 13 formed by the undoped yttrium oxide film. Further, the lower hole 20B has a diameter L2 which is formed in the first sacrificial film 9 formed by the BPSG film, and which is close to the position of the first insulating film 10a and a diameter L3 which is close to the position at which the tantalum nitride film 8 is stopped. The lowermost hole system has a diameter L4.

In the stage before the implementation of the aforementioned wet etching process, there is a magnitude relationship of L0 = L1 > L2 > L3 > L4. When the wet treatment is performed, as described above, the BPSG film-based etching rate is faster than that of the undoped yttrium oxide film, and the widening of the lower electrode 20B is relatively large. In addition, the tantalum nitride film system is not etched. As a result, the relationship between the diameters of the respective positions becomes L2>L1>L0>L3>L4, and the diameter L2 which is close to the position of the first insulating film 10a on which the lower hole 21B of the lower capacitor 21B is formed becomes the largest. . In the stage of forming the cylinder bore 20, L0 and L1 are 50 nm, but in the stage of performing the wet treatment, L1 is 55 nm, L2 is 60 nm, and L3 is changed to 40 nm. The uppermost layer hole and the lowermost layer hole were not widened by being formed on the tantalum nitride film, and L0 was 50 nm, and L4 was 35 nm without change. In the present embodiment, since the diameter of the cylinder bore 20 is widened by the relationship of L2 > L1 > L0 > L3 > L4, the surface area of the lower electrode can be increased to increase the capacity of the capacitor.

Next, as shown in FIG. 4A, a lower electrode material film forming process is performed. That is, the entire semiconductor substrate 1 including the inner surface of the cylinder bore 20 On the surface, a lower electrode material film 21a is formed. As the material of the lower electrode material film 21a, a titanium nitride (TiN) film can be used. Further, a CVD method, an ALD (Atomic Layer Deposition) method, or the like can be used for forming the lower electrode material film 21a. The electrode material film 21a formed in the lower portion of the cylinder bore 20 has a film thickness T1 close to the position of the second insulating film 14a and a film thickness T2 close to the upper surface 10b of the first insulating film 10a, which is close to the first The film thickness T3 at the position below the insulating film 10a is close to the film thickness T4 at which the tantalum nitride film 8 is stopped. These film thickness relationships become T1>T2>T3≧T4. For example, when the film thickness of T1 is 100%, T2 is 85%, T3 is 82%, and T4 is 81%.

However, as shown in FIG. 4B, for the inside of the cylinder bore 20 which is positioned below the second insulating film 14a, the upper end portion of the cylinder bore 20 is ensured when the necessary thickness of the lower electrode material film 21a is formed for the characteristics of the capacitor. A widened portion 40 having a film thickness T7 lower than the portion of the electrode material 21a of about 2 times T1 is formed. When the diameter of the cylinder bore 20 is narrowed, the supply of the film forming gas molecules inside the cylinder bore 20 is insufficient, so that the film forming speed is slow, and the end portion of the film forming gas molecule is not present sufficiently. A phenomenon that is caused by a decrease in the film formation speed and inevitably occurs. Thus, for example, when T1 forms the lower electrode material film 21a at 10 nm, the film thickness T7 at the upper end portion of the side surface of the second insulating film 14a is 18 nm. The T6 system becomes a thicker 25 nm. In the present embodiment, since the uppermost hole diameter L0 is 50 nm, the diameter W5 of the cylinder hole opening portion is narrowed to 14 nm.

Next, as shown in FIGS. 5A, 5B, 5C, 5D, 6A, 6B, 7A, 7B, and 7C, the formation process of the first support film 14 is performed.

First, as shown in FIG. 5A, a protective film 22a made of a ruthenium oxide film is formed in a comprehensive manner by a plasma CVD method. The film thickness of the protective film 22a is, for example, 100 nm. The protective film 22a formed by the plasma CVD method is inferior in coverage, and as shown in FIG. 5C and FIG. 5D, the internal portion of the cylinder bore 20 is not formed, and the upper end portion is closed. The protective film 22a is formed in a photolithography project which is performed by a subsequent process, and is formed in the cylinder bore 20 in order to prevent the photomask film formed by the photoresist. It is difficult to remove the machine when it is buried in a cylinder bore having a large aspect ratio.

Next, a photomask film 23 having a first opening pattern via a second photolithography project is formed on the protective film 22a. As shown in FIG. 5B, a peripheral opening 24a is formed in the peripheral circuit range PCA, and a photomask film 23 is formed in a covered memory cell range MCA. For the photomask film 23, for example, six first openings of OP11 to OP61 are formed. As described with reference to FIG. 1B, one first opening has a width W1 in the X direction and a width W2 in the Y direction. Further, the first opening is a first unit cylinder group in which the first unit lower electrode group corresponding to the four lower electrodes adjacent to the X direction is collectively arranged, and is arranged in the first unit cylinder group. The second unit cylinder group of the second unit lower electrode group formed by the four lower electrodes adjacent in the Y direction is formed in a pattern that is exposed. That is, one first opening is formed across eight cylinder bores.

Fig. 5C is an enlarged cross-sectional view corresponding to the range MC of the first capacitor shown in Fig. 5A. The mask film 23 is formed on the side surface of the first opening OP21 at a central portion in the Y direction corresponding to the cylinder hole of the lower electrode C2. In addition, FIG. 5D is an enlarged cross-sectional view corresponding to the range MD of the second capacitor shown in FIG. 5A. In this case, since the first opening is not formed, the upper surface of the protective film 22a is covered by the photomask film 23.

Next, as shown in FIG. 6A, the mask film 23 is used as a mask, and the protective film 22a exposed in the peripheral opening 24a and the first openings OP11 to OP61 is removed by an anisotropic dry etching method using a fluorine-containing plasma. Thereby, the upper surface of the lower electrode material film 21a is exposed to the inside of the first opening. Next, the upper surface electrode material film 21a is exposed by dry etching using an ion-containing plasma containing chlorine. Thereafter, the photomask film 23 is removed. As a result, the protective film 22a and the lower electrode material film 21a are a new protective film 22 to which the first opening pattern is transferred and a new lower electrode material film 21b. Further, the upper surface of the second insulating film 14a is exposed in the peripheral opening 24a and the first opening OP21. Further, as shown in FIG. 6B, the upper surface of the second portion C2b of the lower electrode C2 is exposed. The lower electrode material film 21b remains in the second insulating film 14a in the range other than the first openings OP11 to OP61.

Next, as shown in FIG. 7A, FIG. 7B, and FIG. 7C, the protective film 22 is used as a mask, and the upper opening and the first opening OP11 to OP61 are removed by using an anisotropic dry etching method using a fluorine-containing plasma. The second insulating film 14a inside. Through this etching, the protective film 22 is also simultaneously Etched and destroyed. Thereby, the first support film 14 formed of the second insulating film 14a is formed. Further, the upper surface of the second sacrificial film 13 is exposed to the peripheral opening and the first opening. A second portion C2b having a lower electrode that is a top surface C2bb that is level with the upper surface 14d of the first support film 14 is formed in the first opening.

Next, as shown in FIG. 8A and FIG. 8B, the removal process of the second sacrificial film 13 is performed. The second sacrificial film 13 exposed to the peripheral opening and the first opening is entirely removed by the fluoric acid-containing solution. As is well known, the solution etching is caused by the isotropic property, and the second sacrificial film 13 positioned below the first support film 14 is also easily removed. Thereby, the lower surface 14c of the first support film 14 and the upper surface 10b of the first insulating film 10a are exposed. Further, a first cavity 30a continuous in the outer periphery of all the lower electrodes is formed below the first support film 14.

Next, as shown in FIG. 9A, a second support film forming process is performed. The first support film 14 on which the lower electrode material 21b is formed is used as a mask, and anisotropic dry etching using a mixed gas plasma containing chlorine and oxygen is used to remove the exposed upper surface and the first opening OP21, OP51. The first insulating film 10a inside. Thereby, the first opening OP21 is formed in the same shape as the first opening, and the OP51 and the second opening OP22 and OP52 whose positions are integrated in the Z direction are formed. Thereby, the second support film 10 made of a tantalum nitride film is formed.

Next, reference is made to Fig. 9B. Fig. 9B is an enlarged cross-sectional view showing a range MC corresponding to the upper capacitor 21A among the lower electrodes C2 of the first capacitor. In the formation process of the second support film 10, as shown in FIG. 9B As shown in the figure, not only the first insulating film 10a formed of the tantalum nitride film but also the electrode material film 21b formed under the upper surface 14d of the first support film 14 is also etched. Thereby, the upper surface 14d of the first support film 14 is exposed, and the first portion C2a of the lower electrode that is in contact with the side surface of the first support film 14 is formed. Further, when the upper surface 14d of the first support film 14 and the upper surface of the first portion C2a formed by etching the tantalum nitride film are formed, a new upper surface 14b is formed for the first support film 14, and the first portion C2a is formed for the first portion C2a. A new first upper C2aa is formed. The film thickness of the first support film 14 is reduced from T5 to T5a. On the other hand, the upper surface of the second portion C2b exposed to the lower electrode in the first opening OP21 is also etched to form a new second upper surface C2bb. The first upper surface C2aa is flattened to the upper surface 14b of the first support film 14, and the second upper surface C2bb is formed lower than the upper surface 14b of the first support film 14.

In the present embodiment, in the formation of the second support film 10, the lower electrodes in the respective cylinder bores 20 are formed at the same time.

Further, in this etching, since the plasma used for etching causes oxygen to be contained, the surface portion of the lower electrode which is formed by oxidizing titanium nitride can be removed. Since the tantalum nitride film and the hafnium oxide film are not oxidized, it is possible to selectively oxidize only the surface portion of the lower electrode formed by the titanium nitride. Titanium nitride is not limited to oxygen ions contained in a plasma environment, and may be oxidized without neutralization of free radicals. Accordingly, it is not limited to the inside of the first opening OP21, and all surfaces of the lower electrode positioned below the first support film 14 are oxidized in a range other than the first opening OP21. The removal is carried out simultaneously with the subsequent first sacrificial film removal process. through When the oxidized titanium nitride is removed, the lower electrode is retracted and the width is reduced. Thereby, the width of the widened portion of the first portion C2a of the lower electrode positioned at the upper end portion of the side surface of the first support film 14 can be reduced from T7 to T7a.

Further, the first portion C2a positioned below the first support film 14 is also retracted, and T1 is reduced to T1a, and T2 is decreased to T2a. For example, the first support film 14 is reduced from a film thickness T5 of 130 nm to a film thickness T5a of 100 nm. The widened portion of the first portion C2a positioned at the upper end portion of the side surface of the first support film 14 is reduced from the width T7 of 18 nm to the width T7a of 12 nm. Further, the first portion C2a and the second portion C2b of the lower electrode C2 are changed from a width T1 of 10 nm to a width T1a of 7 nm, and a width T2 from a width T2 of 9 nm to a width T2a of 6 nm.

Next, reference is made to Fig. 9C. Fig. 9C is an enlarged cross-sectional view showing a range MD corresponding to the upper capacitor 21A among the lower electrodes F2 of the second capacitor. The basic configuration is the same as that of Fig. 9B, and the repeated explanation is abandoned. In the second capacitor, since the lower electrode F2 is not exposed in the first opening, the upper end surface of the lower electrode is spread over the entire circumference and connected to the first support film 14. Accordingly, either of the upper surface F2aa of the first portion F2a and the upper surface F2bb of the second portion F2b constituting the lower electrode F2 are leveled with the upper surface 14b of the first support film 14. As described above, the diameter L0 of the uppermost layer hole is 50 nm, and the width W5 of the upper end opening of the cylinder bore in the state in which the lower electrode material film 21b is formed is 14 nm. When the second support film 10 is formed, the first and the second electrodes F2 located at the upper end portion of the side surface of the first support film 14 are placed. The widened portion of the two portions F2a and F2b is reduced from a width T7 of 18 nm to a width T7a of 12 nm. Accordingly, the width W6 of the opening of the upper end of the cylinder bore is widened to 26 nm. As a result, even if a capacitor insulating film is formed in the subsequent process, the upper end opening of the cylinder bore is not blocked, and the upper electrode can be formed in the cylinder bore.

Next, as shown in FIG. 10, the first sacrificial film removal process is performed. The first sacrificial film formed by the BPSG film is completely removed by the peripheral opening and the second openings OP22 and OP52 by wet etching using a solution containing a hydrofluoric acid. Further, in the first sacrificial film removal process, the titanium oxide oxidized as described above is also removed. Thereby, the lower surface 10c of the second support film 10 and the upper surface of the tantalum nitride film 8 are stopped. Further, a second cavity 30b continuous in the outer periphery of all the lower electrodes is formed below the second support film 10.

Next, as shown in FIG. 1A, FIG. 1C, and FIG. 1D, a capacitor insulating film and an upper electrode are formed. The upper surface 14b including the first support film 14, the lower surface 14c, the upper surface 10b of the second support film 10, the lower surface 10c, the upper surface of the tantalum nitride film 8 and the entire inner and outer surfaces of the lower electrode 21 are used, and the ALD method is used. The capacitor insulating film 25 is formed. The capacitor insulating film 25 is formed by using zirconia as a main constituent. Since the film thickness of the capacitor insulating film 25 is formed at 7 nm, as shown in FIG. 1D, the upper end opening of the cylinder bore 20 is not closed. As described above, the width W6 of the upper end opening portion before the formation of the capacitor insulating film 25 is 26 nm, and the upper end opening having a width of 12 nm is also present at the stage of forming the capacitor insulating film 25. Accordingly, the upper electrode 26 is formed to cover the capacitor insulating film 25, and the film thickness of at least 6 nm is formed in the cylinder bore 20. Thereby, a capacitor can be formed. However, the upper electrode 26 is required to function at least 5 nm in order to function as an electrode, and it is difficult to function as a capacitor in a film thickness smaller than 5 nm.

Next, as shown in FIG. 1A, the upper electrode formed in the peripheral circuit range PCA is removed by photolithography and dry etching. Next, after the second interlayer insulating film 27 is formed in a comprehensive manner, the surface is planarized. Next, the via plug 28 is formed in the second interlayer insulating film 27, and the upper wiring 29 is further formed to manufacture a DRAM.

The preferred embodiments of the present invention have been described above, but the present invention is not limited to the embodiments described above, and various modifications may be made without departing from the spirit and scope of the invention. Within the scope of the invention. For example, the Y direction is the first direction and the X direction is the second direction, but the replacement direction is also the same. In addition, the film formation method or etching method, material, size, etc. are merely exemplified, and these should be appropriately selected.

As described above, according to the present embodiment, a plurality of lower electrodes arranged in a first direction parallel to the surface of the semiconductor substrate and in a second direction perpendicular to the first direction are adjacent to the second direction. The four lower electrodes are arranged in the first direction as the unit lower electrode group, and the adjacent two unit lower electrode groups are collectively exposed to form an opening pattern, so that the pressure of the support film can be relaxed and the distortion of the lower electrode can be avoided. And to prevent the problem of short circuit between the adjacent lower electrodes.

In addition, the capacitor is placed on the upper portion of the second support film. The film thickness of the lower electrode is such that the side surface and the upper surface of the lower electrode are retracted at the position close to the second support film, so that the diameter of the opening of the electrode below the upper end portion of the cylinder bore can be enlarged, and the diameter can be avoided. Blocked to form a capacitor.

The present application claims priority to Japanese Patent Application No. 2012-271555, filed on Dec.

OP11, OP21, OP31, OP41, OP51, OP61‧‧‧ first opening

OP12, OP22, OP32, OP42, OP52, OP62‧‧‧ second opening

PCA‧‧‧ peripheral circuit range

MCA‧‧‧ memory unit range

A1~A8‧‧‧ lower electrode

B1~B8‧‧‧ lower electrode

C1~C8‧‧‧ lower electrode

D1~D8‧‧‧ lower electrode

E1~E8‧‧‧ lower electrode

F1~F8‧‧‧ lower electrode

G1~G8‧‧‧ lower electrode

H1~H8‧‧‧ lower electrode

W1, W2, W3, W4‧‧‧ spacing

Claims (28)

A semiconductor device comprising: disposed on a semiconductor substrate along a first direction parallel to a surface of the semiconductor substrate and a second direction perpendicular to the first direction, and extending over a surface perpendicular to the surface of the semiconductor substrate a plurality of lower electrodes in the third direction and a first support film having a plurality of first openings disposed at positions corresponding to the upper ends of the plurality of lower electrodes, and arranged in the third direction a second support film having a plurality of second openings at a position intermediate the plurality of lower electrodes, a capacitor insulating film covering the surface of the plurality of lower electrodes, and an upper electrode covering the surface of the capacitor insulating film, the first opening of the plurality of openings And the second opening of the plurality of openings is planarly integrated in the same pattern, and is disposed at a position overlapping the third direction, wherein each of the plurality of first openings and the plurality of second openings are plural Among the lower electrodes, four lower electrodes adjacent to the second direction are adjacent to the first direction as a unit lower electrode group A lower electrode 2 to 8 units of a lower portion of each electrode group, a position to collectively form the first opening and the second opening to be constituted by the interior of each opening. The semiconductor device according to claim 1, wherein each of the plurality of lower electrode portions has a planar view ring shape, and the plurality of lower electrode portions are arranged at equal arrangement pitches with respect to the first direction and the second direction. , Each of the plurality of first openings has a length that is equal to three times the length of the arrangement pitch, extends over a long side of the second direction, and has a length equal to the arrangement pitch, and extends in the foregoing The rectangle of the short side of the 1 direction is constructed. The semiconductor device according to the first or second aspect of the invention, wherein the second lower electrode disposed at the both ends of the unit lower electrode group is in the first of the first The corner portion of the opening overlaps with the first opening in plan view, and the two lower electrodes positioned at the center overlap the first opening in a plan view on the long side of the corresponding first opening. The semiconductor device according to any one of claims 1 to 3, wherein each of the plurality of first openings is overlapped with a top surface of each of the four lower electrodes in a plan view. The long side is placed over the upper surface of each of the four lower electrodes, and is disposed across the eight lower electrodes. The semiconductor device according to claim 2, wherein the plurality of first openings adjacent to the second direction are arranged on a straight line, and the interval between the adjacent two first openings is equal to the configuration Spacing. In the semiconductor device according to the second aspect of the invention, the first opening of the plurality of openings is arranged to be equal to or smaller than the arrangement pitch of the first openings arranged in the first direction or more. The first opening adjacent to the second direction is shifted from the first direction by a distance equal to twice the arrangement pitch. Ground, configured as a jagged one. The semiconductor device according to any one of the first aspect, wherein the center line of the first opening of each of the plurality of openings is not closest to the first direction The first opening crossover. The semiconductor device according to any one of the preceding claims, wherein the plurality of first openings are a plurality of open columns including the first openings of two or more along the second direction. And placing the space in the first direction, and the first opening arranged along the first direction on the straight line is disposed in the opening row disposed in the first direction . The semiconductor device according to claim 1, wherein the semiconductor device has a memory cell range and a peripheral circuit range, and the first support film and the second support film are connected to each other in a range of the memory unit. All of the above-mentioned plural lower electrodes are configured to be continuous faces. A semiconductor device comprising: a lower electrode extending in a plurality of directions perpendicular to a third direction of a surface of a semiconductor substrate; and a first opening having a rectangular shape disposed at a position corresponding to an upper end portion of the lower plurality of electrodes a first support film disposed at a position intermediate the third direction of the plurality of lower electrodes, a second support film having a rectangular second opening, and a capacitive insulating film covering the surface of the plurality of lower electrodes, and Covering the upper electrode of the surface of the capacitor insulating film, In the plurality of lower electrodes, the capacitor insulating film and the upper electrode constitute a capacitor group, and the capacitor group includes a portion disposed on a side of the first opening in plan view, and a part of an outer peripheral side surface of the lower electrode a first capacitor connected to the first support film, and a second capacitor that is not exposed in the first opening and that is connected to the first support film on the outer peripheral side surface of the lower electrode, and constitutes the first capacitor The upper surface of the lower electrode has a first upper surface that is flattened from the upper surface of the first support film and a second upper surface that is lower than the upper surface of the first support film. The semiconductor device according to claim 10, wherein each of the plurality of lower electrodes has a ring-shaped upper surface in plan view, and the first upper surface is located on a portion of the lower electrode outside the first opening And the second upper surface is positioned on the other portion of the lower electrode in the first opening. A semiconductor device comprising: a lower electrode extending over a contact plug disposed on a semiconductor substrate and extending in a third direction perpendicular to a surface of the semiconductor substrate; and a peripheral electrode connected to an upper end of the lower electrode a first support film, a second support film connected to an outer periphery of the intermediate portion in the third direction of the lower electrode, a capacitor insulating film covering the surface of the lower electrode, and an upper electrode covering the surface of the capacitor insulating film. In the lower electrode, the capacitor insulating film and the upper electrode constitute a capacitor, and the capacitor includes a lower capacitor positioned between the contact plug upper surface and the second support film, and a lower surface of the second support film and the aforementioned The upper capacitor between the upper surfaces of the first support film has a thickness of the lower electrode at a position close to the first support film of the upper capacitor as T1a, and a second thickness close to the upper capacitor The film thickness of the lower electrode at the position of the support film is T2a, and the film thickness of the lower electrode at a position close to the second support film of the lower capacitor is T3, and the contact plug is close to the lower capacitor. The film thickness of the lower electrode at the position is T4, and the above T2a is the smallest. The semiconductor device according to claim 12, further comprising a stop tantalum nitride film surrounding the bottom of the lower capacitor, and the lower portion of the first support film corresponding to the upper capacitor The outer diameter of the electrode is L0, and the outer diameter of the lower electrode between the first support film and the second support film of the upper capacitor is L1, and is located close to the second support film of the lower capacitor. The outer diameter of the lower electrode is L2, and the outer diameter of the lower electrode at the position close to the stop of the tantalum nitride film of the lower capacitor is L3, and the above L2 is the largest. A method of manufacturing a semiconductor device, comprising: sequentially forming a stop tantalum nitride film on a semiconductor substrate, a first sacrificial film, An insulating film, a second sacrificial film and a second insulating film, and a second insulating film, the second sacrificial film, the first insulating film, the first sacrificial film, and the stop tantalum nitride film. The engineering of the cylinder bore, and the engineering of widening the cylinder bore, and the engineering of forming the membrane of the lower electrode material on the inner surface including the cylinder bore, and the process of forming the protective film on the film of the lower electrode material, and The protective film is formed by forming at least a part of a first opening pattern that maintains a surface of the second insulating film that forms a part of an inner surface of the cylinder bore and the lower electrode material film, and the protective film is formed as a mask. a process of forming a first support film by opening the first insulating film, a process of removing the second sacrificial film by the first opening, and an isotropic dry etching by using the first support film as a mask. In the first insulating film, the second opening formed in the same pattern as the first opening is formed, and the second support film is formed, and the electrode material film formed on the upper surface of the upper surface of the first support film is removed. In the cylinder bore, a process of connecting the outer peripheral side surface to the first support film and the lower electrode of the second support film, and a process of completely removing the first sacrificial film by the second opening to form the second opening And excavating the upper surface of the first support film and the lower portion while retracting the upper surface of the lower electrode The engineer above the electrode. The method of manufacturing a semiconductor device according to claim 14, wherein the expansion of the cylinder bore is performed as a cylinder bore diameter between the first support film and the second support film. L1, between the second support film and the stop tantalum nitride film, the cylinder bore diameter close to the position of the second support film is L2, and the cylinder bore is close to the position at which the tantalum nitride film is stopped. In the case where the diameter is L3, the above L2 is maximized. The method of manufacturing a semiconductor device according to the above aspect of the invention, wherein, in the process of forming the second opening, the retraction of the upper surface of the lower electrode is performed on the first support film and the Between the second support films, the film thickness of the lower electrode close to the position of the first support film is T1a, and is close to the second support film between the first support film and the second support film. The film thickness of the lower electrode at the position is T2a, and the film thickness of the lower electrode which is close to the position of the second support film between the second support film and the stop tantalum nitride film is T3, which is close to In the case where the film thickness of the lower electrode at the position where the tantalum nitride film is stopped is T4, the above T2a is formed to be the smallest. The method of manufacturing a semiconductor device according to any one of the fourteenth aspect, wherein the second opening has the same shape as the first opening pattern, and has the same layout and is formed at a position integrated A position vertically overlapping the third direction of the surface of the semiconductor substrate. The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the step of forming the cylinder bore is formed along a first direction parallel to a surface of the semiconductor substrate and perpendicular to the foregoing The second direction of the first direction is performed by a plurality of cylinder bores arranged in a line, and the lower electrode is formed in plural according to each of the plurality of cylinder bores. The method of manufacturing a semiconductor device according to claim 18, wherein the first opening pattern is a planar view, and four lower electrodes adjacent to the second direction are used as a unit lower electrode group, and are collectively included. One of the eight lower electrodes adjacent to the two unit lower electrode groups in the first direction is formed in the first opening. The method of manufacturing a semiconductor device according to claim 18, wherein the lower electrode is formed in a planar view ring shape. The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the plurality of cylinder bores are formed at equal arrangement intervals with respect to the first direction and the second direction. The first opening is formed by a rectangle having a second direction extending in a length of three times the length of the arrangement pitch, and a rectangle having a length equal to the arrangement pitch and extending in a short side of the first direction. By. The method of manufacturing a semiconductor device according to claim 19, wherein among the four lower electrodes included in the unit lower electrode group, two of the lower electrodes positioned at both ends are in a corner of the first opening The first opening is formed to overlap the first opening in a plan view, and the two lower electrodes positioned at the center are formed such that the long side of the first opening overlaps the first opening in plan view. The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the first opening is superimposed on a top surface of each of the four lower electrodes in a plan view. The long side is formed to overlap the upper surface of each of the four lower electrodes, and is formed by spanning the eight lower electrodes. The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the first opening is formed in a plurality of the first openings in the second direction to be equal to the arrangement pitch. The intervals are arranged to be carried out in a straight line. The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the first opening is formed by two or more of the first openings, and the first opening is equal to the first direction. Arranging the intervals of the arrangement pitches, and arranging the first openings adjacent to the second direction to be shifted from the position in the first direction by a distance equal to twice the arrangement pitch, and arranging the plurality of the first openings 1 The opening is performed in a zigzag manner. The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the first opening is formed The center line in the second direction of each of the plurality of first openings is formed so as not to intersect with the other first opening that is adjacent to the first direction. The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the first opening is formed by arranging a plurality of the first openings along the second direction. The opening row is disposed in the first direction at intervals, and the first opening arranged on the straight line along the first direction is included in the opening row disposed in the first direction Conductor. The method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the first support film and the second support film are connected to each other within a range of one memory cell. The lower electrode is formed by the electrode.