CN108206174A - Capacitor, capacitor manufacture method and semiconductor memory - Google Patents
Capacitor, capacitor manufacture method and semiconductor memory Download PDFInfo
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- CN108206174A CN108206174A CN201711460480.XA CN201711460480A CN108206174A CN 108206174 A CN108206174 A CN 108206174A CN 201711460480 A CN201711460480 A CN 201711460480A CN 108206174 A CN108206174 A CN 108206174A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 89
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000945 filler Substances 0.000 claims abstract description 24
- 239000002131 composite material Substances 0.000 claims abstract description 22
- 238000010276 construction Methods 0.000 claims abstract description 6
- 238000003860 storage Methods 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 34
- 239000007789 gas Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 18
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 6
- 238000009434 installation Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 3
- 230000008859 change Effects 0.000 abstract description 4
- 238000009740 moulding (composite fabrication) Methods 0.000 description 69
- 238000000151 deposition Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 12
- 230000008021 deposition Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000011521 glass Substances 0.000 description 5
- 230000004308 accommodation Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a kind of capacitors, capacitor manufacture method and semiconductor memory, capacitor includes the electrode supporting structure of setting on the insulating layer, electrode supporting structure has capacitance forming hole, top electrode filler is filled in capacitance forming hole and outside electrode supporting structure, electrode supporting structure includes from the bottom to top spaced bottom support layer successively, first middle support layer, second middle support layer and top support layer, spacing between bottom support layer and the first middle support layer, spacing between first middle support layer and the second middle support layer is all higher than the spacing between the second middle support layer and top support layer.Capacitor manufacture method includes forming composite bed on the insulating layer, and composite bed includes four layers of supporting layer and three layers of sacrificial layer, and the thickness of the first sacrificial layer and the second sacrificial layer is more than the thickness of 3rd sacrifice layer.The present invention improves the intensity of support construction, and capacitor profile is made more vertically to change, and improves the performance of finally formed semiconductor memory.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of capacitor, capacitor manufacture method and semiconductor are deposited
Reservoir.
Background technology
Capacitor has the function of voltage adjustment and filtering etc. in circuit as one of necessary component in integrated circuit.
The capacitance of capacitor is directly proportional to the dielectric constant of the area of pole plate and top electrode filler, the thickness with top electrode filler
It is inversely proportional.Therefore need to be formed the capacitance forming hole of larger depth on substrate to obtain larger capacitance, using capacitance into
Type hole side wall provides main polar plate area.But constantly reduce with the size of semiconductor devices, capacitance forming hole depth increases
It also needs to reduce capacitance forming hole opening size while big, significantly to increase the depth-to-width ratio in capacitance forming hole.Such as Fig. 1 institutes
Show, form multiple capacitance forming holes 101 on the substrate 100, and with the increase of 101 depth of capacitance forming hole, capacitance can be caused
There is short circuit so as to contact adjacent lower electrode in the phenomenon that lower electrode 102 around forming hole 101 is bent or collapses.
Disclosed above- mentioned information is only used for strengthening the understanding of the background to the present invention in the background technology, therefore it may be wrapped
Containing the information for not being formed as the prior art that those of ordinary skill in the art are known.
Invention content
In view of this, the embodiment of the present invention provides a kind of capacitor, capacitor manufacture method and semiconductor memory, with solution
Certainly or alleviate technical problem in the prior art, provide at a kind of beneficial selection.
What the technical solution of the embodiment of the present invention was realized in：
According to one embodiment of present invention, a kind of capacitor is provided, including：
Substrate sets insulating layer on the substrate, multiple storage node contact plugs is provided in the insulating layer；
Lower electrode including lower electrode layer and is used to support the electrode supporting structure of the lower electrode layer, the electrode supporting
For structure setting on the insulating layer, the electrode supporting structure has multiple capacitance forming holes, and the lower electrode layer is formed in
In the capacitance forming hole and it is engaged in the storage node contact plug；And
Top electrode, including top electrode filler, the top electrode filler is filled in the capacitance forming hole and covers
The electrode supporting structure；
Wherein, the electrode supporting structure includes from the bottom to top spaced bottom support layer, the first centre branch successively
Support layer, the second middle support layer and top support layer, the bottom support layer are arranged on the upper surface of the insulating layer；Institute
It states in spacing and first middle support layer and described second between bottom support layer and first middle support layer
Between spacing between supporting layer any spacing be all higher than between second middle support layer and the top support layer between
Away from；The bottom support layer, first middle support layer, second middle support layer and the top support layer it is total
Thickness is no more than the electrode supporting structure by upper surface to the lower surface of the bottom support layer of the top support layer
The 10% of height.
In some embodiments, the thickness of the top support layer is more than in first middle support layer and described second
Between supporting layer any thickness, and any thickness of first middle support layer and second middle support layer is all higher than
The thickness of the bottom support layer.
In some embodiments, the second middle support layer installation position is higher than the height of the electrode supporting structure half
Degree.
In some embodiments, the position in the capacitance forming hole is corresponding with the position of the storage node contact plug,
And the bottom opening size in the capacitance forming hole is more than the surface size of the storage node contact plug, so that the lower electricity
Pole layer is coated to the side of the storage node contact plug.
In some embodiments, the upper surface of the insulating layer is protruded from the top of the storage node contact plug.
In some embodiments, the upper surface of the bottom support layer is horizontally disposed with, the lower surface of the bottom support layer
Bumps setting.
In some embodiments, the top electrode further includes upper electrode layer, in the lower electrode layer and the upper electrode layer
Between capacitor dielectric layer is set, the capacitor dielectric layer covers inner surface and the outer surface of the lower electrode layer.
In some embodiments, the outer surface of the lower electrode layer has the supporting surface being connect with the electrode supporting structure
And the dispatch from foreign news agency pole-face of capacitor dielectric layer covering, the ratio of the dispatch from foreign news agency pole-face and the supporting surface are more than 9.
According to one embodiment of present invention, a kind of capacitor manufacture method is provided, including：
Substrate is provided, forms insulating layer over the substrate, interval forms multiple memory nodes and connects in the insulating layer
Touch plug；
Composite bed is formed on the insulating layer, is included on the insulating layer and forms bottom support layer, the bottom branch
It supports layer and covers the storage node contact plug, the first sacrificial layer, the first intermediate supports are sequentially formed in the bottom support layer
Layer, the second sacrificial layer, the second middle support layer, 3rd sacrifice layer and top support layer；Wherein, first sacrificial layer and described
Any thickness of second sacrificial layer is more than the thickness of the 3rd sacrifice layer, the bottom support layer, first intermediate supports
The overall thickness of layer, second middle support layer and the top support layer is not more than the 10% of the composite bed thickness；
Capacitance forming hole is formed in the composite bed, multiple capacitance formings are vertically formed on the composite bed
Hole, the composite bed between each capacitance forming hole form electrode supporting structure；
Lower electrode layer is formed in the capacitance forming hole, the lower electrode layer is engaged in the storage node contact plug；
First sacrificial layer, second sacrificial layer and the 3rd sacrifice layer are removed, to appear the lower electrode layer
Outer surface；
Form inner surface and outer surface of the capacitor dielectric layer in the lower electrode layer；And
Top electrode filler is formed in the capacitance forming hole, and covers the electrode supporting structure.
In some embodiments, the thickness of the top support layer is more than in first middle support layer and described second
Between supporting layer any thickness, and any thickness of first middle support layer and second middle support layer is all higher than
The thickness of the bottom support layer.
In some embodiments, the second middle support layer forming position is higher than the height of the electrode supporting structure half
Degree.
In some embodiments, the hardness of first sacrificial layer is less than the hardness of second sacrificial layer, so that etching
The speed of first sacrificial layer is faster than the speed for etching second sacrificial layer.
In some embodiments, the bottom support layer is deposited in two times, makes the upper surface of the bottom support layer
It is horizontally disposed, the lower surface bumps setting of the bottom support layer.
In some embodiments, the bottom support layer includes the first bottom support portion and the second bottom support portion, is formed
The method of the bottom support layer includes：
First bottom support portion is deposited on the insulating layer, first bottom support portion also covers the storage
Node contact plug；
First bottom support portion is flattened to the top surface of the exposure storage node contact plug, to correct first bottom
The upper surface flatness of portion's support portion；And
Second bottom support portion, second bottom support portion covering institute are deposited on the support portion of first bottom
State the top surface of storage node contact plug.
In some embodiments, in the forming process in the capacitance forming hole, by described in the first etchant gas
Top support layer, second middle support layer, any layer of first middle support layer and the bottom support layer, institute
It states the first etching gas and includes fluorine base gas and oxygen；Pass through the first sacrificial layer, described second described in the second etchant gas
Sacrificial layer and the 3rd sacrifice layer, second etching gas include fluorine base gas, oxygen and Nitrogen trifluoride.
According to one embodiment of present invention, a kind of semiconductor memory is provided, including above-mentioned capacitor.
According to one embodiment of present invention, a kind of capacitor is provided, including：
Substrate sets insulating layer on the substrate, multiple storage node contact plugs is provided in the insulating layer；
Lower electrode including lower electrode layer and is used to support the electrode supporting structure of the lower electrode layer, the electrode supporting
For structure setting on the insulating layer, the electrode supporting structure has multiple capacitance forming holes, and the lower electrode layer is formed in
In the capacitance forming hole and it is engaged in the storage node contact plug；And
Top electrode, including top electrode filler, the top electrode filler is filled in the capacitance forming hole and covers
The electrode supporting structure；
Wherein, the electrode supporting structure includes from the bottom to top spaced bottom support layer, two or two successively
More than middle support layer and top support layer, the bottom support layer are arranged on the upper surface of the insulating layer；Described two
A or more than two middle support layers are parallel to the medium line of the substrate, higher than the electrode supporting structure by the bottom branch
Support layer is parallel to the medium line of the substrate to the top support layer.
In some embodiments, the upper surface of the insulating layer is protruded from the top of the storage node contact plug,
The position in the capacitance forming hole is corresponding with the position of the storage node contact plug, and the bottom in the capacitance forming hole
Opening size is more than the surface size of the storage node contact plug, is connect so that the lower electrode layer is coated to the memory node
Touch the side of plug.
In some embodiments, the upper surface of the bottom support layer is horizontally disposed with, the lower surface of the bottom support layer
Bumps setting.
In some embodiments, the top electrode further includes upper electrode layer, in the lower electrode layer and the upper electrode layer
Between capacitor dielectric layer is set, the capacitor dielectric layer covers inner surface and the outer surface of the lower electrode layer.
In some embodiments, the outer surface of the lower electrode layer has the supporting surface being connect with the electrode supporting structure
And the dispatch from foreign news agency pole-face of capacitor dielectric layer covering, the ratio of the dispatch from foreign news agency pole-face and the supporting surface are more than 9.
The embodiment of the present invention due to using the technology described above, has the following advantages：The first of the embodiment of the present invention is sacrificial
Domestic animal layer and the second sacrificial layer to be formed, therefore improve the verticalization degree to form capacitance forming hole by depositing twice.The present invention
Embodiment improves the intensity of support construction, makes capacitor profile due to being provided with three layers of sacrificial layer and four layers of supporting layer
Relatively verticalization, can reduce short circuit phenomenon and capacitor lower electrode collapses the generation of phenomenon, improve finally formed semiconductor devices
Performance.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature will be what is be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent the same or similar through the identical reference numeral of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is capacitor partial structural diagram in the prior art.
Fig. 2 is the overall structure diagram of the capacitor of the embodiment of the present invention.
Fig. 3 is the forming method flow chart of the capacitor of the embodiment of the present invention.
Fig. 4 is the formation schematic diagram of the composite bed of the capacitor of the embodiment of the present invention.
Fig. 5 is the formation schematic diagram in the capacitance forming hole of the capacitor of the embodiment of the present invention.
Fig. 6 is the formation schematic diagram of the lower electrode layer of the capacitor of the embodiment of the present invention.
Fig. 7 is the formation schematic diagram in the gap of the capacitor of the embodiment of the present invention.
Fig. 8 is the capacitor dielectric layer of capacitor of the embodiment of the present invention and the formation schematic diagram of upper electrode layer.
Fig. 9 is the formation schematic diagram of the first bottom support portion of the capacitor of the embodiment of the present invention.
Figure 10 is the schematic diagram in the cavity of the first bottom of removal support portion of the capacitor of the embodiment of the present invention.
Figure 11 is the formation schematic diagram of the second bottom support portion of the capacitor of the embodiment of the present invention.
Drawing reference numeral explanation：
The prior art：
100- substrates；101- capacitance formings hole；Electrode under 102-.
The present invention：
200- substrates；210- insulating layers；220- storage node contact plugs；
Electrode under 300-；310- electrode supporting structures；320- capacitance formings hole；
601- lower electrode layers；602- capacitor dielectric layers；603- upper electrode layers；
400- top electrodes；410- top electrode fillers；311- bottom support layers；
The first middle support layers of 312-；The second middle support layers of 313-；314- top support layers；
321- gaps；500- composite beds；The first sacrificial layers of 510-；
The second sacrificial layers of 520-；530- 3rd sacrifice layers；515- accommodation spaces；
The first bottoms of 3111- support portion；3112- cavities；The second bottoms of 3113- support portion；
S100~S700- steps.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", " on ", " under ", "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer ", " up time
The orientation or position relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be based on orientation shown in the drawings or
Position relationship is for only for ease of the description present invention and simplifies description rather than instruction or imply that signified device or component must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are only used for description purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the present invention, " multiple " are meant that two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected or integral；Can be that machinery connects
It connects or is electrically connected, can also be communication；It can be directly connected, can also be indirectly connected by intermediary, it can be with
It is the connection of two component internals or the interaction relationship of two components.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature it " on " or it " under "
It can be in direct contact including the first and second features, it is not to be in direct contact but pass through it that can also include the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " including fisrt feature
Right over second feature and oblique upper or fisrt feature level height is merely representative of higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " right over second feature and oblique upper or be merely representative of including fisrt feature
One characteristic level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, itself not indicate between discussed various embodiments and/or setting
Relationship.In addition, the present invention provides various specific techniques and material example, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
The upper position of each attached drawing of the definition present invention for " on ", the lower orientation of each attached drawing for " under ".It should be understood to each implementation
Limited in example " on " and " top " be the upper side position in each attached drawing, " bottom " and " under " be downside in each attached drawing
It puts.The word of other related orientation descriptions should all be interpreted as with the above-mentioned position relationship for being defined as reference data and describing.
A kind of capacitor is provided according to embodiments of the present invention, as shown in Fig. 2, including：
Substrate 200 sets insulating layer 210 on substrate 200, and multiple spaced apart storage sections are provided in insulating layer 210
Point contact plug 220.The common substrat structure of capacitor in the prior art can be used in substrate 200, therefore in embodiments of the present invention
It does not limit, can adaptability selection be carried out to substrate 200 as needed.
Lower electrode 300, lower electrode 300 include lower electrode layer 601 and are used to support the electrode supporting structure of lower electrode layer 601
310.Electrode supporting structure 310 is arranged on insulating layer 210, and electrode supporting structure 310 has multiple capacitance forming holes 320.Under
Electrode layer 601 is formed in capacitance forming hole 320 and is engaged in storage node contact plug 220.
Specifically, on the surface in capacitance forming hole 320 and the surface of electrode supporting structure 310 covered with lower electrode layer 601,
Capacitor dielectric layer 602 and upper electrode layer 603 are covered successively on 601 surface of lower electrode layer.That is lower electrode layer 601 and upper electrode layer
Capacitor dielectric layer 602 is set between 603, and capacitor dielectric layer 602 covers inner surface and the outer surface of lower electrode layer 601.
In an optional embodiment, lower electrode layer 601 be formed in the side surface of electrode supporting structure 310 and capacitance into
The surface of type hole 320.
Top electrode 400, top electrode 400 include top electrode filler 410, and top electrode filler 410 is filled in capacitance forming
In hole 320, and cover electrode supporting structure 310.Top electrode filler 410 is contacted with upper electrode layer 603.
Wherein, electrode supporting structure 310 is included from the bottom to top among spaced bottom support layer 311, first successively
Supporting layer 312, the second middle support layer 313 and top support layer 314, bottom support layer 311 are arranged on the upper of insulating layer 210
On surface.Spacing and the first middle support layer 312 and second between 311 and first middle support layer 312 of bottom support layer
Any spacing of spacing between middle support layer 313 is all higher than between the second middle support layer 313 and top support layer 314
Spacing.Bottom support layer 311, the first middle support layer 312, the second middle support layer 313 and top support layer 314 it is total
Thickness no more than electrode supporting structure 310 by top support layer 314 upper surface to the lower surface of bottom support layer 311 height
10%.By the flying height that each supporting layer overall thickness and two middle support layers is controlled up slightly to improve, supported enough
The ability of lower electrode layer 601 so that the depth-to-width ratio in capacitance forming hole 320 can further improve.
In a preferred embodiment, bottom support layer 311, the first middle support layer 312, the second middle support layer
313 and top support layer 314 it is horizontally disposed.It is spaced about between 311 and first middle support layer 312 of bottom support layer
The 35% of 310 height of electrode supporting structure.It is spaced about between first middle support layer 312 and the second middle support layer 313
The 35% of 310 height of electrode supporting structure.Electrode is spaced about between second middle support layer 313 and top support layer 314
The 23.5% of 310 height of support construction.
In order to ensure 320 verticalization of capacitance forming hole formed on electrode supporting structure 310 and will not collapse, top braces
The thickness of layer 314 is more than any thickness of the first middle support layer 312 and the second middle support layer 313.First middle support layer
312 and second any thickness of middle support layer 313 be all higher than the thickness of bottom support layer 311.
In a preferred embodiment, the thickness of bottom support layer 311 is about the 1% of 310 height of electrode supporting structure.
The thickness of first middle support layer 312 is about the 1.5% of 310 height of electrode supporting structure.The thickness of second middle support layer 313
About the 1.5% of 310 height of electrode supporting structure.The thickness of top support layer 314 is about 310 height of electrode supporting structure
1.8%.
As shown in Fig. 2, in order to further ensure that the electrode supporting structure to be formed 310 will not collapse, cause capacitor short
Second middle support layer, 313 installation position can be higher than at the height of 310 half of electrode supporting structure by road.It is whole so as to improve
The position of centre of gravity of a 310 internal framework of electrode supporting structure.
As shown in Fig. 2, capacitance forming hole 320 is corresponding with the position of storage node contact plug 220.Each capacitance forming hole
Multiple gaps 321 are set between 320.The bottom opening size in capacitance forming hole 320 is more than the surface of storage node contact plug 220
Size, so that lower electrode layer 601 is coated to the side of storage node contact plug 220.
When forming capacitance forming hole 320, in order to avoid the capacitance forming hole in etching process to gradually forming as possible
320 side wall forms lateral erosion, and the top of storage node contact plug 220 can be protruded to the upper surface setting of insulating layer 210.So as to
It is opposite to reduce etching period, 320 bottom of capacitance forming hole is made to manifest storage node contact plug 220 faster.And be conducive to
It is coated in the side of storage node contact plug 220 by lower electrode layer 601.
In one embodiment, in order to ensure that the internal structure of the electrode supporting structure to be formed 310 can be horizontally disposed,
Therefore the upper surface of bottom support layer 311 needs to ensure horizontal, so that subsequently formed in bottom support layer 311 first
Middle support layer 312, the second middle support layer 313 and top support layer 314 are horizontal.And then improve electrode supporting structure 310
Integral strength and structural stability, avoid the occurrence of the phenomenon that electrode supporting structure 310 collapses.Bottom support layer 311
Lower surface bumps setting.
In one embodiment, the outer surface of lower electrode layer 601 have the supporting surface that is connect with electrode supporting structure 310 with
And the dispatch from foreign news agency pole-face that capacitor dielectric layer 602 covers, the ratio of dispatch from foreign news agency pole-face and supporting surface are more than 9.
A kind of capacitor manufacture method is provided according to embodiments of the present invention, as shown in figure 3, including the following steps：
Step S100：As shown in figure 4, provide substrate 200.Insulating layer 210 is formed on the substrate 200, in insulating layer 210
Interval forms multiple storage node contact plugs 220.
200 structure of substrate and generation type can be used same or similar with the substrat structure of existing capacitor and generation type
As mode.Substrate 200 in Fig. 4 is only schematic diagram, and substrate 200 can be multilayered structure.
Step S200：As shown in figure 4, composite bed 500 is formed on insulating layer 210.It is included on insulating layer 210 and forms bottom
Portion's supporting layer 311,311 covering storage node contact plug 220 of bottom support layer.First is sequentially formed in bottom support layer 311
Sacrificial layer 510, the first middle support layer 312, the second sacrificial layer 520, the second middle support layer 313,3rd sacrifice layer 530 and top
Portion's supporting layer 314.
Wherein, any thickness of the first sacrificial layer 510 and the second sacrificial layer 520 is more than the thickness of 3rd sacrifice layer 530.Bottom
Portion's supporting layer 311, the first middle support layer 312, the overall thickness of the second middle support layer 313 and top support layer 314 are little
In the 10% of 500 thickness of composite bed.
In one embodiment, it " sequentially forms " it is to be understood that depositing first in the upper surface of bottom support layer 311
Sacrificial layer 510 deposits the first middle support layer 312, in the first middle support layer 312 in the upper surface of the first sacrificial layer 510
Upper surface depositing second sacrificial layer 520 deposits the second middle support layer 313, in second in the upper surface of the second sacrificial layer 520
Between supporting layer 313 upper surface deposition 3rd sacrifice layer 530, the upper surface of 3rd sacrifice layer 530 deposit top support layer
314。
Composite bed 500 is improved the intensity of capacitor and is hung down using three layers of sacrificial layer and the form of four layers of supporting layer structure
Straightization degree.Wherein, by adjusting three layers of sacrificial layer (the first sacrificial layer 510, the second sacrificial layer 520 and 3rd sacrifice layer 530)
Thickness the capacitance to be formed can be enable to reach specified altitude.
In an optional embodiment, in top support layer 314 can also form the 4th sacrificial layer (does not show in figure
Go out), the generation type of the 4th sacrificial layer and sacrificial layer generation type of the prior art are same or similar seemingly.In the present embodiment
The material that four sacrificial layers include is identical with the material layer that sacrificial layer used in the prior art is included, specific material layer and material
The generation type of the bed of material can be selected according to need of work.Preferably, the 4th sacrificial layer includes polysilicon layer.
Step S300：As shown in fig. 7, capacitance forming hole 320 is formed in composite bed 500.500 upper edge of composite bed is square vertically
To the multiple capacitance forming holes 320 of formation.The top of the corresponding storage node contact plug 220 of 320 bottom-exposed of partition capacitance forming hole
Portion.Composite bed 500 between each capacitance forming hole 320 forms electrode supporting structure 310.
Step S400：As shown in fig. 7, forming lower electrode layer 601 in capacitance forming hole 320, lower electrode layer 601 is engaged in
Storage node contact plug 220.
Step S500：As shown in figure 8, the first sacrificial layer 510 of removal, the second sacrificial layer 520 and 3rd sacrifice layer 530, with
Appear the outer surface of lower electrode layer 601.
Step S600：As shown in figure 8, form inner surface and outer surface of the capacitor dielectric layer 602 in lower electrode layer 601.
Step S700：As shown in Fig. 2, forming top electrode filler 410 in capacitance forming hole 320, and cover electrode branch
Support structure 310.
In one embodiment, formed capacitance forming hole 320 the specific steps are：
As shown in figure 5, forming multiple capacitance forming holes 320 in composite bed 500, the bottom in each capacitance forming hole 320 is sudden and violent
Reveal the top of corresponding storage node contact plug 220.
As shown in fig. 6, forming madial wall and bottom surface of the lower electrode layer 601 in capacitance forming hole 320, lower electrode layer 601 covers
Lid storage node contact plug 220.
As shown in fig. 7, form multiple gaps 321 in composite bed 500, gap 321 be formed in each capacitance forming hole 320 it
Between, each 321 bottom-exposed bottom support layer 311 of gap.The side wall in gap 321 is lower electrode layer 601.
As shown in figure 8, sequentially form capacitor dielectric layer 602 and upper electrode layer 603 in the upper surface of lower electrode layer 601.
In one embodiment, the material of upper electrode layer 603 and lower electrode layer 601 may include titanium nitride (TiN), and capacitance is situated between
Matter layer 602 includes titanium oxide layer (TiOx) or zirconium oxide layer (ZrOx).
Step S400：As shown in Fig. 2, forming top electrode filler 410 in capacitance forming hole 320, and cover electrode branch
Support structure 310.Top electrode filler 410 is contacted with upper electrode layer 603.
At one based in the embodiment of step S200, as shown in figure 4, the first sacrificial layer 510 and the second sacrificial layer 520 are
By the way of being deposited in two times.The first sacrificial layer 510 is divided into two parts deposition, the second sacrificial layer 520 is divided into two parts
Deposition.This depositional mode can so that the deposition effect of the first sacrificial layer 510 and the second sacrificial layer 520 is more preferable.So as to improve
The intensity and compactness of first sacrificial layer 510 and the second sacrificial layer 520.Help the capacitance forming hole 320 being subsequently formed relatively vertical
Change, so as to avoid 310 intensity of the electrode supporting structure formed during follow-up process and verticalization degree inadequate, collapse
Or buckling phenomenon.
In a specific embodiment, the thickness that the first sacrificial layer 510 deposits for the first time be about 150~220nm (including
Endpoint value), the thickness of 510 second of deposition of the first sacrificial layer is about 350~400nm (including endpoint value).Second sacrificial layer 520
The thickness of deposition is about 180~280nm (including endpoint value) for the first time, and the thickness of 520 second of deposition of the second sacrificial layer is about
280~400nm (including endpoint value).
In another specific embodiment, bottom support layer 311, the first middle support layer 312, the second middle support layer
313 and top support layer 314 it is horizontally disposed.First sacrificial layer, 510 (i.e. 311 and first middle support layer of bottom support layer
Spacing between 312) it is about the 35% of 310 height of electrode supporting structure.Second sacrificial layer, 520 (i.e. the first middle support layer 312
With the spacing between the second middle support layer 313) it is about the 35% of 310 height of electrode supporting structure.3rd sacrifice layer 530 is (i.e.
Spacing between second middle support layer 313 and top support layer 314) it is about the 23.5% of 310 height of electrode supporting structure.
In one embodiment, the thickness of top support layer 314 is more than the first middle support layer 312 and the second intermediate supports
The thickness of the thickness of layer 313, the thickness of the first middle support layer 312 and the second middle support layer 313 is all higher than bottom support layer
311 thickness.
In a specific embodiment, the thickness of bottom support layer 311 is about the 1% of 310 height of electrode supporting structure.
The thickness of first middle support layer 312 is about the 1.5% of 310 height of electrode supporting structure.The thickness of second middle support layer 313
About the 1.5% of 310 height of electrode supporting structure.The thickness of top support layer 314 is about 310 height of electrode supporting structure
1.8%.
In order to further ensure that the electrode supporting structure to be formed 310 will not collapse, capacitor short-circuit is caused, it can be by
Two middle support layers, 313 installation position is higher than at the height of 310 half of electrode supporting structure.So as to improve entire electrode supporting knot
The position of centre of gravity of 310 internal framework of structure.
It should be noted that it in the above embodiments, is propped up among bottom support layer 311, the first sacrificial layer 510, first
Support the deposition of layer 312, the second sacrificial layer 520, the second middle support layer 313,3rd sacrifice layer 530 and top support layer 314
Thickness is selected according to actual conditions, however it is not limited to the deposition thickness in the present embodiment.
In order to further improve verticalization degree, the hardness of the first sacrificial layer 510 can be less than the second sacrificial layer 520
Hardness.I.e. so that underlying first sacrificial layer 510 is softer than 520 quality of the second sacrificial layer being located above.So that etching the
The speed of one sacrificial layer 510 is faster than the speed of the second sacrificial layer 520 of etching.So as to avoid pair brought due to etch-rate influence
The side view phenomenon of 320 hole wall of capacitance forming hole of formation.
In one embodiment, when the first sacrificial layer 510 and the second sacrificial layer 520 include boron-phosphorosilicate glass (BPSG)
When, the boron phosphorus concentration ratio in the first sacrificial layer 510 is B%:2~4wt%, P%:2~5wt%.In second sacrificial layer 520
Boron phosphorus concentration ratio is B%:1~3wt%P%:2~4wt%.
In a variable embodiment, the first sacrificial layer 510 and the second sacrificial layer 520 are relatively hard comprising material
Boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
At one based in the embodiment of step S300, as shown in figure 4, the generation type in capacitance forming hole 320 can adopt
Bottom support layer 311, the first sacrificial layer 510, the second sacrificial layer 520,3rd sacrifice layer are removed respectively with logical overetched mode
530th, the first middle support layer 312, the second middle support layer 313 and top support layer 314.
Wherein, pass through the first etchant gas bottom support layer 311, the first middle support layer 312, the second intermediate supports
Layer 313 and top support layer 314.First etching gas includes fluorine base gas and oxygen.Pass through the second etchant gas
One sacrificial layer 510, the second sacrificial layer 520 and 3rd sacrifice layer 530.Second etching gas includes fluorine base gas, oxygen and trifluoro
Change nitrogen.First sacrificial layer 510, the second sacrificial layer 520 and 3rd sacrifice layer 530 can be removed by wet etching mode.
In a preferred embodiment, the etchant gas mixture of top support layer 314 includes fluorine base gas (CHF3,
CH2F2, C4F6) and oxygen.Etching condition is 5~30mTorr of pressure, and working frequency and wattage are 2MHZ, 3000~5000W；
27MHZ, 100~400W；It is etched under the conditions of tri- kinds of 60MHZ, 200~700W.
The etchant gas mixture of 3rd sacrifice layer 530 includes fluorine base gas (C4F6,C4F8), oxygen and Nitrogen trifluoride
(NF3).Etching condition is 5~25mTorr of pressure, and working frequency and wattage are 2MHZ, 4000~8000W；27MHZ, 100~
500W；It is etched under the conditions of tri- kinds of 60MHZ, 700~1500W.
The etchant gas mixture of first middle support layer 312 and the second middle support layer 313 includes fluorine base gas (C4F6,
C4F8, CH2F2) and oxygen.Etching condition is 5~25mTorr of pressure, and working frequency and wattage are 2MHZ, 1000~3000W；
27MHZ, 50~400W；It is etched under the conditions of tri- kinds of 60MHZ, 100~500W.
The etchant gas mixture of first sacrificial layer 510 and the second sacrificial layer 520 includes fluorine base gas (C4F6,C4F8), oxygen
Gas and Nitrogen trifluoride (NF3).Etching condition is 5~25mTorr of pressure, and working frequency and wattage are 2MHZ, 5000~
8000W；27MHZ, 100~400W；It is etched under the conditions of tri- kinds of 60MHZ, 800~1500W.
At one based in the embodiment of step S200, in order to avoid substrate 200 contacts generation with top electrode filler 410
Short circuit, bottom support layer 311 can be deposited in two times.Bottom support 311 specific forming process be：
As shown in figure 9, depositing the first bottom support portion 3111 on the substrate 200, the covering of the first bottom support portion 3111 is deposited
Store up node contact plug 220.
As shown in Figure 10, the first bottom support portion 3111 of leveling is to the top surface of exposure storage node contact plug 220, with removal
Cavity 3112 in first bottom support portion 3111, and correct the upper surface flatness of the first bottom support portion 3111.
As shown in figure 11, the second bottom support portion 3113, the support of the second bottom are deposited on the first bottom support portion 3111
The top surface of 3113 covering storage node contact plug 220 of portion.Ultimately form bottom support layer 311.
In a specific embodiment, the deposition thickness of the first bottom support portion 3111 is about 10~30nm, the second bottom
The deposition thickness of portion's support portion 3113 about 10~30nm.The purpose that bottom support layer 311 deposits in two times be make it is finally formed
Bottom support layer 311 is finer and close will not to have cavity to occur so as to cause short circuit phenomenon.
In order to improve the integral strength of electrode supporting structure 310, as shown in Fig. 2, Fig. 8, after gap 321 is formed, go
It is multiple to be formed except the first sacrificial layer 510, the second sacrificial layer 520 and the 3rd sacrifice layer 530 in electrode supporting structure 310
Accommodation space 515.Capacitor dielectric layer 602 is formed in the inner surface of accommodation space 515.It fills and powers in accommodation space 515
Pole filler 410.
In some embodiments, bottom support layer 311, the first middle support layer 312, the second middle support layer 313 and
The material of top support layer 314 may include silicon nitride.The material of 3rd sacrifice layer 530 may include ethyl orthosilicate (TEOS).
The material of first sacrificial layer 510 and the second sacrificial layer 520 may include boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
Manufactured capacitor can be applied to the capacitance of below 20nm ranks in the embodiment of the present invention.
A kind of capacitor is provided according to another embodiment of the present invention, including：
Substrate 200 sets insulating layer 210 on substrate 200, multiple storage node contact plugs is provided in insulating layer 210
220。
Lower electrode 300 including lower electrode layer 601 and is used to support the electrode supporting structure 310 of lower electrode layer 601, electrode
Support construction 310 is arranged on insulating layer 210, and electrode supporting structure 310 has multiple capacitance forming holes 320, lower electrode layer 601
It is formed in capacitance forming hole 320 and is engaged in storage node contact plug 220.
Top electrode 400, including top electrode filler 410, top electrode filler 410 be filled in capacitance forming hole 320 and
Cover electrode supporting structure 310.
Wherein, electrode supporting structure 310 includes from the bottom to top spaced bottom support layer 311, two successively or two
A Yi Shang middle support layer (can be the first middle support layer 312 and/or the second middle support layer 313) and top braces
Layer 314, bottom support layer 311 is arranged on the upper surface of insulating layer 210；Two or more middle support layers are parallel to lining
First medium line at bottom 200 is parallel to substrate higher than electrode supporting structure 310 by bottom support layer 311 to top support layer 314
200 the second medium line.First medium line can be understood as plane residing for the centre position in region folded by head and the tail middle support layer
On straight line.Second medium line can be understood as the centre position institute in region folded by bottom support layer 311 and top support layer 314
Locate the straight line in plane.
In one embodiment, the top of storage node contact plug 220 protrudes from the upper surface of insulating layer 210, capacitance into
Type hole 320 is corresponding with the position of storage node contact plug 220.Multiple gaps 321 are set between each capacitance forming hole 320.Electricity
The bottom opening size of Rongcheng type hole 320 is more than the surface size of storage node contact plug 220, so that lower electrode layer 601 coats
To the side of storage node contact plug 220.
In one embodiment, the upper surface of bottom support layer 311 is horizontally disposed with, and the lower surface of bottom support layer 311 is recessed
Projection is put.
In one embodiment, top electrode further includes upper electrode layer 603, between lower electrode layer 601 and upper electrode layer 603
Capacitor dielectric layer 602 is set, and capacitor dielectric layer 602 covers inner surface and the outer surface of lower electrode layer 601.
In one embodiment, the outer surface of lower electrode layer 601 have the supporting surface that is connect with electrode supporting structure 310 with
And the dispatch from foreign news agency pole-face that capacitor dielectric layer 602 covers, the ratio of dispatch from foreign news agency pole-face and supporting surface are more than 9.
A kind of semiconductor memory (not shown) is provided according to further embodiment of this invention, including in above-described embodiment
Capacitor.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (21)
1. a kind of capacitor, which is characterized in that including：
Substrate sets insulating layer on the substrate, multiple storage node contact plugs is provided in the insulating layer；
Lower electrode including lower electrode layer and is used to support the electrode supporting structure of the lower electrode layer, the electrode supporting structure
It is arranged on the insulating layer, the electrode supporting structure has multiple capacitance forming holes, and the lower electrode layer is formed in described
In capacitance forming hole and it is engaged in the storage node contact plug；And
Top electrode, including top electrode filler, the top electrode filler is filled in the capacitance forming hole and described in covering
Electrode supporting structure；
Wherein, the electrode supporting structure include from the bottom to top successively spaced bottom support layer, the first middle support layer,
Second middle support layer and top support layer, the bottom support layer are arranged on the upper surface of the insulating layer；The bottom
It is propped up among spacing and first middle support layer and described second between portion's supporting layer and first middle support layer
Any spacing of spacing between support layer is all higher than the spacing between second middle support layer and the top support layer；Institute
State the overall thickness of bottom support layer, first middle support layer, second middle support layer and the top support layer
No more than the electrode supporting structure by the top support layer upper surface to the lower surface of the bottom support layer height
10%.
2. capacitor as described in claim 1, which is characterized in that the thickness of the top support layer is more than among described first
Any thickness of supporting layer and second middle support layer, and first middle support layer and second intermediate supports
Any thickness of layer is all higher than the thickness of the bottom support layer.
3. capacitor as described in claim 1, which is characterized in that the second middle support layer installation position is higher than the electricity
The height of pole support construction half.
4. capacitor as described in claim 1, which is characterized in that the position in the capacitance forming hole connects with the memory node
The position for touching plug is corresponding, and the bottom opening size in the capacitance forming hole is more than the surface of the storage node contact plug
Size, so that the lower electrode layer is coated to the side of the storage node contact plug.
5. capacitor as described in claim 1, which is characterized in that protruded from the top of the storage node contact plug described exhausted
The upper surface of edge layer.
6. capacitor as claimed in claim 5, which is characterized in that the upper surface of the bottom support layer is horizontally disposed with, described
The lower surface bumps setting of bottom support layer.
7. such as claim 1 to 6 any one of them capacitor, which is characterized in that the top electrode further includes upper electrode layer,
Capacitor dielectric layer is set between the lower electrode layer and the upper electrode layer, and the capacitor dielectric layer covers the lower electrode layer
Inner surface and outer surface.
8. capacitor as claimed in claim 7, which is characterized in that the outer surface of the lower electrode layer has and the electrode branch
The supporting surface of support structure connection and the dispatch from foreign news agency pole-face of capacitor dielectric layer covering, the dispatch from foreign news agency pole-face and the supporting surface
Ratio is more than 9.
9. a kind of capacitor manufacture method, which is characterized in that including：
Substrate is provided, forms insulating layer over the substrate, interval forms multiple storage node contact plugs in the insulating layer；
Composite bed is formed on the insulating layer, is included on the insulating layer and forms bottom support layer, the bottom support layer
The storage node contact plug is covered, the first sacrificial layer, the first middle support layer, are sequentially formed in the bottom support layer
Two sacrificial layers, the second middle support layer, 3rd sacrifice layer and top support layer；Wherein, first sacrificial layer and described second
Any thickness of sacrificial layer is more than the thickness of the 3rd sacrifice layer, the bottom support layer, first middle support layer, institute
The overall thickness for stating the second middle support layer and the top support layer is not more than the 10% of the composite bed thickness；
It forms capacitance forming hole and multiple capacitance forming holes is vertically formed in the composite bed, on the composite bed, respectively
The composite bed between the capacitance forming hole forms electrode supporting structure；
Lower electrode layer is formed in the capacitance forming hole, the lower electrode layer is engaged in the storage node contact plug；
First sacrificial layer, second sacrificial layer and the 3rd sacrifice layer are removed, to appear the outer of the lower electrode layer
Surface；
Form inner surface and outer surface of the capacitor dielectric layer in the lower electrode layer；And
Top electrode filler is formed in the capacitance forming hole, and covers the electrode supporting structure.
10. capacitor manufacture method as claimed in claim 9, which is characterized in that the thickness of the top support layer is more than institute
State any thickness of the first middle support layer and second middle support layer, and first middle support layer and described
Any thickness of two middle support layers is all higher than the thickness of the bottom support layer.
11. capacitor manufacture method as claimed in claim 9, which is characterized in that the second middle support layer forming position
Higher than the height of the electrode supporting structure half.
12. capacitor manufacture method as claimed in claim 9, which is characterized in that the hardness of first sacrificial layer is less than institute
The hardness of the second sacrificial layer is stated, so that the speed of etching first sacrificial layer is faster than the speed for etching second sacrificial layer.
13. capacitor manufacture method as claimed in claim 9, which is characterized in that the bottom support layer is sunk in two times
Product, is horizontally disposed with the upper surface of the bottom support layer, the lower surface bumps setting of the bottom support layer.
14. capacitor manufacture method as claimed in claim 13, which is characterized in that the bottom support layer includes the first bottom
Support portion and the second bottom support portion, the method for forming the bottom support layer include：
First bottom support portion is deposited on the insulating layer, first bottom support portion also covers the memory node
Contact plug；
First bottom support portion is flattened to the top surface of the exposure storage node contact plug, to correct first bottom branch
The upper surface flatness of support part；And
Second bottom support portion is deposited on the support portion of first bottom, is deposited described in the covering of second bottom support portion
Store up the top surface of node contact plug.
15. such as claim 9 to 14 any one of them capacitor manufacture method, which is characterized in that in the capacitance forming hole
Forming process in, by top support layer, second middle support layer, described first described in the first etchant gas
Between any layer of supporting layer and the bottom support layer, first etching gas include fluorine base gas and oxygen；Pass through
First sacrificial layer, second sacrificial layer and the 3rd sacrifice layer, second etching gas described in two etchant gas
Include fluorine base gas, oxygen and Nitrogen trifluoride.
16. a kind of semiconductor memory, which is characterized in that including capacitor as described in claim 1.
17. a kind of capacitor, which is characterized in that including：
Substrate sets insulating layer on the substrate, multiple storage node contact plugs is provided in the insulating layer；
Lower electrode including lower electrode layer and is used to support the electrode supporting structure of the lower electrode layer, the electrode supporting structure
It is arranged on the insulating layer, the electrode supporting structure has multiple capacitance forming holes, and the lower electrode layer is formed in described
In capacitance forming hole and it is engaged in the storage node contact plug；And
Top electrode, including top electrode filler, the top electrode filler is filled in the capacitance forming hole and described in covering
Electrode supporting structure；
Wherein, the electrode supporting structure include from the bottom to top successively spaced bottom support layer, two or more
Middle support layer and top support layer, the bottom support layer are arranged on the upper surface of the insulating layer；It is described two or
More than two middle support layers are parallel to the medium line of the substrate, higher than the electrode supporting structure by the bottom support layer
The medium line of the substrate is parallel to the top support layer.
18. capacitor as claimed in claim 17, which is characterized in that protruded from the top of the storage node contact plug described
The upper surface of insulating layer, the position in the capacitance forming hole is corresponding with the position of the storage node contact plug, and
The bottom opening size in the capacitance forming hole is more than the surface size of the storage node contact plug, so that the lower electrode layer
It coats to the side of the storage node contact plug.
19. capacitor as claimed in claim 17, which is characterized in that the upper surface of the bottom support layer is horizontally disposed with, institute
State the lower surface bumps setting of bottom support layer.
20. the capacitor as described in claim 17,18 or 19, which is characterized in that the top electrode further includes upper electrode layer,
Capacitor dielectric layer is set between the lower electrode layer and the upper electrode layer, and the capacitor dielectric layer covers the lower electrode layer
Inner surface and outer surface.
21. capacitor as claimed in claim 20, which is characterized in that the outer surface of the lower electrode layer has and the electrode
The supporting surface of support construction connection and the dispatch from foreign news agency pole-face of capacitor dielectric layer covering, the dispatch from foreign news agency pole-face and the supporting surface
Ratio be more than 9.
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| WO2024169193A1 (en) * | 2023-02-14 | 2024-08-22 | 华为技术有限公司 | Capacitor, storage array, memory, and electronic device |
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