CN208767297U - Capacitance structure - Google Patents
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- CN208767297U CN208767297U CN201821598132.9U CN201821598132U CN208767297U CN 208767297 U CN208767297 U CN 208767297U CN 201821598132 U CN201821598132 U CN 201821598132U CN 208767297 U CN208767297 U CN 208767297U
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Abstract
The utility model provides a kind of capacitance structure, which includes: a substrate, the capacitor contact with multiple intervals；Multiple capacitive posts, capacitive post are formed on the substrate, and with capacitor engagement contacts, capacitive post includes the first upper electrode layer, the first dielectric layer, lower electrode layer, the second dielectric layer and the second upper electrode layer from inside to outside；Top support layer is parallel to the substrate, and multiple capacitive posts form the capacitive post body part of the capacitive post extension and lower section that are located above top support layer through top support layer；Fixing layer, is formed in the periphery of the capacitive post extension, and fixing layer entirely or partly covers the capacitive post extension on perpendicular to the orientation substrate.The capacitance structure improves that the hollow capacitive post itself increased is unstable, easy the problem of collapsing, while also avoiding wet etching easily occurs in its forming process shaking and phenomenon of collapsing, and substantially increases the stability and device performance of capacitance structure.
Description
Technical field
The utility model relates to field of semiconductor manufacture, and in particular to capacitance structure.
Background technique
As dynamic random access memory (DRAM) characteristic size persistently reduces, the capacitor of capacitor is also constantly subtracting
It is small, capacitor is improved by making the capacitor of high aspect ratio structure and forming the dielectric material of two-sided (double side) structure
It is the effective method for improving capacitor.In the application of high aspect ratio structure, it usually needs prepare sacrificial layer to etch height
The materials such as boron-phosphorosilicate glass (boro-phospho-silicate-glass, BPSG) can be used in aspect-ratio holes, sacrificial layer.
However, the capacitance structure for forming high-aspect-ratio can face a series of problems in the case where electrode plate is constantly thinned,
For example, the hollow capacitive post on the one hand increased can be unstable in structure, easily collapse；On the other hand wet process is carved in processing step
When erosion removes high dielectric material of the BPSG to form two-sided (double side), wherein used etching solution is difficult to remove,
The surface tension of solvent can stretch capacitive post, lead to the shaking of capacitance structure.
For this purpose, it is urgent to provide a kind of new capacitance structures and forming method thereof, to solve on existing in the prior art
State variety of problems.
It is noted that information disclosed in aforementioned background art part is only used for reinforcing the background reason to the utility model
Solution, therefore it may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
The purpose of the utility model is to provide a kind of capacitance structures, to solve the structure easily occurred in existing capacitance structure not
Easily cause the problem of structure is destroyed on stable and subsequent technique.
To achieve the goals above, the utility model adopts the following technical solution:
The utility model provides a kind of capacitance structure, comprising:
One substrate, the capacitor contact with multiple intervals；
Multiple capacitive posts, the capacitive post are formed on the substrate, and with the capacitor engagement contacts, the capacitive post
It from inside to outside include the first upper electrode layer, the first dielectric layer, lower electrode layer, the second dielectric layer and the second upper electrode layer；
Top support layer, is parallel to the substrate, and the multiple capacitive post is located at through the top support layer, formation
The capacitive post body part of capacitive post extension and lower section above the top support layer；
Fixing layer is formed in the periphery of the capacitive post extension, and the fixing layer is on perpendicular to the orientation substrate
Entirely or partly cover the capacitive post extension.
An embodiment according to the present utility model, the height of the fixing layer account for the capacitive post height 1/5~
1/3。
An embodiment according to the present utility model, the height of the capacitive post are 800~1600nm.
An embodiment according to the present utility model, the material of the material of the fixing layer and first upper electrode layer
It is identical.
An embodiment according to the present utility model, first upper electrode layer are stuffed entirely with the interior of the capacitive post
Portion.
An embodiment according to the present utility model, the fixing layer have multiple openings, second dielectric layer and
Second upper electrode layer is extended through the opening and is covered in the surface of the fixing layer.
An embodiment according to the present utility model, the capacitance structure further include a bottom support layer, the bottom
Supporting layer is formed on the substrate, and the bottom of the capacitive post body part is engaged in the substrate through the bottom support layer
On capacitor contact.
An embodiment according to the present utility model, the top support layer with a thickness of 30nm~45nm, the bottom
Portion's supporting layer with a thickness of 30nm~45nm.
An embodiment according to the present utility model, first upper electrode layer, the lower electrode layer and described second
The material of upper electrode layer is selected from one of titanium, titanium nitride and tungsten or a variety of；First dielectric layer and second dielectric layer
Material be selected from one of aluminium oxide, silicon nitride, silica and zirconium oxide or a variety of.
An embodiment according to the present utility model, the lower electrode layer power on a thickness of 5~15nm, described second
Pole layer with a thickness of 5~10nm, first dielectric layer with a thickness of 4nm~10nm, second dielectric layer with a thickness of 4nm
~10nm.
An embodiment according to the present utility model, the capacitance structure further includes polysilicon layer, the polysilicon layer
Positioned at the outer surface of second upper electrode layer.
An embodiment according to the present utility model, one of the doping polycrystalline silicon layer boron, arsenic, phosphorus and germanium or more
Kind.
An embodiment according to the present utility model further includes between the polysilicon layer and second upper electrode layer
One layer of metal tungsten layer.
The utility model also provides a kind of forming method of capacitance structure, comprising:
The substrate of the one capacitor contact with multiple intervals is provided；
Composite layer is formed on the substrate, including sequentially forms bottom support layer, the from bottom to top on the substrate
One sacrificial layer, top support layer and the second sacrificial layer；
Multiple capacitance forming holes are formed in the composite layer, the capacitance forming hole is made to manifest the corresponding capacitor
Contact；
Lower electrode layer is formed in the multiple capacitance forming hole, the lower electrode layer is engaged in the capacitor contact；
Second sacrificial layer is removed until appearing the top support layer, the top support layer and extends the top
The lower electrode layer above portion's supporting layer constitutes top channel；
The first dielectric layer is formed on the lower electrode layer and the top support layer；
The first upper electrode layer is formed on first dielectric layer, fills the capacitance forming hole and shape with all or part of
At fixing layer in the top channel, the fixing layer completely or partially covers the top channel；
Multiple top support layers for being opened on the fixing layer, and being etched through in the removal opening are formed, so that institute
The side wall for stating opening manifests the first upper electrode layer and the bottom of the opening is made to appear the first sacrificial layer；
First sacrificial layer is removed to appear corresponding lower electrode layer, then in the fixed layer surface, the institute appeared
The surface for the lower electrode layer stating the first upper electrode layer and appearing forms the second dielectric layer；
The second upper electrode layer is formed on second dielectric layer.
An embodiment according to the present utility model further includes forming polysilicon layer on second upper electrode layer.
An embodiment according to the present utility model further includes forming metal tungsten layer in the polysilicon layer and described
Between two upper electrode layers.
An embodiment according to the present utility model, an opening is only overlapping with a capacitance forming hole,
Or an opening is overlapping with multiple capacitance forming holes simultaneously.
The material of an embodiment according to the present utility model, first sacrificial layer and the second sacrificial layer is selected from oxidation
One of silicon, phosphorosilicate glass and boron-phosphorosilicate glass are a variety of.
An embodiment according to the present utility model, first sacrificial layer with a thickness of 500~1000nm, described
Two sacrificial layers with a thickness of 300~500nm.
An embodiment according to the present utility model, first upper electrode layer, the lower electrode layer and described second
The material of upper electrode layer is selected from one of titanium, titanium nitride and tungsten or a variety of；First dielectric layer and second dielectric layer
Material be selected from one of aluminium oxide, silicon nitride, silica and zirconium oxide or a variety of.
An embodiment according to the present utility model, the height of the fixing layer account for the 1/ of capacitance forming hole height
5~1/3.
An embodiment according to the present utility model, the top support layer with a thickness of 30nm~45nm, the bottom
Portion's supporting layer with a thickness of 30nm~45nm, the lower electrode layer with a thickness of 5~15nm, the thickness of second upper electrode layer
For 5~10nm, first dielectric layer with a thickness of 4nm~10nm, second dielectric layer with a thickness of 4nm~10nm.
Description according to the above technical scheme it is found that the utility model has the beneficial effects that:
The utility model is different from existing hollow capacitor by providing a kind of new capacitance structure and forming method thereof
Column will fill inside capacitive post in capacitance structure forming process and form fixing layer at the top of capacitive post, make capacitance structure more
Add stabilization, easily collapse the problem of unstable so as to improve the hollow capacitive post itself increased, while also avoiding forming process
The shaking (wobbling) and phenomenon of collapsing that middle wet etching (wet etch) easily occurs, substantially increase the stabilization of capacitance structure
Property and device performance.
Detailed description of the invention
In order to which the utility model embodiment can be easier to understand, appended attached drawing is cooperated to elaborate below.It should infuse
Meaning, according to industrial classical example, all parts are not necessarily drawn to scale, and are only used for the purpose illustrated.It is practical
On, in order to make discussion clear understandable, the size of all parts can be arbitrarily expanded or reduced.
Fig. 1 is a kind of schematic perspective view of capacitance structure in the prior art；
Fig. 2 is a capacitive post cross-sectional structure schematic diagram in capacitance structure shown in Fig. 1；
Fig. 3 is a kind of schematic perspective view of the capacitance structure after wet etch process in the prior art；
Fig. 4 is the schematic perspective view of the capacitance structure of one embodiment of the utility model；
Fig. 5 is a capacitive post cross-sectional structure schematic diagram in the capacitance structure of one embodiment of the utility model
Fig. 6 is the schematic cross-sectional view of the capacitance structure of one embodiment of the utility model；
Fig. 7 shows the formation process flow chart of the capacitance structure of one embodiment of the utility model；
Each stage section signal of the formation process for the capacitance structure that Fig. 8 a- Fig. 8 m shows one embodiment of the utility model
Figure.
Wherein, the reference numerals are as follows:
100,200: substrate
101: bottom support layer
102,201: capacitive post
103,202: top support layer
1021,2011: the first dielectric layer
1022,2012: lower electrode layer
1023,2013: the second dielectric layer
1024: upper electrode layer
2010: the first upper electrode layers
2014: the second upper electrode layers
200a: capacitor contact
201a: capacitive post extension
201b: capacitive post body part
203: fixing layer
203a: opening
204: bottom support layer
205: polysilicon layer
206: metal tungsten layer
2001: composite layer
2002: capacitance forming hole
2040: the first sacrificial layers
2020: the second sacrificial layers
V: top channel
Specific embodiment
The following contents provides many different embodiments or example, to realize the different components of the utility model embodiment.
The concrete example of component and configuration mode is described below, to simplify the utility model embodiment.Certainly, these are only example,
And not intended to limit the utility model embodiment.The utility model embodiment can in each example repeat reference numerals and/or
Letter.This repeats to be for purposes of simplicity and clarity, itself to be not intended to specified discussed each embodiment and/or match
Relationship between setting.In addition, in the following description, descriptions of well-known structures and technologies are omitted, to avoid unnecessarily mixing
Confuse the concept of the utility model.
Formed in the utility model embodiment a component on another component, be connected to another component, and/or be coupled to
Another component may include the embodiment to form this component and directly contact another component, and also may include forming additional portion
Part is between these components, so that the embodiment that these components are not directly contacted with.Furthermore in order to be easy description the utility model
Relationship between one component of embodiment and another component, can be used space correlation term herein, for example, " compared with
It is low ", " higher ", "horizontal", " vertical ", " in ... top ", " on ", " in ... lower section ", " ... it is beneath ", " upwards ", " to
Under ", " top ", " bottom " and etc. derived from space correlation term (such as " horizontally ", " vertically ", " upward ", " down "
Deng).These space correlation terms are intended to cover the different direction of the device comprising these components.
Fig. 1 is a kind of schematic perspective view of capacitance structure in the prior art.As shown in Figure 1, the capacitance structure packet
It includes: substrate 100, bottom support layer 101, multiple capacitive posts 102 and top support layer 103.Fig. 2 is in capacitance structure shown in Fig. 1
A capacitive post cross-sectional structure schematic diagram.As shown in Fig. 2, the capacitive post 102 is a hollow capacitive post, include from inside to outside
First dielectric layer 1021, lower electrode layer 1022, the second dielectric layer 1023, upper electrode layer 1024.However, as depicted in figs. 1 and 2,
In the case where electrode plate is constantly thinned, the hollow capacitive post increased as formation can face a series of problems, for example, a side
Face capacitive post itself can be unstable in structure, easily collapses；On the other hand in processing step, it will usually be moved using wet etching
The high dielectric material of two-sided (double side) is formed except sacrificial layer (not shown), sacrificial layer generallys use silica
(SiO2), the materials such as phosphorosilicate glass (PSG) and boron-phosphorosilicate glass (BPSG), it is molten wherein used etching solution is difficult to remove
The surface tension of agent can stretch capacitive post, and then lead to the shaking of capacitance structure (see Fig. 3).
For this purpose, the utility model provides a kind of capacitance structure, Fig. 4 is the capacitive junctions of one embodiment of the utility model
The schematic perspective view of structure, Fig. 5 are a capacitive post cross section in the capacitance structure of one embodiment of the utility model
Structural schematic diagram, Fig. 6 are the diagrammatic cross-section of the capacitance structure of one embodiment of the utility model.In conjunction with Fig. 4-Fig. 6 it is found that
The capacitance structure includes:
One substrate 200, the capacitor contact 200a with multiple intervals；
Multiple capacitive posts 201, the capacitive post are formed on the substrate, and with the capacitor engagement contacts, the electricity
Rong Zhu include from inside to outside the first upper electrode layer 2010, the first dielectric layer 2011, lower electrode layer 2012, the second dielectric layer 2013 and
Second upper electrode layer 2014；
Top support layer 202, is parallel to the substrate 200, and the multiple capacitive post 201 is through the top support layer
202, form the capacitive post body part 201b of the capacitive post extension 201a and lower section that are located above the top support layer；
Fixing layer 203 is formed in the periphery of the capacitive post extension 201a, and the fixing layer is perpendicular to the substrate
The capacitive post extension 201a is entirely or partly covered on direction.
Above-mentioned capacitance structure provided by the utility model, by adding fixing layer above capacitive post top support layer,
The fixing layer is set preferably to play the fixed effect of capacitor.The height of the fixing layer 203 can be higher than or be parallel to capacitor
Column extension can also be lower than the capacitive post extension, to play fixed function.
In some embodiments, the first upper electrode layer is stuffed entirely with the inside of the capacitive post, i.e. first upper electrode layer
Material fills up the space in the capacitive post within the first dielectric layer, so relative to hollow capacitive post or the capacitor being partially filled with
Column, structure are more stable.
In some embodiments, the material of the fixing layer is identical as the material of first upper electrode layer.Fixing layer
Height accounts for the 1/5~1/3 of the capacitive post height.The height of the capacitive post is 800~1600nm.
In some embodiments, above-mentioned capacitance structure can also include bottom support layer 204, the formation of bottom support layer 204
In on the substrate 200, the bottom of the capacitive post body part is engaged in the electricity on the substrate through the bottom support layer
Hold contact.The effect of bottom support layer 204 and top support layer 202 is fixed capacity column, and wherein bottom support layer 204 is used for
The bottom of fixed capacity column, top support layer 202 is used to assist the top of 203 fixed capacity column of fixing layer, in this way, making capacitor
Rod structure is more stable.The top support layer with a thickness of 30nm~45nm, the bottom support layer with a thickness of 30nm~
45nm。
In some embodiments, which has multiple opening 203a, on second dielectric layer and described second
Electrode layer extends through the opening and is covered in the surface of the fixing layer, i.e., can also wrap in 203 upper surface of fixing layer
Containing one layer of second dielectric layer and the second upper electrode layer.
In some embodiments, above-mentioned capacitance structure further includes polysilicon layer 205, which is located at the second electricity
The outer surface of pole layer 2014.By deposit polycrystalline silicon layer 205, it on the one hand can stablize capacitive post, on the other hand can also be used as
Conductive material, the polysilicon layer can also adulterate one of boron, arsenic, phosphorus and germanium or a variety of.
In some embodiments, one layer can also be formed selectively between the polysilicon layer 205 and the second electrode lay
Metal tungsten layer 206.
In some embodiments, the material of first upper electrode layer, the lower electrode layer and second upper electrode layer
Selected from one of titanium, titanium nitride and tungsten or a variety of, wherein the first upper electrode layer material can be with second top electrode
Layer material is identical, can also be different；The material of first dielectric layer and second dielectric layer be selected from aluminium oxide, silicon nitride,
One of silica and zirconium oxide are a variety of, wherein first dielectric layer material can be with the second dielectric layer material phase
Together, it can also be different.
In some embodiments, the lower electrode layer with a thickness of 5~15nm, second upper electrode layer with a thickness of 5
~10nm, first dielectric layer with a thickness of 4nm~10nm, second dielectric layer with a thickness of 4nm~10nm.
The utility model provides a kind of forming method of capacitance structure again, and Fig. 7 shows one embodiment of the utility model
Capacitance structure formation process flow chart, this method comprises:
The substrate of the one capacitor contact with multiple intervals is provided；
Composite layer is formed on the substrate, including sequentially forms bottom support layer, the from bottom to top on the substrate
One sacrificial layer, top support layer and the second sacrificial layer；
Multiple capacitance forming holes are formed in the composite layer, the capacitance forming hole is made to manifest the corresponding capacitor
Contact；
Lower electrode layer is formed in the multiple capacitance forming hole, the lower electrode layer is engaged in the capacitor contact；
Second sacrificial layer is removed until appearing the top support layer, the top support layer and extends the top
The lower electrode layer above portion's supporting layer constitutes top channel；
The first dielectric layer is formed on the lower electrode layer and the top support layer；
The first upper electrode layer is formed on first dielectric layer, fills the capacitance forming hole and shape with all or part of
At fixing layer in the top channel, the fixing layer completely or partially covers the top channel；
Multiple top support layers for being opened on the fixing layer, and being etched through in the removal opening are formed, so that institute
The side wall for stating opening manifests the first upper electrode layer and the bottom of the opening is made to appear the first sacrificial layer；
First sacrificial layer is removed to appear corresponding lower electrode layer, then in the fixed layer surface, the institute appeared
The surface for the lower electrode layer stating the first upper electrode layer and appearing forms the second dielectric layer；
The second upper electrode layer is formed on second dielectric layer.
Each stage section signal of the formation process for the capacitance structure that Fig. 8 a- Fig. 8 m shows one embodiment of the utility model
Figure has multiple capacitor contact 200a, such as tungsten metal interconnecting wires, in the substrate 200 as shown in Figure 8 a on substrate 200
Upper formation composite layer 2001, the composite layer 2001 include the bottom support layer sequentially formed from bottom to top on the substrate 200
204, the first sacrificial layer 2040, top support layer 202 and the second sacrificial layer 2020.Wherein the first sacrificial layer 2040 and second is sacrificed
The material of layer 2020 includes but is not limited to silica (SiO2), phosphorosilicate glass (PSG) and boron-phosphorosilicate glass (BPSG) etc., first is sacrificial
The material and the material of the second sacrificial layer of domestic animal layer can be identical or different, the first sacrificial layer with a thickness of 500~1000nm, second
Sacrificial layer with a thickness of 300~500nm.
As shown in Figure 8 b, the 2001 multiple capacitance forming holes 2002 of formation in the composite layer, make the capacitance forming hole
2002 manifest corresponding capacitor contact (tungsten metal interconnecting wires) 200a.Specifically, in some embodiments, by sacrificial second
Coat photoresist and anti-reflection coating (Anti-Reflection Coating, ARC) on domestic animal layer 2020, using exposure development or
Person's double-exposure technique defines the pattern in capacitance forming hole.Then dry etching is removed comprising compound with multiple material
Layer, etching rest on the upper surface of tungsten metal layer, form the capacitance forming hole 2002 for being connected to bottom.
As shown in Fig. 8 c- Fig. 8 d, lower electrode layer 2012 is formed in the multiple capacitance forming hole, the lower electrode layer connects
Together in the capacitor contact.Specifically, on the basis of structure as shown in Figure 8 b, using chemical vapor deposition (CVD) or original
The method of son vapor deposition (ALD) deposits lower electrode layer 2012, which includes but is not limited to titanium (Ti), titanium nitride
(TiN) or tungsten (W) etc., deposition with a thickness of 5nm~15nm.Then in the structure shown in Fig. 8 c, using dry etching or chemistry
The method of mechanical lapping (CMP) removes the lower electrode layer material of 2020 upper surface of the second sacrificial layer to get knot as shown in figure 8d
Structure.
As figure 8 e shows, remove the second sacrificial layer 2020 until appearing top support layer 202, top support layer 202 with prolong
The lower electrode layer stretched out above the top support layer constitutes top channel V.Wherein, the method packet of the second sacrificial layer 2020 is removed
It includes but is not limited to using diluted hydrofluoric acid (DHF) wet etching.
As illustrated in fig. 8f, the first dielectric layer 2011 is formed on the lower electrode layer 2012 and the top support layer 202.
First dielectric layer material includes but is not limited to aluminium oxide, silicon nitride, silica, zirconium oxide etc. or combinations thereof, with a thickness of 4nm
~10nm.Specifically, forming method can be used chemical vapor deposition (CVD) or atomic vapor deposition (ALD), and forming process can be with
It is batch or one chip reaction.
As illustrated in fig.8g, formed the first upper electrode layer 2010 on first dielectric layer 2011, fill the capacitor at
Type hole 2002 simultaneously forms fixing layer 203 in the top channel V, and the fixing layer 203 can all cover the top channel V.
Wherein, forming method can be used chemical vapor deposition (CVD) or atomic vapor deposition (ALD), the material of fixing layer 203 with it is described
First upper electrode layer material is identical, including but not limited to titanium (Ti), titanium nitride (TiN) or tungsten (W) etc., and the height of fixing layer accounts for institute
State the 1/5~1/3 of capacitance forming hole height.Capacitance forming hole can be stuffed entirely with by the first upper electrode layer material, can also be by portion
Divide filling.Wherein, the thickness range that the first upper electrode layer is grown from the first dielectric layer surface is 6nm~20nm, on even first
Electrode layer fills up the capacitance forming hole, and the thickness of the first upper electrode layer is no more than 40nm in the capacitance forming hole.
As shown in Fig. 8 h, multiple opening 203a are formed in the fixing layer 203, and be etched through and remove in the opening
Top support layer 202, so that the side wall of the opening manifests the first upper electrode layer and the bottom of the opening is made to appear first
Sacrificial layer 2040.One of them described opening only with a capacitance forming hole is overlapping or opening can simultaneously with
Multiple capacitance forming holes are overlapping.Specifically, forming method can be used photoetching technique to the portion of upper surface of fixing layer 203 into
Row exposure development, with chemical gas, such as C4F6、SF6、Cl2、BCl3Equal by top opening, and etch and reach the first sacrificial layer
Until 2040, expose the first sacrificial layer 2040, and expose the first upper electrode layer material of opening sidewalls simultaneously.
As illustrated in fig. 8i, first sacrificial layer 2040 is removed to appear corresponding lower electrode layer.Specifically, using wet process
Etching selectively only etches away the first sacrificial layer material, retains on top support layer 202, bottom support layer 204 and side wall
Each electrode material exposed.
As shown in Fig. 8 j, then the fixed layer surface, first upper electrode layer appeared and appear it is described under
The surface of electrode layer forms the second dielectric layer 2013.Forming method can be heavy using chemical vapor deposition (CVD) or atom gas phase
Product (ALD), the second dielectric layer material include but is not limited to aluminium oxide, silicon nitride, silica, zirconium oxide etc. or combinations thereof, thickness
Degree is 4nm~10nm, and the second dielectric layer material can be identical or not identical with the first dielectric layer material.
As shown in Fig. 8 k, the second upper electrode layer 2014 is formed on second dielectric layer 2013.Forming method can adopt
With chemical vapor deposition (CVD) or atomic vapor deposition (ALD), the second upper electrode layer material includes but is not limited to titanium (Ti), nitrogen
Change titanium (TiN) or tungsten (W) etc., with a thickness of 5~15nm.Second upper electrode layer material can be identical as first layer upper electrode material
Or it is different.
In some embodiments, can also continue to be formed polysilicon layer 205 on second upper electrode layer 2014 (see figure
8l).Forming method can use chemical vapor deposition (CVD) or atomic vapor deposition (ALD), deposition with a thickness of 120nm~
200nm.By deposit polycrystalline silicon layer in column capacitor on the second upper electrode layer, on the one hand can be stablized, on the one hand can also make
For conductive material.In some embodiments, it is also an option that property electrode metal surface selectivity on the second layer deposition one
Redeposited polysilicon layer after layer tungsten metal layer 206.The deposition raw material of polysilicon layer can be silane (Silane) or second silicon
Alkane (disilane) can be simultaneously doped with boron, arsenic, one of phosphorus or Germanium or more persons.
As shown in Fig. 8 m, in some embodiments, the top coating in the capacitance structure as shown in Fig. 8 l can also continue to
Photoresist and anti-reflection coating are powered on top second layer upper electrode material and first layer using exposure development technology dry etching
Pole material etches go out through-hole, and fill conductive metal material, and purpose is grounded the first and second upper electrode materials.
To sum up, by the obtained capacitance structure of the above method, by utilizing the first upper electrode layer material in forming process
Material fills hollow capacitive post, and forms fixing layer at the top of capacitive post simultaneously, and the better stability of capacitance structure may be implemented,
So that the capacitance structure of high-aspect-ratio is unlikely to collapse and shake in the first sacrificial layer material of wet etching, substantially increase
The stability and device performance of capacitance structure.
Those skilled in the art should be noted that embodiment described in the utility model is only exemplary,
Various other replacements, changes and improvements can be made in the scope of the utility model.Thus, the utility model is not limited to above-mentioned reality
Mode is applied, and is only defined by the claims.
Claims (13)
1. a kind of capacitance structure, comprising:
One substrate, the capacitor contact with multiple intervals；
Multiple capacitive posts, the capacitive post are formed on the substrate, and with the capacitor engagement contacts, the capacitive post is by interior
And outside include the first upper electrode layer, the first dielectric layer, lower electrode layer, the second dielectric layer and the second upper electrode layer；
Top support layer, is parallel to the substrate, and the multiple capacitive post is formed described in being located at through the top support layer
The capacitive post body part of capacitive post extension and lower section above top support layer；
Fixing layer is formed in the periphery of the capacitive post extension, and the fixing layer is perpendicular to whole on the orientation substrate
Or partly cover the capacitive post extension.
2. capacitance structure according to claim 1, which is characterized in that the height of the fixing layer accounts for the capacitive post height
1/5~1/3.
3. capacitance structure according to claim 1, which is characterized in that the height of the capacitive post is 800~1600nm.
4. capacitance structure according to claim 1, which is characterized in that the material of the fixing layer and first top electrode
The material of layer is identical.
5. capacitance structure according to claim 1, which is characterized in that first upper electrode layer is stuffed entirely with the capacitor
The inside of column.
6. capacitance structure according to claim 1, which is characterized in that the fixing layer have multiple openings, described second
Dielectric layer and second upper electrode layer are extended through the opening and are covered in the surface of the fixing layer.
7. capacitance structure according to claim 1, which is characterized in that the capacitance structure further includes a bottom support layer,
The bottom support layer is formed on the substrate, and the bottom of the capacitive post body part is engaged in through the bottom support layer
Capacitor contact on the substrate.
8. capacitance structure according to claim 7, which is characterized in that the top support layer with a thickness of 30nm~
45nm, the bottom support layer with a thickness of 30nm~45nm.
9. capacitance structure according to claim 1, which is characterized in that first upper electrode layer, the lower electrode layer and
The material of second upper electrode layer is selected from one of titanium, titanium nitride and tungsten or a variety of；First dielectric layer and described
The material of two dielectric layers is selected from one of aluminium oxide, silicon nitride, silica and zirconium oxide or a variety of.
10. capacitance structure according to claim 9, which is characterized in that the lower electrode layer with a thickness of 5~15nm, institute
State the second upper electrode layer with a thickness of 5~10nm, first dielectric layer with a thickness of 4nm~10nm, second dielectric layer
With a thickness of 4nm~10nm.
11. according to claim 1, capacitance structure described in any one of 6,7, which is characterized in that the capacitance structure further includes
Polysilicon layer, the polysilicon layer are located at the outer surface of second upper electrode layer.
12. capacitance structure according to claim 11, which is characterized in that in the doping polycrystalline silicon layer boron, arsenic, phosphorus and germanium
It is one or more.
13. capacitance structure according to claim 11, which is characterized in that the polysilicon layer and second upper electrode layer
Between further include one layer of metal tungsten layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109148426A (en) * | 2018-09-29 | 2019-01-04 | 长鑫存储技术有限公司 | Capacitance structure and forming method thereof |
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2018
- 2018-09-29 CN CN201821598132.9U patent/CN208767297U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148426A (en) * | 2018-09-29 | 2019-01-04 | 长鑫存储技术有限公司 | Capacitance structure and forming method thereof |
| CN109148426B (en) * | 2018-09-29 | 2024-03-29 | 长鑫存储技术有限公司 | Capacitor structure and forming method thereof |
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