CN109148427A - Capacitance structure and forming method thereof - Google Patents
Capacitance structure and forming method thereof Download PDFInfo
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- CN109148427A CN109148427A CN201811146228.6A CN201811146228A CN109148427A CN 109148427 A CN109148427 A CN 109148427A CN 201811146228 A CN201811146228 A CN 201811146228A CN 109148427 A CN109148427 A CN 109148427A
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000003990 capacitor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims description 52
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 22
- 229910052796 boron Inorganic materials 0.000 claims description 22
- 229910052698 phosphorus Inorganic materials 0.000 claims description 22
- 239000011574 phosphorus Substances 0.000 claims description 22
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 18
- 229910052721 tungsten Inorganic materials 0.000 claims description 18
- 239000010937 tungsten Substances 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 11
- 239000002131 composite material Substances 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of capacitance structure and forming method thereof, which includes: a substrate, the capacitor contact with multiple intervals；Multiple capacitive posts, capacitive post are formed on substrate, and with capacitor engagement contacts, capacitive post includes the first upper electrode layer, the first dielectric layer, lower electrode layer, the second dielectric layer and the second upper electrode layer from inside to outside；Fixing layer, it is parallel to the substrate, multiple capacitive posts form the capacitive post body part of the capacitive post extension and lower section that are located above fixing layer through the fixing layer, and fixing layer entirely or partly covers the capacitive post extension on perpendicular to the orientation substrate.The capacitance structure improves that the hollow capacitive post itself increased is unstable, easy the problem of collapsing, avoid the shaking and phenomenon of collapsing that wet etching in forming process easily occurs, furthermore, the capacitance structure is without top support layer, process costs have been saved again under the premise of guaranteeing that capacitor element performance is stablized, and there is good industrial prospect.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of capacitance structure and forming method thereof
Background technique
As dynamic random access memory (DRAM) characteristic size persistently reduces, the capacitor of capacitor is also constantly subtracting
It is small, capacitor is improved by making the capacitor of high aspect ratio structure and forming the dielectric material of two-sided (double side) structure
It is the effective method for improving capacitor.In the application of high aspect ratio structure, it usually needs prepare sacrificial layer to etch height
The materials such as boron-phosphorosilicate glass (boro-phospho-silicate-glass, BPSG) can be used in aspect-ratio holes, sacrificial layer.
However, the capacitance structure for forming high-aspect-ratio can face a series of problems in the case where electrode plate is constantly thinned,
For example, the hollow capacitive post on the one hand increased can be unstable in structure, easily collapse；On the other hand wet process is carved in processing step
When erosion removes high dielectric material of the BPSG to form two-sided (double side), wherein used etching solution is difficult to remove,
The surface tension of solvent can stretch capacitive post, lead to the shaking of capacitance structure.
For this purpose, it is urgent to provide a kind of new capacitance structures and forming method thereof, to solve on existing in the prior art
State variety of problems.
It is noted that information disclosed in aforementioned background art part is only used for reinforcing understanding background of the invention, because
This it may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The object of the present invention is to provide a kind of capacitance structures and forming method thereof, to solve easily to occur in existing capacitance structure
Structural instability and subsequent technique on easily cause structure destroy the problem of.
To achieve the goals above, the present invention adopts the following technical scheme:
The present invention provides a kind of capacitance structure, comprising:
One substrate, the capacitor contact with multiple intervals；
Multiple capacitive posts, the capacitive post are formed on the substrate, and with the capacitor engagement contacts, the capacitive post
It from inside to outside include the first upper electrode layer, the first dielectric layer, lower electrode layer, the second dielectric layer and the second upper electrode layer；
Fixing layer, is parallel to the substrate, and the multiple capacitive post forms through the fixing layer and is located at the fixation
The capacitive post extension of layer top and the capacitive post body part of lower section, the fixing layer is perpendicular to whole on the orientation substrate
Or partly cover the capacitive post extension.
According to embodiment of the present invention, the height of the fixing layer accounts for the 1/5~1/3 of the capacitive post height.
According to embodiment of the present invention, the height of the capacitive post is 800~1600nm.
According to embodiment of the present invention, the material phase of the material of the fixing layer and first upper electrode layer
Together.
According to embodiment of the present invention, first upper electrode layer is stuffed entirely with the inside of the capacitive post.
According to embodiment of the present invention, the fixing layer has multiple openings, second dielectric layer and described
Second upper electrode layer is extended through the opening and is covered in the surface of the fixing layer.
According to embodiment of the present invention, the capacitance structure further includes a bottom support layer, the bottom support
Layer is formed on the substrate, and the bottom of the capacitive post body part is engaged on the substrate through the bottom support layer
Capacitor contact.
According to embodiment of the present invention, the bottom support layer with a thickness of 30nm~45nm.
According to embodiment of the present invention, first upper electrode layer, the lower electrode layer and described second power on
The material of pole layer is selected from one of titanium, titanium nitride and tungsten or a variety of；The material of first dielectric layer and second dielectric layer
Material is selected from one of aluminium oxide, silicon nitride, silica and zirconium oxide or a variety of.
According to embodiment of the present invention, the lower electrode layer with a thickness of 5~15nm, second upper electrode layer
With a thickness of 5~10nm, first dielectric layer with a thickness of 4nm~10nm, second dielectric layer with a thickness of 4nm~
10nm。
According to embodiment of the present invention, the capacitance structure further includes polysilicon layer, and the polysilicon layer is located at
The outer surface of second upper electrode layer.
According to embodiment of the present invention, one of the doping polycrystalline silicon layer boron, arsenic, phosphorus and germanium or a variety of.
It according to embodiment of the present invention, further include one layer between the polysilicon layer and second upper electrode layer
Metal tungsten layer.
The present invention also provides a kind of forming methods of capacitance structure, comprising:
The substrate of the one capacitor contact with multiple intervals is provided；
Composite layer is formed on the substrate, including sequentially forms bottom support layer, the from bottom to top on the substrate
One sacrificial layer, the second sacrificial layer and 3rd sacrifice layer；
Multiple capacitance forming holes are formed in the composite layer, the capacitance forming hole is made to manifest the corresponding capacitor
Contact；
Lower electrode layer is formed in the multiple capacitance forming hole, the lower electrode layer is engaged in the capacitor contact；
The 3rd sacrifice layer is removed until appearing second sacrificial layer, second sacrificial layer and extends described the
The lower electrode layer above two sacrificial layers constitutes top channel；
The first dielectric layer is formed on the lower electrode layer and second sacrificial layer；
The first upper electrode layer is formed on first dielectric layer, fills the capacitance forming hole and shape with all or part of
At fixing layer in the top channel, the fixing layer completely or partially covers the top channel；
Multiple the second sacrificial layers for being opened on the fixing layer, and being etched through in the removal opening are formed, so that institute
The side wall for stating opening manifests the first upper electrode layer and the bottom of the opening is made to appear the first sacrificial layer；
First sacrificial layer and the second sacrificial layer are removed to appear corresponding lower electrode layer, then in the fixing layer table
The surface in face, first upper electrode layer appeared and the lower electrode layer appeared forms the second dielectric layer；
The second upper electrode layer is formed on second dielectric layer.
According to embodiment of the present invention, the material of first sacrificial layer, the second sacrificial layer and 3rd sacrifice layer
Selected from one of silica, phosphorosilicate glass and boron-phosphorosilicate glass or a variety of.
According to embodiment of the present invention, the material of first sacrificial layer, the second sacrificial layer and 3rd sacrifice layer
It is boron-phosphorosilicate glass, wherein the phosphorus doping that the phosphorus doping density of second sacrificial layer is respectively lower than first sacrificial layer is dense
The phosphorus doping density of degree and 3rd sacrifice layer, the boron doping concentration of second sacrificial layer are respectively higher than first sacrificial layer
The boron doping concentration of boron doping concentration and 3rd sacrifice layer.
According to embodiment of the present invention, the phosphorus doping density of first sacrificial layer is 2.8~4wt%, and boron is mixed
Miscellaneous concentration is 2~4wt%；The phosphorus doping density of second sacrificial layer is 2~4wt%, and boron doping concentration is 3~6.5wt%；
The phosphorus doping density of the 3rd sacrifice layer is 2.5~5.5wt%, and boron doping concentration is 2~3wt%.
According to embodiment of the present invention, the etching selectivity between the 3rd sacrifice layer and the second sacrificial layer is
(800~15000): 1；The etching selectivity of second sacrificial layer and the first sacrificial layer is 1:(800~12000).
According to embodiment of the present invention, the time for removing the first sacrificial layer is 30~45s, described to remove the
The time of two sacrificial layers is 3~5s, and the time for removing 3rd sacrifice layer is 50~150s.
According to embodiment of the present invention, first sacrificial layer is sacrificial with a thickness of 500~1000nm, described second
Domestic animal layer with a thickness of 30~45nm, the 3rd sacrifice layer with a thickness of 300~500nm.
It according to embodiment of the present invention, further include forming polysilicon layer on second upper electrode layer.
It according to embodiment of the present invention, further include forming metal tungsten layer on the polysilicon layer and described second
Between electrode layer.
According to embodiment of the present invention, an opening is only overlapping or one with a capacitance forming hole
A opening is overlapping with multiple capacitance forming holes simultaneously.
According to embodiment of the present invention, first upper electrode layer, the lower electrode layer and described second power on
The material of pole layer is selected from one of titanium, titanium nitride and tungsten or a variety of；The material of first dielectric layer and second dielectric layer
Material is selected from one of aluminium oxide, silicon nitride, silica and zirconium oxide or a variety of.
According to embodiment of the present invention, the height of the fixing layer account for capacitance forming hole height 1/5~
1/3。
According to embodiment of the present invention, the bottom support layer with a thickness of 30nm~45nm, the lower electrode
Layer with a thickness of 5~15nm, second upper electrode layer with a thickness of 5~10nm, first dielectric layer with a thickness of 4nm~
10nm, second dielectric layer with a thickness of 4nm~10nm.
Description according to the above technical scheme it is found that the beneficial effects of the present invention are:
The present invention provides a kind of new capacitance structure and forming method thereof, which is different from existing hollow electricity
Rong Zhu will fill inside capacitive post in capacitance structure forming process and form fixing layer at the top of capacitive post, make capacitance structure
It is more stable, easily collapse the problem of unstable so as to improve the hollow capacitive post itself increased, while also avoiding being formed
The shaking (wobbling) and phenomenon of collapsing that wet etching (wet etch) easily occurs in journey, substantially increase the steady of capacitance structure
Qualitative and device performance.In addition, the forming method of the capacitance structure can utilize the element doping concentration different band of different sacrificial layers
Carry out etching selectivity, to form the capacitance structure without top support layer, is saved again under the premise of guaranteeing that capacitor element performance is stablized
About process costs have good industrial prospect.
Detailed description of the invention
In order to which the embodiment of the present invention can be easier to understand, appended attached drawing is cooperated to elaborate below.It should be noted that root
According to industrial classical example, all parts are not necessarily drawn to scale, and are only used for the purpose illustrated.In fact, being
Make discussion clear understandable, the size of all parts can be arbitrarily expanded or reduced.
Fig. 1 is a kind of schematic perspective view of capacitance structure in the prior art；
Fig. 2 is a capacitive post cross-sectional structure schematic diagram in capacitance structure shown in Fig. 1；
Fig. 3 is a kind of schematic perspective view of the capacitance structure after wet etch process in the prior art；
Fig. 4 is the schematic perspective view of the capacitance structure of one embodiment of the present invention；
Fig. 5 is a capacitive post cross-sectional structure schematic diagram in the capacitance structure of one embodiment of the present invention
Fig. 6 is the diagrammatic cross-section of the capacitance structure of one embodiment of the present invention；
Fig. 7 shows the formation process flow chart of the capacitance structure of one embodiment of the present invention；
Each stage diagrammatic cross-section of formation process for the capacitance structure that Fig. 8 a- Fig. 8 m shows one embodiment of the present invention.
Wherein, the reference numerals are as follows:
100,200: substrate
101: bottom support layer
102,201: capacitive post
103: top support layer
1021,2011: the first dielectric layer
1022,2012: lower electrode layer
1023,2013: the second dielectric layer
1024: upper electrode layer
2010: the first upper electrode layers
2014: the second upper electrode layers
200a: capacitor contact
201a: capacitive post extension
201b: capacitive post body part
202: fixing layer
202a: opening
203: bottom support layer
204: polysilicon layer
205: metal tungsten layer
2001: composite layer
2002: capacitance forming hole
2030: the first sacrificial layers
2031: the second sacrificial layers
2032: 3rd sacrifice layer
V: top channel
Specific embodiment
The following contents provides many different embodiments or example, to realize the different components of the embodiment of the present invention.Below
The concrete example of component and configuration mode is described, to simplify the embodiment of the present invention.Certainly, these are only example, and are not intended to
Limit the embodiment of the present invention.The embodiment of the present invention can in each example repeat reference numerals and/or letter.This repeat be in order to
Simplified and clear purpose, the relationship itself being not intended between specified discussed each embodiment and/or configuration.This
Outside, in the following description, descriptions of well-known structures and technologies are omitted, so as not to unnecessarily obscure the concept of the present invention.
Formed in embodiments of the present invention a component on another component, be connected to another component, and/or be coupled to another
Component may include the embodiment to form this component and directly contact another component, and also may include forming additional component to be situated between
Between these components, so that the embodiment that these components are not directly contacted with.Furthermore in order to be easy the description embodiment of the present invention
Relationship between one component and another component, can be used space correlation term herein, for example, " lower ", " higher ",
"horizontal", " vertical ", " in ... top ", " on ", " in ... lower section ", " ... it is beneath ", " upwards ", " downwards ", " top ", "
Bottom " etc. derived from space correlation term (such as " horizontally ", " vertically ", " upward ", " down " etc.).These spaces
Relative terms are intended to cover the different direction of the device comprising these components.
Fig. 1 is a kind of schematic perspective view of capacitance structure in the prior art.As shown in Figure 1, the capacitance structure packet
It includes: substrate 100, bottom support layer 101, multiple capacitive posts 102 and top support layer 103.Fig. 2 is in capacitance structure shown in Fig. 1
A capacitive post cross-sectional structure schematic diagram.As shown in Fig. 2, the capacitive post 102 is a hollow capacitive post, include from inside to outside
First dielectric layer 1021, lower electrode layer 1022, the second dielectric layer 1023, upper electrode layer 1024.However, as depicted in figs. 1 and 2,
In the case where electrode plate is constantly thinned, the hollow capacitive post increased as formation can face a series of problems, for example, a side
Face capacitive post itself can be unstable in structure, easily collapses；On the other hand in processing step, it will usually be moved using wet etching
The high dielectric material of two-sided (double side) is formed except sacrificial layer (not shown), sacrificial layer generallys use silica
(SiO2), the materials such as phosphorosilicate glass (PSG) and boron-phosphorosilicate glass (BPSG), it is molten wherein used etching solution is difficult to remove
The surface tension of agent can stretch capacitive post, and then lead to the shaking of capacitance structure (see Fig. 3).
For this purpose, Fig. 4 is the solid of the capacitance structure of one embodiment of the present invention the present invention provides a kind of capacitance structure
Structural schematic diagram, Fig. 5 are a capacitive post cross-sectional structure schematic diagram in the capacitance structure of one embodiment of the present invention, figure
6 be the diagrammatic cross-section of the capacitance structure of one embodiment of the present invention.In conjunction with Fig. 4-Fig. 6 it is found that the capacitance structure includes:
One substrate 200, the capacitor contact 200a with multiple intervals；
Multiple capacitive posts 201, the capacitive post are formed on the substrate, and with the capacitor engagement contacts, the electricity
Rong Zhu include from inside to outside the first upper electrode layer 2010, the first dielectric layer 2011, lower electrode layer 2012, the second dielectric layer 2013 and
Second upper electrode layer 2014；
Fixing layer 202, is parallel to the substrate 200, and the multiple capacitive post 201 is formed through the fixing layer 202
The capacitive post body part 201b of capacitive post extension 201a and lower section above the fixing layer, the fixing layer is vertical
In entirely or partly covering the capacitive post extension 201a on the orientation substrate.
Above-mentioned capacitance structure provided by the invention enables the fixing layer more by adding fixing layer above capacitive post
Good plays the fixed effect of capacitor.The height of the fixing layer 202 can be higher than or be parallel to capacitive post extension, can also be low
In the capacitive post extension, to play fixed function.
In some embodiments, the first upper electrode layer is stuffed entirely with the inside of the capacitive post, i.e. first upper electrode layer
Material fills up the space in the capacitive post within the first dielectric layer, so relative to hollow capacitive post or the capacitor being partially filled with
Column, structure are more stable.
In some embodiments, the material of the fixing layer is identical as the material of first upper electrode layer.Fixing layer
Height accounts for the 1/5~1/3 of the capacitive post height.The height of the capacitive post is 800~1600nm.
It in some embodiments, can also include bottom support layer 203,203 shape of bottom support layer in above-mentioned capacitance structure
On substrate 200 described in Cheng Yu, the bottom of the capacitive post body part is engaged on the substrate through the bottom support layer
Capacitor contact.Bottom support layer 203 is used for the bottom of fixed capacity column, so that capacitor rod structure is more stable.The bottom support
Layer with a thickness of 30nm~45nm.
In some embodiments, which has multiple opening 202a, on second dielectric layer and described second
Electrode layer extends through the opening and is covered in the surface of the fixing layer, i.e., can also wrap in 202 upper surface of fixing layer
Containing one layer of second dielectric layer and the second upper electrode layer.
In some embodiments, above-mentioned capacitance structure further includes polysilicon layer 204, which is located at second and is situated between
The outer surface of electric layer 2013.By deposit polycrystalline silicon layer 204, it on the one hand can stablize capacitive post, on the other hand can also be used as
Conductive material, the polysilicon layer can also adulterate one of boron, arsenic, phosphorus and germanium or a variety of.
In some embodiments, one layer of metal can also be formed selectively between the polysilicon layer and the second dielectric layer
Tungsten layer 205.
In some embodiments, the material of first upper electrode layer, the lower electrode layer and second upper electrode layer
Selected from one of titanium, titanium nitride and tungsten or a variety of, wherein the first upper electrode layer material can be with second top electrode
Layer material is identical, can also be different；The material of first dielectric layer and second dielectric layer be selected from aluminium oxide, silicon nitride,
One of silica and zirconium oxide are a variety of, wherein first dielectric layer material can be with the second dielectric layer material phase
Together, it can also be different.
In some embodiments, the lower electrode layer with a thickness of 5~15nm, second upper electrode layer with a thickness of 5
~10nm, first dielectric layer with a thickness of 4nm~10nm, second dielectric layer with a thickness of 4nm~10nm.
The present invention provides a kind of forming method of capacitance structure again, and Fig. 7 shows the capacitive junctions of one embodiment of the present invention
The formation process flow chart of structure, this method comprises:
The substrate of the one capacitor contact with multiple intervals is provided；
Composite layer is formed on the substrate, including sequentially forms bottom support layer, the from bottom to top on the substrate
One sacrificial layer, the second sacrificial layer and 3rd sacrifice layer；
Multiple capacitance forming holes are formed in the composite layer, the capacitance forming hole is made to manifest the corresponding capacitor
Contact；
Lower electrode layer is formed in the multiple capacitance forming hole, the lower electrode layer is engaged in the capacitor contact；
The 3rd sacrifice layer is removed until appearing second sacrificial layer, second sacrificial layer and extends described the
The lower electrode layer above two sacrificial layers constitutes top channel；
The first dielectric layer is formed on the lower electrode layer and second sacrificial layer；
The first upper electrode layer is formed on first dielectric layer, fills the capacitance forming hole and shape with all or part of
At fixing layer in the top channel, the fixing layer completely or partially covers the top channel；
Multiple the second sacrificial layers for being opened on the fixing layer, and being etched through in the removal opening are formed, so that institute
The side wall for stating opening manifests the first upper electrode layer and the bottom of the opening is made to appear the first sacrificial layer；
First sacrificial layer and the second sacrificial layer are removed to appear corresponding lower electrode layer, then in the fixing layer table
The surface in face, first upper electrode layer appeared and the lower electrode layer appeared forms the second dielectric layer；
The second upper electrode layer is formed on second dielectric layer.
Each stage diagrammatic cross-section of formation process for the capacitance structure that Fig. 8 a- Fig. 8 m shows one embodiment of the present invention,
As shown in Figure 8 a, there is multiple capacitor contact 200a, such as tungsten metal interconnecting wires, the shape on the substrate 200 on substrate 200
At composite layer 2001, the composite layer 2001 include the bottom support layer 203 sequentially formed from bottom to top on the substrate 200,
First sacrificial layer 2030, the second sacrificial layer 2031 and 3rd sacrifice layer 2032.Wherein the first sacrificial layer, the second sacrificial layer and third
The material of sacrificial layer includes but is not limited to silica (SiO2), phosphorosilicate glass (PSG) and boron-phosphorosilicate glass (BPSG) etc., first is sacrificial
Domestic animal layer, the second sacrificial layer and 3rd sacrifice layer material can be identical or different, the first sacrificial layer with a thickness of 500~
1000nm, the second sacrificial layer with a thickness of 30~45nm, 3rd sacrifice layer with a thickness of 300~500nm.
In some embodiments, the material of first sacrificial layer 2030, the second sacrificial layer 2031 and 3rd sacrifice layer 2032
Material is boron-phosphorosilicate glass (BPSG), wherein the phosphorus doping density of second sacrificial layer is respectively lower than first sacrificial layer
The boron doping concentration of the phosphorus doping density of phosphorus doping density and 3rd sacrifice layer, second sacrificial layer is respectively higher than described first
The boron doping concentration of sacrificial layer 2030 and the boron doping concentration of 3rd sacrifice layer.
The phosphorus doping density of first sacrificial layer is 2.8~4wt%, and boron doping concentration is 2~4wt%；Described second
The phosphorus doping density of sacrificial layer is 2~4wt%, and boron doping concentration is 3~6.5wt%；The phosphorus doping of the 3rd sacrifice layer is dense
Degree is 2.5~5.5wt%, and boron doping concentration is 2~3wt%.Wherein, the boron phosphorus doped of the first sacrificial layer and 3rd sacrifice layer
Concentration can be different, can also be identical.
In some embodiments, the etching selectivity between the 3rd sacrifice layer and the second sacrificial layer be (800~
15000): 1；The etching selectivity of second sacrificial layer and the first sacrificial layer is 1:(800~12000).
As shown in Figure 8 b, the 2001 multiple capacitance forming holes 2002 of formation in the composite layer, make the capacitance forming hole
2002 manifest corresponding capacitor contact (tungsten metal interconnecting wires) 200a.Specifically, in some embodiments, by sacrificial second
Coat photoresist and anti-reflection coating (Anti-Reflection Coating, ARC) on domestic animal layer 2020, using exposure development or
Person's double-exposure technique defines the pattern in capacitance forming hole.Then dry etching is removed comprising compound with multiple material
Layer, etching rest on the upper surface of tungsten metal layer, form the capacitance forming hole 2002 for being connected to bottom.
As shown in Fig. 8 c- Fig. 8 d, lower electrode layer 2012 is formed in the multiple capacitance forming hole, the lower electrode layer connects
Together in the capacitor contact.Specifically, on the basis of structure as shown in Figure 8 b, using chemical vapor deposition (CVD) or original
The method of son vapor deposition (ALD) deposits 2012 material of lower electrode layer, which includes but is not limited to titanium (Ti), nitrogen
Change titanium (TiN) or tungsten (W) etc., deposition with a thickness of 5nm~15nm.Then in the structure shown in Fig. 8 c, using dry etching or
The method of chemical mechanical grinding (CMP) removes the lower electrode layer material of 2032 upper surface of 3rd sacrifice layer to get as shown in figure 8d
Structure.
As figure 8 e shows, remove 3rd sacrifice layer 2032 until appearing the second sacrificial layer 2031, the second sacrificial layer 2031 with
Extend the lower electrode layer above second sacrificial layer and constitutes top channel V.Wherein, diluted hydrogen is including but not limited to used
Fluoric acid (DHF) or hydrofluoric acid (HF) and ammonium fluoride (NH4F mixed liquor) removes 3rd sacrifice layer in the method for wet etching
2032.In some embodiments, the time for removing 3rd sacrifice layer is 50~150s.As previously described, because in the second sacrificial layer
Boron-doped content is higher, and rate of etch can reduce, and rate of etch, which can reduce, in this way after removing 3rd sacrifice layer even stops erosion
It carves.Second sacrificial layer can have a small amount of etch damage, but since rate of etch reduces, will not be gone when removing 3rd sacrifice layer
It removes.By the difference of the etching selectivity using 3rd sacrifice layer and the second sacrificial layer, the property of can choose to etch away third sacrificial
Domestic animal layer and retain the second sacrificial layer be not etched, thus can continue subsequent technique on the second sacrificial layer.
As illustrated in fig. 8f, the first dielectric layer 2011 is formed in the lower electrode layer 2012 and second sacrificial layer 2031
On.First dielectric layer material includes but is not limited to aluminium oxide, silicon nitride, silica, zirconium oxide etc. or combinations thereof, with a thickness of
4nm~10nm.Specifically, chemical vapor deposition (CVD) or atomic vapor deposition (ALD), forming process can be used in forming method
It can be batch or one chip reaction.
As illustrated in fig.8g, formed the first upper electrode layer 2010 on first dielectric layer 2011, fill the capacitor at
Type hole 2002 simultaneously forms fixing layer 202 in the top channel V, and the fixing layer 202 can all cover the top channel V.
Wherein, forming method can be used chemical vapor deposition (CVD) or atomic vapor deposition (ALD), the material of fixing layer 202 with it is described
First upper electrode layer material is identical, including but not limited to titanium (Ti), titanium nitride (TiN) or tungsten (W) etc., and the height of fixing layer accounts for institute
State the 1/5~1/3 of capacitance forming hole height.Capacitance forming hole can be stuffed entirely with by the first upper electrode layer material, can also be by portion
Divide filling.Wherein, the thickness range that the first upper electrode layer is grown from the first dielectric layer surface is 6nm~20nm, on even first
Electrode layer fills up the capacitance forming hole, and the thickness of the first upper electrode layer is no more than 40nm in the capacitance forming hole.
As shown in Fig. 8 h, multiple opening 202a are formed in the fixing layer 202, and be etched through and remove in the opening
Second sacrificial layer 2031, so that the side wall of the opening manifests the first upper electrode layer and the bottom of the opening is made to appear first
Sacrificial layer 2030.One of them described opening only with a capacitance forming hole is overlapping or opening can simultaneously with
Multiple capacitance forming holes are overlapping.Specifically, forming method can be used photoetching technique to the portion of upper surface of fixing layer 202 into
Row exposure development, with chemical gas, such as C4F6、SF6、Cl2、BCl3Equal by top opening, and etch and reach the first sacrificial layer
Until 2030, expose the first sacrificial layer 2030, and expose the first upper electrode layer material of opening sidewalls simultaneously.
As illustrated in fig. 8i, first sacrificial layer 2030 and the second sacrificial layer 2031 are removed to appear corresponding lower electrode layer
2012.Including but not limited to using diluted hydrofluoric acid (DHF) or hydrofluoric acid (HF) and ammonium fluoride (NH4F mixed liquor)
In the method for wet etching, it is selectively etched out the first sacrificial layer material and the second sacrificial layer material, retains and exposes on side wall
Each electrode material.Specifically, the first sacrificial layer and the second sacrificial layer etch respectively in order, first etch first and sacrifice
Layer, then etches the second sacrificial layer again.For example, etch the first sacrificial layer first, use diluted hydrofluoric acid (such as: concentration for
The HF of 49wt% is diluted with water, wherein HF and H2The volume ratio of O is 1:100) 30~45s of wet etching is carried out, it is sacrificial to remove first
Domestic animal layer；Then the second sacrificial layer is etched, using hydrofluoric acid (HF) and ammonium fluoride (NH4F) mixed liquor (such as: concentration is
The HF of 49wt%, the NH that concentration is 40wt%4The volume ratio of F and water is 1:7:140) 3~5s of wet etching is carried out, remove second
Sacrificial layer.
As shown in Fig. 8 j, then the fixed layer surface, first upper electrode layer appeared and appear it is described under
The surface of electrode layer forms the second dielectric layer 2013.Forming method can be heavy using chemical vapor deposition (CVD) or atom gas phase
Product (ALD), the second dielectric layer material include but is not limited to aluminium oxide, silicon nitride, silica, zirconium oxide etc. or combinations thereof, thickness
Degree is 4nm~10nm, and the second dielectric layer material can be identical or not identical with the first dielectric layer material.
As shown in Fig. 8 k, the second upper electrode layer 2014 is formed on second dielectric layer 2013.Forming method can adopt
With chemical vapor deposition (CVD) or atomic vapor deposition (ALD), the second upper electrode layer material includes but is not limited to titanium (Ti), nitrogen
Change titanium (TiN) or tungsten (W) etc., with a thickness of 5~15nm.Second upper electrode layer material can be identical as first layer upper electrode material
Or it is different.
In some embodiments, can also continue to be formed polysilicon layer 204 on second upper electrode layer 2014 (see figure
8l).Forming method can use chemical vapor deposition (CVD) or atomic vapor deposition (ALD).By deposit polycrystalline silicon layer in
On two upper electrode layers, it on the one hand can stablize column capacitor, on the one hand can also be used as conductive material.In some embodiments,
It is also an option that property ground redeposition polycrystalline after one layer of tungsten metal layer 205 of deposition of electrode metal surface selectivity on the second layer
Silicon layer.The deposition raw material of polysilicon layer can be silane (Silane) or disilane (disilane) can simultaneously doped with
Boron, arsenic, one of phosphorus or Germanium or more persons.
As shown in Fig. 8 m, in some embodiments, the top coating in the capacitance structure as shown in Fig. 8 l can also continue to
Photoresist and anti-reflection coating are powered on top second layer upper electrode material and first layer using exposure development technology dry etching
Pole material etches go out through-hole, and fill conductive metal material, and purpose is grounded the first and second upper electrode materials.
To sum up, by the obtained capacitance structure of the above method, by utilizing the first upper electrode layer material in forming process
Material fills hollow capacitive post, and forms fixing layer at the top of capacitive post simultaneously, and the better stability of capacitance structure may be implemented,
So that the capacitance structure of high-aspect-ratio is unlikely to collapse and shake in the first sacrificial layer material of wet etching, substantially increase
The stability and device performance of capacitance structure.In addition, forming method of the invention also utilizes the second sacrificial layer and other two to sacrifice
The etching selectivity of layer is different, can form required capacitance structure from without top support layer, is guaranteeing that capacitor element performance is steady
Process costs have been saved again under the premise of fixed, there is good industrial prospect.
Those skilled in the art should be noted that embodiment described in the invention is only exemplary, can be
Various other replacements, changes and improvements are made in the scope of the present invention.Thus, the present invention is not limited to the above embodiments, and only
It is defined by the claims.
Claims (26)
1. a kind of capacitance structure, comprising:
One substrate, the capacitor contact with multiple intervals；
Multiple capacitive posts, the capacitive post are formed on the substrate, and with the capacitor engagement contacts, the capacitive post is by interior
And outside include the first upper electrode layer, the first dielectric layer, lower electrode layer, the second dielectric layer and the second upper electrode layer；
Fixing layer, is parallel to the substrate, and the multiple capacitive post forms and is located on the fixing layer through the fixing layer
The capacitive post extension of side and the capacitive post body part of lower section, the fixing layer whole or portion on perpendicular to the orientation substrate
Ground is divided to cover the capacitive post extension.
2. capacitance structure according to claim 1, which is characterized in that the height of the fixing layer accounts for the capacitive post height
1/5~1/3.
3. capacitance structure according to claim 1, which is characterized in that the height of the capacitive post is 800~1600nm.
4. capacitance structure according to claim 1, which is characterized in that the material of the fixing layer and first top electrode
The material of layer is identical.
5. capacitance structure according to claim 1, which is characterized in that first upper electrode layer is stuffed entirely with the capacitor
The inside of column.
6. capacitance structure according to claim 1, which is characterized in that the fixing layer have multiple openings, described second
Dielectric layer and second upper electrode layer are extended through the opening and are covered in the surface of the fixing layer.
7. capacitance structure according to claim 1, which is characterized in that the capacitance structure further includes a bottom support layer,
The bottom support layer is formed on the substrate, and the bottom of the capacitive post body part is engaged in through the bottom support layer
Capacitor contact on the substrate.
8. capacitance structure according to claim 7, which is characterized in that the bottom support layer with a thickness of 30nm~
45nm。
9. capacitance structure according to claim 1, which is characterized in that first upper electrode layer, the lower electrode layer and
The material of second upper electrode layer is selected from one of titanium, titanium nitride and tungsten or a variety of；First dielectric layer and described
The material of two dielectric layers is selected from one of aluminium oxide, silicon nitride, silica and zirconium oxide or a variety of.
10. capacitance structure according to claim 9, which is characterized in that the lower electrode layer with a thickness of 5~15nm, institute
State the second upper electrode layer with a thickness of 5~10nm, first dielectric layer with a thickness of 4nm~10nm, second dielectric layer
With a thickness of 4nm~10nm.
11. according to claim 1, capacitance structure described in any one of 6,7, which is characterized in that the capacitance structure further includes
Polysilicon layer, the polysilicon layer are located at the outer surface of second upper electrode layer.
12. capacitance structure according to claim 11, which is characterized in that in the doping polycrystalline silicon layer boron, arsenic, phosphorus and germanium
It is one or more.
13. capacitance structure according to claim 11, which is characterized in that the polysilicon layer and second upper electrode layer
Between further include one layer of metal tungsten layer.
14. a kind of forming method of capacitance structure, comprising:
The substrate of the one capacitor contact with multiple intervals is provided；
Composite layer is formed on the substrate, including sequentially forms bottom support layer, first sacrificial from bottom to top on the substrate
Domestic animal layer, the second sacrificial layer and 3rd sacrifice layer；
Multiple capacitance forming holes are formed in the composite layer, the capacitance forming hole is made to manifest the corresponding capacitive touch
Point；
Lower electrode layer is formed in the multiple capacitance forming hole, the lower electrode layer is engaged in the capacitor contact；
The 3rd sacrifice layer is removed until appearing second sacrificial layer, second sacrificial layer with to extend described second sacrificial
The lower electrode layer of domestic animal layer top constitutes top channel；
The first dielectric layer is formed on the lower electrode layer and second sacrificial layer；
The first upper electrode layer is formed on first dielectric layer, fills the capacitance forming hole and formation admittedly with all or part of
Given layer completely or partially covers the top channel in the top channel, the fixing layer；
Multiple the second sacrificial layers for being opened on the fixing layer, and being etched through in the removal opening are formed, so that described open
The side wall of mouth manifests the first upper electrode layer and the bottom of the opening is made to appear the first sacrificial layer；
First sacrificial layer and the second sacrificial layer are removed to appear corresponding lower electrode layer, then the fixed layer surface,
The surface of first upper electrode layer appeared and the lower electrode layer appeared forms the second dielectric layer；
The second upper electrode layer is formed on second dielectric layer.
15. forming method according to claim 14, which is characterized in that first sacrificial layer, the second sacrificial layer and
The material of three sacrificial layers is selected from one of silica, phosphorosilicate glass and boron-phosphorosilicate glass or a variety of.
16. forming method according to claim 15, which is characterized in that first sacrificial layer, the second sacrificial layer and
The material of three sacrificial layers is boron-phosphorosilicate glass, wherein to be respectively lower than described first sacrificial for the phosphorus doping density of second sacrificial layer
The phosphorus doping density of domestic animal layer and the phosphorus doping density of 3rd sacrifice layer, the boron doping concentration of second sacrificial layer are respectively higher than institute
State the boron doping concentration of the first sacrificial layer and the boron doping concentration of 3rd sacrifice layer.
17. forming method according to claim 16, which is characterized in that the phosphorus doping density of first sacrificial layer is
2.8~4wt%, boron doping concentration are 2~4wt%；The phosphorus doping density of second sacrificial layer is 2~4wt%, and boron doping is dense
Degree is 3~6.5wt%；The phosphorus doping density of the 3rd sacrifice layer is 2.5~5.5wt%, and boron doping concentration is 2~3wt%.
18. forming method according to claim 16, which is characterized in that between the 3rd sacrifice layer and the second sacrificial layer
Etching selectivity be (800~15000): 1；The etching selectivity of second sacrificial layer and the first sacrificial layer be 1:(800~
12000)。
19. forming method according to claim 14, which is characterized in that it is described remove the first sacrificial layer time be 30~
45s, the time for removing the second sacrificial layer are 3~5s, and the time for removing 3rd sacrifice layer is 50~150s.
20. forming method described in any one of 4~19 according to claim 1, which is characterized in that the thickness of first sacrificial layer
Degree is 500~1000nm, second sacrificial layer with a thickness of 30~45nm, the 3rd sacrifice layer with a thickness of 300~
500nm。
21. forming method according to claim 14, which is characterized in that further include forming polysilicon layer on described second
On electrode layer.
22. forming method according to claim 21, which is characterized in that further include forming metal tungsten layer in the polysilicon
Between layer and second upper electrode layer.
23. forming method according to claim 14, which is characterized in that one it is described opening only with a capacitor at
Type hole is overlapping or an opening is overlapping with multiple capacitance forming holes simultaneously.
24. forming method according to claim 14, which is characterized in that first upper electrode layer, the lower electrode layer
One of titanium, titanium nitride and tungsten or a variety of are selected from the material of second upper electrode layer；First dielectric layer and described
The material of second dielectric layer is selected from one of aluminium oxide, silicon nitride, silica and zirconium oxide or a variety of.
25. forming method according to claim 14, which is characterized in that the height of the fixing layer accounts for the capacitance forming
The 1/5~1/3 of hole height.
26. forming method according to claim 14, which is characterized in that the bottom support layer with a thickness of 30nm~
45nm, the lower electrode layer with a thickness of 5~15nm, second upper electrode layer with a thickness of 5~10nm, first dielectric
Layer with a thickness of 4nm~10nm, second dielectric layer with a thickness of 4nm~10nm.
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