KR101630781B1 - Manufacturing Method Of Semiconductor Device Capacitor Storage Node - Google Patents

Abstract

A method of forming a capacitor lower electrode of a semiconductor device according to the present invention includes the steps of forming a sacrificial insulating film having a first metal deposition rate on an upper surface of a semiconductor substrate having a lower structure including a contact plug and an insulating film, Forming a lower electrode region by etching the support layer and the sacrificial insulation layer so that the contact plug is exposed; forming a metal film on the entire surface of the lower electrode region to fill the lower electrode region; Forming a lower electrode separated by performing a process for etching the metal film, and removing the sacrificial insulating film by a full dip-out process to form an outer wall of the node-separated lower electrode, .

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of forming a capacitor lower electrode of a semiconductor device,

The present invention relates to a method of manufacturing a semiconductor memory device. And more particularly, to a method of forming a lower electrode of a semiconductor memory device capacitor.

As the design rule of a semiconductor memory device has been rapidly reduced, various techniques have been proposed for obtaining a capacitor having a large capacitance with a small area. In order to obtain such a high capacity capacitor, it is required to use a dielectric film having a large dielectric constant, to enlarge the electrode surface area, and to reduce the distance between the electrodes. However, there are limitations in reducing the dielectric film thickness, which is the distance between the electrodes, and studies for forming a capacitor with a high capacity have been conducted by using a dielectric film having a large dielectric constant or widening the electrode surface area. The change in the shape of the lower electrode of the capacitor according to the trend has been developed into a planar structure, a stack structure, a concave structure, and a cylinder structure. In recent years, a capacitor having a pillar type lower electrode structure has been proposed in order to overcome the structural problems caused by the reduction of the design rule in capacitors having such a cylinder structure.

Referring to FIG. 1A, the second sacrificial insulation layer, the NFC nitride layer, the first sacrificial insulation layer, and the etch stop nitride layer are etched to form a lower electrode region where the lower electrode of the capacitor is to be formed. In the process of forming the etch stop nitride film pattern 14 by etching the etch stop nitride film at the lower end in the sequential etching process, the side walls of the NFC nitride film pattern 18 are also etched to have a negative profile W as shown in FIG. The metal deposition rates of the sacrificial insulating film pattern 16 and the NFC nitride film pattern 18 are similar to each other in the process of embedding the metal 24 in the lower electrode region formed through the etching, The seam S is formed near the side wall of the NFC nitride film due to the negative profile W of the side wall of the NFC nitride film pattern 18. [ When the node isolation process is performed, a portion S 'where a core is formed in the lower electrode 24' formed as shown in FIG. 1B is exposed on the surface of the lower electrode 24 ', and then a process of forming a dielectric layer and an upper electrode The step coverage of the dielectric film and the upper electrode material is poor, so that the embedding failure occurs in which the film is not covered to the bottom of the core. Such poor filling causes deterioration of the characteristics of the capacitor.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems of the prior art described above, and its main object is to suppress deterioration of the capacitor characteristics which occurs when the bent portion of the lower electrode surface is exposed.

A method of forming a capacitor lower electrode of a semiconductor device according to the present invention includes the steps of forming a sacrificial insulating film having a first metal deposition rate on an upper surface of a semiconductor substrate having a lower structure including a contact plug and an insulating film, Forming a lower electrode region by etching the support layer and the sacrificial insulation layer so that the contact plug is exposed; forming a metal film on the entire surface of the lower electrode region to fill the lower electrode region; Forming a lower electrode separated by performing a process for etching the metal film, and removing the sacrificial insulating film by a full dip-out process to form an outer wall of the node-separated lower electrode, .

In one embodiment, the sacrificial insulating film is formed of an oxide film, and the support layer is formed of a nitride-based silicon nitride film.

In the method for forming a capacitor lower electrode of a semiconductor device according to the present invention, in one example, the metal film is formed of a titanium nitride film.

The method of forming a lower electrode of a capacitor of a semiconductor device according to the present invention is characterized in that the titanium nitride dry film is formed using a chemical vapor deposition (CVD) method using titanium tetrachloride (TiCl ₄ ) do.

Disclosure of Invention Technical Problem [8] The present invention has an object of preventing the deterioration of the characteristics of the capacitor, which is a problem of the conventional art described above, and the metal deposition rate of the support layer is improved more than the metal deposition rate of the sacrificial insulating film. Therefore, according to the present invention, it is possible to prevent the exposed portion of the bent portion of the lower electrode due to the shim, which is a problem of the conventional technology, so that deterioration of the characteristics of the capacitor can be suppressed.

1 is a cross-sectional view showing a conventional method of forming a lower electrode of a capacitor.
2 to 7 are views showing a method of forming a lower electrode of a capacitor according to the present invention.

2, an etch stop nitride layer 120, a first sacrificial insulating layer 130, and a second sacrificial layer 130 are formed on a semiconductor substrate (not shown) having a lower structure such as an insulating layer 100 and a contact plug 110, A support layer 140 and a second sacrificial insulating layer 150 are formed and a resist pattern 162 is formed on the second sacrificial insulating layer 150. [ The first and second sacrificial insulating layers 130 and 150 function to provide a lower electrode region (see 170 in FIG. 3) for forming the lower electrode. The subsequent planarization process and the full dip-out process, Lt; / RTI > In one example, the sacrificial insulating layer may be a high density plasma (HDP) oxide layer, a boron phosphorus silicate glass (BPSG) layer, a phosphorus silicate glass (PSG) layer, a boron silicate glass (BSG) layer, a tetraethyl orthosilicate A stacked layer formed of at least two layers selected from the group consisting of an un-doped silicate glass (FSG) layer, a fluorinated silicate glass (FSG) layer, a CDO (Carbon Doped Oxide) layer and an OSG (Organo Silicate Glass) . In another example, the sacrificial insulating film is formed by spin coating, such as an SOD (Spin On Dielectric) film.

Referring to FIG. 3, a second sacrificial insulating layer 150, a supporting layer 140, a first sacrificial insulating layer 130, and an etch stop nitride layer 120 are formed to expose the contact plug 110 using the resist pattern formed as an etching mask. Are sequentially etched to form the lower electrode region 170, and the resist pattern 162 is removed. In one example, the removal of the resist pattern 162 is performed by performing an ordinary ashing process. The support layer pattern 142 formed by etching the support layer (see 140 in FIG. 2) is formed later in order to prevent bridge formation of the lower electrode due to the leaning phenomenon that occurs during the subsequent full dip- And a lower electrode to be formed. The sidewall S of the supporting layer pattern 142 is also etched in the process of etching the etch stop nitride layer 120 to form the lower electrode region 170 so that the side wall of the supporting layer pattern has a negative profile. The support layer is formed of a material having a higher metal deposition rate than that of the sacrificial insulating layer in order to prevent the generation of shims due to the negative profile of the side wall of the support layer pattern 142. In one example, the support layer (see 140 in FIG. 3) is a Nitride-rich nitride film rich in Nitrogen (N) compared to an LP-Nitride film that is a nitride film deposited by LPCVD nitride layer. It is well known that the LP-nitride film, which is a nitride film deposited by LPCVD, is composed of silicon (Si) and nitride film (N) in a ratio of 3: 4. Thus, the Nitrogen pre-Ritride film means a film where the ratio of silicon to nitrite is 3: 4 to Nitrogen relative to that of Nitrogen.

Referring to FIG. 4, a metal layer 180 is formed on the front surface to fill the formed lower electrode region 170. In one example, the metal layer 180 is a titanium tetrachloride (TiCl ₄₎ and ammonia (NH ₃₎ to then feed along and purge this purge after the CVD including the step of performing processing after ammonia to remove impurities ( Chemical Vapor Deposition) to form a titanium nitride (TiN) film. As shown in FIG. 5, the higher the nitrogen content in the nitride film, the larger the grain size of titanium nitride formed on the nitride film. Therefore, when a N rich nitride film is used as the supporting layer, the metal deposition rate of the supporting layer is higher than the metal deposition rate of the sacrificial insulating film, so that titanium (Ti) formed on the first sacrificing insulating film pattern 132 Titanium nitride grains having a size larger than that of nitride grains are formed, so that a titanium nitride layer is formed faster than other regions. That is, the metal deposition rate of the support layer pattern is higher than the metal deposition rate of the sacrificial insulation layer, so that the metal layer is formed around the sidewall of the support layer pattern. Therefore, the use of a nitride-rich nitride film as the supporting layer as in the present invention can prevent the formation of seams which was a problem of the prior art.

Referring to FIG. 6, flattening is performed on the formed metal layer (see 180 in FIG. 5) until the support layer pattern 142 is exposed to form each of the lower electrodes 182 separated by a node. By this process, the second sacrificial insulating film pattern (refer to 152 in FIG. 4) above the supporting layer pattern 142 is removed. In one example, the planarization of this step is performed by a CMP (Chemical Mechanical Polishing) process. Looking at the top surface of the lower electrode 182 formed by performing the planarization step, it can be seen that there is no upper surface curvature (see S 'in FIG. 1B) that was exposed around the conventional support layer pattern side wall. In addition, since the metal deposition rate is different between the support layer pattern 142 and the second sacrificial insulation layer pattern 132, the inner shape of the lower electrode formed after the metal layer is embedded is different from the conventional one. However, this change in the internal structure has no influence on the electrical characteristics of the lower electrode.

Referring to FIG. 7, a full dip-out process is performed to remove the first sacrificial insulating film pattern (see 132 in FIG. 6). The portion where the first sacrificial insulating film exists due to the full dip-out process becomes an empty space and the outer wall of the lower electrode 182 is exposed. In one example, the full dip-out process is performed using hydrofluoric acid (HF). In another example, the pool dip-out process is performed using BOE (Buffered Oxide Etchant). The dielectric layer 190 is formed on the surface of the exposed lower electrode 182, and then the upper electrode 200 is formed. Since the upper electrode 200 is formed in the space where the first sacrificial insulating layer pattern is removed, the area where the lower electrode 182 and the upper electrode 200 face each other is increased to increase the capacitance. The dielectric layer 190 may be deposited using atomic layer deposition, and in one example, a dielectric layer 190 may be formed of an oxide selected from the group consisting of aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), or a double film, a triple film, or a mixed film containing any one of them. In another example, the dielectric layer 190 is formed of a high-k dielectric layer such as BTO or BST. The upper electrode 200 is ruthenium (Ru), ruthenium oxide (RuO _2), tungsten (W), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), iridium (Ir), iridium Oxide (IrO ₂ ), and platinum (Pt). In another example, a bilayer of CVD-TiN and PVD-TiN is used.

100: insulating film 110: contact plug
120: etch stop nitride film 130: first sacrificial insulating film
140: support layer 150: second sacrificial insulating film
162: resist pattern 170: lower electrode region
180: metal layer 182: lower electrode
190: Dielectric layer 200: Upper electrode
S: seam

Claims (5)

Forming a sacrificial insulating film having a first deposition rate on the metal film for the lower electrode on the semiconductor substrate on which the lower structure including the contact plug and the insulating film is formed;
Forming a supporting layer having a second deposition rate higher than a first deposition rate on the sacrificial insulating film for the lower electrode metal film;
Forming a lower electrode region by etching the support layer and the sacrificial insulation layer to expose the contact plug;
Filling the lower electrode metal film on the entire surface so that the lower electrode region is filled;
Performing a planarization process on the lower electrode metal film to form a node-separated lower electrode, and
And removing the sacrificial insulating layer by a full dip-out process to expose an outer wall of the node-separated lower electrode. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1,
The forming of the sacrificial insulating layer may be performed by forming an oxide layer, and the forming of the supporting layer may include forming a N rich silicon nitride layer, A method of forming a capacitor lower electrode of a semiconductor device. Claim 3 has been abandoned due to the setting registration fee. The method according to claim 1,
Wherein the metal film for the lower electrode is formed of a titanium nitride (TiN) film. Claim 4 has been abandoned due to the setting registration fee. The method of claim 3,
Wherein the titanium nitride dry film is formed using a chemical vapor deposition (CVD) method using titanium tetrachloride (TiCl ₄ ) gas as a source. Claim 5 has been abandoned due to the setting registration fee. The method according to claim 1,
Wherein the step of planarizing the lower electrode metal film to form a node-separated lower electrode is performed by a CMP (Chemical Mechanical Polishing) process.

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