TW201438179A - 半導體封裝件、其製法及用於該半導體封裝件之封裝材 - Google Patents

半導體封裝件、其製法及用於該半導體封裝件之封裝材 Download PDF

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TW201438179A
TW201438179A TW102109431A TW102109431A TW201438179A TW 201438179 A TW201438179 A TW 201438179A TW 102109431 A TW102109431 A TW 102109431A TW 102109431 A TW102109431 A TW 102109431A TW 201438179 A TW201438179 A TW 201438179A
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package
semiconductor
semiconductor package
oxide
component
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許聰賢
鍾興隆
朱德芳
林幗茵
沈紹明
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矽品精密工業股份有限公司
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Priority to TW102109431A priority Critical patent/TW201438179A/zh
Priority to CN201310093641.1A priority patent/CN104064552A/zh
Priority to US13/968,834 priority patent/US20140264958A1/en
Publication of TW201438179A publication Critical patent/TW201438179A/zh

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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract

一種半導體封裝件，係包括：基體、設於該基體上之半導體元件以及包覆該半導體元件之封裝材，且該封裝材之成份含有金屬氧化物，使該封裝材具有高絕緣阻抗與高散熱率，且能抑制電磁干擾。本發明復提供該半導體封裝件之製法及封裝材。

Description

半導體封裝件、其製法及用於該半導體封裝件之封裝材
本發明係有關一種半導體封裝件，尤指一種半導體晶片為封裝材包覆之半導體封裝件及其製法。
半導體封裝件的製作係將半導體晶片電性連接於一例如導線架或封裝基板之承載件上，再於該承載件上藉由如環氧樹脂之封裝膠體包覆該半導體晶片，以避免該半導體晶片與外界大氣接觸，進而避免受到水氣或汙染物之侵害。
於半導體封裝件於運作時，多少會遭受到外界之電磁干擾(Electromagnetic interference,EMI)，導致該半導體封裝件的電性運作功能不正常，因此影響整體該半導體封裝件的電性效能。
為解決前述電磁干擾之問題，遂有於半導體晶片外覆蓋金屬材之方式提出。如第1圖所示之半導體封裝件1，係於一承載件10上設置半導體晶片11，再以銲線12電性連接該半導體晶片11與該承載件10；接著設置一網狀金 屬罩13於該承載件10上，以令該金屬罩13覆蓋該半導體晶片11，且該金屬罩13接地該承載件10之接地處100；之後，形成封裝材14於該承載件10上，以令該封裝材14包覆該金屬罩13與該半導體晶片11。最後，加熱固化該封裝材14以形成封裝膠體。
習知半導體封裝件1藉由該網狀金屬罩13遮蔽外界電磁干擾該半導體晶片11的運作，以避免該半導體封裝件1電性運作功能不正常。
惟，習知半導體封裝件1中，需製作該網狀金屬罩13，因而增加製程之複雜度，且需將該網狀金屬罩13組設於該承載件10上，因而增加組裝困難度。
再者，當進行封裝製程時，該封裝材14需通過該金屬罩13之網孔方能包覆該半導體晶片11，但當該封裝材14通過該金屬罩13之網孔時容易產生紊流，導致氣泡之產生，致使該封裝材14中容易產生空洞(void)，而於後續加熱製程中產生爆米花效應(popcorn)。
因此，如何克服上述習知技術之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係揭露一種半導體封裝件，係包括：基體；至少一半導體元件，係設於該基體上；以及封裝材，係包覆該半導體元件，且該封裝材含有金屬氧化物。
本發明復提供一種半導體封裝件之製法，係包括：於 一基體上設置至少一半導體元件；以及於該基體上形成封裝材以包覆該半導體元件，其中，該封裝材含有金屬氧化物。
前述之半導體封裝件及其製法中，該半導體封裝件係為打線式封裝件、覆晶式封裝件、混合式封裝件、嵌埋式封裝件或晶圓級封裝件。
前述之半導體封裝件及其製法中，該基體係電性連接至該半導體元件，且該半導體元件係為主動元件或被動元件。
前述之半導體封裝件及其製法中，該金屬氧化物係為鐵之氧化物、錳之氧化物及鋅之氧化物所組成群組之至少一者，如Fe2O3、Mn3O4、ZnO。
另外，本發明亦提供一種封裝材，係包括：高分子樹脂；以及選自鐵之氧化物、錳之氧化物及鋅之氧化物所組成群組之至少一者的金屬氧化物。
前述之封裝材中，該鐵之氧化物係為Fe2O3，該錳之氧化物係為Mn3O4，該鋅之氧化物係為ZnO。
前述之封裝材中，該高分子樹脂係為環氧樹脂。
由上可知，本發明之半導體封裝件及其製法暨封裝材中，係藉由含金屬氧化物之封裝材取代習知金屬罩，使該封裝材具有高絕緣阻抗與高散熱率，且能抑制電磁干擾，故本發明之製法無需製作習知金屬罩即可有效防止電磁干擾，因而能簡化製程，且因無需組設習知金屬罩，而能輕易完成該半導體封裝件之製作。
再者，當進行封裝製程時，該封裝材無需通過習知金屬罩之網孔即能包覆該半導體元件，故該封裝材於流動中不會產生紊流，因而能避免該封裝材產生空洞(void)，進而於後續加熱製程中不會產生爆米花效應(popcorn)
1,2,3,4,5,6,7‧‧‧半導體封裝件
10,20,50,60,70‧‧‧承載件
100‧‧‧接地處
11‧‧‧半導體晶片
12,22,42b‧‧‧銲線
13‧‧‧金屬罩
14,23‧‧‧封裝材
20,50,60,70‧‧‧基體
21,31,41a,41b,71‧‧‧半導體元件
32,42a‧‧‧導電凸塊
第1圖係為習知半導體封裝件之立體示意圖；以及第2A至2B圖係為本發明之半導體封裝件之製法的剖面示意圖；以及第3至7圖係為本發明之半導體封裝件之其它實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2B圖係為本發明之半導體封裝件2之製法之 剖視示意圖，該半導體封裝件2係為打線式封裝件。
如第2A圖所示，於一基體20上設置一半導體元件21。接著，以複數銲線22電性連接該半導體元件21與該基體20。
於本實施例中，該基體20係為如電路板、金屬板或陶瓷板之封裝基板，且該基體20具有線路(圖略)以電性連接該些銲線22。而有關封裝基板之種類繁多，並不限於圖示。
再者，該半導體元件21係為主動元件或被動元件。
如第2B圖所示，形成封裝材23於該基體20上，以令該封裝材23包覆該半導體元件21，該封裝材23並含有金屬氧化物。接著，加熱固化該封裝材23以形成封裝膠體。
於本實施例中，該金屬氧化物係為鐵之氧化物，即Fe2O3，且該金屬氧化物復可含有錳與鋅之氧化物，即Mn3O4與ZnO。舉例而言，所述之封裝材23係將錳、鋅及鐵之燒結物(即氧化物)研磨成粉體後，再將其與如環氧樹脂(Epoxy)之高分子樹脂混攪製成之一種膠材，其具有高絕緣阻抗與高散熱率，且可抑制電磁干擾(Electromagnetic interference,EMI)。
本發明之半導體封裝件2之製法中，藉由該封裝材23之成份含有金屬氧化物，使該封裝材23具有高絕緣阻抗與高散熱率，且能抑制電磁干擾(EMI)，以遮蔽外界電磁干擾該半導體元件21的運作，而避免該半導體封裝件2電性運作功能不正常，故本發明無需製作習知金屬罩即可 有效防止電磁干擾，因而能簡化製程，且因無需組設習知金屬罩，而能輕易完成該半導體封裝件2之製作。因此，相較於習知製法，本發明之製法有利於量產。
再者，當進行封裝製程時，該封裝材23無需通過習知金屬罩之網孔即能包覆該半導體元件21，故該封裝材23於流動中不會產生紊流，因而能避免該封裝材23產生空洞(void)，進而於後續加熱製程中不會產生爆米花效應(popcorn)。
第3至7圖係為本發明之半導體封裝件3,4,5,6,7之不同實施例之剖視示意圖。
如第3圖所示，該半導體封裝件3係為覆晶式封裝件，該基體20係為封裝基板，且該半導體元件31以複數導電凸塊32電性連接該基體20。
如第4圖所示，該半導體封裝件4係為混合式(hybrid)封裝件，該基體20係為封裝基板，且該半導體封裝件4具有複數堆疊之半導體元件41a,41b，其中，該下方半導體元件41a以複數導電凸塊42a電性連接該基體20，而上方半導體元件41b以複數銲線42b電性連接該基體20。
如第5圖所示，該半導體封裝件5係為打線式封裝件，該基體50係為導線架(lead frame)，且該半導體元件21以複數銲線22電性連接該基體50。
如第6圖所示，該半導體封裝件6係為四方平面無引腳(Quad Flat No leads,QFN)之打線式封裝件，該基體60係為導線架(lead frame)或封裝基板，且該半導體元件21 以複數銲線22電性連接該基體60。
如第7圖所示，該半導體封裝件7係為晶圓級封裝件(wafer level package,WLP)或嵌埋式封裝件，該基體70係為多層線路結構，且該基體70以複數導電盲孔(via)電性連接該半導體元件71。
另外，有關半導體封裝件之種類繁多，其態樣並不限於上述實施例，特此述明。
本發明復提供一種半導體封裝件2,3,4,5,6,7，其包括：一基體20,50,60,70、設於該基體20,50,60,70上之半導體元件21,31,41a,41b,71以及封裝材23。
所述之半導體封裝件2,3,4,5,6,7係為打線式封裝件、覆晶式封裝件、混合式封裝件或晶圓級封裝件
所述之基體20,50,60,70係電性連接該半導體元件21,31,41a,41b,71。
所述之半導體元件21,31,41a,41b,71係為主動元件或被動元件。
所述之封裝材23包覆該半導體元件21,31,41a,41b,71，且該封裝材23之成份含有金屬氧化物。
具體地，本發明之封裝材23之成份含有如環氧樹脂之高分子樹脂以及金屬氧化物，如鐵之氧化物(即Fe2O3)、錳之氧化物(即Mn3O4)與鋅之氧化物(即ZnO)。
綜上所述，本發明之半導體封裝件及其製法暨封裝材中，藉由該封裝材之特性，使本發明無需製作習知金屬罩，故能簡化製程，且能輕易完成該半導體封裝件之製作。
再者，當進行封裝製程時，該封裝材無需通過習知金屬罩之網孔即能包覆該半導體元件，因而能避免該封裝材產生空洞，進而不會產生爆米花效應。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
20‧‧‧基體
21‧‧‧半導體元件
22‧‧‧銲線
23‧‧‧封裝材

Claims (24)

  1. 一種半導體封裝件，係包括：基體；至少一半導體元件，係設於該基體上；以及封裝材，係包覆該半導體元件，且該封裝材含有金屬氧化物。
  2. 如申請專利範圍第1項所述之半導體封裝件，其係為打線式封裝件、覆晶式封裝件、混合式封裝件、嵌埋式封裝件或晶圓級封裝件。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該基體係電性連接至該半導體元件。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件係為主動元件或被動元件。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該金屬氧化物係為鐵之氧化物、錳之氧化物及鋅之氧化物所組成群組之至少一者。
  6. 如申請專利範圍第5項所述之半導體封裝件，其中，該鐵之氧化物係為Fe2O3。
  7. 如申請專利範圍第5項所述之半導體封裝件，其中，該錳之氧化物係為Mn3O4。
  8. 如申請專利範圍第5項所述之半導體封裝件，其中，該鋅之氧化物係為ZnO。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中，該金屬氧化物為粉體。
  10. 一種半導體封裝件之製法，係包括：於一基體上設置至少一半導體元件；以及形成封裝材以包覆該半導體元件，該封裝材並含有金屬氧化物。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，其係為打線式封裝件、覆晶式封裝件、混合式封裝件、嵌埋式封裝件或晶圓級封裝件。
  12. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該基體係電性連接至該半導體元件。
  13. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該半導體元件係為主動元件或被動元件。
  14. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該金屬氧化物係為鐵之氧化物、錳之氧化物及鋅之氧化物所組成群組之至少一者。
  15. 如申請專利範圍第14項所述之半導體封裝件之製法，其中，該鐵之氧化物係為Fe2O3。
  16. 如申請專利範圍第14項所述之半導體封裝件之製法，其中，該錳之氧化物係為Mn3O4。
  17. 如申請專利範圍第14項所述之半導體封裝件之製法，其中，該鋅之氧化物係為ZnO。
  18. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該金屬氧化物為粉體。
  19. 一種封裝材，係包括：高分子樹脂；以及 金屬氧化物，係選自鐵之氧化物、錳之氧化物及鋅之氧化物所組成群組之至少一者。
  20. 如申請專利範圍第19項所述之封裝材，其中，該鐵之氧化物係為Fe2O3。
  21. 如申請專利範圍第19項所述之封裝材，其中，該錳之氧化物係為Mn3O4。
  22. 如申請專利範圍第19項所述之封裝材，其中，該鋅之氧化物係為ZnO。
  23. 如申請專利範圍第19項所述之封裝材，其中，該金屬氧化物為粉體。
  24. 如申請專利範圍第19項所述之封裝材，其中，該高分子樹脂係為環氧樹脂。
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