TW201428940A - Semiconductor device, MIS transistor, and multilayer wiring substrate - Google Patents

Semiconductor device, MIS transistor, and multilayer wiring substrate Download PDF

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TW201428940A
TW201428940A TW102141493A TW102141493A TW201428940A TW 201428940 A TW201428940 A TW 201428940A TW 102141493 A TW102141493 A TW 102141493A TW 102141493 A TW102141493 A TW 102141493A TW 201428940 A TW201428940 A TW 201428940A
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film
insulating film
electrode
present
semiconductor device
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Tadahiro Ohmi
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Univ Tohoku
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention addresses the problem of simply and easily providing a highly durable electrical insulation film that makes it possible to manage production with high efficiency while keeping costs down. An electrical insulation film is configured using an anodic oxide film of an aluminum alloy to which 0.01-0.15% of zirconium is added.

Description

半導體裝置、MIS型電晶體及多層配線基板 Semiconductor device, MIS type transistor, and multilayer wiring substrate

本發明是有關半導體裝置，MIS型電晶體及多層配線基板。 The present invention relates to a semiconductor device, a MIS type transistor, and a multilayer wiring board.

隨著個人電腦(PC)或智慧型手機，平板電腦等的資訊終端機器的小型．輕量．薄型化，高速資料處理化，高機能化，使用在該等的半導體裝置或液晶顯示裝置(Liquid Crystal Display Device：LCDD)或有機EL顯示裝置(Organic Electroluminescence Display Device：OELDD)等的顯示裝置用的驅動用半導體裝置是更被要求高集成化．高密度化。 With the personal computer (PC) or smart phone, tablet computer and other information terminal machines are small. Lightweight. It is thinned, high-speed data processing, and high-performance, and is used in display devices such as such semiconductor devices, liquid crystal display devices (LCDD), or organic EL display devices (OELDD). Drive semiconductor devices are more demanding and highly integrated. High density.

半導體裝置的高集成化．高密度化是依存於電晶體開關元件等的電子機能元件的微細化。電子機能元件是越微細，越被要求構成該元件的各構成要素的電性特性及動作可靠度的更提升及構成半導體裝置的多數的電子元件之間的電性特性及動作特性的無偏差的更提升。 High integration of semiconductor devices. The increase in density is dependent on the miniaturization of electronic functional elements such as transistor switching elements. The finer the electronic functional component is, the more the electrical characteristics and the operational reliability of each component constituting the component are required to be improved, and the electrical characteristics and operational characteristics of the plurality of electronic components constituting the semiconductor device are not biased. More improvement.

在半導體裝置中多數使用的電子機能元件之一，例如MIS(Metal-Insulator-semiconductor)型電晶體 (MISTr)，非線形電阻元件之MIM(metal-insulator-Metal)型開關元件(MIMSWE)的動作性能及可靠度的提升的要求更嚴格。MISTr的動作性能及可靠度是對閘極絕緣膜的電性品質及可靠度敏感，且MIMSWE是對被兩電極挾持的絕緣膜的電性品質及可靠度敏感。其他，對於多數使用在半導體裝置的電氣電路的電容器或至少其一部分具有MIM型的配線構造的多層配線基板的電氣絕緣膜的電性品質及可靠度也與對MISTr或MIMSWE的絕緣膜的要求同等以上的要求。 One of the most commonly used electronic functional components in a semiconductor device, such as a MIS (Metal-Insulator-semiconductor) type transistor (MISTr), the MIM (metal-insulator-Metal) type switching element (MIMSWE) of the non-linear resistance element has stricter requirements for improvement in operational performance and reliability. The performance and reliability of MISTr are sensitive to the electrical quality and reliability of the gate insulating film, and MIMSWE is sensitive to the electrical quality and reliability of the insulating film held by the two electrodes. In addition, the electrical quality and reliability of the electrical insulating film of a multilayer wiring board having a MIM-type wiring structure in a capacitor of an electrical circuit of a semiconductor device or at least a part thereof are also equivalent to those of an insulating film of MISTr or MIMSWE. The above requirements.

除了上述的要求外，電子機能元件，電容器及MIM型配線構造的電氣絕緣膜的生產工程的簡單化及生產設備的簡便化，低生產成本化的要求，為了提高完成電氣．電子機器的販賣競爭力，而年年變強。 In addition to the above requirements, the production of electrical functional components, capacitors and MIM wiring structures, the simplification of the production process and the simplification of production equipment, low production cost requirements, in order to improve the completion of electrical. The sales of electronic machines are competitive and become stronger every year.

有鑑於如此的狀況，陽極氧化法之前述絕緣膜的形成法是隱藏形成有力的絕緣膜形成法的可能性。其中，形成MIM型配線構造的絕緣膜的例子是記載於專利文獻1，形成MISTr的閘極絕緣膜的例子是記載於專利文獻2。專利文獻1的例子，專利文獻2的例子，皆陽極氧化用的電解溶液是其液組成由乙二醇，酒石酸銨，水所構成，乙二醇的濃度高。 In view of such a situation, the formation method of the foregoing insulating film by the anodic oxidation method is a possibility of hiding a strong insulating film forming method. In the example of the insulating film which forms the MIM type wiring structure, it is described in the patent document 1, and the example which forms the gate insulating film of MISTr is described in patent document 2. In the example of Patent Document 1, in the example of Patent Document 2, the electrolytic solution for anodizing is composed of ethylene glycol, ammonium tartrate, and water, and the concentration of ethylene glycol is high.

[先行技術文獻] [Advanced technical literature]

[專利文獻] [Patent Literature]

[專利文獻1]日本特開平6-308539號公報 [Patent Document 1] Japanese Patent Laid-Open No. Hei 6-308539

[專利文獻2]日本特開平8-120489號公報 [Patent Document 2] Japanese Patent Laid-Open No. Hei 8-120489

然而，電解液溫，專利文獻1的情況是約25℃，專利文獻2的情況是40℃以下陽極氧化，但若不是該液溫，則形成的陽極氧化膜會在陽極氧化中溶解，陽極氧化速度具有膜表面依存性，在半導體領域是有重要的膜因子亦即表面平滑性佳的氧化膜的形成難之生產管理上的不合適。又，由於陽極氧化時的電解液溫低，因此量產效率不會提升。 However, the temperature of the electrolyte is about 25 ° C in the case of Patent Document 1, and the case of Patent Document 2 is anodization below 40 ° C. However, if it is not the temperature of the liquid, the formed anodized film is dissolved in the anodization, and anodizing The speed has a film surface dependency, and in the semiconductor field, an important film factor, that is, an oxide film having a good surface smoothness, is difficult to be produced in production management. Moreover, since the temperature of the electrolyte at the time of anodization is low, the mass production efficiency does not increase.

本發明是有鑑於上述點而致力研發者，其目的之一是在於提供一種具備高效率，可生產管理且可節省成本的高耐久性的電氣絕緣膜之半導體裝置。 The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device having a high-efficiency, highly durable electrical insulating film which is highly efficient, production-manageable, and cost-effective.

另一目的是在於提供一種具備高效率，可生產管理且可節省成本的高耐久性的層間絕緣膜之半導體裝置用多層配線基板。 Another object of the present invention is to provide a multilayer wiring board for a semiconductor device having a highly durable interlayer insulating film which is highly efficient, production-manageable, and cost-effective.

本發明之一形態為一種半導體裝置，係具備電性絕緣膜的半導體裝置，其特徵為：前述絕緣膜係添加鋯0.01~0.15%之鋁合金的陽極氧化膜(但，鋁合金係不含鎂，鈰的至少一個)。 One aspect of the present invention provides a semiconductor device comprising a semiconductor device comprising an electrically insulating film, wherein the insulating film is an anodized film of an aluminum alloy having a zirconium oxide of 0.01 to 0.15% (however, the aluminum alloy does not contain magnesium) , at least one of you.)

本發明之另一形態為一種半導體裝置用多層配線基板，係在具備層間絕緣膜的半導體裝置用多層配線基板，其特徵為：前述層間絕緣膜係添加鋯0.01~0.15%之鋁合金的陽極氧化膜(但，鋁合金係不含鎂，鈰的至少一個)。 According to another aspect of the invention, a multilayer wiring board for a semiconductor device is a multilayer wiring board for a semiconductor device including an interlayer insulating film, characterized in that the interlayer insulating film is anodized with an aluminum alloy containing 0.01 to 0.15% of zirconium. Membrane (however, the aluminum alloy does not contain magnesium, at least one of bismuth).

本發明之另一形態為一種MIS型電晶體，係於其體上具有閘極電極，閘極絕緣膜，半導體層，源極電極及汲極電極的MIS型電晶體，其特徵為：前述閘極絕緣膜係添加鋯0.01~0.15%之鋁合金的陽極氧化膜(但，鋁合金係不含鎂，鈰的至少一個)。 Another aspect of the present invention is a MIS type transistor, which is a MIS type transistor having a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, and is characterized by: the gate The pole insulating film is an anodized film of an aluminum alloy having a zirconium of 0.01 to 0.15% (however, the aluminum alloy contains at least one of magnesium and niobium).

本發明之另一形態為一種半導體裝置，係具有MIM型構造的半導體裝置，其特徵為：前述MIM型構造的絕緣膜係添加鋯0.01~0.15%之鋁合金的陽極氧化膜(但，鋁合金係不含鎂，鈰的至少一個)。 Another aspect of the present invention provides a semiconductor device having a MIM type structure, characterized in that the insulating film of the MIM type structure is an anodized film of an aluminum alloy having a zirconium addition of 0.01 to 0.15% (however, an aluminum alloy) It is free of magnesium and at least one of bismuth.

若根據本發明，則可簡便地提供一種高效率生產管理且可節省成本之高耐久性的電氣絕緣膜。 According to the present invention, it is possible to easily provide a highly durable electrical insulating film which is highly efficient in production management and can be cost-effective.

本發明的其他的特徵及優點是藉由參照附圖的以下說明可明確得知。另外，在附圖中，在相同或同樣的構成附上同參照號碼。 Other features and advantages of the invention will be apparent from the description and appended claims. In addition, in the drawings, the same or similar components are attached with the same reference numerals.

100，200，300‧‧‧MISTr 100,200,300‧‧‧MISTr

101，205‧‧‧基體 101,205‧‧‧ base

102，202‧‧‧閘極電極 102,202‧‧‧gate electrode

103，203‧‧‧閘極絕緣膜 103,203‧‧‧gate insulating film

104，204‧‧‧半導體層 104,204‧‧‧Semiconductor layer

105，205，305‧‧‧源極電極(部) 105,205,305‧‧‧Source electrode (part)

106，206，306‧‧‧汲極電極(部) 106,206,306‧‧‧汲electrode (part)

107‧‧‧Na擴散防止層 107‧‧‧Na diffusion prevention layer

108‧‧‧耐藥劑性Na擴散防止層 108‧‧‧Drugant-resistant Na diffusion prevention layer

109，209‧‧‧平坦化層領域 109,209‧‧‧Development layer area

207‧‧‧無變形性Na擴散防止層 207‧‧‧No deformation Na diffusion prevention layer

208‧‧‧無變形．耐藥劑性Na擴散防止層 208‧‧‧No deformation. Drug-resistant Na diffusion preventing layer

305a，306a‧‧‧下部電極膜 305a, 306a‧‧‧ lower electrode film

305b，306b‧‧‧上部電極膜 305b, 306b‧‧‧ upper electrode film

附圖是含在說明書中，構成其一部分，顯示 本發明的實施形態，與其記述一起為了說明本發明的原理而被使用。 The drawings are included in the specification, form part of them, and are shown Embodiments of the present invention are used in conjunction with the description to explain the principles of the present invention.

圖1是用以說明本發明的適宜的實施形態之一的MISTr的構成的模式性構成說明圖。 Fig. 1 is a schematic explanatory view showing a configuration of a MISTr according to a preferred embodiment of the present invention.

圖2是用以說明本發明的適宜的實施形態的別的例子的MISTr的構成的模式性構成說明圖。 Fig. 2 is a schematic explanatory view showing a configuration of an MISTr according to another example of a preferred embodiment of the present invention.

圖3是用以說明本發明的適宜的實施形態的另外別的例子的MISTr的構成的模式性構成說明圖。 Fig. 3 is a schematic explanatory view showing a configuration of an MISTr according to another example of a preferred embodiment of the present invention.

圖1所示的MISTr100是在半導體用的基體101上具備閘極電極102、閘極絕緣膜103、半導體層104、源極電極105、汲極電極106。 The MISTr 100 shown in FIG. 1 includes a gate electrode 102, a gate insulating film 103, a semiconductor layer 104, a source electrode 105, and a drain electrode 106 on a substrate 101 for a semiconductor.

MISTr100是在設置半導體層104時，為了消除階差，而在閘極絕緣膜103的左右預設平坦化層領域109a、109b，使其表面在閘極絕緣膜103的上面一致。 In the MISTr 100, in order to eliminate the step, the flattening layer regions 109a and 109b are arranged on the left and right sides of the gate insulating film 103 so that the surface thereof coincides with the upper surface of the gate insulating film 103.

為了節省生產成本，而將基體100例如設為青板玻璃等價格便宜的玻璃基板時，為了防止在該玻璃基板中所含的鈉(Na)擴散至基板外部，而因應所需設有Na擴散防止層107。此情況，若在基體100的下部面設置與Na擴散防止層107同樣Na擴散防止機能外還具備耐藥品機能，特別是耐蝕刻藥劑機能之耐藥劑性Na擴散防止層108，則不僅鈉(Na)的擴散防止，還可防止在MISTr100的製作過程所使用的藥品例如緩衝氫氟酸等之玻璃基體的蝕 刻，因此更佳。 In order to save the production cost, when the base 100 is, for example, an inexpensive glass substrate such as a slate glass, Na diffusion is required in order to prevent the sodium (Na) contained in the glass substrate from diffusing to the outside of the substrate. Prevention layer 107. In this case, if the Na diffusion prevention function is provided on the lower surface of the base 100, and the Na diffusion prevention function is provided in addition to the Na diffusion prevention function, in particular, the drug-resistant Na diffusion prevention layer 108 which is resistant to the etching agent function, not only sodium (Na) The diffusion prevention prevents the etch of the glass substrate used in the manufacturing process of the MISTr 100, such as buffered hydrofluoric acid or the like. Engraved, so better.

Na擴散防止層107，耐藥劑性Na擴散防止層108是可以同材料構成或按照各層所要求的特性以不同的材料構成。如此的材料是例如可舉國際公開第2010/001793號記載的下記有機組成物(A)作為理想的材料。 The Na diffusion preventing layer 107 and the drug-resistant Na diffusion preventing layer 108 may be composed of different materials or different materials depending on the properties required for each layer. Such a material is, for example, the following organic composition (A) described in International Publication No. 2010/001793 as an ideal material.

有機組成物(A)：以一般式((CH3)SiO3/2)x(SiO2)1-x(在此，0<x≦1.0)表示的組成物。 Organic composition (A): a composition represented by the general formula ((CH 3 )SiO 3/2 ) x (SiO 2 ) 1-x (here, 0 < x ≦ 1.0).

例如，具體而言，可舉藉由將甲基三烷氧基矽烷化合物與四烷氧矽烷化合物的混合物予以加水分解縮合反應而取得的縮合物為理想的例子。 For example, a condensate obtained by hydrolyzing a condensation reaction of a mixture of a methyltrialkoxy decane compound and a tetraalkoxy decane compound is preferable.

塗佈含此縮合物的塗佈液來形成塗佈膜，以400℃以下的溫度來熱處理該塗佈膜，藉此形成Na擴散防止層107或耐藥劑性Na擴散防止層108。 The coating liquid containing the condensate is applied to form a coating film, and the coating film is heat-treated at a temperature of 400 ° C or lower to form a Na diffusion preventing layer 107 or a drug-resistant Na diffusion preventing layer 108.

膜厚是即使極薄化至150~300nm程度，Na的擴散防止機能等良好的特性也會被維持。絕緣特性亦佳。例如，在1MV/cm，電流密度1×10-10A/cm2，在3MV/cm，電流密度1×10-9A/cm2，顯示良好的值。 When the film thickness is extremely thinned to about 150 to 300 nm, good characteristics such as diffusion prevention function of Na are maintained. Insulation properties are also good. For example, at 1 MV/cm, the current density is 1 × 10 -10 A/cm 2 , at 3 MV/cm, and the current density is 1 × 10 -9 A/cm 2 , which shows a good value.

其他，可舉被摻雜鎵(Ga)、鋁(Al)、或銦(In)的氧化鋅(ZnO)。 Other examples include zinc oxide (ZnO) doped with gallium (Ga), aluminum (Al), or indium (In).

閘極絕緣膜103是需要選擇可擔保閘極容量及洩漏電流防止(或抑制)的材料及製造製程．條件來形成。在本發明中，閘極絕緣膜103是利用後述的液組成的電解溶液來陽極氧化添加有鋯(Zr)的鋁(Al)合金(「亦有記載 成Al(Zr)合金的情況」)膜而形成。 The gate insulating film 103 is a material and a manufacturing process that are required to ensure the gate capacity and leakage current prevention (or suppression). Conditions are formed. In the present invention, the gate insulating film 103 is anodized with an aluminum (Al) alloy to which zirconium (Zr) is added by an electrolytic solution having a liquid composition to be described later ("also described Formed as a film of Al(Zr) alloy.

為了閘極絕緣膜103形成而設的Al(Zr)合金膜可為閘極電極102形成用者本身，或設在閘極電極102上者。將Al(Zr)合金膜設為閘極電極102形成用的合金膜本身時，是只將Al(Zr)合金膜上部陽極氧化而作為閘極絕緣膜103，下部則是維持Al(Zr)合金不變作為閘極電極102。亦即，將閘極電極102形成用所設的Al(Zr)合金膜的上方的一部分陽極氧化而形成閘極絕緣膜103，不陽極氧化的剩餘下部是設為閘極電極102。 The Al (Zr) alloy film provided for forming the gate insulating film 103 may be formed by the gate electrode 102 itself or on the gate electrode 102. When the Al (Zr) alloy film is used as the alloy film itself for forming the gate electrode 102, only the upper portion of the Al (Zr) alloy film is anodized to serve as the gate insulating film 103, and the lower portion is maintained as the Al (Zr) alloy. It does not change as the gate electrode 102. In other words, the gate electrode 102 is formed by a part of the upper portion of the Al (Zr) alloy film to be anodized to form the gate insulating film 103, and the remaining lower portion which is not anodized is the gate electrode 102.

在本發明中，用以陽極氧化形成閘極絕緣膜103的Al(Zr)合金是以鋁(Al)為主體，添加有鋯(Zr)的Al合金(但，鎂及鈰的任一方是不含)。 In the present invention, the Al(Zr) alloy for forming the gate insulating film 103 by anodization is an aluminum alloy mainly composed of aluminum (Al) and added with zirconium (Zr) (however, neither of magnesium nor germanium is Including).

在前述合金中添加的鋯(Zr)的添加量是按照所被形成的閘極絕緣膜103的設計上的所望電氣特性來適當決定。又，以Al(Zr)合金膜來構成閘極電極102時，對於陽極氧化應作為閘極絕緣膜103的Al(Zr)合金膜而形成的陽極氧化膜，以預定的溫度來實施預定時間熱處理，因此為了防止或抑制藉由此熱處理而形成的陽極氧化膜中的Al2O3的結晶粒成長大到容許以上，而Zr的添加量會按照所望來適當選擇。本發明的Zr的添加量最好是0.01%~0.15%。藉由將Zr的添加量形成此範圍，即使實施350℃程度的熱處理，還是可確實地阻止或抑制結晶粒的成長，可使陽極氧化膜的機械強度及電氣絕緣性更提升。在此「%」是表示「質量%」，在本案中以「%」記載時 是本案說明書全體意思「質量%」。 The addition amount of zirconium (Zr) added to the above-mentioned alloy is appropriately determined in accordance with the desired electrical characteristics of the gate insulating film 103 to be formed. When the gate electrode 102 is formed of an Al (Zr) alloy film, the anodized film formed by anodizing the Al (Zr) alloy film as the gate insulating film 103 is subjected to a predetermined time heat treatment at a predetermined temperature. Therefore, in order to prevent or suppress the growth of crystal grains of Al 2 O 3 in the anodized film formed by the heat treatment to be larger than the above, the amount of Zr added is appropriately selected as desired. The amount of Zr added in the present invention is preferably from 0.01% to 0.15%. By setting the addition amount of Zr to this range, even if heat treatment at 350 ° C is performed, the growth of crystal grains can be surely prevented or suppressed, and the mechanical strength and electrical insulation of the anodized film can be further improved. Here, "%" means "% by mass", and in the case of "%" in this case, it is the "% by mass" of the entire description of the present specification.

本發明的Al(Zr)合金是除了上述量的添加物的剩餘部分為Al及不可避雜質所構成，最好該不可避雜質分別為0.01%以下。該不可避雜質是例如矽(Si)，鐵(Fe)，銅(Cu)等。 The Al(Zr) alloy of the present invention is composed of Al and an unavoidable impurity in addition to the remainder of the above-mentioned additive, and it is preferable that the unavoidable impurities are each 0.01% or less. The unavoidable impurities are, for example, bismuth (Si), iron (Fe), copper (Cu), and the like.

在本發明中，Al(Zr)合金膜的形成是使用旋轉磁控管濺射裝置來形成。旋轉磁控管濺射裝置是例如記載於國際公開第2007/043476號，國際公開第2008/114718號等。濺射成膜條件是成膜用的基板的溫度較理想為室溫~200℃程度，濺射用的氣體是使用Kr/O2(O2：1~5%)混合氣體。 In the present invention, the formation of an Al(Zr) alloy film is formed using a rotary magnetron sputtering apparatus. The rotary magnetron sputtering apparatus is described, for example, in International Publication No. 2007/043476, International Publication No. 2008/114718, and the like. The sputtering film formation condition is such that the temperature of the substrate for film formation is preferably from room temperature to 200 ° C, and the gas for sputtering is a mixed gas of Kr/O 2 (O 2 : 1 to 5%).

所被形成的合金膜的膜厚是依據將膜全體陽極氧化或將膜的一部分膜狀地陽極氧化，按照所望來適當決定。以膜的一部分作為閘極電極來陽極氧化剩餘部分時，最好是1~3μm。 The film thickness of the alloy film to be formed is appropriately determined depending on whether the entire film is anodized or a part of the film is anodized in a film form. When a part of the film is used as a gate electrode to anodize the remaining portion, it is preferably 1 to 3 μm.

在本發明中，Al(Zr)合金膜的陽極氧化是以下那樣實施，但並非限於此，只要是按照本發明的目的的範圍的製作製程或製作條件，便是本發明的範疇。 In the present invention, the anodization of the Al(Zr) alloy film is carried out as follows, but it is not limited thereto, and the production process or production conditions in accordance with the scope of the object of the present invention are within the scope of the present invention.

在本發明的陽極氧化使用的理想電解溶液是以下所記的非水溶液系的陽極氧化用電解溶液(A)。 The ideal electrolytic solution used for the anodic oxidation of the present invention is a non-aqueous solution electrolytic solution (A) for anodizing as described below.

非水溶液系的陽極氧化用電解溶液(A) Non-aqueous solution for anodizing electrolytic solution (A)

溶液(1)：乙二醇(79%) Solution (1): ethylene glycol (79%)

己二酸銨(1%) Ammonium adipate (1%)

水(20%) Water (20%)

溶液(2)：二甘醇(79.5%) Solution (2): diethylene glycol (79.5%)

己二酸銨(0.5%) Ammonium adipate (0.5%)

水(20%) Water (20%)

將在所望的基板上準備的Al(Zr)合金膜(試料A)浸漬於充滿預定量該等的電解溶液(A)的陽極氧化用的浴槽中，在Pt(白金)製對向電極(Pt)之間施加電壓而進行陽極氧化。此時，一定地流動電流密度0.1~0.2mA/cm2的範圍的大小的電流(定電流模式)來進行陽極氧化。試料(1)的陽極氧化面與對向電極(Pt)之間的電壓(V)會隨陽極氧化膜的成長而逐漸地上昇。一旦電壓(V)上昇至25~50V的範圍的電壓，則切換成定電壓模式。若流動於試料(1)與對向電極(Pt)之間的電流(A)充分低於1μA/cm2，則終了陽極氧化。然後，以超純水來充分地洗淨試料(1)。 The Al (Zr) alloy film (sample A) prepared on the desired substrate is immersed in a bath for anodizing filled with a predetermined amount of the electrolytic solution (A), and a counter electrode (Pt) made of Pt (platinum) Anodization is performed by applying a voltage between them. At this time, an anodization is performed by constantly flowing a current (constant current mode) having a current density in the range of 0.1 to 0.2 mA/cm 2 . The voltage (V) between the anodized surface and the counter electrode (Pt) of the sample (1) gradually increases as the anodized film grows. Once the voltage (V) rises to a voltage in the range of 25 to 50 V, it switches to the constant voltage mode. If the current (A) flowing between the sample (1) and the counter electrode (Pt) is sufficiently lower than 1 μA/cm 2 , the anodization is terminated. Then, the sample (1) was sufficiently washed with ultrapure water.

洗淨後，進行其次那樣的熱處理。在減壓(1~10Torr)N2氣體環境中，慢慢地昇溫至300℃，將其狀態維持1~10小時，較理想是3~7小時。其次，取代N2氣體，一邊流動100%O2氣體，一邊在常壓下，300℃，維持1~3小時。 After washing, the next heat treatment is performed. In a reduced pressure (1 to 10 Torr) N 2 gas atmosphere, the temperature is gradually raised to 300 ° C, and the state is maintained for 1 to 10 hours, preferably 3 to 7 hours. Next, instead of the N 2 gas, while flowing 100% of O 2 gas, it was maintained at 300 ° C for 1 to 3 hours under normal pressure.

若使用涉及本發明的非水系電解溶液(A)，則從極薄的膜到厚膜為止，即是在大的面積還是可確實地有效率地形成全面無孔質緻密均一的高絕緣性的陽極氧化膜(勢壘(barrier)型)。其理由之一記載於以下。若像水系的電解溶液的陽極氧化那樣為水主體的溶液，則由於水的比介電常數為80極大，因此在水分子低的電壓解離成H+及 OH-。為了在Al(Zr)合金膜表面以某程度的厚度來形成陽極氧化膜，而必須在對向電極的Pt(白金)電極之間至少施加200V以上的電壓，但所被形成的陽極氧化膜的電性耐性無至此程度的耐性，一般難形成膜至某程度的厚度。為此，在本發明中是添加比介電常數小的乙二醇或二甘醇作為非水溶液，最好是將其比介電常數降低至51~44左右使用。 When the non-aqueous electrolytic solution (A) according to the present invention is used, it is possible to form a substantially non-porous, dense and uniform high insulating property from a very thin film to a thick film, that is, in a large area. Anodized film (barrier type). One of the reasons is described below. If the water-based electrolytic solution is a solution of a water main body, the water has a specific dielectric constant of 80, so that a low voltage of water molecules dissociates into H + and OH - . In order to form an anodized film to a certain thickness on the surface of the Al(Zr) alloy film, at least a voltage of 200 V or more must be applied between the Pt (platinum) electrodes of the counter electrode, but the anodized film formed is formed. Electrical resistance does not have such a degree of resistance, and it is generally difficult to form a film to a certain thickness. For this reason, in the present invention, ethylene glycol or diethylene glycol having a lower specific dielectric constant is added as a non-aqueous solution, and it is preferable to reduce the specific dielectric constant to about 51 to 44.

在本發明的非水系電解液中形成的Al(Zr)合金的勢壘型陽極氧化膜是具有作為不動態膜佳的特徵。又，氧化膜表面的微粗糙度相較於水溶液系電解液的氧化膜非常小。而且，即使在高的溫度中，本發明的勢壘型陽極氧化膜也不會產生熱龜裂等，來自膜的外氣的放出水分量也非常少。顯示顯著的耐蝕性。 The barrier type anodized film of the Al(Zr) alloy formed in the nonaqueous electrolytic solution of the present invention is characterized by being excellent as an ineffective film. Further, the micro-roughness of the surface of the oxide film is extremely smaller than that of the oxide film of the aqueous solution. Further, even at a high temperature, the barrier type anodic oxide film of the present invention does not generate thermal cracking or the like, and the amount of released water from the outside air of the film is extremely small. Shows significant corrosion resistance.

本發明的陽極氧化膜是藉由調整電解溶液的比介電常數及陽極氧化時的施加電壓，可取得預定的膜厚者。在本發明中，陽極氧化膜的膜厚是按照被形成之構成電子元件的絕緣膜或多層配線基板的層間絕緣膜所要求的特性來適當決定。陽極氧化膜的膜厚是5~100nm為理想，更理想是10~70nm，最好是30~60nm。 The anodized film of the present invention can obtain a predetermined film thickness by adjusting the specific dielectric constant of the electrolytic solution and the applied voltage at the time of anodization. In the present invention, the film thickness of the anodized film is appropriately determined in accordance with characteristics required for the insulating film constituting the electronic component or the interlayer insulating film of the multilayer wiring substrate. The film thickness of the anodized film is preferably 5 to 100 nm, more preferably 10 to 70 nm, and most preferably 30 to 60 nm.

本發明之藉由陽極氧化法所形成之來自Al(Zr)合金的陽極氧化膜實質地也包含其膜全體或幾乎膜全體以氧化鋁(Al2O3)所構成，但也包含不可避不純元素來自Al(Zr)合金的元素的混入在達成本發明的目的的範圍內被容許。為了符合絕緣膜所要求的特性，依情況，也有使 來自Al(Zr)合金的金屬(Zr)的氧化物意圖地混入陽極氧化膜中的情形。 The anodized film from the Al(Zr) alloy formed by the anodic oxidation method of the present invention substantially also includes the entire film or almost the entire film composed of aluminum oxide (Al 2 O 3 ), but also contains unavoidable impure elements. The incorporation of an element derived from an Al(Zr) alloy is allowed within the scope of achieving the object of the present invention. In order to meet the characteristics required for the insulating film, there are cases where an oxide of a metal (Zr) derived from an Al(Zr) alloy is intentionally mixed into the anodized film.

在本發明中所被使用的非水系的電解溶液是含前述般的成分，調整成預定的介電常數及pH。在本發明中所被使用的非水系的電解溶液中，只要是不損本發明的目的的範圍，亦可使含其他必要的化學成分。 The non-aqueous electrolytic solution used in the present invention contains the above-described components and is adjusted to have a predetermined dielectric constant and pH. The non-aqueous electrolytic solution used in the present invention may contain other necessary chemical components as long as it does not impair the object of the present invention.

在本發明中基體101是可使用各種的材料，較理想採用的是耐熱塑膠，玻璃，金屬，陶瓷等。如此的材料是例如使用石英，青板玻璃，無鹼金屬玻璃，矽(Si)基板，鋁，不鏽鋼等的金屬基板，鎵砷(GaAs)等的半導體基板，及熱可塑性或熱硬化性的塑膠基板等。並且，亦可使用作為層疊上述材料的其中2種以上的複合層疊體的基體。 In the present invention, various materials can be used for the substrate 101, and heat-resistant plastics, glass, metal, ceramics and the like are preferably used. Such materials are, for example, quartz, blue plate glass, alkali-free metal glass, iridium (Si) substrate, metal substrate such as aluminum or stainless steel, semiconductor substrate such as gallium arsenide (GaAs), and thermoplastic or thermosetting plastic. Substrate, etc. Further, a base body in which two or more types of composite laminates of the above materials are laminated may be used.

在本發明中，閘極電極102通常是可使用在半導體領域所被使用的電極用或電氣配線用的導電性材料的大概者。如此的導電性材料是例如Cr，Al，Ta，Mo，Nb，Cu，Ag，Au(4.9eV)，Pt，Pd，In，Ni，Nd，Ca，Ti，Ta，Ir，Ru，W，Mo，Ru-Mo合金等的金屬及該等金屬的合金(以後也有時記載為「金屬(M)」，但「M≠(Zr)」)，或以Al(Zr)合金來構成。其他，可舉InO2，Sn2，ITO等的導電性的氧化物，TiN，TaN等的導電性氮化物，聚苯胺，聚吡咯，聚噻吩，或聚乙炔等的導電性高分子，石墨烯(Graphene)，奈米碳管(Carbon nanotubes)，，電荷移動錯體等的分子性導體，該等的層疊構造構件。而且，亦 可使用碳黑(carbon black)或分散金屬粒子的導電性的複合材料。 In the present invention, the gate electrode 102 is generally an approximate one of conductive materials for electrodes or electrical wiring used in the field of semiconductors. Such a conductive material is, for example, Cr, Al, Ta, Mo, Nb, Cu, Ag, Au (4.9 eV), Pt, Pd, In, Ni, Nd, Ca, Ti, Ta, Ir, Ru, W, Mo. A metal such as a Ru-Mo alloy or an alloy of these metals (may be described later as "metal (M)", but "M≠ (Zr)") or an Al (Zr) alloy. Other examples include conductive oxides such as InO 2 , Sn 2 , and ITO, conductive nitrides such as TiN and TaN, conductive polymers such as polyaniline, polypyrrole, polythiophene, and polyacetylene, and graphene. (Graphene), a carbon nanotube (carbon nanotubes), a molecular conductor such as a charge transporting complex, or a laminated structural member. Further, a carbon black or a conductive composite material in which metal particles are dispersed may also be used.

閘極電極102最好是考慮形成於其上的層(或膜)的平坦性來發揮電極機能，在不發生針孔的範圍內儘可能形成薄。具體而言，通常是形成100nm以下，最好是50nm以下，更理想是10nm以下的厚度。 It is preferable that the gate electrode 102 exerts an electrode function in consideration of the flatness of a layer (or film) formed thereon, and is formed as thin as possible within a range in which pinholes do not occur. Specifically, it is usually 100 nm or less, preferably 50 nm or less, more preferably 10 nm or less.

在本發明中，閘極電極102並不限於從上述的材料之中選擇的單一材料所構成的單層構成。例如，亦可使用由InO2，SnO2，ITO等的導電性的氧化物，TiN，TaN等的導電性氮化物，及金屬(M)，Al(Zr)合金所選擇的不同的材料來構成複合膜。如此的複合膜是例如從基體101側依序層疊的構成，可舉以下所示者作為理想的電極構成。 In the present invention, the gate electrode 102 is not limited to a single layer composed of a single material selected from the above materials. For example, a conductive oxide such as InO 2 , SnO 2 , or ITO, a conductive nitride such as TiN or TaN, or a different material selected from the metal (M) or Al (Zr) alloy may be used. Composite film. Such a composite film is, for example, a structure which is sequentially laminated from the side of the substrate 101, and is preferably an electrode structure as described below.

D(1)金屬(M)膜/Al(Zr)合金膜 D(1) metal (M) film / Al (Zr) alloy film

D(2)Al(Zr)合金膜/金屬(M)膜 D(2)Al(Zr) alloy film/metal (M) film

D(3)金屬(M1)膜/金屬(M2)膜(在此，M1≠M2) D(3) metal (M1) film / metal (M2) film (here, M1 ≠ M2)

D(4)導電性氧化物膜/Al(Zr)合金膜 D(4) conductive oxide film / Al (Zr) alloy film

閘極電極長是按照元件設計來適當決定，但最好是2~10μm為理想。 The gate electrode length is appropriately determined according to the component design, but it is preferably 2 to 10 μm.

源極電極，汲極電極是可以單一材料的膜單體所構成，或以相異的金屬(M)材料構成的複合膜(層疊構造膜/複膜構成膜)所構成。複合膜是例如若以來自半導體層104側的層疊順序顯示，則可舉以下所示者作為理想的電極構成。 The source electrode and the drain electrode are composed of a single film monomer or a composite film (laminated structure film/film composite film) made of a different metal (M) material. The composite film is, for example, displayed in the order of lamination from the side of the semiconductor layer 104, and is preferably an electrode structure as described below.

SD(1)Mo膜/Al膜 SD (1) Mo film / Al film

SD(2)Mo膜/Cu膜 SD(2)Mo film/Cu film

SD(3)Ti膜/Al膜 SD(3)Ti film/Al film

SD(4)Ti膜/Cu膜 SD (4) Ti film / Cu film

SD(5)Cu膜/Al膜 SD (5) Cu film / Al film

本發明的半導體層104是以有機半導體材料或無機半導體材料所構成。如此的半導體材料是可為結晶質或非結晶質，結晶質時雖也可為單結晶，但基於容易製作大面積的裝置的點，多結晶質或微結晶質者為理想。 The semiconductor layer 104 of the present invention is composed of an organic semiconductor material or an inorganic semiconductor material. Such a semiconductor material may be crystalline or amorphous, and may be a single crystal in the case of a crystalline material. However, it is preferably a polycrystalline or microcrystalline material because it is easy to produce a device having a large area.

有機半導體材料是以並五苯或蒽，紅螢烯等的多環芳香族碳化氫或氰雙甲烷(TCNQ)等的低分子化合物為首，可舉聚乙炔或聚-3-已基噻吩(P3HT)，聚對苯撐(PPV)等的聚合物。 The organic semiconductor material is a polymolecular compound such as polycyclic aromatic hydrocarbon or cyanobismethane (TCNQ) such as pentacene or anthracene or erythroprene, and may be polyacetylene or poly-3-hexylthiophene (P3HT). ), a polymer such as polyparaphenylene (PPV).

無機半導體材料是有非晶形矽(a-Si)，微結晶性(micro及nano)或多結晶性矽(poly-Si)，氧化鋅或二氧化錫，氧化銦或ITO(通常In2O3：SnO2=90：10[wt%])等的氧化物半導體。 Inorganic semiconductor materials are amorphous 矽 (a-Si), microcrystalline (micro and nano) or polycrystalline 矽 (poly-Si), zinc oxide or tin dioxide, indium oxide or ITO (usually In 2 O 3 An oxide semiconductor such as SnO 2 = 90:10 [wt%]).

非晶形矽是有以電洞作為電荷載體的p型，也有以電子作為電荷載體的n型的兩性，但大多是n型。但，也有氧化銅或氧化銀、一氧化錫等作為p型的報告。 The amorphous yttrium has a p-type with a hole as a charge carrier, and an n-type amphoteric with electrons as a charge carrier, but most of them are n-type. However, there are also reports of copper oxide, silver oxide, tin oxide, and the like as a p-type.

但，有希望更適當為本發明所實施的無機半導體材料是所謂「透明非晶形氧化物半導體(TAOS：Transparent Amorphous Oxide Semiconductors)」。使用TAOS系的無機半導體材料來形成的薄膜電晶體(TFT： Thin Film Transistor)是載子移動度為10cm2/Vs以上高，特性偏差亦小，因此具有可抑制在有機EL面板成問題之TFT的特性偏差所造成的顯示不均之優點。由於TAOS膜是可以濺射法來形成，因此製造成本也可降低。又，由於將製造製程溫度降低至接近室溫，因此可利用缺乏耐熱性的樹脂基板，可容易實現能折彎的電子紙等，可撓性的顯示器，而且容易實現活用其透明性的透明顯示器。 However, it is desirable that the inorganic semiconductor material to be implemented in the present invention is a so-called "Transparent Amorphous Oxide Semiconductors (TAOS)". A thin film transistor (TFT: Thin Film Transistor) formed using a TAOS-based inorganic semiconductor material has a carrier mobility of 10 cm 2 /Vs or more and a small variation in characteristics, and thus has a TFT which can suppress problems in the organic EL panel. The advantage of display unevenness caused by the characteristic deviation. Since the TAOS film can be formed by a sputtering method, the manufacturing cost can also be lowered. In addition, since the manufacturing process temperature is lowered to near room temperature, a resin substrate lacking heat resistance can be used, and a bendable electronic paper or the like can be easily realized, and a flexible display can be easily realized, and a transparent display using transparency thereof can be easily realized. .

在本發明中，TAOS系的無機半導體材料之中，持有(1)移動度高，(2)OFF性能高，(3)生產性高等的特徵之非晶形In-Ga-Zn-O(以後也有記載為「IGZO」的情形)為理想的材料。IGZO是電子移動度為被採用於電視(TV)或監視器的a-Si的20~50倍，因此TFT的小型化及配線的細線化充分可能，在IGZO-LCD是可以同等的透過率來足夠地謀求2倍的高精細化。並且，藉由高的OFF性能，亦可實現更低消費電力化。例如，就以往的液晶驅動方式而言，是以60frame/s來重寫，相對的，當不需要重寫靜止畫面的顯示時等畫面時，可設置休止期間，可將消費電力削減至以往的1/5~1/10。若將此休止期間設於a-Si顯示面板，則會發生閃爍，但若採用IGZO，則可無閃爍地實現。藉此OFF性能的高度，可謀求觸控面板的高性能化。例如，藉由使用休止驅動，SN比會提升5倍，碰觸的檢出性能也可格外地提升。 In the present invention, among the inorganic semiconductor materials of the TAOS system, amorphous In-Ga-Zn-O (hereinafter, characterized by high mobility, (2) high OFF performance, and (3) high productivity are present. It is also an ideal material for the case of "IGZO". IGZO is 20 to 50 times the electronic mobility of a-Si used in televisions (TVs) or monitors. Therefore, the miniaturization of TFTs and the thinning of wiring are possible. In IGZO-LCD, the transmittance can be equal. It is enough to achieve twice the high definition. Moreover, with high OFF performance, it is also possible to achieve lower power consumption. For example, in the conventional liquid crystal driving method, 60 frames/s is rewritten, and when it is not necessary to rewrite the display of a still picture, the rest period can be set, and the power consumption can be reduced to the conventional one. 1/5~1/10. If the rest period is set on the a-Si display panel, flickering may occur, but if IGZO is used, it can be realized without flicker. By virtue of the height of the OFF performance, the performance of the touch panel can be improved. For example, by using the rest drive, the SN ratio is increased by a factor of five, and the detection performance of the touch can be exceptionally improved.

以具有如此的優點的IGZO來構成半導體層的MISTr是以其閘極絕緣膜作為本發明的陽極氧化膜，藉此 使其優點更有效地發揮，因此在本發明中是形成更理想的組合。 The MISTr constituting the semiconductor layer with IGZO having such an advantage is a gate insulating film thereof as an anodized film of the present invention, whereby The advantages are made more effective, and thus a more desirable combination is formed in the present invention.

源極電極105及汲極電極106最好是以在與構成半導體層104的材料的關係中適當選擇的材料所構成，而使與半導體層104的電性接觸能夠順利。例如，以形成有活性層領域(通道領域)的半導體層104作為n型動作特性將MISTr100設為nMiSTr時，源極電極105是以功函數小的材料所構成。以並五苯之類的有機半導體材料來構成半導體層104作為n型動作特性時，適當地選擇材料，使能夠在該有機半導體材料的LUMO(Lowest Unoccupied Molecular Orbital)(並五苯的情況是3.2eV)儘可能取整合性。其結果，容易從源極電極105來注入電子至構成半導體層104的材料的LUMO。 The source electrode 105 and the drain electrode 106 are preferably made of a material that is appropriately selected in relation to the material constituting the semiconductor layer 104, and the electrical contact with the semiconductor layer 104 can be smoothly performed. For example, when the MISTr 100 is set to nMiSTr as the n-type operational characteristic of the semiconductor layer 104 in which the active layer region (channel region) is formed, the source electrode 105 is made of a material having a small work function. When the semiconductor layer 104 is formed as an n-type operational characteristic by an organic semiconductor material such as pentacene, a material is appropriately selected so that LUMO (Lowest Unoccupied Molecular Orbital) can be obtained in the organic semiconductor material (in the case of pentacene is 3.2) eV) Take integration as much as possible. As a result, it is easy to inject electrons from the source electrode 105 to the LUMO of the material constituting the semiconductor layer 104.

汲極電極106的材料的選擇基準，在接觸界面的載子的順利的移動的意思是與源極電極105的材料的選擇基準同樣。亦即，汲極電極106的情況是選擇電子容易從構成半導體層104的材料的HOMO(Highest Occupied Molecular Orbital)往汲極電極106放出之類的材料。亦即，以有機半導體材料來構成活性層領域104作為p型動作特性時，適當選擇材料，而使能夠在該有機半導體材料的HOMO(Highest Occupied Molecular Orbital)(並五苯的情況是5.0eV)儘可能取能量水平的整合性。 The selection criteria of the material of the drain electrode 106 means that the smooth movement of the carrier at the contact interface is the same as the selection criterion of the material of the source electrode 105. In other words, in the case of the gate electrode 106, a material such as HOMO (Highest Occupied Molecular Orbital) which is easy to emit electrons from the material constituting the semiconductor layer 104 to the gate electrode 106 is selected. In other words, when the active layer region 104 is formed of an organic semiconductor material as the p-type operating property, the material is appropriately selected, and HOMO (Highest Occupied Molecular Orbital) of the organic semiconductor material (5.0 eV in the case of pentacene) can be obtained. Take the integration of energy levels as much as possible.

構成平坦化層領域109的材料是在形成平坦化層領域109時，只要是其表面平滑性佳者，可採用半導 體領域的大概的材料。其中，在製造製程中，採用需要高溫的工程或熱處理工程時，採用耐熱溫度為150℃以上，例如聚芳基酸酯(PAR)，聚碸(PSF)，聚苯硫醚(PPS)，聚醚醚酮(PEEK)，聚醯亞胺樹脂，氟樹脂等為理想。聚醯胺亞醯胺(PAI)，聚醚醚酮(PEEK)等是具有250℃以上的耐熱性，且長時間的使用也可能，因此採用上述那樣的製造製程時，為特別理想的材料。該等的樹脂以外，可形成無針孔超極薄化膜的聚乙烯基苯酚(PVPh)也是在本發明中為特別理想的材料。 The material constituting the planarization layer region 109 is such that when the planarization layer region 109 is formed, as long as the surface smoothness is good, semiconducting can be employed. Probable material in the field. Among them, in the manufacturing process, when engineering or heat treatment engineering requiring high temperature is employed, the heat resistance temperature is 150 ° C or higher, such as polyarylate (PAR), polyfluorene (PSF), polyphenylene sulfide (PPS), and poly Ether ether ketone (PEEK), polyimide resin, fluororesin, etc. are preferred. Polyacrylamide (PAI), polyetheretherketone (PEEK), etc. have heat resistance of 250 ° C or higher, and may be used for a long period of time. Therefore, it is particularly preferable when the above-mentioned manufacturing process is employed. In addition to these resins, polyvinylphenol (PVPh) which forms a pinhole-free ultra-thin film is also a particularly desirable material in the present invention.

平坦化領域110是除了以樹脂來構成以外，亦可以氧化矽(SiO2)，氮化矽(Si3N4)，氧氮化矽(SiNO)，碳氮化矽(SiCN)等的無機絕緣材料所構成。 The planarization field 110 is an inorganic insulating material such as yttrium oxide (SiO 2 ), tantalum nitride (Si 3 N 4 ), lanthanum oxynitride (SiNO), or tantalum carbonitride (SiCN), in addition to being composed of a resin. Made up of materials.

圖2所示的MISTr200是與圖1所示的MISTr100同樣，在半導體用的基體201上具備閘極電極202，閘極絕緣膜203，半導體層204，源極電極205，汲極電極206，平坦化層領域209。在此，基體201是相當於基體101，閘極電極202是相當於閘極電極102，閘極絕緣膜203是相當於閘極絕緣膜103，半導體層204是相當於半導體層104，源極電極205是相當於源極電極105，汲極電極206是相當於汲極電極106，平坦化層領域209是相當於平坦化層領域109，分別適用與MISTr100的情況同樣的材料及作成條件。 Similarly to the MISTr 100 shown in FIG. 1, the MISTr 200 shown in FIG. 2 includes a gate electrode 202, a gate insulating film 203, a semiconductor layer 204, a source electrode 205, and a drain electrode 206, which are flat on the semiconductor substrate 201. Layer area 209. Here, the base 201 corresponds to the base 101, the gate electrode 202 corresponds to the gate electrode 102, the gate insulating film 203 corresponds to the gate insulating film 103, and the semiconductor layer 204 corresponds to the semiconductor layer 104, and the source electrode 205 corresponds to the source electrode 105, the drain electrode 206 corresponds to the drain electrode 106, and the planarization layer region 209 corresponds to the planarization layer region 109, and the same materials and fabrication conditions as in the case of the MISTr 100 are applied.

無變形性Na擴散防止層207，無變形．耐藥劑性Na擴散防止層208是因應所需設置。層207，層208 的特長是層本身無變形。此無變形性是MISTr200暴露至100℃程度的高溫幾乎不變。構成層207，層208的那樣的材料是例如可舉在氮化矽(Si3N4)添加10%程度碳(C)的SiCN為理想的材料。 Non-deformable Na diffusion preventing layer 207, no deformation. The drug-resistant Na diffusion preventing layer 208 is provided in response to the desired setting. Layer 207, layer 208 is characterized by no deformation of the layer itself. This non-deformability is that the temperature at which the MISTr 200 is exposed to 100 ° C is almost constant. The material constituting the layer 207 and the layer 208 is preferably a material obtained by adding SiNi (10%) carbon (C) to tantalum nitride (Si 3 N 4 ).

源極電極及汲極電極最好是以和半導體層的電性接觸能夠順利的方式在與構成半導體層的材料的關係中適當選擇的材料來構成。那樣的例子是顯示於圖3。 It is preferable that the source electrode and the drain electrode are formed of a material appropriately selected from the relationship with the material constituting the semiconductor layer so that electrical contact with the semiconductor layer can be smoothly performed. An example of this is shown in Figure 3.

圖3所示的MISTr300與圖1所示的MISTr100是僅源極電極部305及汲極電極部306分別與源極電極105及汲極電極106不同，其他則是同樣，因此有關共通部分是使用與圖1共通的符號。 The MISTr 300 shown in FIG. 3 and the MISTr 100 shown in FIG. 1 have only the source electrode portion 305 and the drain electrode portion 306 different from the source electrode 105 and the drain electrode 106, respectively, and the others are the same. Therefore, the common portion is used. The symbol common to Figure 1.

圖3所示的例子是以低功函數的材料來構成源極電極部305的下部電極膜305a，以高功函數的材料來構成汲極電極部306的下部電極膜306a，藉此使MISTr300的電流驅動能力提升者。 The example shown in FIG. 3 constitutes the lower electrode film 305a of the source electrode portion 305 by a material having a low work function, and the lower electrode film 306a of the drain electrode portion 306 is formed of a material having a high work function, thereby making the MISTr 300 Current drive capability enhancer.

以並五苯之類的真性或實質地真性的半導體材料來構成半導體層104時，在半導體層104內部有助於傳導的載子是不存在或實質或幾乎不存在，因此需要自半導體層104外部注入載子來使電流驅動能力提升。為此，在與半導體層104的功函數的關係中，為了載子容易被注入半導體層104，而分別設置相對地低功函數的下部電極膜305a及高功函數的下部電極膜306a。例如，亦可設為以價格便宜容易處理的材料所構成的上部電極領域305b及以功函數小的材料所構成的下部電極領域305a之層疊 構造。具體而言，例如，上部電極領域305b是以Al，Cu等的金屬所構成，下部電極領域305a是以硼化鑭等所構成。尤其下部電極領域305a最好是以後述特性的LaB6(N)所構成。汲極電極部306是例如以Al來構成上部電極領域306b，以Ni來構成下部電極領域306a。藉由如此將電極部305，306設為複合層構造，可擴大電極材料的選擇範圍，因此電極部305，306的複合層構造理想。 When the semiconductor layer 104 is formed of a true or substantially true semiconductor material such as pentacene, a carrier that contributes to conduction inside the semiconductor layer 104 is absent or substantially or almost absent, and thus is required from the semiconductor layer 104. The carrier is externally injected to increase the current drive capability. For this reason, in the relationship with the work function of the semiconductor layer 104, a lower electrode film 305a having a relatively low work function and a lower electrode film 306a having a high work function are respectively provided for the carrier to be easily implanted into the semiconductor layer 104. For example, a laminated structure of the upper electrode region 305b composed of a material which is inexpensive and easy to handle, and a lower electrode region 305a composed of a material having a small work function may be used. Specifically, for example, the upper electrode region 305b is made of a metal such as Al or Cu, and the lower electrode region 305a is made of barium boride or the like. In particular, the lower electrode region 305a is preferably composed of LaB 6 (N) having the characteristics described later. The drain electrode portion 306 is, for example, an upper electrode region 306b formed of Al and a lower electrode region 306a formed of Ni. By thus providing the electrode portions 305 and 306 as a composite layer structure, the selection range of the electrode material can be expanded, and therefore the composite layer structure of the electrode portions 305 and 306 is preferable.

在本發明中，以有機材料來製膜時的製膜法是按照所形成的電子元件的特性或用途，所採用的成膜材料來採用各種的製膜法。在本發明中所被採用的製膜法是可舉塗佈法，真空蒸鍍法，CVD(Chemical Vapor Deposition)，PCVD(Plasma Chemical Vapor Deposition)等。塗佈法是可舉旋轉塗佈法，鑄造法，印刷法等。印刷法是可舉膠印印刷(offset printing)，凸版印刷，凹版印刷，照相凹版(gravure)印刷，網版印刷，噴墨印刷，微觸印刷(micro contact printing)等。在精細度，10μm以下時，是採用噴墨印刷，微觸印刷為理想。特別是在有機TFT中，藉由縮小源極電極及汲極電極的間隔(通道長：L)，元件的開關特性變佳為人所知，因此最好Sub-μm程度的大面積圖案化也可能的微觸印刷的採用。 In the present invention, the film forming method in forming a film from an organic material is a film forming method in accordance with the characteristics and use of the formed electronic component, and the film forming material to be used. The film forming method to be used in the present invention may be a coating method, a vacuum vapor deposition method, a CVD (Chemical Vapor Deposition), or a PCVD (Plasma Chemical Vapor Deposition). The coating method may be a spin coating method, a casting method, a printing method, or the like. The printing method is offset printing, letterpress printing, gravure printing, gravure printing, screen printing, inkjet printing, micro contact printing, and the like. When the fineness is 10 μm or less, inkjet printing is used, and micro-touch printing is desirable. In the organic TFT, in particular, by reducing the interval between the source electrode and the drain electrode (channel length: L), the switching characteristics of the device are improved, and therefore it is preferable to pattern a large area of Sub-μm. Possible use of micro-touch printing.

在本發明中，以易動度小的半導體材料來構成半導體層(104，204)使n型動作時，最好是在半導體層(104，204)與閘極絕緣膜(103，203)之間或與形成於半導體層(104，204)內的通道領域鄰接或接近而靠半導體層 (104，204)內的閘極絕緣膜(103，203)側設置電子供給層領域(X)。 In the present invention, when the semiconductor layer (104, 204) is formed of a semiconductor material having a small mobility to operate in an n-type, it is preferably in the semiconductor layer (104, 204) and the gate insulating film (103, 203). a semiconductor layer adjacent or adjacent to a channel region formed in the semiconductor layer (104, 204) The electron supply layer region (X) is provided on the side of the gate insulating film (103, 203) in (104, 204).

電子供給層領域(X)是以容易放出電子的低功函數的材料所構成。如此的材料是例如可舉硼化鑭(LaB6：六硼化鑭)。最好是以含氮硼化鑭(「LaB6(N)」)所構成。 The electron supply layer field (X) is composed of a material having a low work function for easily emitting electrons. Such a material is, for example, lanthanum boride (LaB 6 : lanthanum hexaboride). It is preferably composed of lanthanum borohydride ("LaB 6 (N)").

在本發明中，層領域(X)更理想是以以下說明的LaB6(N)膜來構成為佳。更理想的LaB6(N)膜是具有結晶構造的同時含氮原子0.3~0.5原子%，且該膜中的全結晶中的10~250nm的粒徑範圍的結晶的比例為20~90%，該膜的結晶化度為20%以上的膜。更理想是粒徑為10~250nm的範圍的結晶粒徑分布的峰值的最大是15~150nm的範圍的膜。 In the present invention, the layer region (X) is more preferably formed by the LaB 6 (N) film described below. More preferably, the LaB 6 (N) film has a crystal structure and contains 0.3 to 0.5 atomic % of a nitrogen atom, and the proportion of crystals having a particle diameter range of 10 to 250 nm in the total crystal in the film is 20 to 90%. The film has a degree of crystallization of 20% or more. More preferably, the film having a maximum particle diameter distribution in the range of 10 to 250 nm in the range of 15 to 150 nm is in the range of 15 to 150 nm.

本發明者等推測時，是在上述的數值範圍，不僅2.4eV的低功函數的LaB6膜，也因為與半導體層(104，204)的界面親和性佳，所以可想像形成界面特性良好，且密著性亦佳的膜。因此，即使裝置的累積使用時間相當長，預期的密著性也會被維持，不會產生膜的浮起或膜剝落，可想像形成歷時變化對抗特性佳的LaB6(N)膜。 The inventors of the present invention have estimated that the LaB 6 film having a low work function of not only 2.4 eV in the above numerical range has good interface affinity with the semiconductor layer (104, 204), so that it is conceivable that the interface characteristics are good. And the film is also excellent in adhesion. Therefore, even if the cumulative use time of the device is relatively long, the expected adhesion is maintained, and no floating or film peeling of the film occurs, and it is conceivable to form a LaB 6 (N) film having excellent resistance characteristics over time.

膜中的全結晶中的10~250nm的粒徑範圍的結晶的比例，最好是上述的數值範圍，但較理想是50~90%，更理想是80~90%。更理想是30~200nm的粒徑範圍的結晶的比例為50~90%最佳。而且，50~150nm的粒徑範圍的結晶的比例為50~90%更佳。 The ratio of the crystal in the range of 10 to 250 nm in the total crystals in the film is preferably in the above numerical range, but is preferably 50 to 90%, more preferably 80 to 90%. More preferably, the ratio of crystals in the particle size range of 30 to 200 nm is preferably 50 to 90%. Further, the ratio of the crystal in the particle diameter range of 50 to 150 nm is preferably from 50 to 90%.

在本發明中，為了取得更良好的含氮六硼化 鑭(「LaB6(N)」)膜，膜的結晶化度也重要。結晶化度，最好是如上述般為20%以上，較理想是30%以上，更理想是50%以上。 In the present invention, in order to obtain a more favorable nitrogen-containing lanthanum hexaboride ("LaB 6 (N)") film, the degree of crystallization of the film is also important. The degree of crystallization is preferably 20% or more as compared with the above, more preferably 30% or more, and still more preferably 50% or more.

為了取得本發明的更適宜的LaB6(N)膜，結晶粒徑分布的峰值位置也為重要的參數。在本發明中，最好粒徑為10~250nm的範圍的結晶粒徑分布的峰值的最大是15~150nm內，較理想是15~120nm，更理想是20~100nm的範圍。 In order to obtain a more suitable LaB 6 (N) film of the present invention, the peak position of the crystal grain size distribution is also an important parameter. In the present invention, the peak of the crystal grain size distribution in the range of 10 to 250 nm is preferably 15 to 150 nm, more preferably 15 to 120 nm, and more preferably 20 to 100 nm.

[實驗1]洩漏電流的測定及膜均一．緻密性的測定 [Experiment 1] Measurement of leakage current and film uniformity. Determination of compactness

「試料A」的準備 Preparation of Sample A

準備：按照在半導體領域通常被實施的洗淨法來洗淨其表面之10(cm)×10(cm)的大小的石英玻璃板。在此石英玻璃板上，利用在半導體領域通常被實施的濺射技術，光蝕刻微影技術，本發明的AlZr(0.1%)合金膜的陽極氧化法來形成MIM型電極構造部。 Preparation: A quartz glass plate having a size of 10 (cm) × 10 (cm) on its surface was washed in accordance with a cleaning method generally performed in the semiconductor field. On the quartz glass plate, an MIM-type electrode structure portion was formed by an anodic oxidation method of an AlZr (0.1%) alloy film of the present invention by a sputtering technique generally performed in the field of semiconductors, a photo-etching lithography technique.

前述電極構造部的下部電極部是寬5(mm)×長度8(cm)的條紋形狀的鋁(Al)電極10個在前述石英玻璃板上以2(mm)間距配列構成。在10個的Al電極上，寬5(mm)×長度5(mm)的陽極氧化膜及其上設置與陽極氧化膜同大小的鋁(Al)個別電極的層疊體是配列成10×10矩陣(100個的層疊體)。 The lower electrode portion of the electrode structure portion is a stripe-shaped aluminum (Al) electrode having a width of 5 (mm) × a length of 8 (cm) and is arranged at a pitch of 2 (mm) on the quartz glass plate. On 10 Al electrodes, an anodized film having a width of 5 (mm) × a length of 5 (mm) and a laminate of aluminum (Al) individual electrodes having the same size as the anodized film are arranged in a 10 × 10 matrix. (100 laminates).

(1)基體洗淨：臭氧水洗淨→氫水使用超音波洗淨→洗滌 (1) Washing the substrate: Washing with ozone water → Washing with hydrogen water using ultrasonic cleaning → Washing

(2)陽極氧化條件： (2) Anodizing conditions:

．電解液(溶液(1))：乙二醇(79%) . Electrolyte (solution (1)): ethylene glycol (79%)

己二酸銨(1%) Ammonium adipate (1%)

水(20%) Water (20%)

．定電壓模式：50V，0/5mA/cm2，23℃，2小時 . Constant voltage mode: 50V, 0/5mA/cm 2 , 23°C, 2 hours

(3)陽極氧化膜的熱處理條件： (3) Heat treatment conditions of anodized film:

1st步驟．．．N2氣體，流量1000cc/min，壓力5Torr，300℃，5小時 1st step. . . N 2 gas, flow rate 1000 cc / min, pressure 5 Torr, 300 ° C, 5 hours

2nd步驟．．．100%O2氣體，流量1000cc/min，常壓，300℃，1小時 2nd step. . . 100% O 2 gas, flow rate 1000 cc / min, atmospheric pressure, 300 ° C, 1 hour

「試料B」的準備 Preparation of Sample B

取代AlZr(0.1%)合金膜，使用AlZr(2%)合金膜，陽極氧化條件是在專利文獻1的實施例記載的條件以外，與試料A同樣製作試料B。 In the case of the AlZr (0.1%) alloy film, the AlZr (2%) alloy film was used, and the anodizing conditions were the same as those described in the examples of Patent Document 1, and the sample B was prepared in the same manner as the sample A.

(1)陽極氧化條件： (1) Anodizing conditions:

．電解液：酒石酸銨水溶液：乙二醇=3：7 . Electrolyte: aqueous ammonium tartrate solution: ethylene glycol = 3:7

．電解時的電解液的溫度．．．25℃(在恆溫槽調整) . The temperature of the electrolyte during electrolysis. . . 25 ° C (adjusted in the thermostat)

．陽極氧化開始時的電流密度．．．．5mA/cm2 . Current density at the beginning of anodization. . . . 5mA/cm 2

．在電壓形成140V的階段切換成140V的定電壓模式 . Switching to a constant voltage mode of 140V during the voltage formation of 140V

．在電流密度形成0.05mA/cm2的階段停止陽極氧化 . Stop anodic oxidation at a current density of 0.05 mA/cm 2

(2)無熱處理 (2) no heat treatment

「試料A」的評價結果 Evaluation result of "sample A"

將試料A設定於洩漏電流測定裝置，分別在100個的層疊體，使施加電壓慢慢地上昇，測定各層疊體的洩漏電流。即使任一層疊體皆為1MV/cm的施加電壓，洩漏電流也是電流密度1×10-9A/cm2以下。顯示良好的絕緣性。 The sample A was set in the leakage current measuring device, and the applied voltage was gradually increased in each of the 100 stacked bodies, and the leakage current of each laminated body was measured. Even if any of the laminates has an applied voltage of 1 MV/cm, the leakage current is also a current density of 1 × 10 -9 A/cm 2 or less. Shows good insulation.

「試料B」的評價結果 Evaluation result of "sample B"

試料B也與試料A同樣設定於洩漏電流測定裝置，測定100個的層疊體的洩漏電流。試料B的情況，從電壓施加最初，100個的層疊體之中，75個短路。一旦慢慢地提高施加電壓，則在0.1MV/cm，全部的層疊體短路。 The sample B was also set in the leakage current measuring device in the same manner as the sample A, and the leakage current of the 100 laminated bodies was measured. In the case of sample B, 75 of the 100 laminates were short-circuited from the initial application of voltage. Once the applied voltage was gradually increased, all of the laminates were short-circuited at 0.1 MV/cm.

分別選擇10個試料A及試料B同矩陣交叉位置的層疊體，攝取各層疊體的SEM照片，觀察其剖面。其結果，試料A的情況，層疊體的下部電極與絕緣膜的界面(1A)及上部電極與絕緣膜的界面(2A)，任一層疊體的情況皆富平滑性光滑，相對的，試料B的情況，層疊體的下部電極與絕緣膜的界面(1B)及上部電極與絕緣膜的界面(2B)，任一層疊體的情況皆缺平滑性，特別是在界面(2B)觀察到大的凹凸。上述那樣的不同被觀察到的主要因素，可推測是因為所使用的合金的組成比的不同及本發明的陽極氧化膜的熱處理的有無。 A laminate of 10 samples A and sample B at the intersection of the matrix and the sample was taken, and an SEM photograph of each laminate was taken, and the cross section was observed. As a result, in the case of the sample A, the interface between the lower electrode and the insulating film of the laminate (1A) and the interface between the upper electrode and the insulating film (2A) were smooth and smooth, and the sample B was relatively smooth. In the case of the interface between the lower electrode and the insulating film of the laminate (1B) and the interface between the upper electrode and the insulating film (2B), the smoothness of any of the laminates is particularly large, especially at the interface (2B). Bump. The main factors observed as described above are presumably due to the difference in the composition ratio of the alloy used and the presence or absence of heat treatment of the anodized film of the present invention.

[實施例1] [Example 1]

按照其次的製造製程及條件，製作以圖1所示的電晶體作為電路構成的一部分之驅動用半導體裝置，裝入市售的LCD面板來使驅動時，確認為達成本發明的目的之良好的半導體裝置。 According to the second manufacturing process and conditions, a semiconductor device having a transistor as shown in FIG. 1 as a part of the circuit configuration was produced, and a commercially available LCD panel was mounted for driving, and it was confirmed that it was excellent in achieving the object of the present invention. Semiconductor device.

在半導體裝置的製作時是利用以下所示的材料，製程條件，驅使在通常的半導體領域使用的成膜技術，光蝕刻微影技術，蝕刻技術，洗淨技術等。所使用的裝置是對市售的裝置施加一部分改良的裝置及自主製作裝置。 At the time of fabrication of a semiconductor device, the following materials and process conditions are used to drive a film formation technique, a photoetching lithography technique, an etching technique, a cleaning technique, and the like which are used in a general semiconductor field. The device used is a partially modified device and an autonomous device that are applied to commercially available devices.

(1)基體：市售的青板玻璃 (1) Base: commercially available blue glass

．基體洗淨：臭氧水洗淨→氫水使用超音波洗淨→洗滌 . Washing the base: Washing with ozone water → Washing with hydrogen water using ultrasonic cleaning → Washing

(2)閘極電極的形成： (2) Formation of gate electrode:

．使用裝置．．．旋轉磁石濺射裝置(簡稱「RMSP裝置」) . Use the device. . . Rotating magnet sputtering device (referred to as "RMSP device")

．靶．．．AlZr(0.1%)合金 . target. . . AlZr (0.1%) alloy

．以RMSP裝置在基體上成膜後，以反應性離子蝕刻((Reactive Ion Etching；簡稱「RIE」)裝置來圖案化(閘極電極長：5μm)。 . After forming a film on the substrate by an RMSP device, it was patterned by a reactive ion etching ("Reactive Ion Etching" ("RIE") device (gate electrode length: 5 μm).

(3)圖案化後的AlZr(0.1%)合金的表面陽極氧化 (3) Surface anodization of patterned AlZr (0.1%) alloy

．電解溶液．．．溶液(1) . Electrolytic solution. . . Solution (1)

．電解條件．．．對向電極Pt(白金)製定電流模式時的電流密度0.2mA/cm2 . Electrolysis conditions. . . The current density when the current mode is set to the counter electrode Pt (platinum) is 0.2 mA/cm 2

．在Pt(白金)製對向電極(Pt)之間的電壓形成45V的 階段切換成定電壓模式。 . The voltage between the counter electrode (Pt) made of Pt (Platinum) forms 45V The phase is switched to a constant voltage mode.

．在電流密度形成，0.1μA/cm2的階段終了陽極氧化。 . At the end of the current density formation, 0.1 μA/cm 2 was anodized.

(4)以超純水來充分洗淨陽極氧化處理後的基體。 (4) The anodized substrate is sufficiently washed with ultrapure water.

(5)在壓力5Torr的N2環境中熱處理洗淨後的基體。熱處理是從室溫慢慢地升溫至300℃，然後將300℃維持2小時。 (5) The washed substrate was heat-treated in an N 2 atmosphere at a pressure of 5 Torr. The heat treatment was slowly raised from room temperature to 300 ° C, and then maintained at 300 ° C for 2 hours.

(6)以以上的工程，在基體上形成閘極電極及閘極絕緣膜的閘極層疊體。 (6) A gate laminated body in which a gate electrode and a gate insulating film are formed on a substrate by the above process.

(7)為了消除閘極層疊體所產生的階差，而以旋轉塗佈法來塗佈聚醯亞胺系的耐熱性樹脂，使固化。 (7) In order to eliminate the step difference generated by the gate laminated body, the polyimide resin-based heat-resistant resin is applied by a spin coating method to be cured.

．以RIE法來除去閘極絕緣膜上的樹脂膜。 . The resin film on the gate insulating film is removed by the RIE method.

(8)半導體層的形成： 使用IGZO的靶(使用混合In2O3粉，Ga2O3粉及ZnO粉的高壓成形者)，以RMSP裝置來將IGZO半導體層形成於前述閘極層疊體上。 (8) Formation of a semiconductor layer: Using an IGZO target (using a mixed In 2 O 3 powder, Ga 2 O 3 powder, and a high-pressure mold of ZnO powder), an IGZO semiconductor layer was formed in the gate stack by an RMSP device. on.

．基體溫度．．．200℃ . Base temperature. . . 200 ° C

．濺射用的氣體．．．．Kr/O2(3%) . Gas for sputtering. . . . Kr/O 2 (3%)

．膜厚．．．40nm . Film thickness. . . 40nm

(9)源極電極．汲極電極的形成 (9) source electrode. Formation of the electrode

．源極電極．．．自半導體層側的順序，LaB6(N：0.4%)膜(膜厚：50nm)/Al膜(膜厚：1μm) . Source electrode. . . From the order of the semiconductor layer side, LaB 6 (N: 0.4%) film (film thickness: 50 nm) / Al film (film thickness: 1 μm)

．汲極電極．．．自半導體層側的順序，Pt膜(膜厚：50nm)/Al膜(膜厚：1μm) . Bungee electrode. . . From the order of the semiconductor layer side, Pt film (film thickness: 50 nm) / Al film (film thickness: 1 μm)

以上，利用圖1~圖3來說明的本發明的實施 形態的合適的幾個例子及該等的變形例皆是MISTr的例子，但本發明並非限於該等的例子，除了該等以外，也適用在MIMSWE，作入半導體基板的電容器及形成於配線基板上的電容器，具有MIM型的配線構造的多層配線基板等，在其構成的一部分具有電氣絕緣膜的電子元件或多層配線基板，具有矩陣配線構造的顯示裝置用基板等。 The implementation of the present invention described above with reference to FIGS. 1 to 3 Several examples of suitable forms and the modifications are examples of MISTr, but the present invention is not limited to these examples, and is also applicable to MIMSWE, a capacitor for forming a semiconductor substrate, and a wiring substrate. The capacitor is a multilayer wiring board having a MIM type wiring structure, and an electronic component or a multilayer wiring board having an electrical insulating film in a part of the capacitor, and a substrate for a display device having a matrix wiring structure.

本發明並非限於上述實施形態，可在不脫離本發明的精神及範圍來實施各種的變更及變形。因此，為了使本發明的範圍公諸於世，而附上以下的請求項。 The present invention is not limited to the embodiments described above, and various modifications and changes can be made without departing from the spirit and scope of the invention. Therefore, in order to make the scope of the present invention public, the following claims are attached.

100‧‧‧MISTr 100‧‧‧MISTr

101‧‧‧基體 101‧‧‧ base

102‧‧‧閘極電極 102‧‧‧gate electrode

103‧‧‧閘極絕緣膜 103‧‧‧Gate insulation film

104‧‧‧半導體層 104‧‧‧Semiconductor layer

105‧‧‧源極電極(部) 105‧‧‧Source electrode (part)

106‧‧‧汲極電極(部) 106‧‧‧汲electrode (part)

107‧‧‧Na擴散防止層 107‧‧‧Na diffusion prevention layer

108‧‧‧耐藥劑性Na擴散防止層 108‧‧‧Drugant-resistant Na diffusion prevention layer

109a、109b‧‧‧平坦化層領域 109a, 109b‧‧‧Development layer area

Claims (4)

一種半導體裝置，係具備電性絕緣膜的半導體裝置，其特徵為：前述絕緣膜係添加鋯0.01~0.15%之鋁合金的陽極氧化膜(但，鋁合金係不含鎂，鈰的至少一個)。 A semiconductor device comprising a semiconductor device comprising an electrically insulating film, wherein the insulating film is an anodized film of an aluminum alloy having a zirconium oxide of 0.01 to 0.15% (however, the aluminum alloy does not contain magnesium or at least one of germanium) . 一種半導體裝置用多層配線基板，係在具備層間絕緣膜的半導體裝置用多層配線基板，其特徵為：前述層間絕緣膜係添加鋯0.01~0.15%之鋁合金的陽極氧化膜(但，鋁合金係不含鎂，鈰的至少一個)。 A multilayer wiring board for a semiconductor device is a multilayer wiring board for a semiconductor device including an interlayer insulating film, characterized in that the interlayer insulating film is an anodized film of an aluminum alloy containing 0.01 to 0.15% of zirconium (however, an aluminum alloy system) Contains no magnesium, at least one of bismuth). 一種MIS型電晶體，係於其體上具有閘極電極，閘極絕緣膜，半導體層，源極電極及汲極電極的MIS型電晶體，其特徵為：前述閘極絕緣膜係添加鋯0.01~0.15%之鋁合金的陽極氧化膜(但，鋁合金係不含鎂，鈰的至少一個)。 A MIS type transistor is a MIS type transistor having a gate electrode, a gate insulating film, a semiconductor layer, a source electrode and a drain electrode, and is characterized in that: the gate insulating film is added with zirconium 0.01 Anodized film of ~0.15% aluminum alloy (however, the aluminum alloy does not contain magnesium, at least one of bismuth). 一種半導體裝置，係具有MIM型構造的半導體裝置，其特徵為：前述MIM型構造的絕緣膜係添加鋯0.01~0.15%之鋁合金的陽極氧化膜(但，鋁合金係不含鎂，鈰的至少一個)。 A semiconductor device having a MIM type structure, characterized in that the insulating film of the MIM type structure is an anodized film of an aluminum alloy having a zirconium of 0.01 to 0.15% (however, the aluminum alloy does not contain magnesium or bismuth). at least one).
TW102141493A 2012-12-28 2013-11-14 Semiconductor device, MIS transistor, and multilayer wiring substrate TW201428940A (en)

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JPS53116087A (en) * 1977-03-22 1978-10-11 Hitachi Ltd Manufacture for multilayer wiring
JPH10133231A (en) * 1996-11-01 1998-05-22 Matsushita Electric Ind Co Ltd Multilayered wiring structure and its production, thin-film transistor array and its production as well as liquid crystal display device
JP3842088B2 (en) * 2000-08-30 2006-11-08 松下電器産業株式会社 LCD screen display
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