TW201428924A - 半導體元件的排列方式及排列方法 - Google Patents

半導體元件的排列方式及排列方法 Download PDF

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TW201428924A
TW201428924A TW102127030A TW102127030A TW201428924A TW 201428924 A TW201428924 A TW 201428924A TW 102127030 A TW102127030 A TW 102127030A TW 102127030 A TW102127030 A TW 102127030A TW 201428924 A TW201428924 A TW 201428924A
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semiconductor
semiconductor elements
semiconductor device
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TWI641104B (zh
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Hsu-Cheng Lin
Ching-Yi Chiu
Pei-Shan Fang
Chun-Chang Chen
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Epistar Corp
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Abstract

一種半導體元件的排列包裝結構，包含：一第一層具有一第一表面及一第二表面；一第二層具有一第一區域及一第二區域；以及複數個半導體元件位於第一層及第二區域之間，其中，第二區域的形狀包含一曲線及一標記。

Description

半導體元件的排列方式及排列方法
本發明係關於半導體元件的排列方式及排列方法。
當運送例如發光二極體或者太陽能電池等半導體元件的時候，半導體元件必須使用分揀設備(Sorter)分類排列成特定的形式以提供其他的設備揀取。傳統上，半導體元件被分類排列成方形的包裝後，以利後續的設備再揀取半導體元件。但是，方形的排列不夠具有經濟效益。
一種半導體元件的排列包裝結構，包含：一第一層具有一第一表面及一第二表面；一第二層具有一第一區域及一第二區域；以及複數個半導體元件位於該第一層及該第二區域之間，其中，該第二區域的形狀包含一曲線及一標記。
1‧‧‧排列包裝結構
1a‧‧‧排列包裝結構
2‧‧‧第一層
21‧‧‧第一表面
22‧‧‧第二表面
23‧‧‧黏性膠層
3‧‧‧配置
3a‧‧‧直徑
3b‧‧‧標記
3c‧‧‧第二平邊
3d,3e‧‧‧曲線
4‧‧‧半導體元件
41‧‧‧第一導電襯墊
42‧‧‧第二導電襯墊
44‧‧‧背面
45‧‧‧上表面
4a‧‧‧空間
4b‧‧‧預定面積
4c‧‧‧最右列
4d‧‧‧方向
5‧‧‧長度
6‧‧‧寬度
7‧‧‧第二層
71‧‧‧第一區域
72‧‧‧第二區域
73‧‧‧第三表面
8‧‧‧區域
9‧‧‧標籤
第1A圖到第1C圖係為複數個半導體元件的排列包裝結構；第2圖係為根據一實施例所示複數個半導體元件的排列包裝結構；
第1A圖顯示複數個半導體元件4的排列包裝結構1。排列包裝結構1包含一第一層2用以盛載複數個半導體元件4，以及一第二層7用以覆蓋複數個半導體元件4以及與第一層2黏著使複數個半導體元件4位於第一層2及第二層7之間。第一層2及第二層7的形狀包含長方形、正方形或圓形。複數個半導體元件4被分揀設備(Sorter)排列形成一配置3，形成一近似圓形或邊數大於四的正多邊形，例如正五角形、正六邊形、正七邊形、正八邊形等。亦即，配置3的周圍為近似圓形或邊數大於四的正多邊形。配置3大約位於排列包裝結構1的中心。在一實施例中，配置3的形狀包含一圓形具有一標記3b，標記3b例如為一平邊，用以使排列包裝結構1在測試設備(Tester)或分揀設備(Sorter)中對齊預定的方向。配置3的中心點到標記3b的最短距離小於配置3的半徑。標記3b亦可以為一凹口或是一記號可實際上打斷一個圓形或者一個正多邊形的連續性、平滑性或規律性。標記3b較佳的是平行於第一層2或者第二層7的其中一邊。如第2圖所示，複數個半導體元 件4依照方向4d逐列地依序排列，其中配置3的最右列4c構成標記3b。另一實施例中，如第2圖所示複數個半導體元件的排列包裝結構1a，當配置3為部份排列，配置3的形狀包含標記3b、一第二平邊3c平行於標記3b、以及兩相對的曲線3d,3e連接標記3b以及第二平邊3c。一標籤9位於第一層2的一角落上。較佳的是標籤9位於第一層2的右上角落，以及標記3b與第一層2的左側邊平行，用以辨認複數個半導體元件4的產品資訊，例如分類碼(bin code)、客戶號碼、晶圓編碼…等。配置3的直徑3a不大於一預設的數值，例如15公分；或者較佳的是不大於7公分。此預設的數值受限於測試、分揀或封裝排列包裝結構1中的複數個半導體元件4的製程或設備。複數個半導體元件4包含從晶圓切割而成的晶片。晶片可為發光二極體晶片、光伏晶片或其他的半導體晶片。當複數個半導體元件4為發光二極體晶片，形成排列包裝結構1的方法包含磊晶形成一半導體發光疊層在一基板晶圓上，處理半導體發光疊層以形成複數個晶片區域以及複數個第一及第二導電接點，黏接半導體發光疊層至一支持元件上，例如藍膜，以及依據複數個晶片區域切割半導體發光疊層以形成獨立的發光二極體晶片，其中每一個發光二極體晶片皆具有第一導電接點及第二導電接點。接著，使用測試設備測試發光二極體晶片。最後，根據測試設備測試的結 果以及預先在分揀設備中設定的分類方式，將發光二極體晶片分類。具有相同分類碼的發光二極體晶片被在排列集合在同一個配置中，例如第1A圖所示的配置3。預先設定的分類方式通常是根據電性或者發光的特性來定義，例如輻射功率、光通量、主波長、發光光譜的半高寬(FWHM)、色溫、演色性指數等。預設的分類方式通常是由製造商或者客戶來定義。測試及分揀製程在本領域中是習知技術，無須在此詳細描述。
第1B圖顯示第1A圖中排列包裝結構1沿AA’虛線的剖面圖。第一層2具有一第一表面21及一第二表面22，其中第一表面21不具黏性。一黏性膠層23形成在第二表面22上。複數個半導體元件4藉由黏性膠層23黏著於第一層2的第二表面22。第一層2可以被擴張為原來面積的兩倍以上。第一層2包含一有彈性的材料或者聚合物，例如聚氯乙烯(Polyvinylchloride,PVC)、聚乙烯(polyethylene,PE)、聚丙烯(Polypropylene,PP)、聚氨酯(polyurethanes,PU)或乙烯-醋酸乙烯共聚物(Poly[ethylene-co-vinylacetate],PEV)其混和物。第一層2較佳的是從一膠帶剪下製成，例如藍膜。第二層7具有一第三表面73面向第一層2。第三表面73包含一第一區域71及一第二區域72。第一區域71藉由黏性膠層23黏著於第一層2的第二表面22。第二區域72覆蓋在複數個半導體元件4上且未與第一層2的第二表面22 相黏。第二層7的與第二區域72和第一層2的第二表面22沒有互相接觸，因此一空間4a形成在任兩個相鄰的半導體元件4之間。第二層7可被輕易地與第二表面22分離而不傷害到第三表面73以及黏性膠層23。第二層7包含離型紙、塑膠膜或玻璃。其中，塑膠膜的材料選自苯並環丁烯(Benezocy-clobutene,BCB)、聚乙烯對苯二甲酸酯(Polyethylene Terephthalate,PET)、聚丙烯(Polypropylene,PP)、高密度聚乙烯(High Density Polyethylene,HDPE)以及低密度聚乙烯(Low Density Polyethylene,LDPE)的其中一種。離型紙的材料較佳地選自超壓光牛皮紙型(Super-calendered Kraft paper,SCK)離型紙、白土塗布紙型(Clay coated Kraft paper,CCK)離型紙、聚乙烯層積型(Polyethylene laminate type)離型紙、格拉辛紙型(Glassine type)離型紙、水性樹脂塗布型(PVA Kraft paper)離型紙以及塑膠薄膜型(Plastic film)離型紙其中一種。在一實施例中，第二層7較佳地為一離型紙。
第1C圖顯示第1A圖中區域8的放大圖。每一個半導體元件4具有一上表面45以及一背面44相對於上表面45，其中一第一導電襯墊41及一第二導電襯墊42形成在上表面45上。背面44藉由黏性膠層23黏附於第一層2的第二表面22。第一導電襯墊41及第二導電襯墊42用於電連接至外部裝置，例如打線連接。半 導體元件4相互對齊，且每一個半導體元件4被放置在第一層22的一預定面積4b，其中預定面積4b具有一長度5及一寬度6。長度5及寬度6皆在50μm及5mm之間，較佳的在100μm及3mm之間。長度5及寬度6的大小是依據半導體元件4的尺寸，長度5與寬度6可以相同或相異。例如，對於配置3具有7公分的直徑3a，當長度5約為1050μm且寬度6約為500μm，在配置3裡可以放置7325個半導體元件4。當長度5約為500μm且寬度6約為500μm，在配置3裡可以放置15384個半導體元件4。當長度5約為800μm且寬度6約為800μm，在配置3裡可以放置6009個半導體元件4。
本發明所列舉之各實施例僅用以說明本發明，並非用以限制本發明之範圍。任何人對本發明所作 之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。
1‧‧‧排列包裝結構
2‧‧‧第一層
3‧‧‧配置
3a‧‧‧直徑
3b‧‧‧標記
4‧‧‧半導體元件
7‧‧‧第二層
8‧‧‧區域
9‧‧‧標籤

Claims (20)

  1. 一種半導體元件的排列裝置，包含：一第一層具有一第一表面及一第二表面；一第二層具有一第一區域及一第二區域；以及複數個半導體元件位於該第一層及該第二區域之間，其中，該第二區域的形狀包含一曲線及一標記。
  2. 如申請專利範圍第1項之半導體元件的排列裝置，其中該些複數個半導體元件包含一發光二極體晶片或一光伏晶片。
  3. 如申請專利範圍第1項之半導體元件的排列裝置，其中該標記包含一平邊。
  4. 如申請專利範圍第1項之半導體元件的排列裝置，更包含一標籤在該第一層的一角落。
  5. 如申請專利範圍第1項之半導體元件的排列裝置，其中該第二區域的形狀為一近似圓形。
  6. 如申請專利範圍第1項之半導體元件的排列裝置，其中該第二區域的形狀上相聚最遠兩點的距離不大於15公分。
  7. 如申請專利範圍第1項之半導體元件的排列裝置，更包含一黏性膠層位於該第一層及該第二層之間。
  8. 如申請專利範圍第7項之半導體元件的排列裝置，其中該些複數個半導體元件黏附於該黏性膠層。
  9. 如申請專利範圍第7項之半導體元件的排列裝置，其中該第一層藉由該黏性膠層黏著於該第二層。
  10. 如申請專利範圍第7項之半導體元件的排列裝置，其中每一個該些複數個半導體元件包含一背面以及一上表面，且該背面黏附於該黏性膠層。
  11. 如申請專利範圍第10項之半導體元件的排列裝置，其中每一 個該些複數個半導體元件更包含一導電襯墊在該上表面上。
  12. 如申請專利範圍第3項之半導體元件的排列裝置，其中該些複數個半導體元件相互對齊。
  13. 如申請專利範圍第12項之半導體元件的排列裝置，其中相鄰兩半導體元件之間的一距離介於50微米及5毫米之間。
  14. 如申請專利範圍第12項之半導體元件的排列裝置，其中該些複數個半導體元件排成一列。
  15. 如申請專利範圍第14項之半導體元件的排列裝置，其中該列平行於該標記。
  16. 如申請專利範圍第1項之半導體元件的排列裝置，其中該第二層的材料包含離型紙、塑膠膜或玻璃。
  17. 如申請專利範圍第1項之半導體元件的排列裝置，其中該第一層可以被擴張為原來面積的兩倍以上。
  18. 一種形成半導體元件的排列裝置的方法，包含下列步驟：提供一第一層包含一黏性膠層；提供複數個半導體元件；依序定位及黏附該些複數個半導體元件到該黏性膠層上；提供一第二層；以及藉由該黏性膠層將該第二層黏著該第一層並覆蓋該些複數個半導體元件以形成一區域，其中該區域的形狀包含一曲線及一標記。
  19. 如申請專利範圍第18之形成半導體元件的排列裝置的方法，其中該些複數個半導體元件被排成一列。
  20. 如申請專利範圍第19之形成半導體元件的排列裝置的方法，其中該些複數個半導體元件被排成複數列，該些複數個半導體元件被一行接一行依序地定位及黏附。
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