CN107644825A - 半导体元件的排列结构 - Google Patents

半导体元件的排列结构 Download PDF

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CN107644825A
CN107644825A CN201710821688.3A CN201710821688A CN107644825A CN 107644825 A CN107644825 A CN 107644825A CN 201710821688 A CN201710821688 A CN 201710821688A CN 107644825 A CN107644825 A CN 107644825A
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semiconductor element
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arrangement architecture
semiconductor
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林徐振
邱静宜
房蓓珊
陈俊昌
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Epistar Corp
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Abstract

本发明提供一种半导体元件的排列结构。半导体元件的排列结构，包含第一层，具有第一表面及第二表面；第二层，具有第一区域及第二区域；以及多个半导体组件，位于该第一层及该第二区域之间，其中，该多个半导体组件相互对齐且相邻两个半导体组件之间的距离介于50微米及5毫米之间，其中该第一层可以被扩张为原来面积的两倍以上。

Description

半导体元件的排列结构
本发明是中国发明专利申请(申请号：201310320164.8，申请日：2013年7月26日，发明名称：半导体元件的排列包装结构及其形成方法)的分案申请。
技术领域
本发明涉及半导体元件的排列包装结构及其形成方法。
背景技术
当运送例如发光二极管或者太阳能电池等半导体元件的时候，半导体元件必须使用分拣设备(Sorter)分类排列成特定的形式以提供其他的设备拣取。传统上，半导体元件被分类排列成方形的包装后，以利后续的设备再拣取半导体元件。但是，方形的排列不够具有经济效益。
发明内容
本发明提供一种半导体元件的排列结构包含第一层，具有第一表面及第二表面；第二层，具有第一区域及第二区域；以及多个半导体组件，位于该第一层及该第二区域之间，其中，该多个半导体组件相互对齐且相邻两个半导体组件之间的距离介于50微米及5毫米之间，其中该第一层可以被扩张为原来面积的两倍以上。
附图说明
图1A到图1C示出了多个半导体元件的排列包装结构；以及
图2示出了根据一实施例的多个半导体元件的排列包装结构。
符号说明
1 排列包装结构 44 背面
1a 排列包装结构 45 上表面
2 第一层 4a 空间
21 第一表面 4b 预定面积
22 第二表面 4c 最右列
23 粘性胶层 4d 方向
3 配置 5 长度
3a 直径 6 宽度
3b 标记 7 第二层
3c 第二平边 71 第一区域
3d,3e 曲线 72 第二区域
4 半导体元件 73 第三表面
41 第一导电衬垫 8 区域
42 第二导电衬垫 9 标签
具体实施方式
图1A显示多个半导体元件4的排列包装结构1。排列包装结构1包含一第一层2用以盛载多个半导体元件4，以及一第二层7用以覆盖多个半导体元件4以及与第一层2粘着使多个半导体元件4位于第一层2及第二层7之间。第一层2及第二层7的形状包含长方形、正方形或圆形。多个半导体元件4被分拣设备(Sorter)排列形成一配置3，形成一近似圆形或边数大于四的正多边形，例如正五角形、正六边形、正七边形、正八边形等。亦即，配置3的周围为近似圆形或边数大于四的正多边形。配置3大约位于排列包装结构1之中心。在一实施例中，配置3的形状包含一圆形具有一标记3b，标记3b例如为一平边，用以使排列包装结构1在测试设备(Tester)或分拣设备(Sorter)中对齐预定的方向。配置3的中心点到标记3b的最短距离小于配置3的半径。标记3b亦可以为一凹口或是一记号可实际上打断一个圆形或者一个正多边形的连续性、平滑性或规律性。标记3b优选的是平行于第一层2或者第二层7的其中一边。如图2所示，多个半导体元件4依照方向4d逐列地依序排列，其中配置3的最右列4c构成标记3b。另一实施例中，如图2所示多个半导体元件的排列包装结构1a，当配置3为部份排列，配置3的形状包含标记3b、第二平边3c平行于标记3b、以及两相对的曲线3d,3e连接标记3b以及第二平边3c。一标签9位于第一层2的一角落上。优选的是标签9位于第一层2的右上角落，以及标记3b与第一层2的左侧边平行，用以辨认多个半导体元件4的产品资讯，例如分类码(bin code)、客户号码、晶片编码…等。配置3的直径3a不大于预设的数值，例如15厘米；或者优选的是不大于7厘米。此预设的数值受限于测试、分拣或封装排列包装结构1中的多个半导体元件4的工艺或设备。多个半导体元件4包含从晶片切割而成的芯片。芯片可为发光二极管芯片、光伏芯片或其他的半导体芯片。当多个半导体元件4为发光二极管芯片，形成排列包装结构1的方法包含外延形成半导体发光叠层在基板晶片上，处理半导体发光叠层以形成多个芯片区域以及多个第一及第二导电接点，粘接半导体发光叠层至一支持元件上，例如蓝膜，以及依据多个芯片区域切割半导体发光叠层以形成独立的发光二极管芯片，其中每一个发光二极管芯片皆具有第一导电接点及第二导电接点。接着，使用测试设备测试发光二极管芯片。最后，根据测试设备测试的结果以及预先在分拣设备中设定的分类方式，将发光二极管芯片分类。具有相同分类码的发光二极管芯片被在排列集合在同一个配置中，例如图1A所示的配置3。预先设定的分类方式通常是根据电性或者发光的特性来定义，例如辐射功率、光通量、主波长、发光光谱的半高宽(FWHM)、色温、演色性指数等。预设的分类方式通常是由制造商或者客户来定义。测试及分拣工艺在本领域中是已知技术，无须在此详细描述。
图1B显示图1A中的排列包装结构1沿AA’虚线的剖面图。第一层2具有第一表面21及第二表面22，其中第一表面21不具黏性。粘性胶层23形成在第二表面22上。多个半导体元件4通过粘性胶层23粘着于第一层2的第二表面22。第一层2可以被扩张为原来面积的两倍以上。第一层2包含一有弹性的材料或者聚合物，例如聚氯乙烯(Polyvinylchloride,PVC)、聚乙烯(polyethylene,PE)、聚丙烯(Polypropylene,PP)、聚氨酯(polyurethanes,PU)或乙烯-醋酸乙烯共聚物(Poly[ethylene-co-vinylacetate],PEV)其混和物。第一层2优选的是从一胶带剪下制成，例如蓝膜。第二层7具有一第三表面73面向第一层2。第三表面73包含一第一区域71及一第二区域72。第一区域71通过粘性胶层23粘着于第一层2的第二表面22。第二区域72覆盖在多个半导体元件4上且未与第一层2的第二表面22相黏。第二层7的与第二区域72和第一层2的第二表面22没有互相接触，因此一空间4a形成在任两个相邻的半导体元件4之间。第二层7可被轻易地与第二表面22分离而不伤害到第三表面73以及粘性胶层23。第二层7包含离型纸、塑胶膜或玻璃。其中，塑胶膜的材料选自苯并环丁烯(Benezocy-clobutene,BCB)、聚乙烯对苯二甲酸酯(Polyethylene Terephthalate,PET)、聚丙烯(Polypropylene,PP)、高密度聚乙烯(High Density Polyethylene,HDPE)以及低密度聚乙烯(Low Density Polyethylene,LDPE)的其中一种。离型纸的材料优选地选自超压光牛皮纸型(Super-calendered Kraft paper,SCK)离型纸、白土涂布纸型(Clay coated Kraftpaper,CCK)离型纸、聚乙烯层积型(Polyethylene laminate type)离型纸、格拉辛纸型(Glassine type)离型纸、水性树脂涂布型(PVA Kraft paper)离型纸以及塑胶薄膜型(Plastic film)离型纸其中一种。在一实施例中，第二层7优选地为一离型纸。
图1C显示图1A中区域8的放大图。每一个半导体元件4具有上表面45以及背面44相对于上表面45，其中一第一导电衬垫41及一第二导电衬垫42形成在上表面45上。背面44通过粘性胶层23粘附于第一层2的第二表面22。第一导电衬垫41及第二导电衬垫42用于电连接至外部装置，例如打线连接。半导体元件4相互对齐，且每一个半导体元件4被放置在第一层22的预定面积4b，其中预定面积4b具有长度5及宽度6。长度5及宽度6皆在50μm及5mm之间，优选的在100μm及3mm之间。长度5及宽度6的大小是依据半导体元件4的尺寸，长度5与宽度6可以相同或相异。例如，对于配置3具有7厘米的直径3a，当长度5约为1050μm且宽度6约为500μm，在配置3里可以放置7325个半导体元件4。当长度5约为500μm且宽度6约为500μm，在配置3里可以放置15384个半导体元件4。当长度5约为800μm且宽度6约为800μm，在配置3里可以放置6009个半导体元件4。
表1.直径7厘米的配置里放置半导体元件的数量vs.不同尺寸的放置区域
本发明所列举的各实施例仅用以说明本发明，并非用以限制本发明的范围。任何人对本发明所作的任何显而易知的修饰或变更皆不脱离本发明的精神与范围。

Claims (10)

1.一种半导体元件的排列结构，包含：
第一层，具有第一表面及第二表面；
第二层，具有第一区域及第二区域；以及
多个半导体组件，位于该第一层及该第二区域之间，
其中，该多个半导体组件相互对齐且相邻两个半导体组件之间的距离介于50微米及5毫米之间，
其中该第一层可以被扩张为原来面积的两倍以上。
2.如权利要求1所述的半导体元件的排列结构，其中该多个半导体组件包含发光二极管芯片或光伏芯片。
3.如权利要求1所述的半导体元件的排列结构，其中该第二区域的形状还包括一标记，且该标记为一平边。
4.如权利要求1所述的半导体元件的排列结构，其中该第二区域的形状为边数大于四的正多边形。
5.如权利要求1所述的半导体元件的排列结构，其中该第二区域的形状上相聚最远两点的距离不大于15厘米。
6.如权利要求1所述的半导体元件的排列结构，还包含：粘性胶层，位于该第一层及该第二层之间，其中该多个半导体组件黏附于该粘性胶层。
7.如权利要求6所述的半导体元件的排列结构，其中该第一层通过该粘性胶层粘着于该第二层。
8.如权利要求6所述的半导体元件的排列结构，其中该多个半导体组件中的每个半导体组件包含背面以及上表面，且该背面黏附于该粘性胶层，该多个半导体组件中的每个半导体组件还包含导电衬垫在该上表面上。
9.如权利要求1所述的半导体元件的排列结构，其中该第二区域的形状包含一曲线。
10.如权利要求1所述的半导体元件的排列结构，其中该第二层的材料包含离型纸。
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