TW201423953A - Chip packaging structure of a plurality of assemblies - Google Patents
Chip packaging structure of a plurality of assemblies Download PDFInfo
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- TW201423953A TW201423953A TW102136207A TW102136207A TW201423953A TW 201423953 A TW201423953 A TW 201423953A TW 102136207 A TW102136207 A TW 102136207A TW 102136207 A TW102136207 A TW 102136207A TW 201423953 A TW201423953 A TW 201423953A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Coils Or Transformers For Communication (AREA)
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Abstract
Description
本發明涉及半導體封裝，尤其涉及一種包括多個組件的晶片封裝結構。 The present invention relates to semiconductor packages, and more particularly to a chip package structure including a plurality of components.
隨著電子元件的小型化，輕量化以及多功能化的需求的增加，對半導體封裝密度的要求越來越高，以來達到縮小封裝體積的效果。因此，多晶片封裝結構已經成為一新的熱點。然而，在多晶片半導體封裝結構中，晶片間的連接方法對半導體封裝的尺寸和性能具有至關重要的影響。 With the miniaturization of electronic components, the demand for lightweight and multi-functionality has increased, the requirements for semiconductor package density have become higher and higher, and the effect of reducing the package volume has been achieved. Therefore, the multi-chip package structure has become a new hot spot. However, in multi-wafer semiconductor package structures, the inter-wafer connection method has a critical impact on the size and performance of the semiconductor package.
圖1所示為採用現有技術的一種多晶片封裝結構的剖面圖。在該實現方式中，下層晶片3和上層晶片5堆疊設置在印刷電路板1上。下層晶片3的一表面透過黏合劑7連接至印刷電路板1的上表面；上層晶片5的一表面透過黏合劑9連接至下層晶片3的另一表面。採用這種實現方式，為了暴露底層晶片3邊緣上的焊墊，上層晶片5的寬度需要小於下層晶片3的寬度。 1 is a cross-sectional view showing a multi-chip package structure using the prior art. In this implementation, the lower wafer 3 and the upper wafer 5 are stacked on the printed circuit board 1. One surface of the lower wafer 3 is connected to the upper surface of the printed circuit board 1 through the adhesive 7; one surface of the upper wafer 5 is bonded to the other surface of the lower wafer 3 via the adhesive 9. With this implementation, in order to expose the pads on the edge of the underlying wafer 3, the width of the upper wafer 5 needs to be smaller than the width of the underlying wafer 3.
底層晶片3上的焊墊和上層晶片5上的焊墊分別透過第一組接合引線11和第二組接合引線15電性連接至印刷 電路板1。因此，第二組接合引線15的高度要大於上層晶片5。這樣，用於封裝第一組接合引線11和第二組接合引線15以及上層晶片5和下層晶片3的塑封殼的厚度會較大。另外，這樣的接合引線由於自身存在電感和/或電阻的干擾，因此影響晶片的高頻性能。 The pads on the underlying wafer 3 and the pads on the upper wafer 5 are electrically connected to the printing through the first set of bonding leads 11 and the second set of bonding leads 15, respectively. Circuit board 1. Therefore, the second set of bonding leads 15 is higher in height than the upper wafer 5. Thus, the thickness of the molded case for encapsulating the first group of bonding wires 11 and the second group bonding wires 15 and the upper wafer 5 and the lower wafer 3 is large. In addition, such a bonding wire affects the high frequency performance of the wafer due to the interference of its own inductance and/or resistance.
有鑒於此，本發明的目的在於提供一種多組件的晶片封裝結構，以解決現有技術中封裝厚度過大，以及封裝結構對晶片性能的不利影響。 In view of this, it is an object of the present invention to provide a multi-component wafer package structure to address the excessive thickness of the package in the prior art and the adverse effects of the package structure on the performance of the wafer.
依據本發明一實施例的多組件的晶片封裝結構，包括，位於底層的第一組件；位於所述第一組件之上的至少一個第二組件；所述第二組件之間相互間隔排列，並且互相不接觸；層疊在所述第二組件之上的至少一個第三組件；每一所述第二組件透過第一組突起結構電性連接至所述第一組件；所述第三組件透過位於所述第二組件的外側的第二組突起結構電性連接至所述第一組件；其中，所述第三組件，所述第一組件和所述第二組突起結構組成一彎折結構。 A multi-component wafer package structure according to an embodiment of the present invention includes: a first component located on a bottom layer; at least one second component located above the first component; the second components are spaced apart from each other, and Not contacting each other; at least one third component stacked on the second component; each of the second components being electrically connected to the first component through a first set of protruding structures; A second set of protrusion structures on an outer side of the second component are electrically connected to the first component; wherein the third component, the first component and the second set of protrusion structures constitute a bent structure.
依據本發明一實施例的晶片封裝結構中，所述第三組件包括第一直線部分和至少一第一彎折部分；所述第一直 線部分位於所述第二組件的上方，並與所述第二組件不接觸；所述第一彎折部分的第一端與所述第一直線部分連接；所述第一彎折部分的第二端透過所述第二組突起結構連接至所述第一組件。 In a chip package structure according to an embodiment of the invention, the third component includes a first straight portion and at least a first bent portion; the first straight a wire portion is located above the second component and is not in contact with the second component; a first end of the first bent portion is coupled to the first straight portion; and a second portion of the first bent portion The end is coupled to the first component through the second set of protrusion structures.
依據本發明另一實施例的晶片封裝結構中，所述第一組件包括第二直線部分和至少一第二彎折部分；所述第二直線部分與所述第一組突起結構連接；所述第二彎折部分的第一端連接至所述第二直線部分；所述第二彎折部分的第二端透過所述第二組突起結構連接至所述第三組件。 In a wafer package structure according to another embodiment of the present invention, the first component includes a second straight portion and at least a second bent portion; the second straight portion is coupled to the first set of protruding structures; A first end of the second bent portion is coupled to the second straight portion; a second end of the second bent portion is coupled to the third assembly through the second set of protruding structures.
進一步的，所述第一組件包括一印刷電路板或者一引線框架。 Further, the first component comprises a printed circuit board or a lead frame.
所述引線框架可以包括多個指狀引腳。 The lead frame may include a plurality of finger pins.
進一步的，所述第二組件包括一晶片。 Further, the second component includes a wafer.
進一步的，所述第三組件包括一晶片或者一磁性元件。 Further, the third component comprises a wafer or a magnetic component.
較佳的，所述第三組件之間以及所述第三組件與所述第二組件之間互相分離，不接觸。 Preferably, the third components and the third component and the second component are separated from each other without contact.
較佳的，所述晶片封裝結構還包括位於所述第二組件和所述第三組件之間，以及所述第三組件之間的黏合層。 Preferably, the chip package structure further includes an adhesive layer between the second component and the third component, and between the third component.
較佳的，所述第一組突起結構和所述第二組突起結構包括凸塊或者焊錫球。 Preferably, the first set of protrusion structures and the second set of protrusion structures comprise bumps or solder balls.
依據本發明實施例的多組件的晶片封裝結構，所有組件都採用倒裝形式的連接方式，位於上層的組件透過彎折部分來實現與底層組件的電性連接，因此晶片封裝結構的 厚度大大减小，避免了接合引線的連接方式給晶片性能帶來的負面影響，不僅具有很好的機械穩定性，同時也具有很好的電氣穩定性。 According to the multi-component chip package structure of the embodiment of the present invention, all components are connected in a flip-chip manner, and the components in the upper layer are electrically connected to the underlying component through the bent portion, and thus the chip package structure is The thickness is greatly reduced, which avoids the negative influence of the connection manner of the bonding wires on the performance of the wafer, and not only has good mechanical stability, but also has good electrical stability.
另外，對磁性元件而言，如電感等，其體積一般都較大，採用依據本發明的層疊式的多組件的晶片封裝結構，將電感和晶片封裝於一單一的封裝結構中，可以容納更大體積，電感值更大的電感，更有利於系統的高集成化和小體積化。 In addition, for a magnetic component, such as an inductor, the volume thereof is generally large, and the stacked multi-component chip package structure according to the present invention is used to package the inductor and the chip in a single package structure, and can accommodate more. Large-volume, larger inductance inductors are more conducive to high integration and small size of the system.
1‧‧‧印刷電路板 1‧‧‧Printed circuit board
3‧‧‧下層晶片 3‧‧‧Under wafer
5‧‧‧上層晶片 5‧‧‧Upper wafer
7‧‧‧黏合劑 7‧‧‧Binder
9‧‧‧黏合劑 9‧‧‧Binder
11‧‧‧第一組接合引線 11‧‧‧First set of bonding leads
15‧‧‧第二組接合引線 15‧‧‧Second set of bonding leads
200‧‧‧晶片封裝結構 200‧‧‧ Chip package structure
201‧‧‧印刷電路板 201‧‧‧Printed circuit board
202‧‧‧焊錫球 202‧‧‧ solder balls
203‧‧‧焊錫球 203‧‧‧ solder balls
204‧‧‧晶片 204‧‧‧ wafer
205‧‧‧晶片 205‧‧‧ wafer
205-1‧‧‧第一直線部分 205-1‧‧‧First straight line
205-2‧‧‧第一彎折部分 205-2‧‧‧First bend
206‧‧‧黏合層 206‧‧‧Adhesive layer
207‧‧‧電感 207‧‧‧Inductance
207-1‧‧‧第一直線部分 207-1‧‧‧First straight line
207-2‧‧‧第一彎折部分 207-2‧‧‧First bend
300‧‧‧晶片封裝結構 300‧‧‧ Chip package structure
301‧‧‧引線框架 301‧‧‧ lead frame
301-1‧‧‧第二直線部分 301-1‧‧‧Second straight part
301-2‧‧‧第二彎折部分 301-2‧‧‧Second bend
302‧‧‧凸塊 302‧‧‧Bumps
303‧‧‧凸塊 303‧‧‧Bumps
304‧‧‧晶片 304‧‧‧ wafer
305‧‧‧黏合層 305‧‧‧Adhesive layer
306‧‧‧電感 306‧‧‧Inductance
圖1所示為採用現有技術的一種多晶片封裝結構的剖面圖；圖2所示為依據本發明實施例1的多組件的晶片封裝結構的剖面圖；圖3所示為依據本發明實施例2的多組件的晶片封裝結構的剖面圖。 1 is a cross-sectional view showing a multi-chip package structure using a prior art; FIG. 2 is a cross-sectional view showing a multi-package chip package structure according to Embodiment 1 of the present invention; and FIG. 3 is a view showing an embodiment of the present invention. A cross-sectional view of a multi-component wafer package structure of 2.
以下結合圖式對本發明的幾個較佳的實施例進行詳細描述，但本發明並不僅僅限於這些實施例。本發明涵蓋任何在本發明的精髓和範圍上做的替代、修改、等效方法以及方案。為了使公眾對本發明有徹底的瞭解，在以下本發明較佳的實施例中詳細說明了具體的細節，而對本領域具有通常知識者來說沒有這些細節的描述也可以完全理解本 發明。 Several preferred embodiments of the present invention are described in detail below with reference to the drawings, but the invention is not limited to the embodiments. The present invention encompasses any alternatives, modifications, equivalents and alternatives to the spirit and scope of the invention. In order to provide a thorough understanding of the present invention, the specific details are described in detail in the preferred embodiments of the present invention, and those of ordinary skill in the art invention.
參考圖2，所示為依據本發明實施例1的多組件的晶片封裝結構的剖面圖。在該實施例中，多組件的晶片封裝結構200包括位於底層的印刷電路板201(第一組件)，位於印刷電路板201之上的晶片204(第二組件)，以及層疊在晶片204之上的晶片205和電感207(第三組件)。在此，晶片204，晶片205和電感207之間相互間隔，互不接觸，以實現良好的電氣隔離。晶片204透過一組焊錫球202(第一連接結構)電性連接至印刷電路板201；晶片205和電感207透過一組位於晶片204外側的另一組焊錫球203電性連接至印刷電路板201。 Referring to FIG. 2, there is shown a cross-sectional view of a multi-component wafer package structure in accordance with Embodiment 1 of the present invention. In this embodiment, the multi-component wafer package structure 200 includes a printed circuit board 201 (first component) on the bottom layer, a wafer 204 (second component) on the printed circuit board 201, and a laminate on the wafer 204. Wafer 205 and inductor 207 (third component). Here, the wafer 204, the wafer 205 and the inductor 207 are spaced apart from each other and do not contact each other to achieve good electrical isolation. The wafer 204 is electrically connected to the printed circuit board 201 through a set of solder balls 202 (first connection structure); the wafer 205 and the inductor 207 are electrically connected to the printed circuit board 201 through a set of another solder balls 203 located outside the wafer 204. .
具體的，晶片205包括一第一直線部分205-1和兩個第一彎折部分205-2；第一直線部分205-1位於晶片204的上方，第一彎折部分205-2位於晶片204的兩側，第一彎折部分205-2的一端與第一直線部分205-1連接，另一端透過焊錫球203連接至印刷電路板201。類似的，電感207包括第一直線部分207-1和兩個第一彎折部分207-2；第一直線部分207-1位於晶片205的第一直線部分205-1的上方，第一彎折部分207-2位於晶片205的第一彎折部分的兩側，第一彎折部分207-2的一端與第一直線部分207-1連接，另一端透過焊錫球203連接至印刷電路板201。 Specifically, the wafer 205 includes a first straight portion 205-1 and two first bent portions 205-2; the first straight portion 205-1 is located above the wafer 204, and the first bent portion 205-2 is located at two of the wafer 204. On the side, one end of the first bent portion 205-2 is connected to the first straight portion 205-1, and the other end is connected to the printed circuit board 201 through the solder ball 203. Similarly, the inductor 207 includes a first straight portion 207-1 and two first bent portions 207-2; the first straight portion 207-1 is located above the first straight portion 205-1 of the wafer 205, and the first bent portion 207- 2 is located on both sides of the first bent portion of the wafer 205. One end of the first bent portion 207-2 is connected to the first straight portion 207-1, and the other end is connected to the printed circuit board 201 through the solder ball 203.
晶片205，印刷電路板201和焊錫球203組成一彎折機構。在該實施例中，透過第三組件(晶片205和電感207)的彎折部分，不僅可以實現與印刷電路板的電性連接，另一方面，與印刷電路板一起也實現了對第三組件的機械支撑作用。為了更好的實現不同組件之間的隔離以及晶片封裝結構的穩定性，在該實施例中，晶片封裝結構200還包括位於晶片204、晶片205和電感207之間的黏合層206，來更好的固定三者之間的位置，以及使整個晶片封裝結構的牢固性更強。 The wafer 205, the printed circuit board 201 and the solder balls 203 constitute a bending mechanism. In this embodiment, through the bent portion of the third component (the wafer 205 and the inductor 207), not only the electrical connection with the printed circuit board but also the third component can be realized together with the printed circuit board. Mechanical support. In order to better achieve the isolation between different components and the stability of the chip package structure, in this embodiment, the chip package structure 200 further includes an adhesive layer 206 between the wafer 204, the wafer 205 and the inductor 207, which is better. The position between the fixed three and the firmness of the entire chip package structure is stronger.
透過對依據本發明實施例的多組件的晶片封裝結構200的詳細說明，本領域具有通常知識者可以得知，位於第一組件(印刷電路板201)之上的第二組件(晶片204)的數目可以不限於一個，可以為多個，多個第二組件之間相互間隔，互不接觸，依次排列於第一組件之上。第三組件覆蓋所有第二組件區域，位於所有第二組件的上方。位於底層的第一組件也可以替換為包括多個引腳的引線框架，不同組件上的電極性透過第一連接結構或者第二連接結構連接至引線框架的相應引腳，從而使引腳具有相應的電極性。 Through a detailed description of a multi-component wafer package structure 200 in accordance with an embodiment of the present invention, one of ordinary skill in the art will recognize that the second component (wafer 204) is located above the first component (printed circuit board 201). The number may not be limited to one, and may be multiple, and the plurality of second components are spaced apart from each other, and are not in contact with each other, and are sequentially arranged on the first component. The third component covers all of the second component areas, above all of the second components. The first component on the bottom layer can also be replaced by a lead frame including a plurality of pins, and the polarity on the different components is connected to the corresponding pins of the lead frame through the first connection structure or the second connection structure, so that the pins have corresponding Electrode.
採用圖2所示的多組件的晶片封裝結構，所有組件都採用倒裝形式的連接方式，位於上層的組件透過彎折部分來實現與底層組件的電性連接，因此晶片封裝結構的厚度大大减小，避免了接合引線的連接方式給晶片性能帶來的負面影響，不僅具有很好的機械穩定性，同時也具有很好 的電氣穩定性。 Using the multi-component chip package structure shown in FIG. 2, all components are connected in a flip-chip manner, and the components in the upper layer are electrically connected to the underlying components through the bent portion, so that the thickness of the chip package structure is greatly reduced. Small, avoiding the negative impact of the connection of the bonding leads on the performance of the wafer, not only has good mechanical stability, but also has good Electrical stability.
另外，對磁性元件而言，如電感等，其體積一般都較大，當採用圖2所示的多組件的晶片封裝結構時，採用層疊式的封裝結構，將電感和晶片封裝於一單一的封裝結構中，可以容納更大體積，電感值更大的電感，更有利於系統的高集成化和小體積化。 In addition, for magnetic components, such as inductors, the volume is generally large. When the multi-component chip package structure shown in FIG. 2 is used, the stacked package structure is used to package the inductor and the chip in a single package. In the package structure, it can accommodate larger inductors with larger inductance values, which is more conducive to high integration and small size of the system.
參考圖3，所示為依據本發明實施例2的多組件的晶片封裝結構的剖面圖。在該實施例中，多組件的晶片封裝結構300包括位於底層的引線框架301(第一組件)，位於引線框架301之上的晶片304(第二組件)，以及層疊在晶片304之上的電感306(第三組件)。其中，晶片304透過一組凸塊302(第一連接結構)連接至引線框架301。 Referring to FIG. 3, there is shown a cross-sectional view of a multi-component wafer package structure in accordance with Embodiment 2 of the present invention. In this embodiment, the multi-component wafer package structure 300 includes a lead frame 301 (first component) on the bottom layer, a wafer 304 (second component) over the lead frame 301, and an inductor stacked on the wafer 304. 306 (third component). The wafer 304 is connected to the lead frame 301 through a set of bumps 302 (first connection structure).
位於上層的電感306與引線框架301之間的連接透過以下連接方式實現：引線框架301設置為成彎折形狀，其包括第二直線部分301-1和第二彎折部分301-2；第二彎折部分301-2位於晶片304的外側區域，並與晶片304分離，其第一端與第二直線部分301-1連接，另一端透過凸塊303與電感306實現電性連接。引線框架301，電感306和凸塊303組成一彎折結構。 The connection between the upper layer of the inductor 306 and the lead frame 301 is achieved by the following connection: the lead frame 301 is disposed in a bent shape including the second straight portion 301-1 and the second bent portion 301-2; The bent portion 301-2 is located in the outer region of the wafer 304 and is separated from the wafer 304. The first end is connected to the second straight portion 301-1, and the other end is electrically connected to the inductor 306 through the bump 303. The lead frame 301, the inductor 306 and the bump 303 constitute a bent structure.
電感306和晶片304相互分離，互不接觸，以實現相 互之間的電氣隔離。透過第一組件(引線框架301)的彎折部分，不僅可以實現與位於上層的第三組件之間的電性連接，另一方面，也實現了對第三組件的機械支撑作用。在該實施例中，晶片封裝結構300還包括位於晶片304和電感306之間的黏合層305，來更好的固定三者之間的位置，以及使整個晶片封裝結構的牢固性更強。不同組件上的電極性透過第一連接結構或者第二連接結構連接至引線框架的相應引腳，從而使引腳具有相應的電極性。 The inductor 306 and the wafer 304 are separated from each other without contacting each other to achieve phase Electrical isolation between each other. Through the bent portion of the first component (lead frame 301), not only the electrical connection with the third component located on the upper layer but also the mechanical support of the third component is achieved. In this embodiment, the die package structure 300 further includes an adhesive layer 305 between the wafer 304 and the inductor 306 to better secure the position between the three and to make the overall chip package structure more robust. The polarity of the electrodes on the different components is connected to the corresponding pins of the lead frame through the first connection structure or the second connection structure, so that the pins have corresponding polarity.
採用圖2所示的多組件的晶片封裝結構，所有組件都採用倒裝形式的連接方式，位於底層的組件透過彎折部分來實現與上層組件的電性連接，因此晶片封裝結構的厚度大大减小，避免了接合引線的連接方式給晶片性能帶來的負面影響，不僅具有很好的機械穩定性，同時也具有很好的電氣穩定性。 Using the multi-component chip package structure shown in FIG. 2, all components are connected in a flip-chip manner, and the underlying components are electrically connected to the upper layer components through the bent portions, so that the thickness of the chip package structure is greatly reduced. Small, avoiding the negative impact of the bonding mode of the bonding leads on the performance of the wafer, not only has good mechanical stability, but also has good electrical stability.
另外，對磁性元件而言，採用層疊式的封裝結構，將電感和晶片封裝於一單一的封裝結構中，可以容納更大體積，電感值更大的電感，更有利於系統的高集成化和小體積化。 In addition, for the magnetic component, the laminated package structure is used to package the inductor and the chip in a single package structure, which can accommodate a larger volume and a larger inductance, which is more conducive to the high integration of the system. Small size.
另外，還需要說明的是，在本文中，諸如第一和第二等之類的關係術語僅僅用來將一個實體或者操作與另一個實體或操作區分開來，而不一定要求或者暗示這些實體或操作之間存在任何這種實際的關係或者順序。而且，術語“包括”、“包含”或者其任何其他變體意在涵蓋非排他性的包含，從而使得包括一系列要素的過程、方法、物品或者 設備不僅包括那些要素，而且還包括沒有明確列出的其他要素，或者是還包括為這種過程、方法、物品或者設備所固有的要素。在沒有更多限制的情况下，由語句“包括一個……”限定的要素，並不排除在包括所述要素的過程、方法、物品或者設備中還存在另外的相同要素。 In addition, it should also be noted that in this context, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities. There is any such actual relationship or order between operations. Furthermore, the terms "include", "comprise," or "include" or "the" or "the" Equipment includes not only those elements, but also other elements that are not explicitly listed, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.
依照本發明的實施例如上文所述，這些實施例並沒有詳盡敘述所有的細節，也不限制該發明僅為所述的具體實施例。顯然，根據以上描述，可作很多的修改和變化。本說明書選取並具體描述這些實施例，是為了更好地解釋本發明的原理和實際應用，從而使所屬技術領域具有通常知識者能很好地利用本發明以及在本發明基礎上的修改使用。本發明僅受申請專利範圍及其全部範圍和等效物的限制。 The embodiments in accordance with the present invention are not described in detail, and are not intended to limit the invention. Obviously, many modifications and variations are possible in light of the above description. The present invention has been chosen and described in detail to explain the embodiments of the invention and the embodiments of the invention. The invention is limited only by the scope of the claims and the full scope and equivalents thereof.
300‧‧‧晶片封裝結構 300‧‧‧ Chip package structure
301‧‧‧引線框架 301‧‧‧ lead frame
301-1‧‧‧第二直線部分 301-1‧‧‧Second straight part
301-2‧‧‧第二彎折部分 301-2‧‧‧Second bend
302‧‧‧凸塊 302‧‧‧Bumps
303‧‧‧凸塊 303‧‧‧Bumps
304‧‧‧晶片 304‧‧‧ wafer
305‧‧‧黏合層 305‧‧‧Adhesive layer
306‧‧‧電感 306‧‧‧Inductance
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| CN103400819B (en) * | 2013-08-14 | 2017-07-07 | 矽力杰半导体技术(杭州)有限公司 | A kind of lead frame and its preparation method and application its encapsulating structure |
| CN103531560A (en) | 2013-10-31 | 2014-01-22 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure and manufacturing method thereof |
| CN103633056B (en) | 2013-12-06 | 2017-09-01 | 矽力杰半导体技术(杭州)有限公司 | Lead frame, package assembling and its manufacture method |
| JP6314731B2 (en) * | 2014-08-01 | 2018-04-25 | 株式会社ソシオネクスト | Semiconductor device and manufacturing method of semiconductor device |
| CN104269385B (en) | 2014-10-21 | 2017-12-19 | 矽力杰半导体技术(杭州)有限公司 | Package assembling and its manufacture method |
| CN105609231A (en) * | 2015-12-24 | 2016-05-25 | 合肥祖安投资合伙企业(有限合伙) | Laminated inductor and manufacturing method therefor and lamination packaging assembly |
| US10199361B2 (en) * | 2016-01-29 | 2019-02-05 | Cyntec Co., Ltd. | Stacked electronic structure |
| CN106057778B (en) | 2016-05-27 | 2018-11-30 | 矽力杰半导体技术(杭州)有限公司 | Encapsulating structure and its manufacturing method |
| CN107808879A (en) | 2017-11-20 | 2018-03-16 | 深圳顺络电子股份有限公司 | A kind of Switching Power Supply module and its method for packing |
| CN109712948A (en) * | 2019-01-24 | 2019-05-03 | 广东气派科技有限公司 | A kind of chip-packaging structure of integrated passive device |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6741494B2 (en) * | 1995-04-21 | 2004-05-25 | Mark B. Johnson | Magnetoelectronic memory element with inductively coupled write wires |
| JP2001077293A (en) * | 1999-09-02 | 2001-03-23 | Nec Corp | Semiconductor device |
| TW429493B (en) * | 1999-10-29 | 2001-04-11 | Huang Jr Gung | Thin type flip chip package |
| KR20050001159A (en) * | 2003-06-27 | 2005-01-06 | 삼성전자주식회사 | Multi-chip package having a plurality of flip chips and fabrication method thereof |
| US7180165B2 (en) * | 2003-09-05 | 2007-02-20 | Sanmina, Sci Corporation | Stackable electronic assembly |
| TWI223879B (en) * | 2003-10-07 | 2004-11-11 | Advanced Semiconductor Eng | Package stack module with vertical conductive wires inside molding compound |
| TWI237882B (en) * | 2004-05-11 | 2005-08-11 | Via Tech Inc | Stacked multi-chip package |
| JP2005353911A (en) * | 2004-06-11 | 2005-12-22 | Toshiba Corp | Semiconductor device |
| TWI304644B (en) * | 2004-11-29 | 2008-12-21 | Advanced Semiconductor Eng | A stack of flip chip packages |
| KR100668857B1 (en) * | 2005-07-07 | 2007-01-16 | 주식회사 하이닉스반도체 | Stack type package |
| US7816769B2 (en) * | 2006-08-28 | 2010-10-19 | Atmel Corporation | Stackable packages for three-dimensional packaging of semiconductor dice |
| US7960997B2 (en) * | 2007-08-08 | 2011-06-14 | Advanced Analogic Technologies, Inc. | Cascode current sensor for discrete power semiconductor devices |
| CN101241904A (en) * | 2008-02-20 | 2008-08-13 | 日月光半导体制造股份有限公司 | Square flat non-connection pin multi-chip encapsulation structure |
| JP2009302212A (en) | 2008-06-11 | 2009-12-24 | Fujitsu Microelectronics Ltd | Semiconductor device and method of manufacturing the same |
| CN101615609A (en) * | 2008-06-27 | 2009-12-30 | 陈石矶 | The stacked structure of Chip Packaging |
| US7843047B2 (en) * | 2008-11-21 | 2010-11-30 | Stats Chippac Ltd. | Encapsulant interposer system with integrated passive devices and manufacturing method therefor |
| TWI377662B (en) * | 2008-12-24 | 2012-11-21 | Powertech Technology Inc | Multiple flip-chip package |
| TWI581384B (en) * | 2009-12-07 | 2017-05-01 | 英特希爾美國公司 | Stacked inductor-electronic package assembly and technique for manufacturing same |
| TWI445103B (en) * | 2010-08-19 | 2014-07-11 | Cyntec Co Ltd | Electronic package structure and method for making the same |
| WO2012107972A1 (en) * | 2011-02-10 | 2012-08-16 | パナソニック株式会社 | Semiconductor device |
| EP2482312A4 (en) * | 2011-04-29 | 2012-09-26 | Huawei Tech Co Ltd | Power supply module and packaging and integrating method thereof |
| US8749056B2 (en) * | 2011-05-26 | 2014-06-10 | Infineon Technologies Ag | Module and method of manufacturing a module |
| CN102738131B (en) * | 2012-03-07 | 2016-02-24 | 苏州晶方半导体科技股份有限公司 | Semiconductor module, encapsulating structure and method for packing thereof |
-
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