TW201407173A - Through impedance standard substrate and manufacture method thereof - Google Patents

Through impedance standard substrate and manufacture method thereof Download PDF

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Publication number
TW201407173A
TW201407173A TW101127677A TW101127677A TW201407173A TW 201407173 A TW201407173 A TW 201407173A TW 101127677 A TW101127677 A TW 101127677A TW 101127677 A TW101127677 A TW 101127677A TW 201407173 A TW201407173 A TW 201407173A
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Taiwan
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conductor
needle
outer panel
window
protection device
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TW101127677A
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Chinese (zh)
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song-mao Wu
rong-shu Huang
Wen-Yi Ruan
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Nat Univ Kaohsiung
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Abstract

The present invention relates to a through impedance standard substrate and a manufacture method thereof, being, respectively, provided with a first outer plate and a second outer plate on upper and lower surfaces of a conductor. The upper surface of the conductor has a first probing area. A first window is formed on the first outer plate at a location corresponding to the first probing area to expose the first probing area. The lower surface of the conductor has a second probing area. A second window is formed on the second outer plate at a location corresponding to the second probing area to expose the second probing area. Because the first and second probing areas are, respectively, located on opposing surfaces of the through impedance standard substrate, after a probe performs a calibration process via the through impedance standard substrate, a chip with signal connection ports on both sides may be directly measured so as to obtain good measurement accuracy.

Description

直通阻抗標準基板及其製法 Through-impedance standard substrate and its preparation method

本發明是一種阻抗標準基板及其製法,特別是指直通阻抗標準基板及其製法。 The invention relates to an impedance standard substrate and a preparation method thereof, in particular to a through-impedance standard substrate and a preparation method thereof.

向量網路分析儀是一種量測儀器,藉由向量網路分析儀量測待測晶片對功率直通係數(Transmitted Coefficient)及反射係數(Reflected Coefficient)之響應,用以評估待測晶片之高頻電氣特性。 The vector network analyzer is a measuring instrument that measures the response of the wafer to be tested to the Transmitted Coefficient and the Reflected Coefficient by a vector network analyzer to evaluate the high frequency of the wafer to be tested. Electrical characteristics.

在使用向量網路分析儀之前,須對向量網路分析儀本身的測試治具進行誤差校正,當測試治具的誤差被校正後,在進行量測待測晶片時,得以獲得較準確的量測結果。其中該些誤差係藉由量測阻抗標準基板(Impedance Standard Substrate,ISS)的阻抗特性而決定,阻抗標準基板包含有短路(Short circuit)基板、負載(Load circuit)基板、斷路(Open circuit)基板與直通(Through circuit)基板等四類。 Before using the vector network analyzer, the error correction of the test fixture of the vector network analyzer itself must be performed. When the error of the test fixture is corrected, a more accurate amount can be obtained when measuring the wafer to be tested. Test results. The errors are determined by measuring impedance characteristics of an Impedance Standard Substrate (ISS), and the impedance standard substrate includes a short circuit substrate, a load circuit substrate, and an open circuit substrate. There are four types, such as a through circuit substrate.

以直通基板為例,主要包含有一板體、一第一電極與一第二電極,該第一電極與第二電極設於該板體的同一表面。 For example, the through-substrate includes a plate body, a first electrode and a second electrode. The first electrode and the second electrode are disposed on the same surface of the plate body.

向量網路分析儀的測試治具包含有一第一探針與一第二探針,當利用所述直通基板進行校正作業時,該第一探針係電連接該第一電極,而第二探針電連接該第二電極,測試治具可產生檢測信號以量測該第一電極與第二電極之間的阻抗,並根據所量測到的阻抗做為校正的基準;當測 試治具進行校正之後,即可對晶片進行量測。 The test fixture of the vector network analyzer includes a first probe and a second probe. When the calibration operation is performed by using the through substrate, the first probe is electrically connected to the first electrode, and the second probe is electrically connected to the first electrode. The needle is electrically connected to the second electrode, and the test fixture generates a detection signal to measure the impedance between the first electrode and the second electrode, and uses the measured impedance as a reference for correction; After the test fixture is calibrated, the wafer can be measured.

隨著積體電路技術演進,系統電路的微型化、系統級構裝(System in Pack,SiP)及三維晶片穿孔(Through Silicon Via,TSV)等各種技術皆蓬勃發展,致使晶片的信號連接埠(I/O Port)位置不限制在單一表面,例如信號連接埠有可能分別位於待測晶片的相對上、下表面。 With the evolution of integrated circuit technology, various technologies such as miniaturization of system circuits, System in Pack (SiP), and Through Silicon Via (TSV) have flourished, resulting in a signal connection between the wafers ( The I/O Port) position is not limited to a single surface, for example, signal connections may be located on opposite upper and lower surfaces of the wafer to be tested, respectively.

如此一來,當探針先透過直通基板進行校正後,再正式對晶片進行量測時,其中一個探針必須翻轉移動到晶片的另一表面,才可以電連接到另一表面的信號連接埠。惟如此翻轉移動的過程涉及複雜的機構,且由於已知測試治具的校正作業是基於形成在板體同一表面的電極,而待測晶片的信號連接埠卻是分別位在不同表面,因此前述的校正值並不適用在待測晶片,進而影響晶片量測的精確度。 In this way, when the probe is first calibrated through the through-substrate, and then the wafer is officially measured, one of the probes must be flipped over to the other surface of the wafer before the signal connection can be electrically connected to the other surface. . However, the process of flipping the movement involves a complicated mechanism, and since the calibration work of the known test fixture is based on the electrodes formed on the same surface of the board, the signal connections of the wafer to be tested are respectively located on different surfaces, so the foregoing The correction value does not apply to the wafer to be tested, which in turn affects the accuracy of wafer measurement.

本發明的主要目的是提供一種直通阻抗標準基板,該直通基板的相對表面分別設有電極,以利測試治具進行校正與檢測作業。 The main object of the present invention is to provide a through-impedance standard substrate, and the opposite surfaces of the through-substrate are respectively provided with electrodes for the test fixture to perform calibration and detection operations.

為達前揭目的,本發明所採用的技術手段是令該直通阻抗標準基板包含有:一導電體,其上表面定義有一第一針測區,其下表面定義有一第二針測區;一第一外板,以一第一黏著層固接於該導電體的上表面,且對應該第一針測區的區域形成一第一窗口,該第一針測區外露於該第一窗口中;以及一第二外板,以一第二黏著層固接於該導電體的下表 面,且對應該第二針測區的區域形成一第二窗口,該第二針測區外露於該第二窗口中。 For the purpose of the prior art, the technical means adopted by the present invention is that the through-impedance standard substrate comprises: an electric conductor having a first needle measuring area defined on the upper surface and a second needle measuring area on the lower surface; The first outer panel is fixed to the upper surface of the electric conductor by a first adhesive layer, and a first window is formed in a region corresponding to the first needle measuring area, and the first needle measuring area is exposed in the first window And a second outer panel fixed to the lower surface of the electrical conductor by a second adhesive layer And a region corresponding to the second needle measuring area forms a second window, and the second needle measuring area is exposed in the second window.

為達前揭目的,本發明所採用的技術手段是令該直通阻抗標準基板的製法包含以下步驟:準備一基板,在該基板表面形成一導電體,該導電體的上表面定義一第一針測區;設置一第一保護裝置於該導電體的第一針測區上,使該第一保護裝置覆蓋該第一針測區;設置一第一外板於該導電體的上表面,其中該第一外板具有一第一窗口供穿設該第一保護裝置;移除該第一保護裝置,使該第一針測區外露於該第一窗口;移除該基板以外露該導電體的下表面,該導電體的下表面定義一第二針測區;設置一第二保護裝置於該導電體的第二針測區上,使該第二保護裝置覆蓋該第二針測區;設置一第二外板於該導電體的下表面,其中該第二外板具有一第二窗口供穿設該第二保護裝置;以及移除該第二保護裝置,以完成直通阻抗標準基板。 For the purpose of the prior art, the technical method adopted by the present invention is that the method for manufacturing the through-impedance standard substrate comprises the steps of: preparing a substrate, forming a conductor on the surface of the substrate, the upper surface of the conductor defining a first pin a first protection device is disposed on the first needle measurement area of the electrical conductor, so that the first protection device covers the first needle measurement area; and a first outer plate is disposed on the upper surface of the electrical conductor, wherein The first outer panel has a first window for penetrating the first protection device; the first protection device is removed to expose the first needle measurement region to the first window; and the substrate is removed to expose the electrical conductor The lower surface of the conductor defines a second needle measurement area; a second protection device is disposed on the second needle measurement area of the conductor, so that the second protection device covers the second needle measurement area; A second outer panel is disposed on the lower surface of the electrical conductor, wherein the second outer panel has a second window for penetrating the second protection device; and the second protection device is removed to complete the through-impedance standard substrate.

根據本發明直通阻抗校正基板的結構,該直通阻抗標準基板的上表面與下表面分別具有針測區,當探針利用該直通阻抗標準基板進行校正作業時,探針已分別位在直通阻抗標準基板的上、下表面,以分別電連接第一針測區與第二針測區;當探針進行校正完畢後,該些探針不需要再透過複雜的翻轉移動,即可直接檢測晶片上的信號連接 埠,有效提升晶片的量測品質。 According to the structure of the through-impedance correcting substrate of the present invention, the upper surface and the lower surface of the through-impedance standard substrate respectively have a needle measuring area, and when the probe performs the correcting operation using the through-impedance standard substrate, the probes are respectively positioned in the through-impedance standard The upper and lower surfaces of the substrate are electrically connected to the first needle measuring area and the second needle measuring area respectively; after the probe is corrected, the probes can be directly detected on the wafer without further complicated flipping movement Signal connection 埠, effectively improve the measurement quality of the wafer.

此外,本發明的製法係相容於現有的印刷電路板製程,係有易於實施的優點。 In addition, the method of the present invention is compatible with existing printed circuit board processes and has the advantage of being easy to implement.

請參考圖1所示,於進行本發明的製法時,首先準備一基板12,該基板12的表面形成一導電體13,該導電體13可為導線或導電片,導電體13具有相對的一第一端部與一第二端部,該第一端部的上表面定義有一供探針接觸的第一針測區14。 Referring to FIG. 1 , in the process of the present invention, a substrate 12 is first prepared, and a surface of the substrate 12 is formed with a conductor 13 , which may be a wire or a conductive sheet, and the conductor 13 has an opposite one. The first end portion and a second end portion define an upper surface of the first needle portion 14 for contacting the probe.

請參考圖2所示,於該導電體13的第一針測區14上設置一第一保護裝置15,使第一保護裝置15覆蓋該第一針測區14,該第一保護裝置15可為一柱狀體,其材質不限為導體或絕緣體。接著於導電體13的上表面形成一第一黏著層16,因第一保護裝置15已設在第一針測區14之上,因此第一黏著層16不會附著在第一針測區14的表面。 As shown in FIG. 2, a first protection device 15 is disposed on the first pin measurement area 14 of the electrical conductor 13, so that the first protection device 15 covers the first needle measurement area 14, and the first protection device 15 can be As a columnar body, the material is not limited to a conductor or an insulator. Then, a first adhesive layer 16 is formed on the upper surface of the electrical conductor 13 . Since the first protection device 15 is disposed on the first needle measurement region 14 , the first adhesive layer 16 does not adhere to the first needle measurement region 14 . s surface.

請參考圖3A與3B所示,當形成該第一黏著層16後,在該第一黏著層16的上表面設置一第一外板17,其中該第一外板17具有一第一窗口18以供穿設該第一保護裝置15。當第一外板17設於第一黏著層16上後,為使第一外板17與導電體13的接合更牢靠,可對第一外板17與導電體13進行壓合,以藉該第一黏著層16固接第一外板17與導電體13。其中,該導電體13與第一外板17上可分別形成相對應的定位孔;於導電體13中,其定位孔與第一保護裝置15之間的相對位置為已知,故在進 行壓合作業前,該第一外板17可根據定位孔預先形成該第一窗口18,令第一窗口18的位置對應於該第一保護裝置15的位置,該第一外板17透過定位孔與導電體13相互對位而設於導電體13上,該第一保護裝置15即可穿設於該第一窗口18中。 Referring to FIGS. 3A and 3B , after the first adhesive layer 16 is formed, a first outer panel 17 is disposed on the upper surface of the first adhesive layer 16 , wherein the first outer panel 17 has a first window 18 . The first protection device 15 is provided for wearing. After the first outer panel 17 is disposed on the first adhesive layer 16, in order to make the first outer panel 17 and the conductor 13 more securely coupled, the first outer panel 17 and the conductor 13 may be pressed together. The first adhesive layer 16 is fixed to the first outer panel 17 and the electrical conductor 13. The conductive body 13 and the first outer plate 17 respectively form corresponding positioning holes; in the electrical conductor 13, the relative position between the positioning hole and the first protection device 15 is known, so Before the pressure cooperation, the first outer panel 17 can pre-form the first window 18 according to the positioning hole, so that the position of the first window 18 corresponds to the position of the first protection device 15, and the first outer panel 17 is positioned through The hole and the electric conductor 13 are disposed opposite to each other and disposed on the electric conductor 13 , and the first protection device 15 can be inserted into the first window 18 .

若第一保護裝置15的高度高於第一外板17的高度,使第一保護裝置15突出於第一外板17的外表面,此時在進行壓合作業時,壓合治具可於對應第一保護裝置15的位置形成凹槽,以容置該凸出的第一保護裝置15,令壓合治具可平穩地壓合第一外板17。 If the height of the first protection device 15 is higher than the height of the first outer panel 17, the first protection device 15 protrudes from the outer surface of the first outer panel 17, and at this time, when the pressure cooperation is performed, the pressing fixture can be A groove is formed corresponding to the position of the first protection device 15 to accommodate the protruding first protection device 15, so that the pressing fixture can smoothly press the first outer panel 17.

請參考圖4所示,當導電體13與第一外板17彼此固接後,將該第一保護裝置15移除,當第一保護裝置15被移除後,該導電體13的第一針測區14將外露於第一窗口18。 Referring to FIG. 4, after the electrical conductor 13 and the first outer panel 17 are fixed to each other, the first protection device 15 is removed. After the first protection device 15 is removed, the first conductor 13 is removed. The needle test area 14 will be exposed to the first window 18.

請參考圖5所示,將基板12移除,以令該導電體13的下表面外露,其中該導電體13第二端部的下表面定義有一第二針測區19,於本較佳實施例中,係以研磨方式移除基板12。 Referring to FIG. 5, the substrate 12 is removed to expose the lower surface of the conductor 13. The lower surface of the second end of the conductor 13 defines a second pinning area 19, which is preferably implemented. In the example, the substrate 12 is removed by grinding.

請參考圖6所示,於該導電體13第二端部的第二針測區19設置一第二保護裝置21,使第二保護裝置21覆蓋該第二針測區19,第二保護裝置21可為一柱狀體,其材質不限為導體或絕緣體。接著於導電體13下表面形成一第二黏著層22,因第二保護裝置21已設在第二針測區19表面,因此第二黏著層22不會附著在第二針測區19的表面。 Referring to FIG. 6 , a second protection device 21 is disposed on the second needle measuring area 19 at the second end of the electrical conductor 13 , so that the second protection device 21 covers the second needle measuring area 19 , and the second protection device 21 may be a columnar body, and the material thereof is not limited to a conductor or an insulator. Then, a second adhesive layer 22 is formed on the lower surface of the conductor 13. Since the second protection device 21 is already disposed on the surface of the second needle measurement area 19, the second adhesive layer 22 does not adhere to the surface of the second needle measurement area 19. .

請參考圖7所示,在該第二黏著層22的下表面設置一第二外板23,該第二外板23具有一第二窗口24以供穿設該第二保護裝置21,該第二外板23與導電體13進行壓合,藉由該第二黏著層22固接導電體13與第二外板23。其中,該導電體13與第二外板23可分別形成相對應的定位孔;於導電體13中,其定位孔與第二保護裝置21之間的相對位置為已知,故在進行壓合作業前,該第二外板23可根據定位孔預先形成該第二窗口24,令第二窗口24的位置對應於該第二保護裝置21的位置,該第二外板23透過定位孔與導電體13相互對位而設於導電體13上,該第二保護裝置21即可穿設於該第二窗口24中。 Referring to FIG. 7 , a second outer panel 23 is disposed on the lower surface of the second adhesive layer 22 , and the second outer panel 23 has a second window 24 for the second protection device 21 . The second outer panel 23 is pressed against the conductor 13 , and the second adhesive layer 22 is used to fix the conductor 13 and the second outer panel 23 . The conductive body 13 and the second outer plate 23 can respectively form corresponding positioning holes; in the electrical conductor 13, the relative position between the positioning hole and the second protection device 21 is known, so the pressure cooperation is performed. The second outer panel 23 can pre-form the second window 24 according to the positioning hole, so that the position of the second window 24 corresponds to the position of the second protection device 21, and the second outer panel 23 passes through the positioning hole and is electrically conductive. The bodies 13 are disposed opposite each other on the electrical conductor 13 , and the second protection device 21 can be disposed in the second window 24 .

請參考圖8所示,當導電體13與第二外板23彼此固接後,將該第二保護裝置21移除,當第二保護裝置21被移除後,將使導電體13的第二針測區19外露;當第二保護裝置21被移除後,即完成本發明之直通阻抗標準基板(Impedance Standard Substrate,ISS)。 Referring to FIG. 8 , when the electrical conductor 13 and the second outer panel 23 are fixed to each other, the second protection device 21 is removed. When the second protection device 21 is removed, the electrical conductor 13 is The two-needle test area 19 is exposed; when the second protection device 21 is removed, the Impedance Standard Substrate (ISS) of the present invention is completed.

請參考圖9所示,本發明直通式阻抗標準基板的結構包含有一導電體30、一第一外板32與一第二外板33。 Referring to FIG. 9, the structure of the straight-through impedance standard substrate of the present invention comprises an electrical conductor 30, a first outer panel 32 and a second outer panel 33.

該導電體30具有相對的一第一端部與一第二端部,該第一端部的上表面定義有一第一針測區301,該第二端部的下表面定義有一第二針測區302。該導電體30可為銅箔、銅線或其他金屬。 The electric conductor 30 has a first end portion and a second end portion. The upper surface of the first end portion defines a first needle measuring area 301, and the lower surface of the second end portion defines a second needle measuring portion. Area 302. The electrical conductor 30 can be a copper foil, copper wire or other metal.

該第一外板32藉由一第一黏著層311固接於該導電體30的上表面,且對應第一針測區301的區域形成一第一窗口321,該第一針測區301外露於該第一窗口321 中,該第一黏著層311為符合一般印刷電路板製程所使用之黏著劑,例如聚丙烯(Polypropylene,PP)膠。 The first outer panel 32 is fixed to the upper surface of the conductor 30 by a first adhesive layer 311, and a first window 321 is formed corresponding to the area of the first needle measuring area 301. The first needle measuring area 301 is exposed. In the first window 321 The first adhesive layer 311 is an adhesive used in a general printed circuit board process, such as a polypropylene (PP) adhesive.

該第二外板33藉由一第二黏著層312固接於該導電體30的下表面,且對應第二針測區302的區域形成一第二窗口331,該第二針測區302外露於該第二窗口331中,該第二黏著層312為符合一般印刷電路板製程所使用之黏著劑,例如聚丙烯(Polypropylene,PP)膠。 The second outer panel 33 is fixed to the lower surface of the conductor 30 by a second adhesive layer 312, and a second window 331 is formed corresponding to the area of the second needle measuring area 302. The second needle detecting area 302 is exposed. In the second window 331, the second adhesive layer 312 is an adhesive used in a general printed circuit board process, such as a polypropylene (PP) adhesive.

請參考圖10所示,在透過本發明的直通阻抗標準基板50進行探針校正時,由於該第一針測區301與第二針測區302分別位在直通阻抗標準基板50相對的表面,因此探針41、42須事先調整到對應的位置,以分別電連接到該第一針測區301與第二針測區302而進行校正作業。 Referring to FIG. 10, when the probe is corrected by the through-impedance standard substrate 50 of the present invention, since the first needle measuring area 301 and the second needle measuring area 302 are respectively located on the opposite surfaces of the through-impedance standard substrate 50, Therefore, the probes 41, 42 must be adjusted to the corresponding positions in advance to be electrically connected to the first and second needle-measuring regions 301, 302, respectively, for correcting work.

當校正作業執行完畢後,由於探針41、42仍處於相對設置的狀態,故探針41、42可以直接用來檢測具有雙側信號連接埠(I/O port)的晶片,相對於先前技術,本發明的直通阻抗標準基板50允許在探針41、42校正之後不需再大幅度的翻轉移動,在維持原有的上下相對位置情況下,對待測晶片進行量測。 After the calibration operation is completed, since the probes 41, 42 are still in a relatively set state, the probes 41, 42 can be directly used to detect a wafer having a double-sided signal connection port (I/O port), compared to the prior art. The through-impedance standard substrate 50 of the present invention allows a large amount of flipping movement after the probes 41, 42 are corrected, and the wafer to be tested is measured while maintaining the original up and down relative position.

12‧‧‧基板 12‧‧‧Substrate

13‧‧‧導電體 13‧‧‧Electric conductor

14‧‧‧第一針測區 14‧‧‧First needle test area

15‧‧‧第一保護裝置 15‧‧‧First protection device

16‧‧‧第一黏著層 16‧‧‧First adhesive layer

17‧‧‧第一外板 17‧‧‧First outer board

18‧‧‧第一窗口 18‧‧‧ first window

19‧‧‧第二針測區 19‧‧‧Second needle survey area

21‧‧‧第二保護裝置 21‧‧‧Second protection device

22‧‧‧第二黏著層 22‧‧‧Second Adhesive Layer

23‧‧‧第二外板 23‧‧‧Second outer board

24‧‧‧第二窗口 24‧‧‧ second window

30‧‧‧導電體 30‧‧‧Electrical conductor

301‧‧‧第一針測區 301‧‧‧first needle test area

302‧‧‧第二針測區 302‧‧‧Second needle survey area

311‧‧‧第一黏著層 311‧‧‧First adhesive layer

312‧‧‧第二黏著層 312‧‧‧Second Adhesive Layer

32‧‧‧第一外板 32‧‧‧First outer board

321‧‧‧第一窗口 321‧‧‧ first window

33‧‧‧第二外板 33‧‧‧Second outer board

331‧‧‧第二窗口 331‧‧‧ second window

41‧‧‧探針 41‧‧‧Probe

42‧‧‧探針 42‧‧‧Probe

50‧‧‧直通阻抗標準基板 50‧‧‧through impedance standard substrate

圖1~8:本發明製法於各步驟的示意圖。 1 to 8 are schematic views of the steps of the present invention.

圖9:本發明直通阻抗標準基板的示意圖。 Figure 9 is a schematic view of a through-impedance standard substrate of the present invention.

圖10:本發明直通阻抗標準基板的使用狀態參考圖。 Fig. 10 is a view showing the state of use of the through-impedance standard substrate of the present invention.

30‧‧‧導電體 30‧‧‧Electrical conductor

301‧‧‧第一針測區 301‧‧‧first needle test area

302‧‧‧第二針測區 302‧‧‧Second needle survey area

311‧‧‧第一黏著層 311‧‧‧First adhesive layer

312‧‧‧第二黏著層 312‧‧‧Second Adhesive Layer

32‧‧‧第一外板 32‧‧‧First outer board

321‧‧‧第一窗口 321‧‧‧ first window

33‧‧‧第二外板 33‧‧‧Second outer board

331‧‧‧第二窗口 331‧‧‧ second window

Claims (8)

一種直通阻抗標準基板,包含:一導電體,其上表面定義有一第一針測區,其下表面定義有一第二針測區;一第一外板,以一第一黏著層固接於該導電體的上表面,且對應該第一針測區的區域形成一第一窗口,該第一針測區外露於該第一窗口中;以及一第二外板,以一第二黏著層固接於該導電體的下表面,且對應該第二針測區的區域形成一第二窗口,該第二針測區外露於該第二窗口中。 A through-impedance standard substrate comprises: a conductor having a first needle measuring area defined on an upper surface thereof and a second needle measuring area defined on a lower surface thereof; a first outer panel fixed to the first adhesive layer An upper surface of the electrical conductor, and a region corresponding to the first needle measuring area forms a first window, the first needle measuring area is exposed in the first window; and a second outer panel is fixed by a second adhesive layer Connected to the lower surface of the electric conductor, and a region corresponding to the second needle measuring area forms a second window, and the second needle measuring area is exposed in the second window. 如請求項1所述之直通阻抗標準基板,該導電體為銅箔。 The through-impedance standard substrate according to claim 1, wherein the conductor is a copper foil. 一種直通阻抗標準基板的製法,其步驟包含:準備一基板,在該基板表面形成一導電體,該導電體的上表面定義一第一針測區;設置一第一保護裝置於該導電體的第一針測區上,使該第一保護裝置覆蓋該第一針測區;設置一第一外板於該導電體的上表面,其中該第一外板具有一第一窗口供穿設該第一保護裝置;移除該第一保護裝置,使該第一針測區外露於該第一窗口;移除該基板以外露該導電體的下表面,該導電體的下表面定義一第二針測區;設置一第二保護裝置於該導電體的第二針測區上,使該第二保護裝置覆蓋該第二針測區; 設置一第二外板於該導電體的下表面,其中該第二外板具有一第二窗口供穿設該第二保護裝置;以及移除該第二保護裝置,以完成直通阻抗標準基板。 A method for manufacturing a through-impedance standard substrate, the method comprising: preparing a substrate, forming a conductor on a surface of the substrate, the upper surface of the conductor defining a first pin measurement area; and providing a first protection device to the conductor The first protection device covers the first needle measurement area; the first outer panel is disposed on the upper surface of the electrical conductor, wherein the first outer panel has a first window for wearing the first needle a first protection device; removing the first protection device to expose the first needle measurement area to the first window; removing the substrate to expose a lower surface of the electrical conductor, the lower surface of the electrical conductor defining a second a second measuring device is disposed on the second needle measuring area of the electrical conductor, so that the second protective device covers the second measuring area; A second outer panel is disposed on the lower surface of the electrical conductor, wherein the second outer panel has a second window for penetrating the second protection device; and the second protection device is removed to complete the through-impedance standard substrate. 如請求項3所述直通阻抗標準基板的製法,其中:於設置第一外板於該導電體的上表面的步驟中,係先形成一第一黏著層於該導電體的上表面,該第一外板設於該第一黏著層的上表面;及於設置第二外板於該導電體的下表面的步驟中,係先形成一第二黏著層於該導電體的下表面,該第二外板設於該第二黏著層的下表面。 The method for manufacturing a through-impedance standard substrate according to claim 3, wherein in the step of disposing the first outer plate on the upper surface of the electrical conductor, forming a first adhesive layer on the upper surface of the electrical conductor, the first An outer plate is disposed on the upper surface of the first adhesive layer; and in the step of disposing the second outer plate on the lower surface of the electrical conductor, a second adhesive layer is formed on the lower surface of the electrical conductor. The second outer plate is disposed on the lower surface of the second adhesive layer. 如請求項3或4所述直通阻抗標準基板的製法,在設置該第一外板於導電體上表面的步驟中,該導電體與第一外板上分別形成相對應的定位孔,且該第一外板根據定位孔而預先形成該第一窗口,該第一外板透過定位孔與導電體相互對位而設於導電體上。 The method for manufacturing a through-impedance standard substrate according to claim 3 or 4, wherein in the step of disposing the first outer plate on the upper surface of the electric conductor, the electric conductor and the first outer plate respectively form corresponding positioning holes, and The first outer panel is pre-formed according to the positioning hole, and the first outer panel is disposed on the electric conductor through the positioning hole and the electric conductor. 如請求項5所述直通阻抗標準基板的製法,在設置該第二外板於導電體下表面的步驟中,該導電體與第二外板上分別形成相對應的定位孔,且該第二外板根據定位孔而預先形成該第二窗口,該第二外板透過定位孔與導電體相互對位而設於導電體上。 The method for manufacturing a through-impedance standard substrate according to claim 5, wherein in the step of disposing the second outer panel on the lower surface of the conductor, the conductor and the second outer panel respectively form corresponding positioning holes, and the second The second plate is pre-formed according to the positioning hole, and the second outer plate is disposed on the electric conductor through the positioning hole and the electric conductor. 如請求項6所述直通阻抗標準基板的製法,在移除該基板的步驟中,係以研磨方式磨除該基板。 In the method of fabricating the through-impedance standard substrate according to claim 6, in the step of removing the substrate, the substrate is removed by grinding. 如請求項6所述直通阻抗標準基板的製法,該導電體為銅箔。 The method of manufacturing the through-impedance standard substrate according to claim 6, wherein the conductor is a copper foil.
TW101127677A 2012-08-01 2012-08-01 Through impedance standard substrate and manufacture method thereof TW201407173A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104237832A (en) * 2014-10-13 2014-12-24 北京东方计量测试研究所 Calibration method and device of complex impedance standard device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104237832A (en) * 2014-10-13 2014-12-24 北京东方计量测试研究所 Calibration method and device of complex impedance standard device
CN104237832B (en) * 2014-10-13 2017-09-05 北京东方计量测试研究所 A kind of calibration method and device of complex impedance standard

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