TW201345005A - Method for manufacturing light emitting diode package and structure thereof - Google Patents

Abstract

This invention provides a method for manufacturing semiconductor package, which includes following of steps, first, provides a LED chip, in the LED chip use grain size etched to N type semiconductor layer, and formed a rough layer on the N type semiconductor layer, next, set N and P type electrode pad, formed a first insulated layer on the grain, and in electrode location etched the first insulated layer to growth the electrode pad, and then, series connection the grain, electric connection at least two grains and cover a second insulated layer, the second insulated layer of surface formed a external electrode of the N and P type electrode pad, followed by, provides a electrode substrate, the electrode substrate has N and P type electrode pattern, finally, forming high voltage LED chip, use the electrode substrate to electric connection series connection the grain.

Description

Light-emitting diode package manufacturing method and package structure thereof

The present invention relates to a method for fabricating a light emitting diode package and a package structure thereof, and more particularly to a method for fabricating a light emitting diode package for forming a high voltage light-emitting diode (HVLED) wafer and a package structure thereof.

The LED industry is one of the most watched industries in recent years. Since its development, LED products have the advantages of energy saving, power saving, high efficiency, fast response time, long life cycle, mercury free, and environmental benefits. However, due to the current low-voltage and high-current circuit structure, LED lighting requires a special switching power supply controller that maintains a constant current, and requires AC and DC power converters to provide a large voltage drop, in addition to high current. The resulting high heat dissipation problem has caused LED lighting fixtures to still have the disadvantages of high cost, large size and high energy consumption. In view of the shortcomings of LED lighting fixtures, a high-voltage light-emitting diode (HVLED) light source has been developed. The high-voltage light-emitting diode is divided into a plurality of fine crystal grains on the existing area of the LED wafer, and is electrically processed in the process. The plurality of crystal grains are connected in series to form a light emitting diode module. The LED module can be designed with a high forward working voltage and a low operating current according to the number and size of the crystal chips in series, which can be several tens of times higher than the general LED. The current can be reduced by a hundred times. Through the high-voltage design, when the lighting fixture is used, it can eliminate the special power supply controller and its converter with the voltage drop and stabilize the current. In addition, the low current can greatly reduce the heat generation, which can effectively improve the heat dissipation setting problem. The cost and power consumption of the luminaire can be effectively reduced. However, how the crystal series structure of the high-voltage light-emitting diode can obtain a better current distribution and improve the luminous efficiency, and the important one is the manufacturing technology of the high-voltage light-emitting diode, especially in the fine-grained dividing technology and the crystal grain. Insulation technology and electrical connection technology between the crystal grains. Therefore, in the process of the high-voltage light-emitting diode, the structure heat dissipation is better, the light-emitting efficiency is higher, and continuous research and improvement are required.

In view of the above, it is necessary to provide a method of fabricating a light emitting diode package having an electrode substrate and surface roughening, and a package structure thereof.

A method for manufacturing a light emitting diode package, comprising the following steps,

Providing an LED chip, etched to the N-type semiconductor layer in a grain size on the LED wafer, and forming a rough layer on the N-type semiconductor layer,

Providing an N, P type electrode pad, forming a first insulating layer on the die, and etching the first insulating layer at the electrode position to grow the electrode pad,

Connecting the crystal grains in series, electrically connecting at least two of the crystal grains and covering with a second insulating layer, the surface layer of the second insulating layer forming an external electrode of the N, P type electrode pad,

Providing an electrode substrate having an N, P type electrode pattern thereon, and

A high voltage LED chip is formed, and the electrode substrate is electrically connected to the die.

A package structure comprising a high voltage LED chip and an electrode substrate, the high voltage LED chip being disposed on the electrode substrate, the electrode substrate having an N-type electrode and a P-type electrode, the high-voltage LED chip comprising at least two crystal grains, The dies are electrically connected to each other and have an N-type external electrode and a P-type external electrode. The N- and P-type external electrodes are electrically connected to the N- and P-type electrodes, and the high-voltage LED chip has a rough layer. A rough layer is on the N-type semiconductor of the high voltage LED chip.

In the above method for manufacturing a light-emitting diode package, the electrode substrate is electrically connected to the high-voltage LED chip, and the electrode substrate contributes to heat conduction of the high-voltage LED chip, and the N-type semiconductor layer of the high-voltage LED chip The surface has the rough layer, which can improve the light extraction efficiency, and can optimize the heat dissipation and light efficiency of the high voltage LED chip.

The present invention will be specifically described below with reference to the accompanying drawings.

Please refer to FIG. 1 , which is a flow chart showing the steps of a method for fabricating a light emitting diode package according to the present invention, which includes the following steps;

S11 provides an LED chip on which an N-type semiconductor layer is etched in a grain size and a rough layer is formed on the N-type semiconductor layer.

S12 is provided with N and P type electrode pads, a first insulating layer is formed on the die, and the first insulating layer is etched at the electrode position to grow the electrode pad.

S13 is connected in series with the die, electrically connecting at least two of the die and covered by a second insulating layer, the surface layer of the second insulating layer forming an external electrode of the N, P type electrode pad,

S14 provides an electrode substrate having an N, P type electrode pattern thereon, and

S15 forms a high voltage LED chip, and the electrode substrate is electrically connected to the die in series.

Step S11 provides an LED chip 12, which is etched into the N-type semiconductor layer 122 by a grain size on the LED chip 12, and a rough layer 1222 is formed on the N-type semiconductor layer 122. The LED chip 12 structure includes a substrate 120. The substrate 120 is sequentially an N-type semiconductor layer 122, a luminescent layer (Multi Quantum Wells, MQWs) 124, a P-type semiconductor layer 126, and a conductive layer 128. The N-type semiconductor layer 122 is provided with a nitrogen. Aluminum layer (AlN) 123. The material of the substrate 120 may be a sapphire material or an aluminum oxide (Al ₂ O ₃ ) material. The material of the N, P type semiconductor layers 122 and 126 is N, P type gallium nitride (GaN), and the conductive layer 128 The material is a metal, alloy, composite or graphene. The LED chip 12 is etched by the grain size, and the plurality of crystal grains 102 (shown in FIG. 2) are cut by the trench A on the LED chip 12 by wet etching or dry etching, and the trench A is The etching depth is such that the N-type semiconductor layer 122 reaches the aluminum nitride layer 123 but does not reach the substrate 120. The rough layer 1222 etches the N-type semiconductor layer 122 layer in the trench A with an acidic or alkaline solution to form the rough layer 1222 on the side surface of the N-type semiconductor layer 122 of the die 102. The acidic or alkaline solution may be potassium hydroxide KOH, sulfuric acid H ₂ SO ₄ , hydrochloric acid HCI or nitric acid HNO ₃ . The rough layer 1222 has an amount of light that increases the light emission of the LED die 102.

In this step S12, N and P type electrode pads 1224 and 1262 are disposed, a first insulating layer 104 is formed on the die 102, and the first insulating layer 104 is etched at the electrode position to grow the electrode pads 1224 and 1262. The electrode position of the N-type electrode pad 1224 is on the N-type semiconductor layer 122, and the electrode position of the P-type electrode pad 1262 is on the conductive layer 128. The first insulating layer 104 is formed on the die 102 to cover the trench A and the surface of the die 102. The first insulating layer 104 is etched along the trench A to reach the electrode position of the N-type semiconductor pad 122 as the N-type electrode pad 1224, and the conductive layer 128 is etched to the P-type electrode pad 1262 electrode position. The position of the electrode of the N-type electrode pad 1224 does not reach the aluminum nitride layer 123. After the first insulating layer 104 is etched at the electrode position, the N, P type electrode pads 1224 and 1262 are grown to electrically connect the N and P type electrode pads 1224 and 1262 from the first insulating layer 104. Blocking (as shown in Figure 3). The material of the first insulating layer 104 is cerium oxide SiO ₂ or cerium nitride SiN.

The step S13 connects the die 102 in series, electrically connects at least two of the die 102 and is covered by a second insulating layer 106. The surface layer of the second insulating layer 106 forms one of the N, P type electrode pads 1224, 1262. The external electrodes 1226, 1264 are electrically connected in series by an electrode lead B between the adjacent N, P type electrode pads 1224, 1262. The electrode lead B is electrically connected to at least two of the crystal grains 102, and the plurality of serially connected crystal grains 102 are covered by the second insulating layer 106, and the electrode lead B and the first insulating layer 104 are included. The die 102 in series is left with a single N, P type electrode pad 1224, 1262, and the second insulating layer 106 is etched at a position of the N, P type electrode pads 1224, 1262, and the cover is removed. After the second insulating layer 106, electrodes may be deposited at a position of the single N, P type electrode pads 1224, 1262 for forming the external electrodes 1226, 1264 on the surface layer of the second insulating layer 106 (as shown in FIG. 4). Show). The N-type external electrode 1226 is an extension of the N-type electrode pad 1224, and the P-type external electrode 1264 is an extension of the P-type electrode pad 1262. The extended P-type external electrode 1264 covers the second insulating layer 106, but does not include the N-type external electrode 1226 and the die 102 that are not connected in series. The material of the second insulating layer 106 is cerium oxide SiO ₂ or cerium nitride SiN.

In this step S14, an electrode substrate 14 is provided. The electrode substrate 14 has an N- and P-type electrode pattern 142. The electrode substrate 14 is a silicon wafer (Si Wafer) or a tantalum carbide (SiC) plate. The N- and P-type electrode patterns 142 are disposed on a surface 140 of the electrode substrate 14. The N- and P-type electrode patterns 142 include a plurality of N-type electrodes 1422 and a plurality of P-type electrodes 1424, and the N-type electrodes 1422 and the P The type electrodes 1424 are arranged one-to-one with each other. Referring to FIG. 5, the N-type electrode 1422 is coupled with the P-type electrode 1424 to form an N- and P-type electrode 1422, 1424 units. The electrode pattern 142 is composed of a combination of a plurality of N and P type electrodes 1422 and 1424. The material of the N and P type electrodes 1422 and 1424 is a composite material of gold Au, silver Ag, chromium Cr, nickel Ni, copper Cu, diamond-like carbon, diamond graphene or alloy thereof.

Finally, the step S15 forms a high voltage LED chip 10, and the electrode substrate 14 is electrically connected to the die 102 in series. The N and P type electrode patterns 142 of the electrode substrate 14 are matched with the die 102 in series. The N-type electrode 1422 and the P-type electrode 1424 are opposed to the N-type external electrode 1226 and the P-type external electrode 1264, respectively. In other words, the electrode substrate 14 is electrically connected to the die 102 in series, and the N-type electrode 1422 and the N-type external electrode 1226 and the P-type electrode 1424 and the P-type external electrode 1264 are respectively connected one-to-one. The electrical connection is achieved, and the high voltage LED wafer 10 is formed after electrical connection is achieved (as shown in FIG. 6). After the high voltage LED chip 10 is formed, the surface of the high voltage LED chip 10 is further roughened. The surface roughening step of the high voltage LED chip 10 is to remove the substrate 120 of the LED chip 12 and then etch the N-type semiconductor layer 122. surface. The surface of the N-type semiconductor layer 122 is etched with an acidic or alkaline solution, which may be potassium hydroxide KOH, sulfuric acid H ₂ SO ₄ , hydrochloric acid HCI or nitric acid HNO ₃ . The etching of the surface of the N-type semiconductor layer 122 also forms the rough layer 1222, so that the rough layer 1222 on the surface and the side surface of the N-type semiconductor layer 122 can increase the amount of light emitted by the high-voltage LED wafer 10.

The package structure 100 manufactured by the above-described method for manufacturing a light-emitting diode package includes a high-voltage LED chip 10 and an electrode substrate 14. The high-voltage LED chip 10 is disposed on the electrode substrate 14, and the electrode substrate 14 has an N-type electrode. 1422 and a P-type electrode 1424. The high-voltage LED chip 10 includes at least two die 102. The die 102 is electrically connected to each other and has an N-type external electrode 1226 and a P-type external electrode 1264. The external electrodes 1226 and 1264 are electrically connected to the N and P electrodes 1422 and 1424. The high voltage LED chip 10 has a rough layer 1222. The rough layer 1222 is located on an N-type semiconductor layer 122 on the surface of the high voltage LED chip 10. . The rough layer 1222 is located on the upper surface of the N-type semiconductor layer 122 and on the inner side surface of the die 102 (as shown in FIG. 7). The N-type semiconductor layer 122 is sequentially followed by a light-emitting layer (Multi Quantum Wells, MQWs) 124, a P-type semiconductor layer 126, and a conductive layer 128. The N-type semiconductor layer 122 is provided with an aluminum nitride layer (AlN). ) 123. An electrode lead B is disposed between the dies 102. The electrode lead B connects an N-type electrode pad 1224 and a P-type electrode pad 1262 between the adjacent dies 102. A first insulating layer 104 is disposed between the dies 102, and the first insulating layer 104 is covered with a second insulating layer 106. The first insulating layer 104 covers the die 102 and electrically blocks the N, P type electrode pads 1224, 1262. The N, P type external electrodes 1226, 1264 are located on the second insulating layer 106.

In summary, in the method for fabricating a light-emitting diode package of the present invention, the LED wafer 12 is etched and cut into a plurality of crystal grains 102 by a grain size, through the N- and P-type electrode pads 1224 and 1262 and the N- and P-type external electrodes 1226. The arrangement of 1264 can electrically connect the die 102 to form the high voltage LED chip 10. At the same time, the rough layer 1222 is formed on the N-type semiconductor layer 122 of the high-voltage LED chip 10, and is connected to the electrode substrate 14, so that the rough layer 1222 can effectively improve the light extraction efficiency of the high-voltage LED wafer 10, and the electrode substrate 14 The high-voltage LED chip 10 can have better heat dissipation performance, and has good practical performance with simple process and stable package structure.

It should be noted that the above-described embodiments are merely preferred embodiments of the present invention, and those skilled in the art can make other changes within the spirit of the present invention. All changes made in accordance with the spirit of the invention are intended to be included within the scope of the invention.

10. . . High voltage LED chip

102. . . LED die

104. . . First insulating layer

106. . . Second insulating layer

12. . . LED chip

120. . . Substrate

122. . . N-type semiconductor layer

1222. . . Rough layer

1224. . . N-type electrode pad

1226. . . N type external electrode

123. . . Aluminum nitride layer

124. . . Luminous layer

126. . . P-type semiconductor layer

1262. . . P-type electrode pad

1264. . . P type external electrode

128. . . Conductive layer

14. . . Electrode substrate

140. . . Electrode substrate surface

142. . . N, P type electrode pattern

1422. . . N-type electrode

1424. . . P-type electrode

100. . . Package structure

A. . . Trench

B. . . Electrode lead

1 is a flow chart showing the steps of a method for fabricating a light emitting diode package of the present invention.

2 is a cross-sectional view showing the steps of providing an LED wafer corresponding to FIG. 1.

Fig. 3 is a cross-sectional view showing a step of providing N, P type electrode pads corresponding to Fig. 1.

4 is a cross-sectional view of the step of connecting the crystal grains in series corresponding to FIG. 1.

Figure 5 is a cross-sectional view showing the steps of providing an electrode substrate corresponding to Figure 1.

Figure 6 is a cross-sectional view showing the steps of forming a high voltage LED wafer corresponding to Figure 1.

Figure 7 is a cross-sectional view of the package structure of the present invention.

The representative diagram is a flow chart with no component symbols.

Claims (19)

A method of manufacturing a light emitting diode package, comprising the steps of:
Providing an LED chip, etched to the N-type semiconductor layer in a grain size on the LED wafer, and forming a rough layer on the N-type semiconductor layer,
Providing an N, P type electrode pad, forming a first insulating layer on the die, and etching the first insulating layer at the electrode position to grow the electrode pad,
Connecting the crystal grains in series, electrically connecting at least two of the crystal grains and covering with a second insulating layer, the surface layer of the second insulating layer forming an external electrode of the N, P type electrode pad,
An electrode substrate is provided, the electrode substrate has an N- and P-type electrode pattern, and a high-voltage LED chip is formed, and the electrode substrate is electrically connected to the die. The method for manufacturing a light emitting diode package according to claim 1, wherein in the step of providing an LED wafer, the N-type semiconductor layer is disposed on a substrate, and the N-type semiconductor layer has an aluminum nitride. The layer is formed by trench etching on the LED wafer by wet etching or dry etching, and the trench is etched to a depth that reaches the N-type semiconductor layer beyond the aluminum nitride layer but does not reach the substrate. The method for manufacturing a light-emitting diode package according to claim 1, wherein in the step of providing an LED wafer, the rough layer is an acidic or alkaline solution in the trench to the N-type semiconductor layer. Etching is performed to form the rough layer on the side of the N-type semiconductor layer of the crystal grain. The method for manufacturing a light-emitting diode package according to claim 3, wherein the acidic or alkaline solution may be potassium hydroxide KOH, sulfuric acid H ₂ SO ₄ , hydrochloric acid HCI or nitric acid HNO ₃ . The method for manufacturing a light-emitting diode package according to claim 1, wherein in the step of providing an N- and P-type electrode pad, the first insulating layer covers the trench and a conductive surface of the die surface a layer, the conductive layer is an electrode position of the P-type electrode pad, and an electrode position of the N-type electrode pad is on the N-type semiconductor layer, and the aluminum nitride layer is not reached. The method for manufacturing a light-emitting diode package according to claim 1, wherein in the step of connecting the crystal grains, the crystal grains are passed through an electrode lead between the adjacent N- and P-type electrode pads. In series, the second insulating layer covers the die in series, and includes the electrode lead and the first insulating layer. The method of manufacturing a light emitting diode package according to claim 6, wherein the series of the crystal grains are left with a single N, P type electrode pad, and the single N, P type electrode pad is used. The positional etching removes the second insulating layer to form the external electrode by depositing an electrode. The method of manufacturing a light emitting diode package according to claim 7, wherein the N-type external electrode of the external electrode is an extension of an N-type electrode pad, and the P-type external electrode is the P-type electrode pad The extension, the extended P-type external electrode covers the second insulating layer, but does not include the N-type external electrode and the non-series of the die. The method for manufacturing a light emitting diode package according to claim 6, wherein the second insulating layer and the material of the first insulating layer are cerium oxide SiO ₂ or cerium nitride SiN. The method for manufacturing a light-emitting diode package according to claim 1, wherein in the step of providing an electrode substrate, the N- and P-type electrode patterns are disposed on a surface of the electrode substrate, the N, P The electrode pattern is composed of a plurality of N and P type electrode units, and the N and P type electrode units are combined with one of the N type electrodes. The method for manufacturing a light emitting diode package according to claim 10, wherein the material of the N and P electrodes is gold Au, silver Ag, chromium Cr, nickel Ni, copper Cu, diamond-like carbon Diamond-Like. A composite of Carbon, Graphene Graphene or an alloy thereof. The method of manufacturing the LED package of claim 1, wherein in the step of forming a high voltage LED chip, the electrode substrate is electrically connected to the die in series, the N-type electrode and the N-type external electrode. And electrically connecting the P-type electrode and the P-type external electrode one-to-one. The method for manufacturing a light-emitting diode package according to claim 1, wherein the step of forming a high-voltage LED wafer further comprises a step of roughening a surface of the high-voltage LED wafer by removing the substrate of the LED wafer and etching the substrate. The surface of the N-type semiconductor layer forms the rough layer. A package structure includes a high voltage LED chip and an electrode substrate. The high voltage LED chip is disposed on the electrode substrate. The electrode substrate has an N-type electrode and a P-type electrode. The high-voltage LED chip includes at least two crystal grains. The die is electrically connected to each other and has an N-type external electrode and a P-type external electrode. The N- and P-type external electrodes are electrically connected to the N- and P-type electrodes, and the high-voltage LED chip has a rough layer. The layer is on the N-type semiconductor of the high voltage LED chip. The package structure of claim 14, wherein the rough layer is located on an upper surface of the N-type semiconductor layer and on an inner side surface connecting the crystal grains. The package structure of claim 14, wherein the N-type semiconductor layer is sequentially followed by a light-emitting layer, a P-type semiconductor layer and a conductive layer, and the N-type semiconductor layer is provided with an aluminum nitride. Floor. The package structure of claim 14, wherein an electrode lead is disposed between the crystal grains, the electrode lead is connected to an N-type electrode pad and a P-type electrode pad adjacent between the die. pad. The package structure of claim 17, wherein a first insulating layer is disposed between the crystal grains, and the first insulating layer is covered with a second insulating layer, the first insulating layer covering the die and electrically The N, P type electrode pads are blocked. The package structure of claim 14, wherein the N, P type external electrodes are located on the second insulating layer.