CN203434159U - Insulated structure of GaN-based semiconductor LED chip - Google Patents
Insulated structure of GaN-based semiconductor LED chip Download PDFInfo
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- CN203434159U CN203434159U CN201320572011.8U CN201320572011U CN203434159U CN 203434159 U CN203434159 U CN 203434159U CN 201320572011 U CN201320572011 U CN 201320572011U CN 203434159 U CN203434159 U CN 203434159U
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Abstract
The utility model relates to an insulated structure of GaN-based semiconductor LED chip. The insulated structure comprises a substrate; and a plurality of light-emitting units are arranged at the substrate. Moreover, the insulated structure is characterized in that the light-emitting units are separated by insulated tapes formed by etching; and SiO2 insulation layers are arranged at the surfaces of the light-emitting units and the insulated tapes. Upper portions of P type metal electrodes and N type metal electrodes of the light-emitting units expose the upper surfaces of the SiO2 insulation layers; and the P type metal electrodes of the light-emitting units and the N type metal electrodes of the adjacent light-emitting units are connected by metal leads. The light-emitting units include epitaxial wafers arranged at the surface of the substrate, wherein the epitaxial wafers are N type gallium nitride layers, quantum wells and P type gallium nitride layers successively from bottom to top; and current extension layers are arranged on the epitaxial wafers; and P type metal electrodes are arranged on the current extension layers; and N type metal electrodes are arranged on the N type gallium nitride layers of the epitaxial wafers. With the insulated structure, all conductive objects can be isolated well; the process can be implemented conveniently; the cost is low; the process is reliable; and the production yield is high.
Description
Technical field
The utility model relates to a kind of insulation system of high-voltage LED chip, especially a kind of insulation system for GaN base semiconductor LED chip.
Background technology
The feature of high voltage LED is that a plurality of luminescence units are integrated in a LEDs chip, and this type of chip only comes for whole luminescence unit power supplies with a set of PN electrode interface, and its driving voltage is generally several times or the decades of times of common LED chip in use.As shown in Figure 1, be the structure chart of the single luminescence unit in existing high voltage LED chip, wherein 1a is P type gallium nitride, and 2a is quantum well, and 3a is n type gallium nitride, and 4a is substrate, and 5a is current extending, and 6a is P type electrode metal, and 7a is N-type electrode metal.Above-mentioned high voltage LED possesses: the advantages such as packaging cost is low, light efficiency is higher, downstream (encapsulation and light fixture production process) is easy to use, drive circuit simplicity of design, drive circuit power consumption minimizing.
The core technology of manufacturing high voltage LED chip is the integrated of a plurality of luminescence units, and the Key Techniques in Integration of multi-illuminating unit is: 1, inner lead interconnection technique; 2, between Jian, unit, unit Jian Yu unit and wire, the insulation technology between wire and wire.When a plurality of luminescence units are integrated, need to use wire that each luminescence unit is integrated, at this moment between each conductive materials, must use insulating tape isolation, otherwise LED can occur by the problem of short circuit.
Summary of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, and a kind of insulation system skill for GaN base semiconductor LED chip is provided, and this insulation system can be isolated each conductive materials in good condition.
The technical scheme providing according to the utility model, the described insulation system for GaN base semiconductor LED chip, comprise substrate, a plurality of luminescence units are set on substrate, it is characterized in that: the insulating tape being formed by etching between described luminescence unit is separated, on the surface of luminescence unit and the surface of insulating tape, SiO is set
2insulating barrier; The P type metal electrode of described luminescence unit and the top of N-type metal electrode expose SiO
2the upper surface of insulating barrier, the P type metal electrode of luminescence unit and the N-type metal electrode of adjacent luminescence unit are connected by plain conductor.
Described luminescence unit comprises the epitaxial wafer that is positioned at substrate surface, epitaxial wafer is followed successively by n type gallium nitride layer, quantum well and P type gallium nitride layer from bottom to up, current extending is set on epitaxial wafer, P type metal electrode is set on current extending, on the n type gallium nitride layer of epitaxial wafer, N-type metal electrode is set.
Described substrate is Sapphire Substrate or SiC substrate.
The utility model is suitable for integrated form GaN base LED chip or high voltage gan base LED chip; At epitaxial wafer, partly carry out etching, after etching, between each luminescence unit, only have substrate to be partly connected to each other, between each luminescence unit, formed insulating tape; SiO grows on epitaxial wafer
2, after carrying out litho pattern transfer according to the design configuration of high voltage LED chip, use SiO
2etching solution is removed unnecessary SiO according to design configuration
2, the SiO not removing
2as insulating barrier, be retained in epitaxial wafer surface, this SiO
2between insulating barrier and each more than epitaxial wafer circuit structure, play insulating effect.
Accompanying drawing explanation
Fig. 1 is the structure chart of the single luminescence unit in existing high voltage LED chip.
Fig. 2 is the structural representation of the insulation system of LED chip described in the utility model.
Fig. 3 is the schematic diagram of the epitaxial wafer of LED chip described in the utility model.
Fig. 4 is the schematic diagram of the insulating tape of LED chip described in the utility model.
Sequence number in figure is: P type gallium nitride layer 1, quantum well 2, n type gallium nitride layer 3, substrate 4, current extending 5, P type metal electrode 6, N-type metal electrode 7, insulating tape 8, SiO
2 insulating barrier 9, plain conductor 10.
Embodiment
Below in conjunction with concrete accompanying drawing, the utility model is described in further detail.
As shown in Figure 2, Figure 4 shows: the described insulation system for GaN base semiconductor LED chip comprises substrate 4, and a plurality of luminescence units are set on substrate 4, the insulating tape 8 being formed by etching between luminescence unit is separated; On the surface of described luminescence unit and the surface of insulating tape 8, SiO is set
2 insulating barrier 9, the P type metal electrode 6 of luminescence unit and the top of N-type metal electrode 7 expose SiO
2the upper surface of insulating barrier 9; The P type metal electrode 6 of luminescence unit and the N-type metal electrode 7 of adjacent luminescence unit are connected by plain conductor 10,
Described luminescence unit comprises the epitaxial wafer that is positioned at substrate 4 surfaces, epitaxial wafer is followed successively by n type gallium nitride layer 3, quantum well 2 and P type gallium nitride layer 1 from bottom to up, current extending 5 is set on epitaxial wafer, P type metal electrode 6 is set on current extending 5, on the n type gallium nitride layer 3 of epitaxial wafer, N-type metal electrode 7 is set;
Described substrate 4 is Sapphire Substrate or SiC substrate.
Embodiment mono-: a kind of manufacturing process of the insulation system for GaN base semiconductor LED chip, comprises the following steps:
(1) at the epitaxial wafer surface deposition SiO of LED chip
2layer, depositing temperature is 200 ℃, according to etching, needs SiO
2the deposit thickness of layer is 20nm;
(2) SiO depositing in step (1)
2the surface of layer is coated with one deck photoresist and obtains mask layer, then adopts mask plate photoetching, exposes, is developed in and on mask layer, form etching window; According to the etching window on mask layer, use plasma etching machine etching on epitaxial wafer to form insulating tape 8, etching gas is chlorine and boron chloride, and volume ratio is 10:1, and vacuum degree is 0.4Pa, and power is 280W; Insulating tape 8 is extended to the upper surface of substrate by the upper surface of epitaxial wafer; After etching, remove mask layer, obtain etching the epitaxial wafer (as shown in Figure 4) of insulating tape 8;
(3) the epitaxial wafer surface deposition SiO of the LED chip after step (2) is processed
2, obtain covering the SiO on epitaxial wafer surface and insulating tape surface
2insulating barrier 9;
(4) at SiO
2on insulating barrier 9, adopt SiO
2etching solution etches opening at P type metal electrode 6 and N-type metal electrode 7 places, and described etching liquid is that mass ratio is the hydrofluoric acid of 1:4 and the mixed solution of ammonium fluoride, and the mass percentage concentration of hydrofluoric acid is 20%, and the mass percentage concentration of ammonium fluoride is 20%; At above-mentioned opening part, adopt metal evaporation mechanism to make plain conductor 10, vacuum degree is 10
-4pa, the material of plain conductor 10 is gold or platinum, completes the insulation system of LED chip.
Under embodiment: a kind of manufacturing process of the insulation system for GaN base semiconductor LED chip, comprises the following steps:
(1) at the epitaxial wafer surface deposition SiO of LED chip
2layer, depositing temperature is 400 ℃, according to etching, needs SiO
2the deposit thickness of layer is 10000nm;
(2) SiO depositing in step (1)
2the surface of layer is coated with one deck photoresist and obtains mask layer, then adopts mask plate photoetching, exposes, is developed in and on mask layer, form etching window; According to the etching window on mask layer, use plasma etching machine etching on epitaxial wafer to form insulating tape 8, etching gas is chlorine and boron chloride, and volume ratio is 10:1, and vacuum degree is 0.4Pa, and power is 280W; Insulating tape 8 is extended to the upper surface of substrate by the upper surface of epitaxial wafer; After etching, remove mask layer, obtain etching the epitaxial wafer (as shown in Figure 4) of insulating tape 8;
(3) the epitaxial wafer surface deposition SiO of the LED chip after step (2) is processed
2, obtain covering the SiO on epitaxial wafer surface and insulating tape surface
2insulating barrier 9;
(4) at SiO
2on insulating barrier 9, adopt SiO
2etching solution etches opening at P type metal electrode 6 and N-type metal electrode 7 places, and described etching liquid is that mass ratio is the hydrofluoric acid of 1:4 and the mixed solution of ammonium fluoride, and the mass percentage concentration of hydrofluoric acid is 30%, and the mass percentage concentration of ammonium fluoride is 60%; At above-mentioned opening part, adopt metal evaporation mechanism to make plain conductor 10, vacuum degree is 10
-4pa, the material of plain conductor 10 is gold or platinum, completes the insulation system of LED chip.
Embodiment tri-: a kind of manufacturing process of the insulation system for GaN base semiconductor LED chip, comprises the following steps:
(1) at the epitaxial wafer surface deposition SiO of LED chip
2layer, depositing temperature is 300 ℃, according to etching, needs SiO
2the deposit thickness of layer is 1000nm;
(2) SiO depositing in step (1)
2the surface of layer is coated with one deck photoresist and obtains mask layer, then adopts mask plate photoetching, exposes, is developed in and on mask layer, form etching window; According to the etching window on mask layer, use plasma etching machine etching on epitaxial wafer to form insulating tape 8, etching gas is chlorine and boron chloride, and volume ratio is 10:1, and vacuum degree is 0.4Pa, and power is 280W; Insulating tape 8 is extended to the upper surface of substrate by the upper surface of epitaxial wafer; After etching, remove mask layer, obtain etching the epitaxial wafer (as shown in Figure 4) of insulating tape 8;
(3) the epitaxial wafer surface deposition SiO of the LED chip after step (2) is processed
2, obtain covering the SiO on epitaxial wafer surface and insulating tape surface
2insulating barrier 9;
(4) at SiO
2on insulating barrier 9, adopt SiO
2etching solution etches opening at P type metal electrode 6 and N-type metal electrode 7 places, and described etching liquid is that mass ratio is the hydrofluoric acid of 1:4 and the mixed solution of ammonium fluoride, and the mass percentage concentration of hydrofluoric acid is 60%, and the mass percentage concentration of ammonium fluoride is 70%; At above-mentioned opening part, adopt metal evaporation mechanism to make plain conductor 10, vacuum degree is 10
-4pa, the material of plain conductor 10 is gold or platinum, completes the insulation system of LED chip.
Claims (3)
1. the insulation system for GaN base semiconductor LED chip, comprise substrate (4), on substrate (4), a plurality of luminescence units are set, it is characterized in that: the insulating tape being formed by etching between described luminescence unit (8) is separated, and on the surface of luminescence unit and the surface of insulating tape (8), SiO is set
2insulating barrier (9); The P type metal electrode (6) of described luminescence unit and the top of N-type metal electrode (7) expose SiO
2the upper surface of insulating barrier (9), the P type metal electrode (6) of luminescence unit and the N-type metal electrode (7) of adjacent luminescence unit are connected by plain conductor (10).
2. the insulation system for GaN base semiconductor LED chip as claimed in claim 1, it is characterized in that: described luminescence unit comprises the epitaxial wafer that is positioned at substrate (4) surface, epitaxial wafer is followed successively by n type gallium nitride layer (3), quantum well (2) and P type gallium nitride layer (1) from bottom to up, current extending (5) is set on epitaxial wafer, P type metal electrode (6) is set on current extending (5), on the n type gallium nitride layer (3) of epitaxial wafer, N-type metal electrode (7) is set.
3. the insulation system for GaN base semiconductor LED chip as claimed in claim 2, is characterized in that: described substrate (4) is Sapphire Substrate or SiC substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320572011.8U CN203434159U (en) | 2013-09-14 | 2013-09-14 | Insulated structure of GaN-based semiconductor LED chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320572011.8U CN203434159U (en) | 2013-09-14 | 2013-09-14 | Insulated structure of GaN-based semiconductor LED chip |
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| Publication Number | Publication Date |
|---|---|
| CN203434159U true CN203434159U (en) | 2014-02-12 |
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| CN201320572011.8U Expired - Fee Related CN203434159U (en) | 2013-09-14 | 2013-09-14 | Insulated structure of GaN-based semiconductor LED chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489887A (en) * | 2013-09-14 | 2014-01-01 | 江苏新广联科技股份有限公司 | Insulation structure used for GaN-based semiconductor LED chip and manufacturing process thereof |
-
2013
- 2013-09-14 CN CN201320572011.8U patent/CN203434159U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489887A (en) * | 2013-09-14 | 2014-01-01 | 江苏新广联科技股份有限公司 | Insulation structure used for GaN-based semiconductor LED chip and manufacturing process thereof |
| CN103489887B (en) * | 2013-09-14 | 2016-04-13 | 江苏新广联科技股份有限公司 | For insulation system and the manufacturing process thereof of GaN base semi-conductor LED chips |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140212 Termination date: 20170914 |