TW201332017A - Semiconductor device fabrication method and semiconductor device - Google Patents

Abstract

To provide a method for fabricating a semiconductor device in which, by suppressing the concentration of cavities in Cu wiring, the formation of voids within the Cu wiring is suppressed and the occurrence of stress migration, which refers to faulty wiring such as wire breakage, is suppressed in areas such as the via connecting points in a two-layer wiring system. In a method for fabricating a semiconductor device having a Damascene wiring structure, provided is a semiconductor fabrication method in which a thermal cycle step for heating and cooling the processed substrate is performed after the wiring is formed.

Description

Semiconductor device manufacturing method and semiconductor device

The present invention relates to a method of fabricating a semiconductor device and a semiconductor device.

In recent years, in order to reduce the resistance and high reliability of the wiring of the semiconductor device, Cu wiring is used. Since the Cu wiring is difficult to be formed by dry etching, it has a damascene wiring structure in which wiring is formed in a plurality of layers. The damascene wiring structure is formed by depositing a Cu film on a trench of a wiring pattern formed on the interlayer insulating film, and then removing it by a chemical polishing (hereinafter, also referred to as a CMP method). Cu.

Here, the Cu wiring is formed inside the interlayer insulating film. Then, a plurality of interlayer insulating films are laminated. Therefore, after the temperature rise and the temperature removal process of the heat treatment in the manufacturing process of the Cu wiring, the stress generated by the difference in the thermal expansion coefficient of each material or the compressive stress of the interlayer insulating film may affect, for example, several hundred MPa. The tensile stress acts on the Cu wiring. The stress concentration at the Cu wiring due to the tensile stress causes a stress gradient in the Cu wiring. The stress becomes a driving force for the movement of the pores (atomic pores) existing in the Cu wiring. These holes are accumulated in the Cu wiring to form voids (voids), and the Cu wiring is broken due to pore growth, which causes a problem of wiring failure called stress migration. In particular, in the two-layer wiring system in which the via wiring (interlayer wiring) is bonded, the stress is concentrated in the vicinity of the joint portion between the via wiring and the Cu wiring, and the wiring is likely to be broken at the bonding portions. The problem of poor wiring. Therefore, it is required to suppress the wiring of the Cu wiring or the via wiring in the semiconductor device. Bad to extend the life of the device.

Then, for example, Patent Document 1 discloses a semiconductor device which protects the surface of a metal region such as a wiring structure by a metal having a high recrystallization temperature such as silver or a metal having a narrow hysteresis in a temperature-stress curve. The above stress migration is suppressed.

Patent Document 1: Japanese Patent Laid-Open Publication No. 2004-39916

However, in the technique described in Patent Document 1, the stress migration is attributed to the stress concentration caused by the difference in the coefficient of thermal expansion of the different materials, and the solution is to protect the surface of the metal region by silver or the like. However, the inventors of the present invention have found that the cause of the stress migration is the movement of the pores accompanied by the stress concentration, and the movement of the pores (that is, the pore concentration) cannot be protected by the metal such as silver (wiring structure). Controlling the surface, the technique described in the above Patent Document 1 cannot sufficiently suppress the occurrence of stress migration. In addition, in the technique described in the above-mentioned Patent Document 1, since a film of silver or the like is provided on the surface of the metal region (wiring structure), a film forming step of the film is required. Therefore, in the manufacture of the semiconductor device, There are problems with doubts such as an increase in the number of processes or an increase in costs.

The present invention has been made in view of the above problems, and an object of the invention is to provide a method for manufacturing a semiconductor device and a semiconductor device which suppress the formation of voids in a Cu wiring by suppressing concentration of voids in the Cu wiring to suppress, for example, double layer. A wiring defect such as a disconnection of a so-called stress migration occurs in a via hole connection portion of the wiring system or the like.

In order to achieve the above object, according to the present invention, a method of manufacturing a semiconductor device having a copper wiring structure, which is a thermal cycle process for heating and removing heat of a substrate to be processed after formation of a copper wiring layer including heat treatment, can be provided. .

Moreover, according to the present invention, a method of manufacturing a semiconductor device can be provided in a method of manufacturing a semiconductor device having a damascene wiring structure. After the wiring formation is completed, a thermal cycle process of heating and removing heat of the semiconductor device is performed.

Furthermore, according to another aspect of the present invention, there is provided a semiconductor device comprising a semiconductor device having a damascene wiring structure, wherein a thermal cycle for heating and removing heat of the semiconductor device is performed after the wiring is formed.

According to the present invention, it is possible to provide a semiconductor device manufacturing method and a semiconductor device capable of suppressing the formation of voids in the Cu wiring by suppressing the concentration of voids in the Cu wiring, thereby suppressing, for example, a via hole of the double-layer wiring system. A wiring defect such as a disconnection of a so-called stress migration occurs at a connection portion or the like.

1‧‧‧Substrate body

2‧‧‧Interlayer insulating film

4‧‧‧ wiring trench

5‧‧‧Resistance metal (BM) layer

7‧‧‧Cu plating seed layer

10‧‧‧Cu conductive layer

15‧‧‧Cu wiring

18‧‧‧Cu wiring structure

18a‧‧‧1st floor

18b‧‧‧2nd floor

20‧‧‧Interlayer wiring

1 is a cross-sectional view of a substrate for explaining a manufacturing process of a semiconductor device according to an embodiment of the present invention, and shows a state in which wiring trenches are formed on a surface of an interlayer insulating film.

2 is a cross-sectional view of a substrate for explaining a manufacturing process of a semiconductor device according to an embodiment of the present invention, in which a barrier metal layer and a Cu plating seed layer are continuously formed on an interlayer insulating film.

3 is a cross-sectional view of a substrate for explaining a manufacturing process of a semiconductor device according to an embodiment of the present invention, and is a state in which a Cu conductive layer is formed on the entire surface of the substrate.

4 is a cross-sectional view of a substrate for explaining a manufacturing process of a semiconductor device according to an embodiment of the present invention, showing a state in which a Cu conductive layer and a barrier metal layer are removed from above the interlayer insulating film.

5 is a cross-sectional view of a substrate for explaining a manufacturing process of the two-layer structure semiconductor device according to the embodiment of the present invention, and shows a state in which wiring trenches are formed on the surface of the interlayer insulating film.

6 is a cross-sectional view of a substrate for explaining a manufacturing process of a two-layer structure semiconductor device according to an embodiment of the present invention, in which a barrier metal layer and a Cu plating seed layer are continuously formed on an interlayer insulating film.

Figure 7 is a perspective view of a two-layer structure semiconductor package according to an embodiment of the present invention. A cross-sectional view of the substrate in the manufacturing process is shown in a state in which a Cu conductive layer is formed on the entire surface of the substrate.

8 is a cross-sectional view of a substrate for explaining a manufacturing process of the two-layer structure semiconductor device according to the embodiment of the present invention, showing a state in which a Cu conductive layer is removed from above the interlayer insulating film.

FIG. 9 is a graph showing conditions when a semiconductor device is subjected to a thermal cycle process after completion of a wiring forming process or a process of applying heat or heat to another semiconductor device.

Fig. 10 is a graph showing the change in the pore concentration at the interlayer joint portion with time when the thermal cycle process is carried out under the conditions shown in Fig. 9.

Fig. 11 is a view showing the pore concentration distribution (a) after 1000 hours at the interlayer hole joint portion in the case where the heat cycle process is not performed, and the via hole joint portion in the case where the ⊿T is 200 °C for the thermal cycle process. The measured data of the pore concentration distribution (b) after 1000 hours.

Fig. 12 is a graph showing simulation results for specifying the thermal fatigue temperature ⊿T for causing the condensation and release of the pore concentration, and is a graph showing the thermal fatigue load condition.

Figure 13 is a graph showing the change in pore concentration and time under the conditions shown in Figure 12.

Fig. 14 is a graph showing the conditions of the thermal cycle process in the case where the soaking time is changed in the heat cycle process.

Fig. 15 is a view showing the change in the pore concentration at the interlayer hole joint portion with time when the thermal cycle process is carried out under the conditions shown in Fig. 14.

Fig. 16 is a graph showing the conditions of the thermal cycle process in the case where the heat removal time is changed in the heat cycle process.

Fig. 17 is a view showing the change in the pore concentration at the interlayer joint portion with time when the thermal cycle process is carried out under the conditions shown in Fig. 16.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in this specification and the drawings, the composition having the same functional structure is substantially The same elements are denoted by the same reference numerals, and the repeated description is omitted.

FIG. 1 to FIG. 4 are explanatory views showing a manufacturing process of the Cu wiring structure. In other words, in the substrate W to be processed of a semiconductor formed of Si or the like, a process of forming a Cu wiring on the upper surface of the substrate body 1 is shown. The substrate body 1 has an arbitrary structure such as a CMOS (not shown). 5 to 8 are explanatory views showing a manufacturing process of the semiconductor device A in which the Cu wiring has a two-layer structure, and in particular, FIG. 8 shows a semiconductor device A according to the embodiment of the present invention.

First, as shown in FIG. 1, for example, an interlayer insulating film 2 is formed above the substrate body 1. The interlayer insulating film 2 is exemplified by a film containing Si such as SiO ₂ or SiCO, or a low specific dielectric film containing CF _x such as carbon or fluorine. Next, the wiring trench 4 is formed on the surface of the interlayer insulating film 2 by photolithography and reactive ion etching (RIE).

Next, as shown in FIG. 2, a barrier metal (hereinafter referred to as BM) film 5 and a Cu plating seed layer 7 are continuously formed on the interlayer insulating film 2 like the inner surface of the wiring trench 4. The BM film 5 is formed by sputtering a Ta film on the entire surface of the interlayer insulating film 2. The BM film 5 is a single film of a Ta film, a TaN film, a Ta compound film or a Ta alloy film, or a single film of a Ti film, a TiN film, a Ti compound film or a Ti alloy film, or two or more layers thereof. Film accumulation. Further, the Cu plating seed layer 7 is formed by, for example, sputtering.

Next, as shown in FIG. 3, the Cu conductive layer 10 is formed in the entire surface of the substrate W by embedding the wiring trench 4 from above the Cu plating seed layer 7. The Cu conductive layer 10 is not limited to pure Cu, and may be a Cu alloy or formed by electrolytic plating or the like. Further, the Cu plating seed layer 7 and the Cu conductive layer 10 are integrally formed by the formation of the Cu conductive layer 10.

Next, as shown in FIG. 4, portions of the Cu conductive layer 10 and the BM film 5 are left inside the wiring trench 4, and Cu is removed from the upper portion of the interlayer insulating film 2 by CMP (Chemical Mechanical Polishing) method. Conductive layer 10 and BM film 5. In this manner, the inside of the wiring trench 4 is formed with the Cu wiring 15 (Cu conductive layer 10) in a state surrounded by the BM film 5, whereby the Cu wiring structure 18 having the damascene wiring structure is manufactured.

As shown in FIGS. 1 to 4, the manufactured Cu wiring structure 18 is disposed in plural in the semiconductor device A, and is usually connected in a double layer. Therefore, a semiconductor device A having a structure in which a double-layered Cu wiring structure 18 (hereinafter referred to as a first layer 18a and a second layer 18b) is connected with a via hole will be described below with reference to FIGS. 5 to 8. Manufacturing process. In addition, in FIGS. 5 to 8, the same components as those in the above-described FIGS. 1 to 4 are denoted by the same reference numerals.

First, as shown in FIG. 5, for example, referring to FIGS. 1 to 4, a Cu wiring structure 18 (first layer 18a) is manufactured by the above method, and wiring holes and wiring trenches are formed thereon by an arbitrary method. 4 interlayer insulating film 2. Next, as shown in FIG. 6, the BM film 5 and the Cu plating seed layer 7 are continuously formed as in the inner surface of the wiring trench 4 as in the above-described FIG.

Then, as shown in FIG. 7, the Cu conductive layer 10 is formed in the same manner as the wiring trench 4 is buried from above the Cu plating seed layer 7. In the state in which the Cu conductive layer 10 is embedded, annealing treatment or heat cycle treatment of the present invention described later is performed in order to stabilize the film, and then the Cu conductive layer 10 and the BM film are formed as shown in FIG. 5 remains inside the wiring trench 4, and the Cu conductive layer 10 and the BM film 5 exposed on the upper portion of the wiring trench 4 are removed by a CMP method to form a Cu wiring structure 18 (second layer 18b). The Cu wiring structure called a so-called dual damascene structure is manufactured in such a manner that the semiconductor device A is double-layered. Further, the connection wiring connecting the first layer 18a and the second layer 18b in the semiconductor device A is referred to as a wiring of the via hole wiring 20.

In the formation of the Cu wiring structure 18 in the semiconductor device A shown in FIGS. 5 to 8 , since the heat treatment step is performed in order to stabilize the Cu conductive layer, the temperature rise and the temperature are lowered in the process. When the temperature rises and the temperature is lowered, thermal stress is generated at the interface between the materials due to the difference in thermal expansion of the different materials, and as a result, residual stress is generated inside the Cu wiring 15 . Further, as described above, in the processes of photolithography, reactive ion etching (RIE), and sputtering, temperature rise and temperature drop are also performed in the process.

The inside of the Cu wiring 15 inevitably has pores of an atomic size. Therefore, in the semiconductor device A having the structure in which the via hole is connected as shown in FIG. 8, for example, when residual stress generated inside the Cu wiring 15 acts in the vicinity of the via hole wiring 20, stress is caused by the structure. Concentration occurs in the vicinity of the via hole wiring 20 (particularly, the via hole 20 and the bonding portion 20a of the Cu wiring 15 in the first layer 18a). With this stress concentration, the pores dispersed in the Cu wiring are concentrated in the vicinity of the via wiring 20, and voids (voids) are formed inside the Cu wiring 15. Due to the formation of the voids in the Cu wiring 15, an increase in resistance or a wiring failure such as disconnection occurs, resulting in device failure.

Further, when the semiconductor device is fabricated into a product in a state in which residual stress is generated inside the Cu wiring 15, the internal pores are concentrated due to stress concentration due to the use of the device or the passage of time. The pores of the pores. Therefore, there is a concern that the life of the device is shortened.

Then, the inventors of the present invention found that the semiconductor device (that is, the substrate W to be processed) is finished after the treatment process of applying heat or heat to the semiconductor device, such as wiring formation processing or other sintering treatment or annealing treatment, is completed. By performing a thermal cycle process (at least a thermal cycle including a heating step and a heat removal step, preferably including a soaking step), stress concentration on the Cu wiring structure 18 or the via wiring 20 (especially Cu wiring) can be suppressed. In the joint portion with the via hole wiring, as a result, concentration (hole agglutination) of the voids in the semiconductor device can be suppressed. Hereinafter, the above findings will be described.

FIG. 9 is a graph showing conditions when a semiconductor device is subjected to a thermal cycle process after the completion of the processing step of applying heat or heat to the semiconductor device, such as wiring formation processing or other sintering treatment or annealing treatment. Further, in the conditions shown in Fig. 9, after the heat treatment step of heat treatment at 360 ° C, only heating and heat removal were performed for 1 hour (0.5 hr to 1.5 hr in Fig. 9), and thermal fatigue at this time was performed. The temperature ⊿T (temperature of heating and heat removal) was changed to 50 ° C, 100 ° C, 150 ° C, and 200 ° C to perform a thermal cycle process. In addition, the actual processing temperature can be due to thermal fatigue temperature ⊿T plus before the thermal cycling process or heat The actual processing temperature is obtained by the temperature after the cycle. The temperature before and after the heat cycle process is, for example, room temperature, and is 20 ° C in Fig. 9 .

Moreover, FIG. 10 is a view showing the hole concentration at the vicinity of the joint portion (hereinafter also referred to as a via hole joint portion) of the Cu wiring and the via hole wiring in the case where the thermal cycle process is performed under the conditions shown in FIG. A chart that changes the simulation results. In addition, FIG. 10 also illustrates the hole concentration and time variation at the interlayer hole joint portion in the case where the heat cycle process is not performed (⊿T=0° C.).

As shown in FIG. 9 and FIG. 10, the pore concentration at the joint of the mesopores at 1 hour after the enthalpy T is 50° C., 100° C., 150° C., and 200° C. is compared with the case where the thermal cycle process is not performed. To increase. On the other hand, the pore concentration at the via hole joint portion after 1000 hours in the case where ⊿T is 100 ° C, 150 ° C, and 200 ° C is reduced as compared with the case where the heat cycle process is not performed. In other words, in the semiconductor device in which the thermal cycle is performed at a temperature of 100 ° C, 150 ° C, and 200 ° C in the semiconductor device, the pore concentration is increased, but the concentration (pore agglomeration) of the pores is slowed. As a result, it was found that the concentration of voids at the junction of the via holes after a long period of time was lower than that of the semiconductor device which was not subjected to thermal cycling. Moreover, as shown in FIG. 10, it is understood that a preferable heating temperature in the case of performing a thermal cycle process is 150 ° C or more in order to effectively suppress the pore concentration and the time change at the via hole joint portion.

Further, Fig. 11 shows the pore concentration distribution (a) after 1000 hours at the via hole joint portion in the case where the heat cycle process is not performed, and the via hole in the case where the ⊿T is 200 °C for the thermal cycle process. The simulation result of the pore concentration distribution (b) after 1000 hours at the joint. From the results shown in Fig. 11, it is also known that the concentration of voids at the junction of the via holes after a long period of time in the semiconductor device in which thermal cycling is performed is lower than that of the semiconductor device which is not subjected to thermal cycling.

On the other hand, Fig. 12 and Fig. 13 are graphs showing simulation results for specifying the thermal fatigue temperature ⊿T for causing condensation and release of the pore concentration, and Fig. 12 shows the thermal fatigue load condition, Fig. 13 is Display so that ⊿T is 50 ° C, 100 ° C, 150 ° C, 200 ° C, and keep the temperature at In a certain case (that is, in the case of the condition shown in Fig. 12), the pore concentration at the interlayer joint portion (corner portion) changes with time. In addition, FIG. 13 also illustrates the hole concentration and time variation at the interlayer hole joint in the case where the heating step is not performed (⊿T=0° C.).

As shown in Fig. 13, when ⊿T is 100 ° C, 150 ° C, and 200 ° C, the increase and decrease of the pore concentration occur due to the heating step. That is, condensation and release of the pore concentration occur. On the other hand, when ⊿T is 50 ° C, the increase and decrease of the pore concentration, that is, the condensation and release of the pore concentration, are not caused by the heating step. Therefore, it is known that the thermal fatigue temperature ⊿T (heating temperature in the heat cycle process) at which the pore concentration at the interlayer pore joint portion can be lowered by the condensation and release of the induced pore concentration is 100 ° C or higher.

On the other hand, FIG. 14 is a graph showing conditions in a thermal cycle process including a heating step, a soaking step, and a heat removing step of the semiconductor device after the processing step of applying heat or heat to the semiconductor device is completed. Fig. 15 shows a graph showing the results of the simulation of the pore concentration and the time change at the via hole joint portion in the case where the thermal cycle process was carried out under the conditions shown in Fig. 14. Moreover, as a condition of the thermal cycle process shown in FIG. 14, the thermal fatigue temperature ⊿T was 200 ° C, and the soaking time t _{3 was} changed to 0 hr, 0.5 hr, 2 hr, and ∞ (infinity). Further, when t ₃ is 0 hr, since the soaking time is 0 hr, it is the same as the case where ⊿T shown in Fig. 9 is 200 °C. Further, when t ₃ is ∞, since the soaking time is ∞, it is the same as the case where ⊿T shown in Fig. 13 is 200 °C. Further, Fig. 15 also shows the change in the concentration of the pores at the junction of the via holes in the case where the thermal cycle process is not performed. The heating step here is heated to a specific temperature (for example, ⊿T is 100 ° C or higher) to release the pore condensation, and the soaking step is maintained until the end of the release of the pore condensation.

14, FIG. 15, the semiconductor device was warmed to compare the retention time (soaking time) t ₃ is the case where 0hr, and t ₃ to 0.5hr, 2hr case when the vacancy concentration in a state of 200 ℃ After the change, it was found that the soaking time t ₃ was 0.5 hr and 2 hr, and the pore concentration at the junction of the mesopores was suppressed to be low. Further, as shown in Fig. 15, when t ₃ is ∞ (infinity), the pore concentration and time change from 1 hour to 100 hours are not suppressed. Therefore, it has been found that there is a preferred soaking time t ₃ in the thermal cycle process, for example, the preferred soaking time t _{3 is} from 0 hr to 2 hr from the data of FIG. 15 . Further, since the treatment time is preferably as short as possible from the viewpoint of productivity, the preferred soaking time t3 is 0 hr or more and 0.5 hr or less. Furthermore, if the heat removal time in the heat removal step is long, voiding may occur due to heat removal, so that the heat removal time is also shorter.

Moreover, FIG. 16 is a graph showing the conditions of the thermal cycle process in the case of changing the heat removal time in the heat cycle process including the heating step, the soaking step, and the heat removal step, and FIG. 17 shows the condition shown in FIG. In the case of a thermal cycle process, a plot of the hole concentration at the interfacial well junction and the time-varying simulation results. Further, as a condition of the heat cycle step shown in Fig. 16, the thermal fatigue temperature ⊿T was 200 ° C, the soaking time t ₃ was 0.5 hr, and the heat removal time t _{4 was} changed to 0.5 hr, 1 hr, and 2 hr. In addition, FIG. 11 also illustrates the hole concentration and time variation at the interlayer hole joint portion in the case where the heat cycle process is not performed.

16 and 17, it is found that the shorter the time (heat removal time) t _{4 of} heat removal of the semiconductor substrate heated to 200 ° C, the lower the pore concentration at the via hole joint portion is suppressed. That is, it can be known that in the case of performing heat removal in the heat cycle process, the heat removal time t _{4 is} shorter, that is, the cooling rate in the heat removal is faster. Here, as a preferable cooling rate, the data of FIG. 17 is 100 ° C / h or more.

As described above, from the data shown in FIG. 9 to FIG. 17, it is found that the semiconductor device is subjected to a thermal cycle process after the processing step of applying heat or heat to the semiconductor device, such as wiring formation processing or other sintering treatment or annealing treatment. The hole concentration at the Cu wiring structure 18 or the via hole wiring 20 (particularly, the via hole junction portion) is suppressed from changing with time. Further, it is also estimated that the conditions for temporal change of the pore concentration are efficiently suppressed in the thermal cycle step.

Further, it is estimated from the above data that the pore concentration is related to the diffusion due to the pore condensation and the pore concentration gradient caused by the stress in the semiconductor device. That is, when the temperature rises, the pore condensing speed increases due to the stress and the pore concentration increases, but the pore condensing speed has a maximum value, and decreases after becoming a certain temperature or higher. On the other hand, if the pore concentration gradient becomes large due to the condensation of the pores, the diffusion speed becomes large. Therefore, the pore concentration decreases due to the decrease in the pore condensation rate caused by the stress and the increase in the diffusion speed caused by the pore concentration gradient, and the void in the wiring is caused by the release of the pore condensation. Concentration will be suppressed.

According to the above findings, in the semiconductor device manufacturing process, by performing the thermal cycle process under favorable conditions, it is possible to suppress the occurrence of aggregates (cavities) called pores in the so-called pores in the Cu wiring, thereby suppressing The Cu wiring is called the occurrence of wiring defects such as disconnection of stress migration. In addition, in the semiconductor device manufacturing process, by performing the thermal cycle process under favorable conditions, it is possible to suppress the occurrence of voids in the Cu wiring structure or the via hole joint portion after a long period of time after the product is formed. The concentration rises, so the device life of the semiconductor device can be extended.

Although an example of the embodiment of the present invention has been described above, the present invention is not limited to the form shown in the drawings. It is to be understood that those skilled in the art to which the present invention pertains may be able to make various changes or modifications in the scope of the invention as described in the appended claims.

For example, in the above-described embodiment, a mosaic wiring structure (particularly a dual damascene wiring structure) is exemplified as the Cu wiring structure in the semiconductor device A, but the manufacturing method of the thermal cycle process of the present invention can also be applied. A general Cu wiring structure other than the wiring structure.

The present invention is applicable to a method of manufacturing a semiconductor device and a semiconductor device.

1‧‧‧Substrate body

2‧‧‧Interlayer insulating film

4‧‧‧ wiring trench

5‧‧‧Resistance metal (BM) layer

10‧‧‧Cu conductive layer

15‧‧‧Cu wiring

18‧‧‧Cu wiring structure

18a‧‧‧1st floor

18b‧‧‧2nd floor

20‧‧‧Interlayer wiring

20a‧‧‧ joints

Claims (12)

A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a copper wiring structure, which is a thermal cycle process of heating and removing heat of a substrate to be processed after formation of a copper wiring layer including heat treatment. The method of manufacturing a semiconductor device according to claim 1, wherein the heating temperature in the thermal cycle is 100 ° C or higher. The method of manufacturing a semiconductor device according to claim 1, wherein the heat cycle is performed after heating for 2 hours or more. The method of manufacturing a semiconductor device according to claim 1, wherein the heat removal in the heat cycle is performed at a cooling rate of 100 ° C / h or more. A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a damascene wiring structure, which is a thermal cycle process of heating and removing heat of a substrate to be processed after wiring formation. The method of manufacturing a semiconductor device according to claim 5, wherein the heating temperature in the heat cycle step is 100 ° C or higher. The method of manufacturing a semiconductor device according to claim 5, wherein the heat cycle is performed after heating for 2 hours or more. The method of manufacturing a semiconductor device according to claim 5, wherein the heat removal in the heat cycle is performed at a cooling rate of 100 ° C / h or more. A semiconductor device is a semiconductor device having a damascene wiring structure, which is subjected to a thermal cycle of heating and removing heat of a substrate to be processed after wiring is formed. The semiconductor device of claim 9, wherein the heating temperature in the thermal cycle is 100 ° C or higher. The semiconductor device of claim 9, wherein in the thermal cycle, the soaking within 2 hours after heating is performed. The semiconductor device of claim 9, wherein the thermal cycle The heat removal system is carried out at a cooling rate of 100 ° C / h or more.