KR100886257B1 - Method For Fabricating Copper Damascene - Google Patents

Abstract

A copper damascene formation method capable of suppressing void generation and producing a highly reliable copper wiring is disclosed. Copper damascene formation method according to the invention comprises the steps of forming a first insulating layer 320 on the substrate 310; Selectively etching the first insulating layer 320 to form the lower trench 324; Filling the lower trench 324 with the first copper layer 330; Forming a second insulating layer 340 on the first insulating layer 322 and the first copper layer 330; Selectively etching the second insulating layer 340 to form the via holes 344 and the upper trenches 346; And filling the second copper layer 350 on the via hole 344 and the upper trench 346. In particular, the present invention provides a first copper layer in the lower trench 324 with a portion of the non-etched insulating layer 326 remaining on the lower trench 324 in the step of selectively etching the first insulating layer 320. 330 is filled.

Metal wiring, reliability, copper damascene, wiring defect, void

Description

Method for Fabricating Copper Damascene}

1 is a view showing a conventional method for forming copper damascene.

2 is a view showing a conventional method for forming copper damascene.

3 is a diagram illustrating a real time crystal growth process of a copper plating layer.

4 shows the microstructure of a copper plating layer.

Figure 5 is a schematic diagram showing a mechanism for suppressing the generation of grain triple point of the copper plating layer in the present invention.

6 is a view showing a copper damascene formation method according to an embodiment of the present invention.

Description of the main parts of the drawing

310: silicon wafer

320, 340: first and second insulating layers

330 and 350: first and second copper layers

324, 346: lower and upper trenches

326: insulator structure

344: Via Hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a copper damascene formation method, and more particularly, to a copper damascene formation method capable of producing highly reliable copper wiring by suppressing the formation of voids that cause wiring defects.

Semiconductors are formed by stacking integrated circuits on a single chip. In recent years, design rules have become increasingly strict according to the high integration trend of semiconductors. As a result, the process of forming a multi-layer wiring in semiconductor manufacturing has become even more important, and has become a major factor in determining yield and reliability of devices.

Meanwhile, with the trend of higher integration of semiconductors, as the gap between transistors decreases, the problem of RC delay (resistance capacitance delay) becomes important, and copper, which has lower electrical resistance than aluminum, which has been used as a conventional wiring material, is spotlighted as a new wiring material. However, copper has a fatal disadvantage that it is difficult to dry etch compared to aluminum, so that its application as a wiring material has been limited. However, such a problem of copper has been solved by the development of a copper damascene process, and as a result, copper is increasingly employed as a wiring material for semiconductors.

In the copper damascene process, a trench pattern of an insulator is formed on a silicon wafer in advance, and copper is filled in the trench by using an electroplating method, and then unnecessary copper formed in a region other than the trench is removed by CMP (Chemical Mechanical Polishing). As a method, copper wiring can be formed without using the dry etching process of copper.

However, the copper damascene process has a problem in that voids are generated on the copper wiring. It is known that the main reason for the voids is due to the thermal stress caused by the accumulation of thermal budget by the subsequent heat treatment process following the wiring formation. Such voids cause a serious decrease in the reliability of the copper wiring, such as increasing the resistance of the copper wiring or even shorting the copper wiring. Accordingly, various attempts have been made to improve the reliability of copper wiring.

1 is a view showing a method of improving the reliability of the copper wiring disclosed in US Patent No. 6,737,351. The method of FIG. 1 is based on the theory that the supersaturated atomic vacancy remaining in the copper film is diffused and aggregated through a stress gradient to a region where stress concentration is caused by a via hole pattern, thereby forming voids. It is a method of suppressing the generation of voids by blocking the inflow of the atomic vacancy from the peripheral area as much as possible by blocking the peripheral part of the contact area. As shown in FIG. 1, in the method of FIG. 1, a lower layer pattern 110 having a large line width and an upper pattern 120 having a narrow line width are formed at an upper end thereof, and a via hole 130 penetrating through layers for electrical connection between upper and lower layers. In the structure that is formed, the area in contact with the via hole 130 of the lower pattern 110 in order to minimize the generation of voids due to the diffusion of atomic vacancies appearing in the area in contact with the via hole 130 of the lower pattern 110. It is characterized in that to install the insulating buffer (150, 160) that can block the peripheral portion of the maximum to suppress the inflow of atomic vacancy. However, since the method of FIG. 1 basically requires an insulating buffer part, manual work is required when designing a wiring, which makes it difficult to automate the process. In the case of using a wrong pattern formed by manual work, process time and process cost are required. There is a problem to increase.

2 is also a view showing a method of improving the reliability of another copper wiring disclosed in US Patent No. 6,737,351. As shown in FIG. 2, the method of FIG. 2 manufactures two via holes 130 and 140 in the upper pattern 120 having a small line width, and the two via holes 130 and 140 contact the lower pattern 110 having a large line width at the same time. In such a way, even if one via hole is electrically shorted, the current can be maintained through the other remaining via hole. However, the method of FIG. 2 has been pointed out as a problem in the process hassle for forming two via holes.

In addition, a method of using a copper-aluminum alloy as a wiring material instead of copper, as in the case of aluminum wiring, has also been proposed, but this method also has a problem in that the process cost increases, CMP is difficult for copper-aluminum, and wiring resistivity becomes large. .

Accordingly, an object of the present invention is to provide a copper damascene formation method capable of producing a highly reliable copper wiring by suppressing the formation of voids on the copper wiring as a solution to the conventional problems as described above. have.

In order to achieve the above object, the copper damascene forming method according to the present invention comprises the steps of selectively etching the insulating layer to form a trench; And filling copper in the trench, wherein the copper is filled in the trench with a portion of the non-etched insulating layer remaining on the trench in the selective etching of the insulating layer.

And, in order to achieve the above object, the copper damascene forming method according to the present invention comprises the steps of forming a first insulating layer on the substrate; Selectively etching the first insulating layer to form a lower trench; Filling the lower trench with a first copper layer; Forming a second insulating layer on the first insulating layer and the first copper layer; Selectively etching the second insulating layer to form a via hole and an upper trench; And filling a second copper layer on the via hole and the upper trench, wherein the lower portion of the lower trench is left in the lower trench with a portion of the non-etched insulating layer remaining on the lower trench in the selective etching of the first insulating layer. The trench is filled with the first copper layer.

In addition, the method may further include sequentially forming a barrier metal layer and a seed layer before filling the first and second copper layers.

The barrier metal layer may be formed of a single layer composed of any one of Ta, TaN, TaAlN, TaSiN, TaSi2, Ti, TiN, WN, TiSiN, or a plurality of layers composed of a combination thereof.

The barrier metal layer may have a thickness in the range of 50 to 1,000 mm 3.

The seed layer may be a metal including Cu, Pt, Au, Ag, Ni, or an alloy thereof.

The seed layer may have a thickness in the range of 100 to 5,000 microns.

The first and second copper layers may be formed using an electroplating method.

The method may further include removing a portion of the first and second copper layers by chemical mechanical polishing (CMP) after the filling of the first and second copper layers.

The method may further include annealing the first and second copper layers before removing a portion of the first and second copper layers by chemical mechanical polishing (CMP).

The first and second copper layers may be annealed at a temperature of 100 to 300 ° C. and for a time of 1 to 3,600 minutes.

The non-etched insulating layer may be disposed near the via hole.

The non-etched portion of the insulating layer may include at least one insulator structure, and the structure may surround a portion around the via hole.

The structure may serve to suppress the growth of the crystal grains of the first copper layer in a predetermined direction.

Hereinafter, the configuration of the present invention will be described in detail with reference to the accompanying drawings.

First of all, the present inventors have found that the cause of voids on the copper wiring in the copper damascene process is not caused by the stress concentration phenomenon caused by the above-described via hole pattern, but when the copper plating layer is grown in the trench. This is derived from the idea that the triple point of grain size of the copper plating layer is formed. In other words, the present inventors regard that the triple point of the crystal grains formed during the growth of the copper plating layer becomes a void, and when the void is placed inside the via hole, defects in the copper wiring are generated, and generation of voids is possible if the formation of the triple point can be suppressed. The present invention has been made in view of the fact that it can be suppressed.

That is, in the case of forming a copper wiring through a copper damascene process, the insulating layer is selectively etched to form a trench, and the trench is filled through copper plating. Although there is no significant difference, the subsequent heat treatment of the copper plated layer, the growth behavior of the copper grains varies depending on the line width of the trench, and as a result, the triple point formation of the copper grains is also changed. Here, the triple point of crystal grains means a portion where crystal grains which have grown in three different directions meet each other.

In addition, the present inventors also found that when the copper plating layer grows in a trench having a small line width, the grain growth direction of the copper is limited in a specific direction, so that triple points of the crystal grains are not formed, so that generation of voids is difficult. That is, in the copper damascene process, it was observed that wiring defects caused by voids did not occur at the portion where the trench and the via hole having a small line width met.

This result is in contrast with that in the case of the conventional aluminum wiring formation, a large number of wiring defects caused by voids are generated at a portion where a pattern having a small line width and a via hole meet. There are two reasons for this opposite result. First, in the case of aluminum wiring, an aluminum layer is formed by physical vapor deposition and heat-treated to grow aluminum grains, and then patterned. Therefore, the structure of aluminum grains affects the size of line widths unlike copper. Because do not receive. In addition, the passivation process is performed after the wiring is formed because the thermal stress caused by the passivation is more likely to be generated in the pattern having the smaller line width.

The mechanism of void growth in the copper damascene process as described above can be confirmed through experimental results as shown in FIGS. 3 and 4.

3A and 3B show the results of observing the crystal growth behavior of the copper plating layer. The crystal orientation of the copper plating layer can be observed by analyzing electron backscattered diffraction. Each color in the figure represents the orientation of the crystal in the vertical direction. As shown, red corresponds to {5 1 1}, blue corresponds to {1 1 1}, ultramarine blue corresponds to {5 7 13}, and {1 1 1} and {5 7 for {5 1 1} 13} each have a twin grain relationship.

In FIGS. 3A and 3B, I to VIII indicate crystal growth directions of the copper plating layer, and Table 1 shows the results of measuring crystal orientations in the I to VIII directions. In Table 1, ND, GD, TD and TD 'are calculated by the normal direction, the apparent growth direction, the transverse direction observed during growth, ND and GD, respectively It means a calculated transverse direction. As shown in Table 1, in most cases, the TD is in the <1 1 0> direction, and assuming that the crystal growth direction is the <1 1 1> direction, it can be seen that the direction transferred to the corresponding ND plane becomes GD. This indicates that the crystal growth direction is <1 1 1>.

TABLE 1

This can be confirmed through FIG. 3C. 3C is a diagram illustrating GD and TD that may appear when the ND plane directions of the copper crystals are <5 1 1> and <1 1 1>, for convenience, as <1 0 0> and <1 1 1>. . If the growth plane of the crystal is assumed to be in the <1 1 1> direction, it is <1 1 0> in the {1 0 0} plane, and the <1 1 1> direction in the crystal growth direction is in the {1 0 0} plane. In the {1 1 1} plane, it can be seen that the crystal growth direction is represented by <1 1 2>. Also, it can be seen that in both cases, the TD is <1 1 0>.

Taken together, it can be seen that the growth of the copper crystal proceeds toward the <1 1 1> direction as a whole. In particular, when twin grain boundaries occur, it can be observed that Σ3 twin grain boundaries have a 60 degree rotational relationship in the crystal growth direction (<1 1 1> direction). If so, it can predict the direction of crystal growth.

FIG. 4 is a view showing the results of observing the microstructure around the voids generated when copper plating is formed in trenches having a large line width (10 μm × 10 μm). 4 shows the grain interface of the copper plating layer on the far right, from which the mechanism of void growth can be confirmed. At this time, the portion indicated by the black line is the grain boundary interface and the portion indicated by the white line is the twin grain boundary surface, and it is possible to track the progress of copper crystal growth by connecting an arrow (white arrow in the photo) perpendicular to the twin grain boundary surface.

From these experimental results, the grain boundary is formed at the point where the grains that have been grown in different directions meet, and the grain triple point is formed where the grains which have been grown in three different directions meet, and the void is generated at the grain triple point. It can be seen (in the far right picture of FIG. 4, the dark blue void region is the point where the white arrows of three different directions meet). Taken together, it can be expected that when the growth of copper crystals in a specific direction is blocked, grain triplets can be suppressed, and as a result, generation of voids can also be suppressed.

FIG. 5 is a diagram illustrating a triple point formation inhibition model of grains based on the experimental results of FIG. 4. This model forms the basis of the present invention. The basic principle is as follows. That is, as can be seen from Figure 4, when the growth of the copper crystals in a particular direction is blocked, since the formation of grain triple point is suppressed, when the structure is formed to block the growth of copper crystals in a particular direction when forming the copper wiring It is possible to suppress the occurrence of voids. In this case, the structure is preferably installed in a region where voids occur well, that is, in a region where the trench and the via hole having a large line width having a high probability of void generation in the copper damascene process are in contact with each other.

5 shows a model for installing a structure that can block the growth of copper crystals in a specific direction near the via hole.

Referring to FIG. 5A, first, the size of the via hole 230 is assumed to be a square having a diameter of 0.2 μm (the actual shape of the mask of the via hole is not a circle but a square). Assume a frame. Subsequently, a space about about the space where the via hole contacts is opened, and when the blocking structure 250 having a length of about 3 spaces (for example, 0.6 μm) is installed, the blocking structure 250 is separated from the contact portion of the via hole 230. It is possible to block the growth of copper crystals in the direction toward. On the other hand, the material of the blocking structure is preferably made of an insulator such as silicon oxide in consideration of the overall copper damascene process, which will be described in detail below.

To more reliably inhibit copper growth in a particular direction, the number and shape of the barrier structures can be changed. Referring to FIG. 5B, two independent structures 250 for blocking two left and right directions based on the via hole 230 may be installed. In addition, referring to FIG. 5C, one structure 250 may be installed to block two upper and left directions based on the via hole 230. In addition, referring to FIG. 5D, one structure 250 may be installed to block three upper and left directions based on the via hole 230. In addition, various types and structures can be installed near the via holes to suppress copper growth in a specific direction.

FIG. 6 is a view illustrating a copper damascene formation method according to one embodiment of the present invention, in which the triple point formation suppression model described in FIG. 5 is applied to a copper damascene process. As shown, this embodiment is a case of applying the model of FIG. 5 by taking a dual damascene process of the copper damascene process as an example, but is not necessarily limited thereto and is applied to a single damascene process. It is also possible. Dual damascene and single damascene processes are well known in the art and thus a detailed description thereof will be omitted herein.

Referring to FIG. 6A, a first insulating layer 320 is formed on the silicon wafer substrate 310. A lower trench having a large line width is formed in the first insulating layer 320. The first insulating layer 320 may include silicon oxide.

Referring to FIG. 6B, the first insulating pattern layer 322 is formed by selectively etching the first insulating layer 320 using a conventional photolithography process. The lower trench 324 having a large line width is formed by the first pattern layer 322. The width of the lower trench 324 may be in the range of 1 μm to 100 μm and the depth of 0.1 μm to 3 μm. Conventional photolithography processes are already known in the art, and thus a detailed description thereof will be omitted herein.

Meanwhile, in the process of selectively etching the first insulating layer 320, a structure 326 capable of suppressing copper growth in a specific direction as described above is formed. That is, in the present invention, since the structure 326 is formed at the same time as the lower trench in the lower trench forming step, there is no additional process according to the installation of the structure 326. Thus, the material of the structure 326 is the same as the material of the first insulating layer 320 and the first insulating pattern layer 322, the structure 326 may include silicon oxide.

FIG. 6I is a top view of the lower trench 324 pattern after completing the step of FIG. 6B. As shown, two independent structures 326 are installed on the left and right sides of the lower trench 324 based on the positions at which the via holes are to be formed in the future, which is the case when the model of FIG. 5B is applied. do.

Referring to FIG. 6C, a first copper layer 330 is filled in the lower trench 324. The first copper layer 330 may be formed using an electroplating method. The thickness of the first plating layer 330 is preferably adjusted to be at least such that the lower trench 324 is completely filled. Therefore, it is usually appropriate to plate about 120 to 150% of the height of the lower trench 324 so that the thickness of the first plating layer 330 is greater than or equal to the height of the lower trench 324.

Meanwhile, a barrier metal layer and a seed layer may be sequentially formed on the lower trench 324 before filling the lower trench 324 with the first copper layer 330. . Here, the barrier metal layer serves to prevent the copper atoms of the first copper layer 330 from diffusing to the silicon wafer substrate 310, and the seed layer forms an electrode when the first copper layer 330 is formed by electroplating. Plays a role. At this time, the barrier metal layer may be composed of a single layer composed of any one of Ta, TaN, TaAlN, TaSiN, TaSi2, Ti, TiN, WN, TiSiN, or a plurality of layers composed of a combination thereof, the thickness of the barrier metal layer is 50 to It may be in the range of 1,000 ms. In addition, the seed layer may be a metal including Cu, Pt, Au, Ag, Ni, or an alloy thereof, and the thickness of the seed layer may range from 100 to 5,000 mm 3. In addition, the barrier metal layer and the seed layer may be formed using physical vapor deposition or chemical vapor deposition.

Referring to FIG. 6D, the unnecessary first copper layer 330, that is, the first copper layer 330 formed beyond the height of the lower trench 322 is removed. The first copper layer 330 may be removed using a chemical mechanical polishing (CMP) method. In the process of removing the first copper layer 330, the barrier metal layer and the seed layer formed on the first insulating pattern 322 may be removed together.

6J is a top view of the lower trench 324 pattern after completing the step of FIG. 6D. As shown in the figure, two independent structures 326 are installed at both left and right sides of the lower trench 324 based on the position at which the via hole is to be formed in the future, and the first metal layer 330 is disposed in the other lower trench 3240. You can see that) is filled.

Meanwhile, before removing the first copper layer 330 using CMP, the first copper layer 330 may be annealed. The annealing temperature may be in the range of 100 to 300 ° C. and the annealing time in the range of 1 to 3,600 minutes.

Referring to FIG. 6E, a second insulating layer 340 is formed on the first insulating pattern 322 and the first copper layer 330. In the second insulating layer 340, a via hole and an upper trench having a small line width are formed. The second insulating layer 340 may include silicon oxide.

Referring to FIG. 6F, the second insulating pattern layer 342 is formed by selectively etching the second insulating layer 340 using a conventional photolithography process. The via hole 344 and the upper trench 346 having a small line width are formed by the second insulating pattern layer 342. As a result, the structure 326 capable of suppressing copper growth in a particular direction is disposed near the via hole 344 to surround a portion around the via hole 344. The via hole 324 may have a width of 0.01 μm to 0.5 μm and a depth of 0.1 μm to 5 μm. In addition, the upper trench 326 may have a width of 0.01 μm to 100 μm and a depth of 0.1 μm to 1 μm.

Referring to FIG. 6G, the second copper layer 350 is filled in the via hole 324 and the upper trench 326. The second copper layer 350 may also be formed using an electroplating method. The thickness of the second plating layer 350 may be adjusted to at least fill the via hole 324 and the upper trench 326. Therefore, it is usually appropriate to plate about 120 to 150% of the height of the upper trench 326 so that the thickness of the second plating layer 350 is equal to or greater than the height of the upper trench 326.

Referring to FIG. 6H, the unnecessary second copper layer 330, that is, the second copper layer 350 formed beyond the height of the upper trench 346 is removed. The second copper layer 350 may also be removed using the CMP method.

Meanwhile, like the first copper layer 330, the second copper layer 350 may also form the barrier metal layer and the seed layer before the FIG. 6g step, and may anneal the second copper layer 350 before the FIG. 6h step. have. Barrier metal layer and seed layer formation conditions and annealing conditions are the same as in the case of the first copper layer. In addition, the barrier metal layer and the seed layer formed on the second insulating pattern 342 may be removed together in FIG. 6H.

Thereby, the copper damascene process which can form the copper wiring by which void generation is suppressed is completed. That is, the present invention is a structure pattern installed in the peripheral portion connected to the via hole when the copper layer filled in the trench pattern through plating grows from the initial fine grain (about tens of nm in diameter) to coarse grain (diameter of several μm or more) By controlling the recrystallization growth direction of the copper crystal grains (that is, suppressing the growth of the copper crystal grains in a specific direction), it is possible to suppress the formation of the triple point of the grain boundary. Therefore, the copper damascene formation method which concerns on this invention can suppress the generation | occurrence | production of the defect (void) of a copper wiring, and can improve the reliability of a copper wiring.

Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above embodiments and various modifications made by those skilled in the art without departing from the spirit of the present invention. Modifications and variations are possible. Such modifications and variations are intended to fall within the scope of the invention and the appended claims.

According to the present invention, there is an effect of suppressing a phenomenon in which voids are generated on a copper wiring when copper damascene is formed, thereby producing a highly reliable copper wiring.

Claims (14)

Selectively etching the insulating layer to form a trench; And Filling the trench with a copper layer Including; In the step of selectively etching the insulating layer, the copper layer is filled in the trench with a portion of the non-etched insulating layer remaining on the trench, and the non-etched portion of the insulating layer has a predetermined grain size of the copper layer. A copper damascene formation method, which serves to suppress growth in a direction. Forming a first insulating layer on the substrate; Selectively etching the first insulating layer to form a lower trench; Filling the lower trench with a first copper layer; Forming a second insulating layer on the first insulating layer and the first copper layer; Selectively etching the second insulating layer to form a via hole and an upper trench; And Filling a second copper layer over the via hole and the upper trench; Including; Selectively etching the first insulating layer to fill the lower trench with the first copper layer while the non-etched insulating layer remains on the lower trench; 1 The copper damascene formation method which functions to suppress the growth of the crystal grain of a copper layer to a predetermined direction. The method of claim 2, And sequentially forming a barrier metal layer and a seed layer before filling the first and second copper layers. The method of claim 3, The barrier metal layer is a copper damascene formation method, characterized in that consisting of a single layer consisting of any one of Ta, TaN, TaAlN, TaSiN, TaSi2, Ti, TiN, WN, TiSiN or a plurality of combinations thereof. The method of claim 3, The thickness of the barrier metal layer is a copper damascene forming method, characterized in that the range of 50 to 1,000Å. The method of claim 3, The seed layer is a copper damascene formation method, characterized in that the metal containing Cu, Pt, Au, Ag, Ni or alloys thereof. The method of claim 3, The thickness of the seed layer is a copper damascene forming method, characterized in that in the range of 100 to 5,000Å. The method of claim 2, Wherein said first and second copper layers are formed using electroplating. The method of claim 2, And removing a portion of the first and second copper layers by chemical mechanical polishing (CMP) after filling the first and second copper layers. The method of claim 9, And annealing the first and second copper layers prior to removing portions of the first and second copper layers with chemical mechanical polishing (CMP). The method of claim 10, The first and second copper layers are annealed in a temperature range of 100 to 300 ° C., time 1 to 3,600 minutes. The method of claim 2, And wherein the unetched portion of the insulating layer is disposed near the via hole. The method of claim 12, And wherein the non-etched insulating layer comprises at least one insulator structure, the structure surrounding a portion around the via hole. delete

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