JP4234019B2 - How to rework the interconnect layer - Google Patents

Description

  The present invention relates generally to integrated circuit processes, and more particularly to a method adapted to an integrated circuit rework process on a semiconductor wafer.

  Currently, integrated circuit BEOL (post-semiconductor process line) rework processes are used for both ASIC (application specific integrated circuit) design qualification and normal production. These rework processes have been developed for both aluminum and copper multilevel metal interconnects and are commonly used to correct yield or reliability problems or photomask errors. Such a rework process enables QTAT (short turn around time) design verification and saves integrated circuit manufacturing costs. An example of a rework process is given in US Pat. No. 6,332,988, the entire disclosure of which is incorporated by reference, wherein a process for reworking an electroplated solder bump wafer is disclosed. Is done.

The introduction of copper and low dielectric constant (k) technology provides an opportunity for additional rework process definition. This is because the physical and chemical properties of low-k dielectric materials are significantly different from silicon dioxide and are therefore not amenable to similar rework methods. Such a rework process is integrated into a POR BEOL (process of record back-end-of-line) process sequence, which remains flat throughout the rework process, and Si ₃ N ₄ , low-k organic dielectric The top surface of the dielectric and tungsten interconnect region that removes many thin films, including body, copper, and liner material, and is present on an electronic active device such as a transistor (typically called the front end) Need to stop on. The dielectric in this region is typically boron doped SiO ₂ or “BPSG” (phosphorborosilicate glass). Within the BPSG, an electrical conductor made of tungsten damascene is typically used and can therefore be abbreviated as “BPSG / W”. Some conventional processes teach how to rework a defective SiLK® layer caused by improper coating, for example due to a photoresist lithography process. However, these conventional processes do not address the reintegration of the final integrated metal in addition to the dielectric BEOL.

  In addition, the integrated circuit device dimensions are reduced corresponding to each of the following technologies, so that the pitch at the lower interconnect level is less than that of photolithographic overlay shorting, copper vias / copper vias in low-k materials. Be challenging with regard to via resistance, metal line / metal line capacitance, and metal level / metal level cooling issues.

  Thus, an additional vertical space is created between some or all BEOL levels, providing a means to facilitate removal and reconstruction of defective BEOL levels, with respect to overlay, via resistance, line capacitance, and cooling. There is a need for an integrated circuit rework process that can be a means of ensuring a desired process window latitude.

  The present invention has been made in view of the foregoing, and it is an object of the present invention to provide a method for both single chip interconnect or interconnect metal level and multilevel rework processes.

  In accordance with one aspect of the present invention, a method is provided for reworking a damascene metallurgy BEOL (post-process line) interconnect level, wherein each of the levels is embedded in a plurality of dielectric layers. A line portion and a via portion. The method includes sequentially removing interconnect levels by selectively removing a plurality of dielectric layers starting from the top dielectric layer. The interconnect level line and via portions are then exposed. The exposed line and via portions at the interconnect level are then coplanar. Finally, replace the removed interconnect level with the complete interconnect level of Damascene Metallurgy.

  Further, a plurality of dielectric layers are formed by laminating the first dielectric layer on the second dielectric layer, wherein the first dielectric layer is a material having a lower dielectric constant than the second dielectric layer. including. Also, the plurality of dielectric layers are removed from the top dielectric layer to the scratch stop layer located below the lowest level of the BEOL interconnect level. Further, the line portion and the via portion form a wiring conductor, and the wiring conductor includes copper. In addition, the line and via portions are removed at a faster rate than the plurality of dielectric layers.

The method further includes the step of depositing a polish stop layer over the exposed line and via portions, wherein the polish stop layer is up to a thickness coplanar with the bottom dielectric layer. Makes it possible to remove the part. Further, a plurality of dielectric layers including a first dielectric layer and a second dielectric layer are formed, wherein the first dielectric layer and the second dielectric layer have different removal characteristics. The via portion at the first interconnect level is connected to the via portion at the second interconnect level, wherein the via portion at the first interconnect level is formed smaller than the via portion at the second interconnect level. In addition, the method further includes depositing a cap hard mask layer over the exposed line and via portions, the cap hard mask layer comprising nitride, oxide, Si ₃ N ₄ , TaN, Contains one of Ta or W.

  Alternatively, a method for reworking a damascene metallurgy BEOL (post process line) metallization level includes forming multiple BEOL metallization levels on a substrate and lines within the BEOL metallization level. Forming a portion and a via portion; selectively removing at least one of the BEOL metallization levels to expose line portions and via portions; and removing the removed BEOL metallization level to at least one new Replacing the BEOL metallization level, wherein the BEOL metallization level includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a lower dielectric constant than the second dielectric layer. Contains materials.

  The present invention provides an integrated circuit structure having a first section that includes logic and functional devices and an interconnect layer over the first section. Each of the interconnect layers includes a first insulator layer, a second insulator layer over the first insulator layer, and electrical wiring within the first insulator layer and the second insulator layer. The first insulator layer has a lower dielectric constant than the second insulator layer, and the second insulator layer is harder than the first insulator layer.

The second layer includes a protective layer that protects the first layer during the rework process performed on the overlying interconnect layer. The first insulator layer includes an organic insulator. The second insulator layer includes one of nitride, oxide, Si ₃ N ₄ , TaN, Ta, and W. The electrical wiring includes damascene copper. Each group of first insulator layer, second insulator layer, and electrical wiring constitutes a single interconnect layer within the structure.

  The present invention further provides a method for reworking such interconnect layers over the logic and functional layers of an integrated circuit structure. The method removes the upper insulator of the first interconnect layer and the first interconnect with a selective removal process that does not affect the upper insulator of the second interconnect layer located directly below the first interconnect layer. Remove layer electrical wiring and lower insulator. The upper insulator protects the lower insulator of the second interconnect layer during the process of removing the electrical wiring and lower insulator in the first interconnect layer. The process completely removes the first interconnect layer and leaves the second interconnect layer intact. An alternative interconnect layer is then formed instead of the first interconnect layer.

The process of removing the upper insulator also removes part of the lower insulator and exposes part of the electrical wiring. After removing the top insulator, the present invention optionally deposits a polish stop layer over the partially removed portion of the lower insulator and over the exposed portion of the electrical wiring. After deposition of the polish stop layer, the present invention removes the electrical wiring, leaving a partially removed portion of the first lower insulator and a portion of the polish stop layer. Subsequently, the polish stop layer is removed. The polish stop layer protects the lower insulator during the process of removing the electrical wiring.

  The present invention provides a structure including a protective hard insulator layer on a lower soft low dielectric constant (low k) layer within each interconnect layer. This structure allows each interconnect layer in the BEOL process layer to be removed individually. More specifically, in the first stage of the removal process, the upper hard dielectric is first removed (along with a portion of the lower soft low-k dielectric). Next, the remainder of the low-k dielectric and the metal wiring lines are removed in the second stage of the removal process. This second stage of the removal process does not affect the adjacent hard insulator of the interconnect layer located immediately below the interconnect layer being removed. Thus, the present invention is very selective, even if it is a low-k dielectric layer without affecting the next underlying layer (protected by its own upper hard protective insulator layer). ) Makes it possible to remove a single interconnect layer; This makes the BEOL layer rework much easier (by allowing a single layer to be reworked).

  Creates additional vertical space between some or all BEOL levels, providing a means to facilitate removal and reconstruction of defective BEOL levels, as desired for overlay, via resistance, line capacitance, and cooling There is a need for an integrated circuit rework process that can be a means of ensuring process window margin.

  Referring to the drawings, and in particular to FIGS. 1-30, preferred embodiments of the method and structure according to the present invention are shown. Specifically, a first embodiment of the present invention is described in FIGS. Traditionally, low-k dielectrics have not been used for the interconnect layer (BEOL process layer) formed on the logic / functional layer (BEOL process section) of the integrated circuit chip. The present invention provides a structure having a protective hard insulator layer on a lower soft low dielectric constant (low k) layer within each interconnect layer. This structure allows each interconnect layer in the BEOL process layer to be removed separately. More specifically, in the first stage of the removal process, the upper hard dielectric is first removed (along with a portion of the lower soft low-k dielectric). Next, the remainder of the low-k dielectric and the metal wiring lines are removed in the second stage of the removal process. This second stage of the removal process does not affect the adjacent hard insulator of the interconnect layer located immediately below and next to the interconnect layer being removed. Thus, the present invention is highly selective and is a low-k dielectric layer without affecting the next underlying layer (protected by its own upper hard protective insulator layer). Also) allows the removal of a single interconnect layer. This makes BEOL layer rework much easier (by allowing a single layer to be reworked). According to a first embodiment of the present invention, a novel multi-level rework process for copper / low kBEOL manufacturing is shown.

  The BEOL manufacturing process is configured to maintain flatness. This is because each subsequent metal level is typically formed using damascene and dual damascene techniques. In accordance with the present invention, the multi-level rework process substantially retains this flatness when the level and film are removed simultaneously. A method for realizing this multi-level, multi-film removal is given by the first embodiment of the present invention.

In FIG. 1, a multilevel integrated circuit structure 100 formed on a BPSG / W substrate 110 is shown. Over the substrate 110 is a first insulator layer 120 comprising a low dielectric constant material (low k dielectric), which is obtained from a polymer low k dielectric product such as Dow Chemical Company, NY, USA. Available SiLK®, FLARE available from Honeywell, New Jersey, USA, and conventional materials such as silicon dioxide, fluorinated silicon dioxide (FSG), and microporous glass such as Honeywell, Inc., New Jersey, USA Nanoglass (porous SiO ₂ ) available, plus Black Diamond (carbon doped SiO ₂ ) available from Applied Material, California, USA; Coral (silicon carbide based) available from Novellus Systems, Inc., California, USA And Xerogel available from Allied Signal, New Jersey, USA.

  Overlying the first insulator layer 120 is a first hard mask layer 125 that includes one of a nitride, an oxide, and a metal such as TaN, Ta, or W. Over the first hard mask layer 125, for example, SiLK®, FLARE, and conventional materials such as microporous glass such as silicon dioxide, silicon fluoride fluoride (FSG), and Nanoglass, and Black Diamond, Coral. And a second insulator layer 130 comprising a low dielectric constant material such as Xerogel. Next, a second hard mask layer 135 is formed on the second insulator layer 130, and the second hard mask layer 135 is similarly made of nitride, oxide, and metal such as TaN, Ta or W. One of these.

  The first insulator layer 120 and the first hard mask layer 125 form the first metallization layer 101, while the second insulator layer 130 and the second hard mask layer 135 form the second metallization layer 102. Within the first and second metallization layers 101, 102 of the integrated circuit structure 100 are a plurality of wiring conductors 115 that preferably include copper but may include other metals such as tungsten or silver, gold, and the like. Dotted.

  As shown in FIG. 2, the integrated circuit structure 100 has undergone an RIE (reactive ion etching) process, in which the second hard mask layer 135 is removed from the top of the second metallization layer 102 to partially The upper surface of the wiring conductor 115 is exposed. Next, a CMP (Chemical Mechanical Polishing) process is performed, in which part of the second insulator layer 130 and part of the wiring conductor 115 in the second metallization layer 102 are removed. This is shown in FIG.

  The next step in the rework process includes exposing the integrated circuit structure 100 to another CMP process, as shown in FIG. 4, thereby removing a larger portion of the second insulator layer 130 and the second as well. Most of the wiring conductor 115 in the metallization layer 102 is removed. Finally, as shown in FIG. 5, a single level rework is completed, in which the entire second insulator layer 130 and wiring conductor 115 inside the second metallization layer 102 are removed by a CMP process, Only the first metallization layer 101 in which the plurality of wiring conductors 115 are scattered inside the one insulator layer 120 and the first hard mask layer 125 is kept in a complete state. As described above, the hard mask layer 125 protects the interconnect layer 101 when the overlying interconnect layer 102 is removed. More specifically, the portion of the removal process that removes the last portion of the soft low-k dielectric 130 in FIG. 5 is selective to the soft low-k dielectric 130 and includes a hard insulator hard mask layer 125. Almost no effect. This allows the underlying interconnect layer 102 to be completely removed without affecting the underlying interconnect layer 101, and the underlying BEOL / BEOL layer (layer 101 and the underlying layers). ) Allows the interconnect layer 102 to be individually reworked without sacrificing any of the costs, time, and expense associated with forming. Layer 101 and underlying layers can be similarly removed, thereby accurately controlling the amount of layer that needs to be reworked.

In this first embodiment, each level (here, one metallization level 102) is removed sequentially, starting from the top surface of the integrated circuit structure 100 using a substantially uniform removal process. The CMP polish uses a slurry, preferably a slurry configured to remove copper and dielectric, and removes a portion of the second insulator layer 130, the second hard mask layer 135, and the wiring conductor 115. Alternatively, these layers may be removed using a wet or dry etch such as an HF (hydrofluoric acid) etch. When using an etchant, a repetitive arrangement of etchants can be used for optimal removal of the exposed film at various points during the process. For example, a perfluorocarbon dry etch is optimal for removing Si ₃ N ₄ , while a nitrogen-based etch is optimal for removing most organic low-k materials.

  In addition, a low-k material, such as a low-k material in the second insulator layer 130, may be heat treated prior to removal to change its removal rate. Instead, the second insulator layer 130 is first heat treated (or chemically treated, etc.) to reduce its bond strength or mechanical strength, and lift off tape, liquid chemicals such as HF, or vapor HF. Is removed using a dry etching chemical such as the above, and this further causes part or all of the wiring conductor 115 to be peeled off. The removal process is then completed using copper polish.

As a further alternative, the integration of a hard dielectric (eg, Si ₃ N ₄ or silicon carbide) scratch stop is used during initial integrated circuit fabrication. This scratch stop exists under a repetitive arrangement of low-k dielectrics and copper interconnect structures, and BPSG / W levels above electronic devices such as transistors below the BPSG / W level. Located on the same plane. If multi-level rework is required, remove the membrane down to the scratch stop. Also, the film can be removed using a combination of the RIE process and the CMP process described above, and this is repeated to remove each metallization level. Here, the copper removal rate is preferably greater than the low k removal rate.

  If the scratch layer is not fully effective, a strap-local interconnect or “MC” may be formed over the first MC, post-recording (“POR”) line post-processing (“BEOL”) The process is used to remanufacture multi-level BEOL. The above procedure may be performed alone or in combination with an ultrasonic or megasonic cleaning process to vibrate the BEOL structure or to BEOL for subsequent easy removal. The structure may be deteriorated. Thus, as shown, the first embodiment of the present invention is an effective process for reworking a multi-level copper / low-k integrated circuit interconnect BEOL structure 100.

  A second embodiment is shown in FIGS. This second embodiment teaches applying a polish stop after performing some or all dielectric (low k) removal. This polish stop will remove the wiring conductor 215 (typically copper) to a thickness that is coplanar with the dielectric or the underlying level (if the dielectric is completely removed). It works to make it possible.

  FIGS. 6-10 illustrate the order for the method of performing this embodiment according to the invention. As shown in FIG. 6, the first step includes a substrate 210 (eg, a silicon substrate) having a BEOL (line post-process) device and one or more BEOL metallization levels 201, 202 formed thereon. Including the step of preparing. The integrated circuit device 200 includes a first insulator layer 220, as shown, in particular, which includes a low dielectric constant material (low k dielectric) such as SiLK®, FLARE, and conventional Materials include microporous glasses such as silicon dioxide, fluorinated silicon dioxide (FSG), and Nanoglass, and Black Diamond, Coral, and Xerogel.

Overlying the first insulator layer 220 is a first hard mask layer 225 that includes one of a metal such as nitride, oxide, Si ₃ N ₄ , and TaN, Ta, or W. Overlying the first hard mask layer 225 is a second insulator layer 230, which comprises a low dielectric constant material such as SiLK®, FLARE, and conventional materials such as silicon dioxide, fluoride. Includes silicon dioxide (FSG), and microporous glasses such as Nanoglass, and Black Diamond, Coral, and Xerogel. Next, on top of the second insulator layer 230 is a second hard mask layer 235, which is also made of a metal such as nitride, oxide, Si ₃ N ₄ , and TaN, Ta or W. Including one of them.

  The first insulator layer 220 and the first hard mask layer 225 form the first BEOL metallization layer 201, while the second insulator layer 230 and the second hard mask layer 235 form the second BEOL metallization layer 202. To do. A plurality of wiring conductors 215, preferably made of copper, are interspersed within the first and second BEOL metallization layers 201, 202 of the integrated circuit structure 200.

In the next stage of the rework process, as shown in FIG. 7, the second hard mask layer 235 is removed to expose the second insulator layer 230 and the wiring conductor 215 of the second BEOL metallization layer 202. This removal process is performed by using known techniques such as N ₂ RIE or O ₂ / N ₂ RIE to a depth just below the depth of the wiring conductor in the second metallization level 202.

Next, a thin film polish stop 240 is deposited over the integrated circuit device 200 as shown in FIG. This is preferably done using a directional thin film deposition method such as physical vapor deposition or “PVD” involving TaN, Ta, W, or other metals, such as SiO ₂ oxide or Si ₃ N ₄ nitride or Dielectric deposition methods including other dielectrics such as silicon carbide are also possible. As shown in FIG. 9, the integrated circuit structure 200 is polished by removing the wiring conductor 215 protruding from the second metallization level 202 and removing the polish stop layer 240, the second insulator layer 230, the dielectric The polish stop layer 240 on the region 230 (that is, the second insulator layer 230) and the exposed wiring conductor 215 will be exposed.

Finally, as shown in FIG. 10, the integrated circuit device 200 is further polished, thereby removing the remaining exposed polish stop film 240, and the wiring conductor 215 in the second insulator layer 230 and the second BEOL metallization layer 202. To produce a clean and flat top surface. At the completion of this rework process, the BEOL level may be reconstructed using POR. This polish stop 240 allows the metal to be polished without damaging the soft low k insulator 230.

  Presumably, in the current BEOL level reconstruction process, rework artifacts (not shown) will remain as extended vias. On the other hand, the entire structure may be reworked so that no by-products remain. That is, if only the line portion of the dual damascene structure is removed, only the line may be remanufactured using a single damascene process sequence so that no by-product remains. The method taught by the second embodiment can be used for the removal of single or partial BEOL levels, or the process can be repeated several times to remove all BEOLs.

In the third embodiment described in FIGS. 11 to 19 (b), a cap dielectric hard mask material 325, 335, 345 (eg, SiO ₂ , Si ₃ N ₄ , inorganic material, silsesquioxane, etc.) Low dielectric constant materials 320, 330, 340 (eg, SiLK®, FLARE, and conventional materials such as silicon dioxide, fluorinated silicon dioxide (FSG), and microporous glasses such as Nanoglass, and Black Diamond, Coral, and Xerogel, organic materials, and other low-k dielectrics) are shown, wherein the cap material and the bottom dielectric material are internal to the copper BEOL structure 300. Has different removal characteristics at some or all levels.

  Cap dielectrics 325, 335, and 345 serve as thin film removal endpoint stops that are not currently available in the Cu / low k BEOL scheme due to the “lower modulus” of low k thin films. 11 and 12 show the basic structure of a device 300 provided by a third embodiment according to the present invention. The basic structure of the integrated circuit device 300 is similar to the devices 100 and 200 of the first and second embodiments, but is repeated here for clarity.

  As shown in FIG. 11, the first step consists of a substrate 310 (eg, a silicon substrate) having a BEOL (post-process) device and one or more BEOL metallization levels 301, 302, 303 formed thereon. , 304 is included. The integrated circuit device 300 includes a first insulator layer 320, as illustrated, which includes a low dielectric constant material (low k dielectric) such as SiLK (R), FLARE, and conventional Materials include microporous glasses such as silicon dioxide, fluorinated silicon dioxide (FSG), and Nanoglass, and Black Diamond, Coral, and Xerogel.

Overlying the first insulator layer 320 is a first hard mask layer 325 comprising one of a nitride, oxide, Si ₃ N ₄ , and a metal such as Tan, Ta or W. Above the first hard mask layer 325 is a second insulator layer 330 comprising a low dielectric constant material such as those described above. Next, on the second insulator layer 330 is a second hard mask layer 335, such as nitride, oxide, Si ₃ N ₄ , and TaN, Ta, or W. One of the various metals. Next, over the second hard mask layer 335 is a third insulator layer 340 comprising a low dielectric constant material such as those described above. Next, on the third insulator layer 340 is a third hard mask layer 345, which is also the above-mentioned material provided in the first and second hard mask layers 325, 335. One of these.

  The first insulator layer 320 and the first hard mask layer 325 form a first BEOL metallization layer 301, while the second insulator layer 330 and the second hard mask layer 335 form a second BEOL metallization layer 302. Similarly, the third insulator layer 340 and the third hard mask layer 345 form a third BEOL metallization layer 303. A plurality of wiring conductors 315, preferably made of copper, are interspersed within the first, second, and third BEOL metallization layers 301, 302, 303 of the integrated circuit structure 300.

Referring to FIG. 12, a dual damascene method for fabricating the required Cu / cap dielectric / bottom dielectric BEOL for subsequent single or multiple level removal is as follows. First, a substrate 310 having a BEOL device and one or more BEOL levels 301, 302, 303 thereon are prepared. Next, a thin film removal end point stop (first lower dielectric thin film) 350 is deposited on the device 300. The thin film 350 is thicker than POR Si ₃ N ₄ . The thickness of the thin film 350 can be controlled to a desired thickness or depth. Next, a second lower dielectric thin film 355 such as SiLK®, FLARE, and conventional materials such as silicon dioxide, fluorinated silicon dioxide (FSG), and nanoporous glass such as Nanoglass, and Black Diamond, A layer containing Coral and Xerogel is deposited on the first lower dielectric film 350. Next, a cap hard mask material 360 is deposited over the second lower dielectric film 355. Hard mask material 360 preferably comprises one of nitrides, oxides, Si ₃ N ₄ , and metals such as TaN, Ta, or W.

  The next step in the process is to use a typical copper interconnect photolithography / etch, liner / seed, and electroplating method into the hard mask 360 and the first and second dielectric thin film layers 350, 355. Forming a dual damascene via and line wiring pattern and forming a fourth metallization level 304; Upon completion of these steps, a typical copper interconnect dual damascene pattern creates structure 315. Finally, the device 300 is polished using typical copper CMP to produce a completely flat integrated circuit device 300.

  13 to 19 show a modification of the structure of the third embodiment, in which the steps described in FIGS. 11 and 12 may be interchanged and / or repeated. Specifically, FIGS. 13-17 illustrate various dual damascene approaches, where all figures displayed as (a) and (c) represent structures prior to rework, and (b) and All figures displayed as (d) represent the structure after rework. The difference between the structure before reworking and the structure after reworking is the difference in geometric structure, for example, the first and / or second dielectric layers 350 (b), 350 (d), 355 (b), 355 (d ) The depth difference of the metallization level including any thickness difference.

13 (a), 13 (b), 14 (a), and 14 (b) are dual damascene integrated circuit structures 400a, 400a, which are separate representations of the fourth metallization level 304 of the device 300 shown in FIG. 400b, 500a, and 500b will be described. The devices 400a, 400b, 500a, 500b include third hard mask layers 345a, 345b, and the third hard mask layers 345a, 345b are made of nitride, oxide, Si ₃ N ₄ , and TaN, Ta, or W. One of such metals. Above the third hard mask layers 345a and 345b are thin film removal end points (first lower dielectric thin films) 350a and 350b. The thickness of the thin films 350a and 350b can be controlled to a desired thickness or depth. Next, second lower dielectric films 355a, 355b such as SiLK®, FLARE, and conventional materials such as silicon dioxide, fluorinated silicon dioxide (FSG), and microporous glass such as Nanoglass, and Black A diamond, coral, and xerogel containing material is deposited over the first lower dielectric thin film 350a, 350b. Next, cap and hard mask materials 360a and 360b are deposited on the second lower dielectric thin films 355a and 355b. The hard mask material 360a, 360b preferably comprises one of nitrides, oxides, Si ₃ N ₄ , and metals such as TaN, Ta, or W. The difference between each of the devices 400a, b and 500a, b of FIGS. 13 and 14 is the relative thickness difference of the second lower dielectric film 355a, 355b.

  Other variations of the schematic configuration will be further described (devices 600a, b, c, d, 700a, b, 800a, b, 900a, b, 1000a, b). Here, the second dielectric thin films 355a and 355b sandwich the first dielectric thin films 350a and 350b as shown in FIGS. 15 (a) and 15 (b), or FIGS. 15 (c) and 15 (d). As shown in FIG. 4, the first dielectric thin films 350c and 350d allow part or all of the level to be removed with the second dielectric thin films 355c and 355d interposed therebetween. Also, as shown in FIGS. 16 (a) and 16 (b) and 17 (a) and 17 (b), the second dielectric thin films 355a and 355b are below the first dielectric thin films 350a and 350b. Further, FIGS. 17A and 17B also show third hard mask layers 345a and 345b sandwiching the second dielectric thin films 355a and 355b. Similarly, a single damascene method may be used to form a Cu / first dielectric / second dielectric BEOL that leads to single or multiple level removal to give a structure similar to that shown in FIGS.

  Further, in FIGS. 18 (a), 18 (b), and 19 (b), it is shown that the third hard mask layers 345a and 345b sandwich the first dielectric thin films 350a and 350b. In addition, FIG. 19 (a) shows a double third hard mask layer 346a over the third hard mask layer 345a. These variations also describe a number of ways to integrate the first dielectric / second dielectric insulator structure within the copper interconnect level, all of the variations of the structures and methods shown are within the scope of the present invention. The scope and purpose of this are illustrated.

The sequential rework process begins by providing the copper / first dielectric / second dielectric BEOL structure described above (shown in the figures labeled by (a) and (c)). Next, the remaining surface level hard mask material 360 (eg, Si ₃ N ₄ , SiO _2, etc.) is removed using known RIE, wet etching, or CMP techniques. Next, the first or second dielectric material 350, 355 exposed at this stage is removed to a desired depth using a known RIE, wet etching, or CMP technique. Here, the process can be optimized by removing the single dielectric thin film or the multi-level dielectric thin film and stopping on the dielectric thin film. Next, the copper wiring conductor 315 is removed so as to be flat with the dielectric thin films 350 and 355. Once the level is removed, the standard POR follows and reconstructs the level (as shown in the diagrams displayed by (b) and (d)).

  In a fourth embodiment, a solution of a method for integrating an extended via layer into a dual damascene low kBEOL level is shown. According to this embodiment, an extended via structure 1100 is disclosed that can be integrated within one or more BEOL levels. This extended via structure is formed using a single damascene process sequence that uses a process optimized to form the via smaller than the dual damascene via to which the via is connected. The fourth embodiment introduces two variations of other possible rework processes in addition to the rework process described above. Here, the fourth embodiment can be used together with the first, second, third, or fifth embodiment (described later).

FIGS. 20-22 illustrate a first process sequence that forms such an integrated extended via structure 1100, which initially includes a silicon substrate 1110 having a BEOL device and one or more possible overlies. And preparing a new BEOL level 1104, 1105. Here, a first (cap) thin film layer 1120 such as Si ₃ N ₄ is deposited on the substrate 1110. Next, a second (low k dielectric) thin film layer 1125 such as SiLK®, FLARE, and conventional materials such as silicon dioxide, fluorinated silicon dioxide (FSG), and microporous glass such as Nanoglass, and A black diamond, coral, and xerogel containing material is deposited over the first (cap) thin film layer 1120. Upon completion of this step, a first via pattern 1114 is defined in the first and second thin film layers 1120 and 1125 by photolithography. Here, the first via definition process is optimized to form a first via 1114 that is smaller than the subsequently formed second via 1116 (the lower portion of the structure 1116 shown in FIG. 22).

The exposed first and second thin film layers 1120, 1125 are then removed using typical photolithography / RIE damascene and dual damascene processes, and the typical dual damascene liner / seed thin film 1109 is removed from the first via. It adheres in 1114. Thereafter, a conductor (wiring conductor) 1115, preferably including a conductive material such as copper or tungsten, is deposited in the first via 1114 and on the liner film 1109. Next, a polishing process is performed to form a completely flat device 1100. Thereafter, a third (cap) thin film layer 1130, such as Si ₃ N ₄ , is deposited on the planarization device 1100, which is shown in FIG.

  Next, a fourth (or alternatively fourth and fifth) (low dielectric constant) thin film layer 1135 such as SiLK®, FLARE, and conventional materials such as silicon dioxide, silicon fluoride oxide (FSG), and Nanoglass. A microporous glass such as, and including Black Diamond, Coral, and Xerogel is deposited over the third (cap) thin film layer 1130. The next step in the process includes photolithography to define a dual damascene second via / line pattern 1116 in the fourth (or fourth and fifth) (low dielectric constant) thin film layer 1135. Next, the exposed fourth (or fourth and fifth) (low dielectric constant) thin film layer 1135 and third (cap) thin film layer 1130 are removed, and a typical dual damascene liner / seed thin film 1109 is second. It adheres in the via 1116. After this, a conductor (wiring conductor) 1115, preferably comprising a conductive material such as copper or tungsten, is deposited in the second via 1116 and on the liner / seed film 1109. Next, a polishing process is performed to form the completely flat device 1100 shown in FIG. In the fourth embodiment, the second via 1116 may be formed using the same photomask used for the first via 1114. On the other hand, the photo exposure conditions may be optimized so that the resulting two vias 1114 and 1116 have different sizes. For example, the first via 1114 is about 30% smaller than the second via 1116 to handle the pitch related process window problem.

In a second process according to the fourth embodiment of the present invention shown in FIGS. 23-25, initially preparing a silicon substrate 1210 having a BEOL device and one or more possible BEOL levels 1204 thereon. A sequence for forming an integrated extended via structure 1200 is shown. Here, a first (cap) thin film layer 1220 such as Si ₃ N ₄ is deposited on the substrate 1210 as shown in FIG. Next, a second (low dielectric constant) thin film layer 1225 such as SiLK®, FLARE, and conventional materials such as silicon dioxide, fluorinated silicon dioxide (FSG), and microporous glass such as Nanoglass, and Black A diamond, coral, and xerogel containing layer is deposited over the first (cap) thin film layer 1220, for example, at a thickness of about 200 nm. Upon completion of this step, a first via pattern 1214 is defined in the first and second thin film layers 1220, 1225 by photolithography. Here, the first via definition process is optimized to form a first via 1214 that is larger than the subsequently formed second via 1216.

  Next, the exposed first and second thin film layers 1220 and 1225 are removed. Next, a third (low dielectric constant) thin film material 1235 such as SiLK®, FLARE, and conventional materials such as silicon dioxide, fluorinated silicon dioxide (FSG), and microporous glass such as Nanoglass, and Black Including Diamond, Coral, and Xerogel is deposited over the second thin film layer 1225 as best shown in FIG. Next, a thin hard mask material 1240 is deposited over the third (low dielectric constant) thin film material 1235. The next step in the process includes photolithography to define a dual damascene second via / line pattern 1216 in the third (low dielectric constant) thin film material 1235 and hard mask layer 1240. Thereafter, the hard mask layer 1240 and the exposed third (low dielectric constant) thin film material 1235 are removed. A typical dual damascene liner / seed film 1209 is then deposited in the first and second vias 1214 and 1216. At the completion of this step, a conductor (wiring conductor) 1215, preferably comprising a conductive material such as copper or tungsten, is deposited in the second via / line pattern 1216 and on the liner film 1209. Next, a polishing process is performed to form a completely flat device 1200 as shown in FIG. The process sequence results in an extended via 1216 formed in the same low-k material 1235 as the dual damascene line / via 1214, where the extended via 1216 is a first embedded within the low-k material 1235. The dielectric 1225 is also surrounded.

  A fifth embodiment of the present invention is shown in FIGS. This embodiment includes a rework process and solves the problem of how to remove and reconstruct partial integrated circuit BEOL interconnect levels. The dual stud interconnect structure 1300 of the present invention includes discretely formed vias 1316 that are integrated between three photolithographic process sequences and two or more deposition sequences. The process includes providing a silicon substrate 1310 having a BEOL device and one or more BEOL levels 1301, 1302a, 1303 thereon.

Here, as shown in FIG. 26, the structure of the device 1300 includes a first cap thin film layer 1320 such as Si ₃ N ₄ , and the first cap thin film layer 1320 is deposited on the substrate 1310. Next, a first low dielectric constant thin film layer 1325 such as SiLK (R) or SiO ₂ is deposited on the first cap thin film layer 1320. Next, a second cap thin film layer 1330 such as Si ₃ N ₄ is deposited on the first low dielectric constant thin film layer 1325. Thereafter, a second low dielectric constant thin film layer 1335 such as SiLK®, FLARE, and conventional materials such as silicon dioxide, fluorinated silicon dioxide (FSG), and microporous glass such as Nanoglass, and Black Diamond, Coral , And Xerogel on the second cap thin film layer 1330, and then a third cap thin film layer 1340 such as Si ₃ N ₄ and a third low dielectric constant thin film layer 1345 such as SiLK®, FLARE , And conventional materials such as silicon dioxide, fluorinated silicon dioxide (FSG), and microporous glasses such as Nanoglass, and Black Diamond, Coral, and Xerogel are subsequently deposited thereon.

  The first cap and dielectric thin film layers 1320, 1325 form the first metallization layer 1301 after the typical photolithography / etch and subsequent liner / seed, electroplating and CMP steps described above. Similarly, the second cap and dielectric thin film layers 1330, 1335 form the second metallization layer 1302a after the typical photolithography / etch and subsequent liner / seed, electroplating and CMP steps described above. Similarly, the third cap and dielectric thin film layers 1340, 1345 form a third metallization layer 1303 after the typical photolithography / etch and subsequent liner / seed, electroplating and CMP steps described above. A plurality of wiring conductors 1315, preferably made of copper, are interspersed within the first, second, and third metallization layers 1301, 1302 a, 1303 of the integrated circuit structure 1300.

The next step in the process includes removing one or more BEOL levels 1303 using known techniques. Thus, as shown in FIG. 27, the regions of the first via 1316 and liner material 1309 and the region of the second low dielectric constant thin film layer 1335 are exposed at this point, resulting in a changed second metallization level 1302b. . Next, as shown in FIG. 28, a fourth cap thin film layer 1350 such as Si ₃ N ₄ is deposited on the third low dielectric constant thin film layer 1335. Next, a fourth low dielectric constant thin film layer 1355 such as SiLK®, FLARE, and conventional materials such as microporous glass such as silicon dioxide, fluorinated silicon dioxide (FSG), and Nanoglass, and Black Diamond, Coral and Xerogel containing are deposited on the fourth cap thin film layer 1350.

  The next step in the process includes forming a second via 1317 on the first via 1316 by photolithography. Here, the second via 1317 is preferably larger than the first via 1316, but the second via 1317 may be smaller than the first via 1316. A typical damascene liner / seed film 1309 is then deposited in the second via 1317. Next, a conductor (wiring conductor such as copper) 1315 is deposited in the second via 1317 and on the liner film 1309 using typical copper damascene techniques. This is followed by a CMP polishing process resulting in a flat device 1300. The fourth thin film layer 1355, the fourth cap thin film layer 1350, and the conductor 1315 within the second via 1317 together form a new third metallization level 1304.

Next, as shown in FIG. 29, a fifth cap thin film layer 1360 such as Si ₃ N ₄ is deposited on the fourth low dielectric constant thin film layer 1355. Next, a fifth low dielectric constant thin film layer 1365 such as SiLK® or SiO ₂ is deposited on the fifth cap thin film layer 1360. The next step in the process includes photolithography to define a dual damascene line / via pattern 1318 in the fifth low dielectric constant thin film layer 1365. A typical damascene liner / seed film 1309 is then deposited in the third via 1318. A conductive film 1315 is then deposited in the third via 1318 and on the liner film 1309 using typical copper damascene techniques. After this, a polishing process is performed resulting in a flat device 1300. This is followed by BEOL level manufacturing using POR. In addition, the resulting interconnect structure 1300 shown in FIG. 29 has one connecting via 1319 formed in three photolithography steps to facilitate a partial level of rework and address optical overlay constraints.

  FIG. 30 illustrates a flow diagram of the rework process according to the present invention. A method for reworking a damascene metallurgy BEOL (post-process line) interconnect level includes first forming a first interconnect level on a substrate 2000, and further comprising a first dielectric on the substrate. Depositing a layer 2010, laminating a second dielectric layer 2020 over the first dielectric layer, and forming line 20 and via regions 2030 in the first and second dielectric layers. The first dielectric layer includes a material having a lower dielectric constant than the second dielectric layer. Next, a plurality of interconnect levels are formed on the first interconnect level (step 2040). Next, starting with the highest interconnect level, the selected interconnect level is removed (step 2050). Finally, the removed interconnect level is replaced with a new interconnect level (step 2060).

  The advantage of each embodiment is that it provides a different means of reworking a single interconnect level or all BEOL interconnects to make up for part of the process (and hence cost) already on the wafer. For example, the cost or more specifically the price of a wafer processed by BEOL is quite high, and the price of the same type of wafer processed by a part of the repetitive BEOL metal interconnect process is even higher. Thus, if a defect or misprocess or other effect occurs on a wafer, it can be compensated for using one or more of these methods rather than discarding the wafer. The second matter that is compensated by the rework described above is time. That is, the time for processing a wafer through BEOL is quite large and the time for passing through BEOL is even longer. Thus, the rework process illustrated by one or more embodiments can be used to make up for the time required to process the wafer. This is important. This is because, at best, 20 days are required to manufacture a wafer, and it is critical to start over if a defect or misprocess step occurs at one or more BEOL levels. Rework avoids much of this lost time.

Currently, there is no prior art in the industry regarding rework processes for the production of SiO ₂ -copper damascene BEOL semiconductor wafers. In accordance with technological advances that require performing semiconductor devices, the dielectric used has changed from SiO ₂ to low-k materials, as previously described. Reworking these materials is virtually non-existent and there is no teaching of how to rework damascene interconnect structures.

  The present invention provides a structure having a protective hard insulator layer on a lower soft low dielectric constant (low k) layer within each interconnect layer. This structure allows each interconnect layer in the BEOL process layer to be removed individually. More specifically, in the first stage of the removal process, the upper hard dielectric is first removed (along with a portion of the lower soft low-k dielectric). Next, the remainder of the low-k dielectric and the metal wiring lines are removed in the second stage of the removal process. This second stage of the removal process does not affect the adjacent hard insulator of the interconnect layer located immediately below the interconnect layer being removed. Thus, the present invention is highly selective and is a low-k dielectric layer without affecting the next underlying layer (protected by its own upper hard protective insulator layer). Also) allows the removal of a single interconnect layer. This makes BEOL layer rework much easier (by allowing a single layer to be reworked).

In summary, the following matters are disclosed regarding the configuration of the present invention.
(1) An integrated circuit structure comprising a first section including a logic device and a functional device, and at least one interconnect layer on the first section, the interconnect layer comprising a first insulator layer And a second insulator layer on the first insulator layer, and electrical wiring inside the first insulator layer and the second insulator layer, wherein the first insulator layer is the first insulator layer. An integrated circuit structure having a dielectric constant lower than two insulator layers.
(2) The structure according to (1), wherein the second insulator layer is harder than the first insulator layer.
(3) The structure of (1) above, wherein the second insulator layer includes a protective layer that protects the first insulator layer during a rework step performed on an overlying interconnect layer.
(4) The structure according to (1), wherein the first insulator layer includes one of carbon-doped SiO ₂ , porous SiO ₂ , a silicon carbide-based dielectric, and a polymer dielectric.
(5) The structure according to (1), wherein the second insulator layer includes one of nitride, oxide, Si ₃ N ₄ , TaN, Ta, and W.
(6) The structure according to (1), wherein the electrical wiring includes damascene copper.
(7) The structure according to (1), wherein the first insulator layer, the second insulator layer, and the electric wiring constitute a single interconnect layer inside the structure.
(8) An integrated circuit structure comprising a first section including a logic device and a functional device, and a plurality of interconnect layers on the first section, each interconnect layer comprising a first insulator A layer, a second insulator layer on the first insulator layer, and electrical wiring inside the first insulator layer and the second insulator layer, the first insulator layer comprising: An integrated circuit structure having a lower dielectric constant than the second insulator layer.
(9) The structure according to (8), wherein the second insulator layer is harder than the first insulator layer.
(10) The structure of (8) above, wherein the second insulator layer includes a protective layer that protects the first insulator layer during a rework step performed on an overlying interconnect layer.
(11) The structure according to (8), wherein the first insulator layer includes one of carbon-doped SiO ₂ , porous SiO ₂ , a silicon carbide-based dielectric, and a polymer dielectric.
(12) The structure according to (8), wherein the second insulator layer includes one of nitride, oxide, Si ₃ N ₄ , TaN, Ta, and W.
(13) The structure according to (8), wherein the electrical wiring includes damascene copper.
(14) The structure according to (8), wherein each group of the first insulator layer, the second insulator layer, and the electric wiring constitutes a single interconnect layer inside the structure.
(15) A method of reworking an interconnect layer on a logic layer and a functional layer of an integrated circuit structure, the interconnect layer including an upper insulator layer and an electrical wiring on a lower insulator layer, The lower insulator layer has a lower dielectric constant than the upper insulator layer, and the method includes removing a first upper insulator of a first interconnect layer of the interconnect layers; and Removing the first electrical wiring and the first lower insulator of the first interconnect layer by a selective removal process that does not affect the second upper insulator of the second interconnect layer located immediately below the connection layer; And a method comprising:
(16) The second upper insulator protects the second lower insulator of the second interconnect layer during the process of removing the first electrical wiring and the first lower insulator. The method described.
(17) The removal process completely removes the first interconnect layer, leaving the second interconnect layer intact, and the method includes an alternative interconnect layer instead of the first interconnect layer. The method according to (15), further comprising the step of forming
(18) The process of removing the first upper insulator also removes a part of the first lower insulator to expose a part of the electrical wiring, and the method removes the first upper insulator. The method according to (15), further comprising a step of depositing a polish stop layer on the partially removed portion of the first lower insulator and on the exposed portion of the electrical wiring after the process of forming the first lower insulator. .
(19) After the process of attaching the polish stop layer, removing the electrical wiring to leave a partially removed portion of the first lower insulator and a part of the polish stop layer And the step of removing the polish stop layer.
(20) The method according to (19), wherein the polish stop layer protects the first lower insulator during a process of removing the electrical wiring.

1 is a schematic cross-sectional view of a first embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. 1 is a schematic cross-sectional view of a first embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. 1 is a schematic cross-sectional view of a first embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. 1 is a schematic cross-sectional view of a first embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. 1 is a schematic cross-sectional view of a first embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 6 is a schematic cross-sectional view of a second embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 6 is a schematic cross-sectional view of a second embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 6 is a schematic cross-sectional view of a second embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 6 is a schematic cross-sectional view of a second embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 6 is a schematic cross-sectional view of a second embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 6 is a schematic cross-sectional view of a third embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 6 is a schematic cross-sectional view of a third embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. (A) It is the cross-sectional schematic of 3rd Embodiment of the integrated circuit structure which receives the rework process based on this invention. (B) is a schematic cross-sectional view of a third embodiment of an integrated circuit structure subjected to a rework process according to the present invention. (A) It is the cross-sectional schematic of 3rd Embodiment of the integrated circuit structure which receives the rework process based on this invention. (B) is a schematic cross-sectional view of a third embodiment of an integrated circuit structure subjected to a rework process according to the present invention. (A) It is the cross-sectional schematic of 3rd Embodiment of the integrated circuit structure which receives the rework process based on this invention. (B) is a schematic cross-sectional view of a third embodiment of an integrated circuit structure subjected to a rework process according to the present invention. (C) Schematic cross-section of a third embodiment of an integrated circuit structure that undergoes a rework process according to the present invention. (D) It is the cross-sectional schematic of 3rd Embodiment of the integrated circuit structure which receives the rework process based on this invention. (A) It is the cross-sectional schematic of 3rd Embodiment of the integrated circuit structure which receives the rework process based on this invention. (B) is a schematic cross-sectional view of a third embodiment of an integrated circuit structure subjected to a rework process according to the present invention. (A) It is the cross-sectional schematic of 3rd Embodiment of the integrated circuit structure which receives the rework process based on this invention. (B) is a schematic cross-sectional view of a third embodiment of an integrated circuit structure subjected to a rework process according to the present invention. (A) It is the cross-sectional schematic of 3rd Embodiment of the integrated circuit structure which receives the rework process based on this invention. (B) is a schematic cross-sectional view of a third embodiment of an integrated circuit structure subjected to a rework process according to the present invention. (A) It is the cross-sectional schematic of 3rd Embodiment of the integrated circuit structure which receives the rework process based on this invention. (B) is a schematic cross-sectional view of a third embodiment of an integrated circuit structure subjected to a rework process according to the present invention. FIG. 7 is a schematic cross-sectional view of a fourth embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 7 is a schematic cross-sectional view of a fourth embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 7 is a schematic cross-sectional view of a fourth embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 7 is a schematic cross-sectional view of a fourth embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 7 is a schematic cross-sectional view of a fourth embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 7 is a schematic cross-sectional view of a fourth embodiment of an integrated circuit structure that undergoes a rework process in accordance with the present invention. FIG. 7 is a schematic cross-sectional view of a fifth embodiment of an integrated circuit structure that undergoes a rework process according to the present invention. FIG. 7 is a schematic cross-sectional view of a fifth embodiment of an integrated circuit structure that undergoes a rework process according to the present invention. FIG. 7 is a schematic cross-sectional view of a fifth embodiment of an integrated circuit structure that undergoes a rework process according to the present invention. FIG. 7 is a schematic cross-sectional view of a fifth embodiment of an integrated circuit structure that undergoes a rework process according to the present invention. It is a flowchart explaining the suitable method of this invention.

Explanation of symbols

100, 200, 300 Integrated circuit structure 101, 102, 201, 202, 301, 302, 303, 304 Methylation layer 110, 210, 310, 1110, 1210, 1310 Substrate 115, 215, 315, 1115, 1215, 1315 Wiring conductors 120, 220, 320 First insulator layers 125, 225, 325 First hard mask layers 130, 230, 330 Second insulator layers 135, 235, 335 Second hard mask layer 240 Polish stop 340 Third insulation Body layer 345 Third hard mask layer 350 First lower dielectric thin film 355 Second lower dielectric thin film 360 Cap hard mask material 400, 500, 600, 700, 800, 900, 1000 Device 1100, 1200 Extended via structure 1104 1105, 1204 301, 1302, 1303, 1304, 1305 BEOL level 1109, 1209, 1309 Liner thin film 1114, 1214, 1316 First via 1116, 1216, 1317 Second via 1120, 1220 First thin film layer 1125, 1225 Second thin film layer 1130, 1235 Third thin film layer 1135 Fourth thin film layer 1240 Hard mask material 1300 Double stud interconnect structure 1318 Third via 1319 Connection via 1320 First cap thin film layer 1325 First low dielectric constant thin film layer 1330 Second cap thin film layer 1335 First 2 low dielectric constant thin film layer 1340 third cap thin film layer 1345 third low dielectric constant thin film layer 1350 fourth cap thin film layer 1355 fourth low dielectric constant thin film layer 1360 fifth cap thin film layer 1365 fifth low dielectric constant thin film layer

Claims (4)

A method for reworking an interconnect layer over a logic layer and a functional layer of an integrated circuit structure, the interconnect layer including an upper insulator layer and electrical wiring over a lower insulator layer, the lower insulator The layer has a lower dielectric constant than the upper insulator layer;
The method includes removing a first upper insulator of a first interconnect layer of the interconnect layers;
A first electrical wiring and a first lower insulator of the first interconnect layer in a selective removal process that does not affect the second upper insulator of the second interconnect layer located immediately below the first interconnect layer; And a step of removing
Removing the first upper insulator, the even part of the first lower insulator is removed to a depth just below the depth of the first electric wire, it is projected a part of the first electric wire,
The method includes the step of depositing a polish stop layer on the exposed portion of the first lower insulator and on the protruding portion of the first electric wiring after the step of removing the first upper insulator. seen including,
After the step of depositing the polish stop layer,
Using the polish stop layer as a polish stop layer, removing the first electrical wiring by polishing, leaving an exposed portion of the first lower insulator and a portion of the polish stop layer;
Removing the polish stop layer . The method of claim 1, wherein the second upper insulator protects the second lower insulator of the second interconnect layer during the step of removing the first electrical wiring and the first lower insulator. The step of removing the first electrical wiring and the first lower insulator completely removes the first interconnect layer and leaves the second interconnect layer intact, and the method includes the first interconnect layer. The method of claim 1, further comprising forming an alternative interconnect layer instead of the connection layer. The polish stop layer is between you removed by polishing the first electrical interconnection method of claim 1, wherein for protecting the first lower insulator.

Images