JP2013089716A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which inhibits formation of voids in Cu wiring by inhibiting concentration of electron holes in the Cu wiring, and inhibits an occurrence of wiring failure such as disconnection so-called stress migration at a via connection part and the like in two-layer wiring, for example.SOLUTION: A semiconductor device manufacturing method having a damascene wiring structure comprises performing a heat cycle process of heating a processed substrate and removing heat from the processed substrate after wiring formation.

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  In recent years, Cu wiring is used for wiring of semiconductor devices for the purpose of lowering resistance and increasing reliability. Since Cu wiring is difficult to form by dry etching, it has a damascene wiring structure in which wiring is formed in multiple layers. The damascene wiring structure is a method in which a Cu film is deposited in a groove of a wiring pattern formed on an interlayer insulating film, and thereafter, Cu deposited other than the groove is removed by chemical mechanical polishing (hereinafter also referred to as CMP method). Made with.

  Here, the Cu wiring is formed inside the interlayer insulating film. The plurality of interlayer insulating films are stacked. For this reason, after the temperature rising / de-heating process in the heat treatment in the Cu wiring manufacturing process, for example, several hundreds of Cu wiring is caused by the stress caused by the difference in thermal expansion coefficient of each material and the compressive stress of the interlayer insulating film. The tensile stress of MPa will act. Due to the stress concentration in the Cu wiring due to the tensile stress, a stress gradient is generated in the Cu wiring. The stress becomes a driving force for moving vacancies (atomic vacancies) existing in the Cu wiring. These vacancies gather in the Cu wiring to form voids (cavities), and when the voids grow, the Cu wiring is disconnected, resulting in a wiring defect called so-called stress migration. In particular, in a two-layer wiring system joined by via wiring (interlayer wiring), the stress concentration is concentrated in the vicinity of the joint portion between the via wiring and the Cu wiring, and a wiring defect such as disconnection occurs in the joint portion. Easy was the problem. Therefore, it is required to extend the life of the device by suppressing the wiring defects of the Cu wiring and via wiring in the semiconductor device.

  Therefore, for example, in Patent Document 1, the stress migration is suppressed by protecting the surface of a metal region such as a wiring structure with a metal having a high recrystallization temperature such as silver or a metal having a narrow hysteresis width in a temperature-stress curve. A semiconductor device is disclosed.

JP 2004-39916 A

  However, in the technique described in Patent Document 1, the cause of stress migration is stress concentration that occurs due to the difference in thermal expansion coefficient between different materials, and the solution is to make the surface of the metal region silver or the like. The present inventors have found that the cause of stress migration is the movement of vacancies due to stress concentration, and the movement of vacancies (that is, the vacancy concentration) is The surface protection with a metal such as silver in the metal region (wiring structure) cannot be controlled, and the technique described in Patent Document 1 cannot sufficiently suppress the occurrence of stress migration. In addition, in the technique described in Patent Document 1, since a process of providing a film of silver or the like on the surface of the metal region (wiring structure) is performed, a film forming process of the film is necessary. There was also a problem that there were concerns about an increase in the number of processes in manufacturing and an increase in cost.

  The present invention has been made in view of such points, and by suppressing the concentration of vacancies in the Cu wiring, the formation of voids in the Cu wiring is suppressed. For example, in a via connection portion in a two-layer wiring system, etc. An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device in which occurrence of wiring defects such as disconnection called so-called stress migration is suppressed.

  In order to achieve the above object, according to the present invention, in the method of manufacturing a semiconductor device having a copper wiring structure, a thermal cycle step of heating and removing heat from the substrate to be processed after the formation of the copper wiring layer including heat treatment is performed. A method for manufacturing a semiconductor device is provided.

  In addition, according to the present invention, there is provided a method for manufacturing a semiconductor device having a damascene wiring structure, in which a thermal cycle process for heating and removing the semiconductor device is performed after completion of wiring formation.

  In the semiconductor device manufacturing method, the heating temperature in the thermal cycle step may be 100 ° C. or higher. In the heat cycle step, soaking may be performed within 2 hours after heating. The heat removal in the heat cycle step may be performed at a cooling rate of 100 ° C./h or more.

  Furthermore, according to another aspect of the present invention, there is provided a semiconductor device having a damascene wiring structure, which is subjected to a thermal cycle for heating, soaking and removing heat after completion of wiring formation. Is done.

  In the semiconductor device, the heating temperature in the thermal cycle may be 100 ° C. or higher. In the thermal cycle, soaking may be performed within 2 hours after heating. The heat removal in the thermal cycle may be performed at a cooling rate of 100 ° C./h or more.

  According to the present invention, the formation of voids in the Cu wiring is suppressed by suppressing the concentration of vacancies in the Cu wiring. For example, a disconnection called so-called stress migration in a via connection portion in a two-layer wiring system, etc. A method of manufacturing a semiconductor device and a semiconductor device in which the occurrence of wiring defects is suppressed are provided.

It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device concerning embodiment of this invention, and has shown the state by which the wiring groove | channel was formed in the surface of an interlayer insulation film. It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device concerning embodiment of this invention, and has shown the state by which the barrier metal layer and Cu plating seed layer were continuously formed on the interlayer insulation film . It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device concerning embodiment of this invention, and has shown the state in which Cu conductive layer was formed in the whole surface of a board | substrate. It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device concerning embodiment of this invention, and has shown the state from which the Cu conductive layer and the barrier metal layer were removed from the upper direction of an interlayer insulation film. It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device of the 2 layer structure concerning embodiment of this invention, and has shown the state by which the wiring groove | channel was formed in the surface of an interlayer insulation film. It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device of the two-layer structure concerning embodiment of this invention, and the state by which the barrier metal layer and Cu plating seed layer were continuously formed on the interlayer insulation film Is shown. It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device of the 2 layer structure concerning embodiment of this invention, and has shown the state in which the Cu conductive layer was formed in the whole surface of the board | substrate. It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device of the 2 layer structure concerning embodiment of this invention, and has shown the state from which the Cu conductive layer was removed from the upper direction of an interlayer insulation film. It is a graph which shows the conditions at the time of performing a thermal cycle process with respect to the semiconductor device which the wiring formation process and the process process of loading or removing heat to other semiconductor devices were completed. FIG. 10 is a graph showing the change over time in the vacancy concentration in the via junction when the thermal cycle process is performed under the conditions shown in FIG. 9. Vacancy concentration distribution (a) after 1000 hours at the via junction when the thermal cycle process is not performed and vacancy concentration after 1000 hours at the via junction when ΔT is set to 200 ° C. It is measurement data which shows distribution (b). It is a graph which shows the result of the simulation performed in order to identify thermal fatigue temperature (DELTA) T for condensation and release of a void | hole density | concentration, and is a graph which shows thermal fatigue load conditions. FIG. 13 shows changes with time in the pore concentration under the conditions shown in FIG. It is a graph which shows the conditions of the heat cycle process in the case of changing soaking time in a heat cycle process. It is a graph which shows a time-dependent change of the void | hole density | concentration in a via junction part at the time of performing a heat cycle process on the conditions shown in FIG. It is a graph which shows the conditions of the heat cycle process in the case of changing heat removal time in a heat cycle process. FIG. 17 is a graph showing the change over time in the vacancy concentration at the via junction when the thermal cycle process is performed under the conditions shown in FIG. 16.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

1 to 4 are explanatory views showing the manufacturing process of the Cu wiring structure. That is, a process of forming a Cu wiring on the upper surface of the substrate body 1 in the semiconductor substrate W made of Si or the like is illustrated. The substrate body 1 has an arbitrary structure such as a CMOS (not shown). 5 to 8 are explanatory views showing the manufacturing process of the semiconductor device A in which the Cu wiring has a two-layer structure. In particular, FIG. 8 shows the semiconductor device A according to the embodiment of the present invention.

First, as shown in FIG. 1, for example, an interlayer insulating film 2 is formed on the substrate body 1. Examples of the interlayer insulating film 2 include a film containing Si such as SiO ₂ and SiCO, and a low relative dielectric constant film such as CFx containing carbon and fluorine. Subsequently, a wiring groove 4 is formed on the surface of the interlayer insulating film 2 by photolithography and reactive ion etching (RIE).

  Next, as shown in FIG. 2, a barrier metal (hereinafter referred to as BM) film 5 and a Cu plating seed layer 7 are continuously formed on the interlayer insulating film 2 so as to cover the inner surface of the wiring groove 4. Is done. The BM film 5 is formed by sputtering a Ta film over the entire surface of the interlayer insulating film 2. The BM film 5 is a single layer film of Ta film, TaN film, Ta compound film or Ta alloy film, single layer film of Ti film, TiN film, Ti compound film or Ti alloy film, or a laminated film of two or more of these. is there. The Cu plating seed layer 7 is formed by sputtering, for example.

Next, as shown in FIG. 3, the Cu conductive layer 10 is formed on the entire surface of the substrate W so as to fill the wiring groove 4 from above the Cu plating seed layer 7. The Cu conductive layer 10 is not limited to pure Cu but may be a Cu alloy, and is formed by electrolytic plating or the like. The Cu plating seed layer 7 is integrated with the Cu conductive layer 10 by forming the Cu conductive layer 10.

Next, as shown in FIG. 4, the Cu conductive layer 10 and the BM film 5 are formed by CMP (chemical reaction) from above the interlayer insulating film 2 while leaving the portions of the Cu conductive layer 10 and the BM film 5 inside the wiring trench 4. Mechanical polishing). Thus, the Cu wiring 15 (Cu conductive layer 10) is formed in the wiring groove 4 surrounded by the BM film 5, and the Cu wiring structure 18 having the damascene wiring structure is manufactured.

A plurality of Cu wiring structures 18 manufactured as shown in FIGS. 1 to 4 are arranged in the semiconductor device A and are often connected between two layers. Therefore, referring to FIGS. 5 to 8, a semiconductor device having a structure in which a Cu wiring structure 18 (hereinafter, referred to as a first layer 18 a and a second layer 18 b) arranged in two layers is via-connected. A manufacturing process of A will be described. 5-8, the same code | symbol is attached | subjected about the component same as what was described in the said FIGS. 1-4.

First, as shown in FIG. 5, for example, a Cu wiring structure 18 (first layer 18 a) is formed by the method described above with reference to FIGS. 1 to 4, and wiring holes and wiring grooves 4 are formed on the upper surface by an arbitrary method. An interlayer insulating film 2 provided with is formed. Next, as shown in FIG. 6, the BM film 5 and the Cu plating seed layer 7 are continuously formed so as to cover the inner surface of the wiring groove 4 as in FIG.

Then, as shown in FIG. 7, the Cu conductive layer 10 is formed so as to fill the wiring groove 4 from above the Cu plating seed layer 7. An annealing process for stabilizing the film and a thermal cycle process according to the present invention, which will be described later, are performed in a state where the Cu conductive layer 10 is buried, and thereafter, inside the wiring groove 4 as shown in FIG. The Cu conductive layer 10 and the BM film 5 exposed on the upper part of the wiring groove 4 are removed by the CMP method while leaving the Cu conductive layer 10 and the BM film 5, and a Cu wiring structure 18 (second layer 18b) is formed. Thus, a semiconductor device A in which a Cu wiring structure called a so-called dual damascene structure is connected between two layers is manufactured. Note that the connection wiring that connects the first layer 18 a and the second layer 18 b in the semiconductor device A is a wiring called a via wiring 20.

In the formation of the Cu wiring structure 18 in the semiconductor device A shown in FIGS. 5 to 8, a heat treatment process for stabilizing the Cu conductive layer is performed, so that the temperature is raised and lowered in the process. Due to the difference in thermal expansion between different materials due to the temperature rise and fall, thermal stress is generated at the interface between the materials, and as a result, residual stress is generated inside the Cu wiring 15. Further, as described above, the temperature is increased and decreased in the processes such as photolithography, reactive ion etching (RIE), and sputtering.

There are unavoidably vacancies at the atomic level inside the Cu wiring 15. Therefore, for example, in the semiconductor device A having a via connection structure as shown in FIG. 8, when the residual stress generated in the Cu wiring 15 acts in the vicinity of the via wiring 20, the via wiring is caused by the structure. Stress concentration occurs in the vicinity of 20 (particularly, the joint portion 20a between the via wiring 20 and the Cu wiring 15 in the first layer 18a). Along with this stress concentration, vacancies scattered in the Cu wiring are concentrated in the vicinity of the via wiring 20, and voids (cavities) are formed inside the Cu wiring 15. The formation of voids in the Cu wiring 15 causes wiring failures such as an increase in electrical resistance and disconnection, and induces device failure.

Further, when a semiconductor device is commercialized in a state where residual stress has been generated inside the Cu wiring 15, internal voids are concentrated due to stress concentration with the use of the device and the passage of time, and voids are formed. There is also a fear. As a result, there is a concern that the life of the apparatus will be shortened.

Accordingly, the present inventors have completed the semiconductor device (that is, the substrate to be processed) after the completion of the processing steps such as wiring formation processing, other sintering processing, annealing processing, etc., for applying or removing heat to the semiconductor device. Cu wiring structure 18 and via wiring 20 (especially Cu wiring and via wiring) by performing a thermal cycle process (at least a heating step and a heat removal step, preferably including a soaking step) on W). It has been found that the stress concentration in the bonding portion) can be suppressed, and as a result, the concentration of holes (aggregation of holes) in the semiconductor device can be suppressed. This knowledge will be described below.

FIG. 9 is a graph showing conditions for performing a thermal cycle process on a semiconductor device that has been subjected to a process such as wiring formation process, other sintering process, annealing process, etc., in which heat is applied to or removed from the semiconductor apparatus. It is. 9, after the heat treatment step of applying heat at 360 ° C., only heating and heat removal are performed for 1 hour (0.5 hr to 1.5 hr in FIG. 9), and the thermal fatigue temperature ΔT ( The heat cycle process is performed by changing the temperature of heating and heat removal to 50 ° C., 100 ° C., 150 ° C., and 200 ° C. The actual processing temperature can be obtained by adding the temperature before the heat cycle step or the temperature after the heat cycle step to the thermal fatigue temperature ΔT. The temperature before and after the heat cycle step is, for example, room temperature, and is 20 ° C. in FIG.

  FIG. 10 shows a simulation result of the change in the vacancy concentration with time in the vicinity of the joint between the Cu wiring and the via wiring (hereinafter also referred to as via junction) when the thermal cycle process is performed under the conditions shown in FIG. It is a graph to show. FIG. 10 also shows the change over time in the vacancy concentration at the via junction when the thermal cycle process is not performed (ΔT = 0 ° C.).

  As shown in FIGS. 9 and 10, the vacancy concentration in the via junction after 1 hour when ΔT is 50 ° C., 100 ° C., 150 ° C., and 200 ° C. is compared to the case where the thermal cycle process is not performed. It has increased. On the other hand, when ΔT is 100 ° C., 150 ° C., and 200 ° C., the void concentration in the via junction after 1000 hours is reduced as compared with the case where the thermal cycle process is not performed. That is, in a semiconductor device that has been subjected to a thermal cycle process with ΔT set to 100 ° C., 150 ° C., and 200 ° C., the vacancy concentration increases, but the rate of subsequent vacancy concentration (vacancy aggregation) slows down. As a result, it is found that the vacancy concentration in the via junction after a long time is lower than that of a semiconductor device that is not subjected to thermal cycling. Also, as shown in FIG. 10, it can be seen that the preferred heating temperature when performing the thermal cycling step is 150 ° C. or higher in order to effectively suppress the aging of the vacancy concentration at the via junction. .

  Further, FIG. 11 shows the vacancy concentration distribution (a) after 1000 hours in the via junction when the thermal cycle process is not performed and 1000 in the via junction when ΔT is 200 ° C. and the thermal cycle process is performed. It is a simulation result which shows the void | hole density | concentration distribution (b) after time. Also from the result shown in FIG. 11, the vacancy concentration in the via junction after a long time elapses in the semiconductor device subjected to the thermal cycle is lower than that in the semiconductor device not subjected to the thermal cycle. I understand.

  On the other hand, FIG. 12 and FIG. 13 are graphs showing the results of simulations performed to identify the thermal fatigue temperature ΔT for causing the condensation and release of the vacancy concentration, and FIG. 12 shows the thermal fatigue load conditions. In FIG. 13, ΔT is set to 50 ° C., 100 ° C., 150 ° C., and 200 ° C., and when the temperature is kept constant (that is, in the case of the condition shown in FIG. 12), the vacancy at the via junction (corner portion) is obtained. The change with time of the pore concentration is shown. FIG. 13 also shows the change over time in the vacancy concentration at the via junction when the heating step is not performed (ΔT = 0 ° C.).

As shown in FIG. 13, when ΔT is 100 ° C., 150 ° C., and 200 ° C., it can be seen that the increase and decrease in the vacancy concentration due to the heating step occur. That is, the condensation and release of the vacancy concentration occurs. On the other hand, when ΔT is 50 ° C., the increase and decrease of the vacancy concentration due to the heating step, that is, the condensation and release of the vacancy concentration does not occur. Therefore, it can be seen that the thermal fatigue temperature ΔT (heating temperature in the thermal cycle process) that can lower the vacancy concentration at the via junction by causing the condensation and release of the vacancy concentration is 100 ° C. or higher.

On the other hand, FIG. 14 is a graph showing conditions when a heat cycle process including a heating step, a soaking step, and a heat removal step is performed on a semiconductor device that has been subjected to a treatment process that loads or removes heat from the semiconductor device. FIG. 15 is a graph showing a simulation result of a change with time in the vacancy concentration in the via junction when the thermal cycle process is performed under the conditions shown in FIG. As the conditions of the thermal cycle process shown in FIG. 14, the thermal fatigue temperature ΔT is 200 ° C., and the soaking time t ₃ is changed to 0 hr, 0.5 hr, 2 hr, ∞ (infinity). In the case t ₃ is 0Hr, for soaking time is 0Hr, has the same graph and if ΔT is 200 ° C. as shown in FIG 9. Also, t ₃ is the case of ∞, because the soaking time is ∞, so has the same graph and if ΔT shown in FIG 13 is 200 ° C.. FIG. 15 also shows the change over time in the vacancy concentration at the via junction when the thermal cycle process is not performed. Here, the heating step is to release the condensation of holes by heating to a predetermined temperature (for example, ΔT is 100 ° C. or more), and the soaking step is to hold the time until the release of the condensation of holes is completed. It is.

As shown in FIG. 14 and FIG. 15, the holes when the semiconductor device is held at a temperature of 200 ° C. (soaking time) t ₃ is 0 hr and when t ₃ is 0.5 hr and 2 hr comparing the time course of concentration, soaking time t ₃ is 0.5 hr, better in the case of 2 hr, the finding that the vacancy concentration is kept low in more via junction. As shown in FIG. 15, when t ₃ is ∞ (infinite), the change with time in the vacancy concentration after 1 hour to 100 hours is not suppressed. Thus, in the thermal cycle process is finding that the preferred soaking time t ₃ exists, for example, a suitable soaking time t ₃ is within 2hr or more 0hr from the data in Figure 15. Moreover, processing time, because it is better as short as possible from the viewpoint of throughput, preferred soaking time _{t 3} is within 0.5hr least 0Hr. Furthermore, if the heat removal time in the heat removal step is long, vacancy condensation occurs during heat removal, so it is preferable that the heat removal time be short.

FIG. 16 is a graph showing the conditions of the heat cycle process when the heat removal time is changed in the heat cycle process including the heating step, the soaking step, and the heat removal step, and FIG. 17 is the condition shown in FIG. It is a graph which shows the simulation result of the time-dependent change of the void | hole density | concentration in a via junction part at the time of performing a heat cycle process. The conditions of the heat cycle step shown in FIG. 16 are as follows: the thermal fatigue temperature ΔT is 200 ° C., the soaking time t ₃ is 0.5 hr, and the heat removal time t ₄ is changed to 0.5 hr, 1 hr, 2 hr. Yes. Note that FIG. 11 also shows the change over time in the vacancy concentration at the via junction when the thermal cycle process is not performed.

16, from FIG. 17, be vacancy concentration is kept low at 200 ° C. to heat the semiconductor substrate time to heat removal was (heat removal time) as t ₄ is shorter via joints are finding. That is, when performing the heat removal in the heat cycling process, the short heat removal time t _4, i.e. more cooling rate is high it is preferable seen in heat removal. Here, the preferable cooling rate is 100 ° C./h or more from the data of FIG.

  As described above, with the data shown in FIGS. 9 to 17, the thermal cycle process is performed on the semiconductor device in which the process such as the wiring forming process, the other sintering process, the annealing process, etc. is performed to load or remove the heat from the semiconductor device. It is found that the aging changes in the vacancy concentration in the Cu wiring structure 18 and the via wiring 20 (particularly the via junction) are suppressed by performing the above. Moreover, it will be guessed about the conditions by which the time-dependent change of a void | hole density | concentration is efficiently suppressed in a heat cycle process.

  From the above data, it is presumed that the vacancy concentration is related to vacancy condensation due to stress in the semiconductor device and diffusion due to the vacancy concentration gradient. That is, when the temperature is increased, the vacancy condensation rate due to stress increases and the vacancy concentration increases, but the vacancy condensation rate has a maximum value and decreases when the temperature exceeds a certain temperature. On the other hand, the diffusion rate increases as the hole concentration gradient increases due to hole condensation. Therefore, the concentration of vacancies in the wiring is suppressed by reducing the vacancy concentration due to the decrease in the vacancy condensation rate due to stress and the increase in the diffusion rate due to the vacancy concentration gradient, thereby releasing the vacancy condensation. Will be.

As can be seen from the above knowledge, by performing the thermal cycle process under suitable conditions in the semiconductor device manufacturing process, it becomes possible to suppress the generation of void aggregates (cavities) called voids in the Cu wiring. In addition, the occurrence of wiring defects such as disconnection called so-called stress migration in the Cu wiring is suppressed. Furthermore, by performing the thermal cycle process under suitable conditions in the semiconductor device manufacturing process, it is possible to suppress an increase in the vacancy concentration in the Cu wiring structure and via junction over a long period after commercialization. It is possible to extend the life of the device.

  As mentioned above, although an example of embodiment of this invention was demonstrated, this invention is not limited to the form of illustration. It is obvious for those skilled in the art that various modifications or modifications can be conceived within the scope of the idea described in the claims, and these naturally belong to the technical scope of the present invention. It is understood.

  For example, in the above embodiment, a damascene wiring structure, particularly a dual damascene wiring structure, has been exemplified and described as the Cu wiring structure in the semiconductor device A. However, the manufacturing method for performing the thermal cycling process according to the present invention is not limited to these wiring structures. The present invention is also applicable to the general Cu wiring structure.

  The present invention can be applied to a semiconductor device manufacturing method and a semiconductor device.

DESCRIPTION OF SYMBOLS 1 ... Substrate body 2 ... Interlayer insulating film 4 ... Wiring groove 5 ... Barrier metal (BM) layer 7 ... Cu plating seed layer 10 ... Cu conductive layer 15 ... Cu wiring 18 ... Cu wiring structure 18a ... First layer 18b ... Second Layer 20: Via wiring

Claims (12)

In a method for manufacturing a semiconductor device having a copper wiring structure,
A method for manufacturing a semiconductor device, comprising performing a thermal cycle process of heating and removing a substrate to be processed after formation of a copper wiring layer including heat treatment. The method for manufacturing a semiconductor device according to claim 1, wherein a heating temperature in the thermal cycle step is 100 ° C. or higher. The method for manufacturing a semiconductor device according to claim 1, wherein in the heat cycle step, soaking is performed within 2 hours after heating. The method for manufacturing a semiconductor device according to claim 1, wherein the heat removal in the thermal cycle step is performed at a cooling rate of 100 ° C./h or more. In a method for manufacturing a semiconductor device having a damascene wiring structure,
A method for manufacturing a semiconductor device, comprising performing a thermal cycle step of heating and removing a substrate to be processed after wiring formation. The method for manufacturing a semiconductor device according to claim 5, wherein a heating temperature in the thermal cycle process is 100 ° C. or higher. The method for manufacturing a semiconductor device according to claim 5, wherein in the heat cycle step, soaking is performed within 2 hours after heating. The method for manufacturing a semiconductor device according to claim 5, wherein the heat removal in the thermal cycle step is performed at a cooling rate of 100 ° C./h or more. A semiconductor device having a damascene wiring structure,
A semiconductor device subjected to a thermal cycle for heating and removing a substrate to be processed after wiring formation. The semiconductor device according to claim 9, wherein a heating temperature in the thermal cycle is 100 ° C. or higher. The semiconductor device according to claim 9 or 10, wherein soaking is performed within 2 hours after heating in the thermal cycle. The semiconductor device according to claim 9, wherein the heat removal in the thermal cycle is performed at a cooling rate of 100 ° C./h or more.