TW201330118A - Package module with package embedded therein and method for manufacturing the same - Google Patents

Abstract

A package, a package module with the package embedded therein, and a method for manufacturing the same are disclosed. The package includes a first semiconductor chip, a dielectric layer, a first circuit layer, and a first molding material. The package module mainly includes the package, a second semiconductor chip, and a second molding. Because the package which is confirmed with good performance is used in the package module, the package module does not have the problem of bad performance due to the defect of the package.

Description

Package module with embedded package and manufacturing method thereof

The present invention relates to a package module and a package and a method for manufacturing the same, and more particularly to a known good die package, a package module in which the package is embedded, and a package thereof The manufacturing method of both.

With the rapid development of the electronics industry, electronic products tend to be light, thin and short in terms of type, and gradually become a high-function, high-performance, high-speed research and development direction in terms of functions. In order to meet the high integration and miniaturization requirements of semiconductor devices, the size of the embedded semiconductor wafer is also miniaturized, so the area of the electrode pads on the semiconductor wafer for electrical connection with the external is also the same. Shrinking, this situation increases the difficulty in electrically connecting and packaging the semiconductor wafer.

The semiconductor chip is electrically connected and packaged, and after the wafer carrier manufacturer transfers the carrier plate (such as the substrate or the lead frame) suitable for the semiconductor chip to the semiconductor package manufacturer, the semiconductor packager adheres the back surface of the semiconductor chip to the top of the package substrate. The surface is bonded by wire bonding, or the active surface of the semiconductor wafer is bonded to the package substrate by Flip chip bonding, and the solder ball is implanted on the back surface of the substrate to electrically connect with other electronic devices or passive components.

However, if a plurality of semiconductor wafers having a large size difference are to be packaged in the above packaging process, the package yield is lowered due to difficulty in consistent control of the process; or, due to poor packaging of the micro semiconductor wafer, the wafer The carrier board contains a short circuit or an open circuit or the micro semiconductor wafer is not electrically connected to the carrier board, resulting in electrical failure of the entire package module.

Accordingly, if a package technology can be developed, the micro semiconductor chip can be packaged first, and after testing to determine that it is a good good die package, the package is further pushed to a larger type. Forming a package module on another semiconductor wafer will ensure the yield and performance of the packaged module, and also avoid the overall package module caused by short circuit, open circuit or poor electrical connection of the microchip package. Unable to act.

The main object of the present invention is to provide a package body and a manufacturing method thereof, wherein a package for a microchip is used, and a metal foil, a release film and a carrier plate are used as a temporary substrate, and a wiring layer is formed in the process to remove the release pattern. The film and the carrier, but the metal foil can be retained and planned to form another circuit layer, so that the package can be completed through a simple and low-cost process without using the wafer carrier as conventionally, and the resulting package can be used first. Tested to determine its good performance, once further used to package the module, the possibility of the package being problematic can be ruled out.

To achieve the above object, an aspect of the present invention provides a package having a first surface and a second surface opposite to each other, and comprising: a dielectric layer having a wafer setting region on one side; The circuit layer is disposed on the side of the dielectric layer having the wafer mounting region, and has a first electrical connection pad and a conductive via hole, wherein the conductive via hole penetrates the dielectric layer and electrically connects the first layer a second circuit layer; a second circuit layer disposed on the opposite side of the dielectric layer and having a second electrical connection pad; at least one first semiconductor wafer disposed in the wafer setting region and having a first active a first passive surface, and a first electrode pad on the first active surface, wherein the first electrode pad is electrically connected to the first electrical connection pad, and the first passive surface faces the first And a first encapsulating material that encapsulates the first semiconductor wafer, the first wiring layer, and an electrical connection between the first electrical connection pad and the first electrode pad.

The above package can be manufactured by the following method. The method can include the following steps: providing a carrier, wherein the surface of the carrier has a release film; forming a conductive layer on the surface of the release film; Forming a patterned dielectric layer on the surface of the conductive layer, wherein the dielectric layer has a blind via; a patterned resist layer is formed on the dielectric layer, wherein the resist layer has an open area corresponding to Forming the blind hole; forming a first circuit layer in the opening area and the blind hole, wherein the first circuit layer has a first electrical connection pad and a conductive blind hole; removing the resistance layer to reveal a wafer setting area; at least one first semiconductor wafer is disposed on the wafer mounting area, wherein the first semiconductor wafer has a first active surface, a first passive surface, and a first surface of the first active surface An electrode pad, and the first passive surface of the first semiconductor wafer faces the wafer setting region; electrically connecting the first electrode pad and the first electrical connection pad; and molding the first semiconductor with a first encapsulation material Wafer, the first line a layer and an electrical connection between the first electrical connection pad and the first electrode pad; removing the carrier and the release film to expose the conductive layer; and patterning the conductive layer to form a second circuit layer, wherein the second circuit layer has a second electrical connection pad.

Compared with the prior art, the present invention sequentially applies a release film and a metal foil on the surface of the carrier as a temporary support plate to facilitate the use of a dielectric material in combination with a yellow light process and an electroplating process to form a circuit. The layer and the conductive blind hole of the two adjacent circuit layers are electrically connected. Finally, even after the release film and the carrier are removed, the metal foil can be retained to further form another circuit layer. Therefore, if the line is staggered, the circuit layer can be directly used for this purpose, so the line is The layer becomes a redistribution layer. If necessary, the electrical connection pads of the package can be concentrated on one side, and the package is electrically connected to other components. In addition, the above circuit layer can be formed by multiple electroplating to form a multi-layer metal structure, such as a copper/nickel/gold three-layer metal structure. In addition to having high strength, the multi-layer metal structure is also advantageous for semiconductor wafers and other components. Sexual connection.

In a preferred embodiment of the present invention, the method for fabricating the package further includes the steps of: forming a seed crystal on the surface of the dielectric layer and the inner wall of the blind via before the resist layer is formed on the dielectric layer. After the layer is removed, and the resist layer is removed, the seed layer is patterned according to the first circuit layer to expose the wafer setup region. In other words, the formed package may include a patterned seed layer disposed between the dielectric layer and the first circuit layer and between the first circuit layer and the second circuit layer. And the pattern of the seed layer is the same as the first circuit layer. In addition, the method for manufacturing the package further includes the steps of: forming a first adhesive film on the first passive surface before the first semiconductor wafer is placed on the wafer placement region; and the second electrical connection pad The surface forms a metal back layer. In other words, in the package, a first adhesive film is disposed between the first semiconductor wafer and the dielectric layer.

Another object of the present invention is to provide a package module and a manufacturing method thereof, which can be first classified according to the size of the wafer, and the wafers of similar size are designed and integrated for packaging to reduce the possibility of excessive size difference. The difficulty of the package is increased, resulting in a decrease in yield. The package is continuously packaged by using the tested and functional package, and the package module with high yield and high performance is formed by stacking the package and the wafer. A package in package with a package embedded therein.

In order to achieve the above object, another aspect of the present invention provides a package module comprising: a package substrate having a third electrical connection pad; and a second semiconductor chip having a second active surface and a second passive And a second electrode pad disposed on the second active surface, and disposed on the surface of the package substrate having the third electrical connection pad; a package having a first surface and a first surface opposite to the first surface Facing the second surface of the second active surface, and the package body comprises: a dielectric layer having a wafer setting region on one side thereof; a first circuit layer disposed on the dielectric layer and having the wafer setting region The first electrical connection pad and a conductive blind hole, wherein the conductive blind hole penetrates the dielectric layer and is electrically connected to the second circuit layer; a second circuit layer is disposed on the side On the opposite side of the electrical layer, and having a second electrical connection pad; a first semiconductor wafer disposed in the wafer placement region and having a first active surface, a first passive surface, and a first active a first electrode pad, wherein the first An electrode pad is electrically connected to the first electrical connection pad, and the first passive surface faces the first surface; and a first encapsulation material encapsulates the first semiconductor wafer, the first circuit layer, and the first Electrical connection between the first connection pad and the first electrode pad, wherein the second electrical connection pad is electrically connected to the third electrical connection pad and the second electrode pad; and a second encapsulation material Sealing the package, the second electrical connection pad, the second semiconductor wafer, the second electrode pad, the third electrical connection pad, the second electrical connection pad and the third electrical connection pad An electrical connection between the two and an electrical connection between the second electrical connection pad and the second electrode pad.

The package module of the present invention can be manufactured by the following method. The method can include the following steps: providing a package substrate, wherein the package substrate has a third electrical connection pad; and the package substrate has the third a second semiconductor wafer is stacked on the surface of the connection pad, wherein the second semiconductor wafer has a second active surface, a second passive surface, and a second electrode pad on the second active surface, and the second electrode pad The second passive surface faces the package substrate; a package is stacked on the second active surface, wherein the package has a first surface and a surface opposite to the first surface and facing the second active surface a second surface, and the package includes: a dielectric layer having a wafer placement region on one side; a first circuit layer disposed on the side of the dielectric layer having the wafer setup region and having a first An electrical connection pad and a conductive via hole, wherein the conductive via hole penetrates the dielectric layer and is electrically connected to the second circuit layer; a second circuit layer is disposed on an opposite side of the dielectric layer and has a Second electric a first semiconductor wafer disposed in the wafer setting region, and having a first active surface, a first passive surface, and a first electrode pad on the first active surface, wherein the first electrode Electrically connecting the first electrical connection pad, and the first passive surface faces the first surface; and a first encapsulation material, molding the first semiconductor wafer, the first circuit layer, and the first electrical An electrical connection between the connection pad and the first electrode pad; electrically connecting the second electrical connection pad and the third electrical connection pad and the second electrical connection pad and the second electrode pad; And molding the package body, the second electrical connection pad, the second semiconductor wafer, the second electrode pad, the third electrical connection pad, the second electrical connection pad and the second package material An electrical connection between the third electrical connection pad and an electrical connection between the second electrical connection pad and the second electrode pad.

In the above package module and the manufacturing method thereof, the package body of the present invention described above has similar advantages and effects. In addition, the package module of the present invention can protect the first semiconductor wafer sealed only by the first encapsulating material, avoiding the corrosion of the wafer or the electrical connection by external factors such as air humidity and improper stress, and can also improve the package. The structural strength prevents the package from being damaged due to insufficient strength of the first package material.

In the manufacturing method of the package module, before the second semiconductor wafer is stacked on the package substrate, and before the package is stacked on the second active surface, the method may include the following steps: The passive surface and the second surface respectively form a third adhesive film and a second adhesive film. In other words, a third adhesive film and a second adhesive film are respectively disposed between the second semiconductor wafer and the package substrate, and between the package and the second semiconductor wafer, to determine that each component is disposed on Pre-determined location.

Further, the above electrical connection is not particularly limited and may be wire bonding or flip chip bonding. In a preferred embodiment of the present invention, the electrical connection between the first electrical connection pad and the second electrical connection pad and the first electrical connection pad and the second electrode pad The electrical connection between them is wire bonding.

The embodiments of the present invention are described by way of specific examples, and those skilled in the art can readily appreciate the other advantages and advantages of the present invention. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

The drawings in the embodiments of the present invention are simplified schematic diagrams. However, the drawings show only the components related to the present invention, and the components shown therein are not in actual implementation, and the number of components, the shape, and the like in actual implementation are a selective design, and the component layout thereof. The pattern may be more complicated.

Embodiment 1

Referring to FIG. 1A to FIG. 1N, it is a schematic flow chart of manufacturing a package body in this embodiment.

First, as shown in FIG. 1A, a carrier 9 is provided, and a release film 10 is attached to the surface of the carrier 9. The material of the release film 10 and the carrier 9 is not particularly limited, and materials commonly used in the present invention can be used. Next, as shown in FIG. 1B, a conductive layer 11 is attached to the surface of the release film 10. In the present embodiment, a metal copper foil having a thickness of about 18 μm is used as the conductive layer 11.

As shown in FIG. 1C, a patterned dielectric layer 12 is formed on the surface of the conductive layer 11. The material of the dielectric layer 12 is not particularly limited, and a dielectric material commonly used in the art can be used. Next, a plurality of blind vias 120 are formed in the dielectric layer 12 by laser ablation or the like. Next, as shown in FIG. 1E, a seed layer 13 is formed on the surface of the dielectric layer 12 and the inner wall of the blind via 120. The material of the seed layer 13 is not particularly limited as long as the effect of conducting current can be achieved.

Then, as shown in FIG. 1F, a patterned resist layer 14 is formed on the surface of the seed layer 13 by photolithography. The resist layer 14 has an open area 141 corresponding to and completely revealing the blind via 120. . Here, the material used for the resist layer 14 is not particularly limited, and a photoresist material commonly used in the art can be used. Then, as shown in FIG. 1G, a first circuit layer 15 is formed in the open region 141 and the blind via 120. The first circuit layer 15 has a first electrical connection pad 153 and a conductive via hole. 152. In this step, the first wiring layer 15 of the multilayer metal layer structure may be formed by multiple electroplating, and the metal materials of the respective layers may be different. In this embodiment, the first circuit layer 15 is a circuit layer having a three-layer structure of a gold layer/nickel layer/copper layer and wherein the copper layer is a bottom layer contacting the seed layer 13, so that subsequent wire bonding can be facilitated. Or other similar electrical connections can also increase the strength of the circuit layer.

As shown in FIG. 1H, the resist layer 14 is removed, and the seed layer 13 not covered by the first wiring layer 15 is removed by etching to expose the wafer setting region Z. Next, as shown in FIG. 1I, at least one first semiconductor wafer 16 is prepared. The first semiconductor wafer 16 has a first active surface 16a, a first passive surface 16b, and a first surface of the first active surface 16a. Electrode pad 161. A first adhesive film 160 is attached to the first passive surface 16b of the first semiconductor wafer 16, and the first semiconductor wafer 16 is placed in the wafer setting region Z by the first adhesive film 160. This also means that the first semiconductor wafer 16 is disposed in the wafer setting region Z with the first passive surface 16b. Further, the material of the first adhesive film 160 is not particularly limited as long as the first semiconductor wafer 16 can be disposed in the wafer setting region Z.

Then, as shown in FIG. 1J, the first electrode pad 161 and the first electrical connection pad 153 are bonded by wire bonding. Next, as shown in FIG. 1K, the first semiconductor wafer 16, the first circuit layer 15, and the first electrical connection pad 153 and the first electrode pad 161 are encapsulated by a first encapsulation material 18. Electrical connection.

As shown in FIG. 1L, the carrier 9 and the release film 10 are removed to expose the conductive layer 11. Next, as shown in FIG. 1M, the conductive layer 11 is patterned to form a second wiring layer 11', wherein the second wiring layer 11' has a second electrical connection pad 113. Finally, as shown in FIG. 1N, a metal back layer 19 is formed on the surface of the second electrical connection pad 113. The metal back layer 19 may be a single layer or a plurality of layers of metal structures, and the material thereof may be determined as needed. If the second electrical connection pads 113 are used for wire bonding, a nickel/gold double layer structure or formation may be formed. An electroless nickel/electroless palladium/immersion gold (ENEPIG) multilayer structure is used as the metal back layer 19.

Accordingly, the package body 1 has a first surface 1a and a second surface 1b opposite thereto, and includes: a dielectric layer 12 having a wafer mounting region Z on one side; a first circuit layer The conductive layer 12 is disposed on the side of the dielectric layer 12 and has a first electrical connection pad 153 and a conductive via 152. The conductive via 152 extends through the dielectric layer 12 and Electrically connecting the second circuit layer 11'; a second circuit layer 11' is disposed on the opposite side of the dielectric layer 12 and has a second electrical connection pad 113; a first semiconductor wafer 16 is disposed on The first electrode pad 16 is disposed on the first active surface 16a, and the first electrode pad 161 is electrically connected to the first electrode pad 161. a first electrical connection pad 153, and the first passive surface 16b faces the first surface 1a; a first encapsulation material 18, the first semiconductor wafer 16, the first circuit layer 15, and the first electrical An electrical connection between the connection pad 153 and the first electrode pad 161; a patterned seed layer 13 disposed on the Between the dielectric layer 12 and the first circuit layer 15 and the first circuit layer and the second circuit layer 11', wherein the pattern of the seed layer 13 is the same as the first circuit layer 15; The adhesive film 160 is disposed between the first semiconductor wafer 16 and the dielectric layer 12; and a metal back layer 19 is disposed on the surface of the second electrical connection pad 113.

Embodiment 2

Referring to FIG. 2A to FIG. 2C , it is a schematic flowchart of manufacturing a package module according to the embodiment.

First, as shown in FIG. 2A, a package substrate 30 and a second semiconductor wafer 20 are provided. The package substrate 30 has a second electrical connection pad 301, and the second semiconductor wafer 20 has a second active surface 20a. a second passive surface 20b and a second electrode pad 201 on the second active surface 20a. A third adhesive film 21 is attached to the second passive surface 20b of the second semiconductor wafer 20.

Next, as shown in FIG. 2B, the second semiconductor wafer 20 is disposed on the surface of the package substrate 30 having the second electrical connection pad 301 by the third adhesive film 21. In addition, a second adhesive film 22 is attached between the second surface 1b of the package 1 made in the first embodiment and the second active surface 20a of the second semiconductor wafer 20.

Finally, as shown in FIG. 2C, the second electrical connection pad 113 and the third electrical connection pad 301 and the second electrical connection pad 113 and the second electrode pad 201 are bonded by wires 31 and 32, respectively. The package body 1, the second electrical connection pad 113, the second semiconductor wafer 20, the second electrode pad 201, the third electrical connection pad 301, and the second module are molded by a second encapsulation material 33. The electrical connection between the electrical connection pad 113 and the third electrical connection pad 301 and the electrical connection between the second electrical connection pad 113 and the second electrode pad 201 are electrically connected.

Accordingly, the package module comprises: a package substrate 30 having a third electrical connection pad 301; a second semiconductor wafer 20 having a second active surface 20a, a second passive surface 20b, and a second electrode pad 201 disposed on the second active surface 20a, and disposed on the surface of the package substrate 30 having the third electrical connection pad 301; a package body 1 having a first surface 1a opposite to the first surface a second surface 1b, and comprising: a dielectric layer 12 having a wafer setting region Z on one side thereof; a first wiring layer 15 disposed on the side of the dielectric layer 12 having the wafer setting region Z, and having a first electrical connection pad 153 and a conductive via 152, wherein the conductive via 152 extends through the dielectric layer 12 and is electrically connected to the second circuit layer 11'; a second circuit layer 11' is disposed on On the opposite side of the dielectric layer 12, and having a second electrical connection pad 113; at least one first semiconductor wafer 16, disposed in the wafer setting area Z, and having a first active surface 16a and a first passive surface 16b, and a first electrode pad 161 located on the first active surface 16a, wherein the first electrode pad 1 The first electrical connection pad 153 is electrically connected to the first electrical connection pad 153, and the first passive surface 16b faces the first surface 1a; a first encapsulation material 18 encapsulates the first semiconductor wafer 16, the first circuit layer 15 and An electrical connection between the first electrical connection pad 153 and the first electrode pad 161; a patterned seed layer 13 disposed on the dielectric layer 12 and the first circuit layer 15 and the first Between a circuit layer and the second circuit layer 11', wherein the pattern of the seed layer 13 is the same as the first circuit layer 15; a first adhesive film 160 is disposed on the first semiconductor wafer 16 and the Between the dielectric layers 12; and a metal back layer 19 disposed on the surface of the second electrical connection pad 113; a second encapsulation material 33, the package body 1, the second electrical connection pad 113, the Electrical connection between the second semiconductor wafer 20, the second electrode pad 201, the third electrical connection pad 301, the second electrical connection pad 113 and the third electrical connection pad 301, and the Electrical connection between the two electrical connection pads 113 and the second electrode pad 201; and a third adhesive film 21 and a second adhesive film 22 And disposed between the second semiconductor wafer 20 and the package substrate 30 and between the package 1 and the second semiconductor wafer 20 respectively.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

Z. . . Wafer setup area

1. . . Package

1a. . . First surface

1b. . . Second surface

9. . . Carrier board

10. . . Release film

11’. . . Second circuit layer

11. . . Conductive layer

113. . . Second electrical connection pad

12. . . Dielectric layer

120. . . Blind hole

13. . . Seed layer

14. . . Resistance layer

141. . . Open area

15. . . First circuit layer

152. . . Conductive blind hole

153. . . First electrical connection pad

16. . . First semiconductor wafer

16a. . . First active surface

16b. . . First passive surface

160. . . First adhesive film

161. . . First electrode pad

17, 31, 32. . . line

18. . . First packaging material

19. . . Metal back layer

20. . . Second semiconductor wafer

20a. . . Second active surface

20b. . . Second passive surface

201. . . Second electrode pad

twenty one. . . Third adhesive film

twenty two. . . Second adhesive film

30. . . Package substrate

301. . . Second electrical connection pad

33. . . Second encapsulating material

1A to FIG. 1N are schematic diagrams showing the process of manufacturing a package according to Embodiment 1 of the present invention.

2A to 2C are schematic diagrams showing the process of manufacturing a package module according to Embodiment 2 of the present invention.

1. . . Package

113. . . Second electrical connection pad

31, 32. . . line

201. . . Second electrode pad

301. . . Second electrical connection pad

33. . . Second encapsulating material

Claims (19)

A package module includes: a package substrate having a third electrical connection pad; a second semiconductor chip having a second active surface, a second passive surface, and a second active surface An electrode pad disposed on the surface of the package substrate having the third electrical connection pad; a package having a first surface and a second surface opposite the first surface and facing the second active surface The package includes: a dielectric layer having a wafer placement region on one side; a first circuit layer disposed on the side of the dielectric layer having the wafer setup region and having a first electrical connection pad And a conductive via hole, wherein the conductive via hole penetrates the dielectric layer and is electrically connected to the second circuit layer; a second circuit layer is disposed on the opposite side of the dielectric layer and has a second electrical property a first semiconductor wafer disposed in the wafer setting region, and having a first active surface, a first passive surface, and a first electrode pad on the first active surface, wherein the first electrode Pad electrically connecting the first electrical connection pad, and The first passive surface faces the first surface; and a first encapsulating material encapsulates the first semiconductor wafer, the first wiring layer, and the electricity between the first electrical connection pad and the first electrode pad The second electrical connection pad is electrically connected to the third electrical connection pad and the second electrode pad; and a second encapsulation material, the package body, the second electrical connection pad, Electrical connection between the second semiconductor wafer, the second electrode pad, the third electrical connection pad, the second electrical connection pad and the third electrical connection pad, and the second electrical connection An electrical connection between the pad and the second electrode pad. The package module of claim 1, further comprising: a third adhesive film and a second adhesive film respectively disposed between the second semiconductor wafer and the package substrate and the package and the package Between the second semiconductor wafers. The package module of claim 1, wherein the electrical connection between the second electrical connection pad and the third electrical connection pad and the second electrical connection pad and the first The electrical connection between the two electrode pads is a wire bonding. The package module of claim 1, wherein the package further comprises: a first adhesive film disposed between the first semiconductor wafer and the dielectric layer. The package module of claim 1, wherein the package further comprises: a metal back layer disposed on the surface of the second electrical connection pad. A method for manufacturing a package module, comprising the steps of: providing a package substrate, wherein the package substrate has a third electrical connection pad; and the package substrate has a surface of the third electrical connection pad a second semiconductor wafer, wherein the second semiconductor wafer has a second active surface, a second passive surface, and a second electrode pad on the second active surface, and the second passive surface faces the package substrate; A package body is stacked on the second active surface, wherein the package body has a first surface and a second surface opposite to the first surface and facing the second active surface, and the package body comprises: a dielectric layer having a wafer mounting region on one side thereof; a first wiring layer disposed on the side of the dielectric layer having the wafer mounting region and having a first electrical connection pad and a conductive via hole The conductive via hole penetrates the dielectric layer and is electrically connected to the second circuit layer; a second circuit layer is disposed on the opposite side of the dielectric layer and has a second electrical connection pad; Semiconductor wafer, set a first electrode surface, a first active surface, a first passive surface, and a first electrode pad on the first active surface, wherein the first electrode pad is electrically connected to the first electrical connection pad And the first passive surface faces the first surface; and a first encapsulating material, the first semiconductor wafer, the first circuit layer, and the first electrical connection pad and the first electrode pad are molded Electrical connection; electrically connecting the second electrical connection pad and the third electrical connection pad and the second electrical connection pad and the second electrode pad; and molding the package with a second encapsulation material The second electrical connection pad, the second semiconductor wafer, the second electrode pad, the third electrical connection pad, the second electrical connection pad and the third electrical connection pad An electrical connection and an electrical connection between the second electrical connection pad and the second electrode pad. The method for manufacturing a package module according to claim 6, further comprising the step of forming a third adhesive film on the second passive surface before the second semiconductor wafer stack is disposed on the package substrate. The method for manufacturing a package module according to claim 6, further comprising the step of forming a second adhesive film on the second surface before the package is disposed on the second active surface. The method of manufacturing a package module according to claim 6, wherein the electrical connection between the second electrical connection pad and the third electrical connection pad and the second electrical connection pad The electrical connection between the second electrode pad and the second electrode pad is a wire bonding. The method of manufacturing a package module according to claim 6, wherein the package further comprises: a first adhesive film disposed between the first semiconductor wafer and the dielectric layer. The method of manufacturing a package module according to claim 6, wherein the package further comprises: a metal back layer disposed on the surface of the second electrical connection pad. A package having a first surface opposite to the second surface, and comprising: a dielectric layer having a wafer mounting region on one side; a first wiring layer disposed on the dielectric layer a first electrical connection pad and a conductive blind hole, wherein the conductive blind hole penetrates the dielectric layer and is electrically connected to the second circuit layer; and a second circuit layer is disposed on An opposite side of the dielectric layer and having a second electrical connection pad; a first semiconductor wafer disposed in the wafer placement region and having a first active surface, a first passive surface, and a first a first electrode pad of the active surface, wherein the first electrode pad is electrically connected to the first electrical connection pad, and the first passive surface faces the first surface; and a first encapsulating material is molded a semiconductor wafer, the first circuit layer, and an electrical connection between the first electrical connection pad and the first electrode pad. The package of claim 12, further comprising: a patterned seed layer disposed between the dielectric layer and the first circuit layer and between the first circuit layer and the second circuit layer Wherein the pattern of the seed layer is the same as the first circuit layer. The package of claim 12, further comprising: a first adhesive film disposed between the first semiconductor wafer and the dielectric layer. The package of claim 12, further comprising: a metal back layer disposed on the surface of the second electrical connection pad. A method for manufacturing a package, comprising the steps of: providing a carrier plate, wherein the surface of the carrier plate has a release film; forming a conductive layer on the surface of the release film; and forming a patterned layer on the surface of the conductive layer An electric layer, wherein the dielectric layer has a blind via; a patterned resist layer is formed on the dielectric layer, wherein the resist layer has an open area corresponding to and reveals the blind via; Forming a first circuit layer in the blind via, wherein the first circuit layer has a first electrical connection pad and a conductive blind via; removing the resist layer to expose a wafer setup region; Depositing a first semiconductor wafer thereon, wherein the first semiconductor wafer has a first active surface, a first passive surface, and a first electrode pad on the first active surface, and the first semiconductor wafer a first passive surface facing the wafer setting region; electrically connecting the first electrode pad and the first electrical connection pad; molding the first semiconductor wafer, the first circuit layer, and the first Electrical connection pad and the first electrode Electrically connecting the two; removing the carrier and the release film to expose the conductive layer; and patterning the conductive layer to form a second circuit layer, wherein the second circuit layer has a The second electrical connection pad. The method for manufacturing a package according to claim 16, further comprising the steps of: forming a seed crystal on the surface of the dielectric layer and the inner wall of the blind via before the resist layer is formed on the dielectric layer; After the layer is removed, and the resist layer is removed, the seed layer is patterned according to the first circuit layer to expose the wafer setup region. The method for manufacturing a package according to claim 16, further comprising the step of forming a first adhesive film on the first passive surface before the first semiconductor wafer is placed on the wafer setting region. The method for manufacturing a package according to claim 16, further comprising the step of forming a metal back layer on the surface of the second electrical connection pad.