TW201318074A - Fabricating method of semiconductor element - Google Patents

Abstract

The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.

Description

Semiconductor component manufacturing method

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of fabricating a semiconductor device in an integrated circuit process.

1A and FIG. 1B, which are schematic top plan views showing the layout of some components on the integrated circuit wafer, mainly showing the active region 10 of the MOS transistor and the gate conductor structures 11, 12, due to the circuit layout. As needed, gate conductor structures 11, 12, respectively, having different extension directions as in Figures 1A and 1B, respectively, are produced. The active regions 10 on either side of the gate conductor structures 11, 12 are source/drain regions, and the active regions 10 covered by the gate conductor structures 11, 12 are where the channels are located. Thus, the widths W1, W2 of the gate conductor structures 11, 12 substantially define the length of the channel.

Due to the design requirements of the circuit, MOS transistors of different channel lengths are required on the same integrated circuit chip to provide different circuit characteristics, such as the on current Ion, and therefore, the width W1 of the gate conductor structures 11, 12. W2 has changing needs. In addition, the circuit characteristics of the MOS transistor can also be changed by changing the ion implantation angle when the source/drain region is defined.

However, as the size of the components is smaller and smaller, the widths W1 and W2 of the gate conductor structures 11 and 12 are also reduced, and the limit of the resolution of the exposure and development technology is almost reached, and the critical dimension of the gate conductor structure can be reduced (Critical) The degree of variation of Dimension (CD), a dipole exposure technique, was developed to change the shape of the source of the laser source for exposure, and to change the shape of the light source like the doughnut to Figure 2. The light source shape 20 is shown to enhance the exposure effect in the direction of the arrow 22 (parallel to the y direction) in the figure, but with the accompanying effect of the attenuation of the exposure effect in the direction of the arrow 21 (perpendicular to the y direction) in the figure. Therefore, if the light source shape 20 shown in FIG. 2 is used for exposure, the degree of variation of the critical dimension (CD) of the gate conductor structure 11 parallel to the y direction in FIG. 1A can be effectively controlled, but The width W2 of the gate conductor structure 12 perpendicular to the y-direction in 1B will not fall to the desired level due to the attenuation of the exposure effect, that is, the width W2 cannot reach the required critical dimension. However, according to the requirements of the current process, the width requirement of the gate conductor structure 12 has reached a smaller critical dimension, so the gold oxide semi-transistor having a smaller critical length of the channel in FIG. 1B cannot be utilized as shown in FIG. The shape of the light source is 20, and the limitations of this manufacturing method will result in a product design that is not flexible. How to improve such a deficiency is the main purpose of the development of this case.

An object of the present invention is to provide a method for fabricating a semiconductor device which can complete two axial integrated circuit wirings under the limitation of a dipole exposure technique, thereby increasing the flexibility of component fabrication.

In one embodiment of the invention, a method of fabricating a semiconductor device includes the steps of: providing a substrate; forming a first wiring structure having a first width over the substrate; above the first wiring structure having the first width Forming an etching mask to expose a portion of the first wiring structure; and etching the first wiring structure by using an etching mask to form a second wiring structure having a second width, wherein the The second width is less than the first width.

In another embodiment of the invention, the substrate is a germanium substrate, the first wiring structure is a first polysilicon gate structure, and the second wiring structure is a second polysilicon gate structure.

In another embodiment of the present invention, a method of forming the first polysilicon gate structure includes the steps of: forming a polysilicon gate layer and a first photoresist layer over a substrate on which an active region has been formed; The first mask defines a first photoresist layer to form a first photoresist mask; and the first photoresist mask is used to define the polysilicon gate layer to form a first polysilicon gate structure.

In another embodiment of the invention, one of the exposure processes is a dipole exposure when the first photoresist is used to define the first photoresist layer.

In another embodiment of the present invention, the substrate is a germanium substrate, the first wiring structure is a first active region, and the second wiring structure is a second active region.

In another embodiment of the present invention, the method for forming the first active region includes the steps of: forming a first photoresist layer over the substrate; defining a first photoresist layer using a first mask to form a first light a mask: defining a substrate using a first photoresist mask to form a plurality of shallow trenches and a first active region surrounded by shallow trenches.

In another embodiment of the present invention, a method of forming an etch mask includes the steps of: forming a second photoresist layer over a substrate on which the first wiring structure has been formed; and defining a second photoresist using a second mask The layers form an etch mask.

In another embodiment of the present invention, a first wiring structure having a first width is formed over the substrate, and a third wiring structure having a third width is formed over the active region, and the extending direction of the third wiring structure is The extending direction of the first wiring structure is substantially orthogonal.

In another embodiment of the invention, the third width is less than the first width.

In the above method for manufacturing a semiconductor device, by using an etching mask which exposes a part of the gate structure and an etching process, two axial integrated circuit wirings can be completed under the limitation of dipole exposure, and further Increase the flexibility of component fabrication.

In order to improve the lack of effective reduction of the gate conductor structure width in the conventional means, the present invention proposes a schematic diagram of the steps of the semiconductor device manufacturing method shown in FIGS. 3A to 3C. First, FIG. 3A shows that the germanium substrate 3 has been completed. There is an active region 30, a first gate conductor structure 31 and a third gate structure 31', wherein the active region 30 can be formed by a shallow trench isolation structure (STI, which is not shown in the figure). The enclosure is defined to complete the source/drain regions and channel regions in the MOS transistor. The active region 30 covered by the first gate conductor structure 31 is where the channel region is located. The first gate conductor structure 31 can be completed by forming a polysilicon gate layer (not shown in this figure) and a first photoresist layer (not shown in the figure) above the substrate 3 on which the active region 30 has been formed. Defining the first photoresist layer using a first mask to form a first photoresist mask (not shown in the figure), using the first photoresist mask to define the polysilicon gate layer to form a gate conductor structure, The first gate conductor structure 31 and the third gate conductor structure 31' extending in the x direction and the y direction, respectively, are included.

When the first gate conductor structure 31 and the third gate conductor structure 31' are defined by dipole exposure, wherein the third gate conductor structure 31' extends in the direction (y direction) and the bipolar exposure technique The extending direction (y direction) of the shape of the laser light source used is parallel, as shown in the left half of FIG. 3A, so that the width D1' of the third gate conductor structure 31' can be reduced to a predetermined value, for example, 120 nm. However, since the extending direction (x direction) of the first gate conductor structure 31 is not parallel or even orthogonal to the extending direction (y direction) of the shape of the laser light source used in the bipolar exposure technique, as shown in the right half of FIG. 3A. As shown, this will cause the width D1 of the first gate conductor construction 31 to fail to achieve the desired smaller CD requirements. In order to increase the flexibility of the design, another reticle lithography process is used to form the etch mask 32 as shown in FIG. 3B, for example, the first gate conductor structure 31 and the third gate conductor have been formed. Forming a second photoresist layer (not shown in the figure) on the substrate 3 of the structure 31', and then defining the second photoresist layer using a second mask to form the etching mask 32 for exposing a portion The first gate conductor construction 31. The exposure technology used in the reticle lithography process uses a conventional circular light source for exposure instead of dipole exposure, so there is no problem that the exposure effect is attenuated.

Then, the exposed portion of the first gate conductor structure 31 is etched by the etching mask 32 to form a second gate conductor structure 33 having a width D2 as shown in FIG. 3C. It is apparent that D2 is smaller than D1. In order to overcome the limitation of resolution, two masks have been used in the conventional method - two etching (2P2E) technology is applied to the production process of integrated circuit wiring, so another reticle lithography added in this case The process can be integrated into the second mask and the second etch in the 2P2E without adding process steps.

In addition, the technology of the present invention can be applied to other similar wiring structures, such as active regions surrounded by shallow trenches, in addition to the fabrication of the gate conductor structure.

In summary, after the technology of the present invention is improved, the problem of the conventional means can be effectively improved, and the two axial integrated circuit wiring can be completed under the limitation of the dipole exposure technique. , thereby increasing the flexibility of component fabrication.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10, 30. . . Active area

11,12. . . Gate conductor construction

20. . . light source

21, 22. . . arrow

3. . .矽 substrate

31. . . First gate conductor construction

32. . . Etching mask

33. . . Second gate conductor construction

31’. . . Third gate conductor construction

W1, W2, D1, D2, D1'. . . width

1A to 1B, which are schematic top views showing the layout of some components on an integrated circuit wafer.

Figure 2 is a schematic diagram showing the shape of a light source in a bipolar exposure technique.

3A-3C are schematic diagrams showing the steps of a method for fabricating a semiconductor device disclosed in the present disclosure.

30. . . Active area

31. . . First gate conductor construction

31’. . . Third gate conductor construction

32. . . Etching mask

Claims (10)

A semiconductor device manufacturing method comprising the steps of: providing a substrate; forming a first wiring structure having a first width over the substrate; forming an etching mask over the first wiring structure having the first width And exposing a portion of the first wiring structure; and etching the first wiring structure by using the etching mask to form a second wiring structure having a second width, wherein the second width Less than the first width. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is a germanium substrate, the first wiring structure is a first polysilicon gate structure, and the second wiring structure is a second poly layer.矽 Gate structure. The method of fabricating a semiconductor device according to claim 2, wherein the method of forming the first polysilicon gate structure comprises the steps of: forming a polysilicon gate layer and a layer over the substrate on which an active region has been formed. a first photoresist layer; defining a first photoresist layer using a first mask to form a first photoresist mask; and defining the polysilicon gate layer using the first photoresist mask to form the first plurality Crystal gate structure. The method of manufacturing a semiconductor device according to claim 3, wherein one of the exposure processes is a dipole exposure when the first photomask is used to define the first photoresist layer. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is a germanium substrate, the first wiring structure is a first active region, and the second wiring structure is a second active region. The method of fabricating a semiconductor device according to claim 5, wherein the method of forming the first active region comprises the steps of: forming a first photoresist layer over the substrate; defining the first using a first mask The photoresist layer forms a first photoresist mask; the first photoresist mask is used to define the substrate to form a plurality of shallow trenches and the first active region surrounded by the shallow trenches. The method of manufacturing a semiconductor device according to claim 6, wherein one of the exposure processes is a dipole exposure when the first photomask is used to define the first photoresist layer. The method of fabricating a semiconductor device according to claim 1, wherein the method of forming the etch mask comprises the steps of: forming a second photoresist layer over the substrate on which the first wiring structure has been formed; and using A second mask defines the second photoresist layer to form the etch mask. The method of fabricating a semiconductor device according to claim 1, wherein the third wiring structure having the first width is formed over the substrate, and the third region having a third width is formed over the active region. The wiring structure, the extending direction of the third wiring structure is substantially orthogonal to the extending direction of the first wiring structure. The method of manufacturing a semiconductor device according to claim 9, wherein the third width is smaller than the first width.