TW201539718A - Integrated circuit layout and semiconductor device - Google Patents

Abstract

Provided is an embedded FinFET SRAM structure and methods of making the same. The embedded FinFET SRAM structure includes an array of SRAM cells. The SRAM cells have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction. The first and second pitches are configured so as to align fin active lines and gate features of the SRAM cells with those of peripheral logic circuits. A layout of the SRAM structure includes three layers, wherein a first layer defines mandrel patterns for forming fins, a second layer defines a first cut pattern for removing dummy fins, and a third layer defines a second cut pattern for shortening fin ends. The three layers collectively define fin active lines of the SRAM structure.

Description

Structure and method of fin field effect transistor static random access memory

The semiconductor integrated circuit industry has experienced rapid growth. During the growth of the integrated circuit, the functional density (e.g., the number of internal connections per wafer area) is increased as the geometry (e.g., the smallest component (or line) created by the process) is reduced. The general benefit of such a reduction process is to increase production efficiency and reduce associated costs. Such reduction processing also increases the complexity of processing and manufacturing integrated circuits, and in order to achieve these developments, it is necessary to make the same development in the manufacture of integrated circuits.

For example, logic circuits and embedded static random access memory (SRAM) cells are often integrated into semiconductor devices to increase functional density. In the industry, such applications include scientific subsystems, automotive electronics, cell phones, digital cameras, microprocessors, etc. In order to meet the high SRAM density requirements, simply reducing the feature size of the semiconductor is not sufficient. For example, in the fabrication of smaller sized semiconductors, the performance of conventional SRAM cell structures with flat transistors can be reduced and have large leakage currents. To solve the problem, one technique uses a three-dimensional transistor having a fin or multi-fin structure (such as a fin field effect transistor). For example, fin field effect transistors can be used to control the short channel effects of metal oxide semiconductor field effect transistors (MOSFETs). In order to achieve the desired short channel control and reduced area, it is desirable to thin the fin structure as much as possible. In order to thin the fin structure, a technique utilizes gap lithography. For example, A gap will be formed in the sidewall of the mandrel pattern. When the fin structure is formed, when the mandrel pattern is removed, the gap becomes an etch mask for etching a substrate. The mandrel pattern and the size of the gap control the width and spacing of the fin structure. In implantable fin field effect transistor SRAM, it is a challenge to strictly control the homogenization of the important dimension (CD) of the mandrel pattern and the gap.

A detailed description of each aspect of the disclosure can be better understood with reference to the following drawings. It should be noted that various features are not drawn to scale in accordance with standard practice in the art. In fact, the dimensions of the various features can be arbitrarily enlarged or reduced for clarity of discussion.

1 is a simplified block diagram of an integrated circuit with implanted SRAM cells in accordance with many aspects of the present disclosure.

Figure 2 shows an implanted SRAM cell with peripheral logic circuitry in accordance with many aspects of the present disclosure.

Figure 3 shows a possible embodiment of some of the components of the peripheral logic of Figure 2.

4A and 4B are schematic views showing a six transistor 單埠SRAM cell according to an embodiment.

Figures 5-7 show different embodiments of the partial layout of the six transistor 單埠SRAM cells shown in Figure 4A.

Figure 8 shows a possible schematic of a double-twist SRAM cell.

Figure 9 shows a different embodiment of the partial layout of the double-turn SRAM cell shown in Figure 8.

Figures 10A and 10B show implants in accordance with many aspects of the present disclosure Schematic diagram of metal traces designed by SRAM.

Figure 11 is a simplified block diagram of an integrated circuit with implanted SRAM cells in accordance with many aspects of the present disclosure.

Figure 12A shows a layout of the fin active line of a four SRAM cell in accordance with many aspects of the present disclosure.

Figure 12B shows a possible schematic diagram of a three-layer splitting of the fin active line layout shown in Figure 12A.

Figure 12C shows a possible schematic diagram of the partially overlapping gate features of the fin active lines of the four SRAM cells shown in Figure 12A.

Figure 13 shows a schematic diagram of a method of forming an integrated circuit with implanted SRAM cells in accordance with many aspects of the present disclosure.

Figures 14-20B show top and cross-sectional views of an implanted SRAM cell formed using the method illustrated in Figure 13.

Figure 21 shows a schematic diagram of a method of forming an integrated circuit with implanted SRAM cells in accordance with many aspects of the present disclosure.

Figures 22A-24C show top and cross-sectional views of an implanted SRAM cell formed using the method illustrated in Figure 21.

Figure 25A shows a layout diagram of a fin active line of four SRAM cells in accordance with many aspects of the present disclosure.

Fig. 25B shows a three-layer splitting diagram of the fin active line office shown in Fig. 25A.

Fig. 25C is a diagram showing the gate characteristics of the fin type active line of the four SRSM cells partially overlapped in Fig. 25A.

The disclosure provides various embodiments or examples to implement different features of the subject matter. The specific embodiments described below are for the purpose of simplifying the disclosure, but the disclosure is not limited thereto. For example, a description of a first feature above or in a second feature may include forming the first and second features in direct contact with one embodiment, and may also include an additional feature formed in the first Between the second feature and the second feature, and the first and second features may not be in direct contact with one embodiment. Furthermore, the disclosure may reuse reference numerals and/or nouns in the various embodiments. The above repetitive views are for simplicity and clarity and do not indicate one of the various embodiments and/or configurations discussed.

In addition, plural relative terms such as "above", "below", "below", "above", "above", etc. are used for convenience of explanation. The description illustrates the relationship between one element or feature and another element or feature. The relative terms are intended to cover the particular orientation of the device in the various orientations of the application or the operation. The device may have other orientations (eg, rotated 90 degrees or other directions) and the relative terms used in this disclosure may also be interpreted accordingly.

FIG. 1 shows a semiconductor device 100 having an SRAM macro 102. The semiconductor device can be, for example, a microprocessor, a specific application integrated circuit, a programmable logic gate array, or a digital signal processor. The correct function of the semiconductor device 100 is not limited to the above.

2 is a partial detailed schematic diagram of an SRAM macro 102 in accordance with the present disclosure. Referring to FIG. 2, the SRAM macro 102 includes a plurality of SRAM cells 202 and a plurality of peripheral logic circuits 210. When peripheral logic circuit 210 performs many logic functions, such as write and/or read address decoding, character/bit selection, data drive Motion, memory self-test, etc., each SRAM cell 202 stores a memory bit. Logic circuit 210 has a plurality of fin field effect transistors. Each fin field effect transistor has a gate feature 218 and a finned active line 212. Although not shown, each SRAM cell 202 also has a plurality of fin field effect transistors, each fin field effect transistor. It has a gate feature and a fin active line. Additionally, while FIG. 2 shows only 16 SRAM cells 202, the SRAM macro 102 in the semiconductor device 100 may include a greater number of SRAM cells 202. For example, SRAM macro 102 may have thousands or millions of SRAM cells 202.

As shown in FIG. 2, the SRAM cell 202 overlaps a plurality of P-type well regions or P-type doped regions (such as an n-type fin field effect transistor or an N-fin field effect transistor) and a complex N-type well region or N-type doping. A region (such as a p-type fin field effect transistor or a P-fin field effect transistor), wherein the P-type well region N-type well region is a rectangular semiconductor region, which is alternately disposed in the X direction. As will be shown later, each SRAM cell 202 has a plurality of N-fin field effect transistors and a plurality of P-Fin field effect transistors. In addition, the SRAM cells 202 are arranged in an array with the immediately adjacent SRAM cells. Each SRAM cell 202 occupies a rectangular region of the SRAM macro 102, wherein the rectangular region has a first dimension 204 in the X direction and a second dimension 206 in the Y direction, the X direction being perpendicular to the X direction. In the following description, the first size 204 is referred to as the X pitch of the SRAM cell 202, and the second size 206 is referred to as the Y pitch of the SRAM cell 202.

In addition, each SRAM cell 202 is arranged in one of four directions. As shown in FIG. 2, group 203 includes four SRAM cells 202 in a 2X2 matrix, represented by symbols Cell-R0, Cell-Mx, Cell-My, and Cell-R180, respectively, for ease of discussion. In an embodiment, the gate feature of the symbol Cell-R0 and the fin active line are symbols Cent-Mx at the center point through the group 203 and in the X direction The mapped image of the dotted line A-A. Similarly, the gate feature of the symbol Cell-R0 and the fin active line are mapped images of the symbol Cell-My at the center point of the group 203 and the dotted line B-B in the Y direction. Similarly, the gate feature and the fin active line of the symbol Cell-R180 are the mapped image of the symbol Cell-Mx at the broken line B-B and the mapped image of the corresponding symbol Cell-My at the dotted line A-A.

As semiconductor technology progresses to small feature sizes, such as 32 nm, 20 nm, or less, limited design rules are often followed to change the design product. The structure of SRAM macro 102 shown in FIG. 2 allows features of peripheral logic circuit 210 (such as gate feature 218 and fin active line 212) to be aligned with corresponding features of SRAM cell 202. This can be done by carefully considering the ratio between the X pitch 204 and the fin pitch 214 and the ratio between the Y pitch 206 and the gate pitch 216. Such an arrangement can increase the density of the fin active line, thus providing a number of benefits, such as high density SRAM cells, high manufacturing reliability in optical proximity effects, and the like. In addition, a fixed ratio between the Y pitch 206 and the gate pitch 216 causes certain peripheral logic circuits (such as word line drivers, decoders, etc.) to be automatically generated as a circuit group, which are individually extended. Set up with SRAM cells. Likewise, a fixed ratio between the X pitch 204 and the fin pitch 214 causes certain peripheral logic circuits (such as row selectors, bit line precharge circuits, decoders, etc.) to be automatically generated and set.

FIG. 3 is a partial top view of peripheral logic circuit 210. Each fin type active line 212 has a rectangular shape with a long side extending in the Y direction and a wide side extending in the X direction. In this embodiment, the gap between the edges of the two adjacent fin active lines 212 is used as the fin spacing 214, or the gap between the center line and the center line of the two adjacent fin active lines 212 is used as a fin. Interval 214. Gate Sign 218 vertical fin active line 212. Each of the gate features 218 has a rectangular shape with a long side extending in the X direction and a wide side extending in the Y direction. In the present embodiment, the gate pitch 216 is the gap between the opposite sides of two adjacent gate features 218 or the gap between the centerline and centerline of two adjacent gate features 218. The peripheral logic circuit 210 further includes a plurality of active contacts 220 coupled to the plurality of fin active lines 212 for forming a common germanium/source of the corresponding fin field effect transistors.

Figure 4A is a schematic diagram of a SRAM cell having six transistors (6T) 單埠 (SP), which can be used as the SRAM cell 202 of Figure 2. Referring to FIG. 4A, the six-electrode 單埠SRAM cell 202 has two P-fin field effect transistors PU-1 and PU-2, two N-fin field effect transistors PD-1 and PD-2, and two N-fin fields. Effect transistors PG-1 and PG-2. P-Fin field effect transistors PU-1 and PU-2 are used as pull-up transistors. N-fin field effect transistors PD-1 and PD-2 are used as pull-down transistors. The N-fin field effect transistors PG-1 and PG-2 function as pass gate transistors. PU-1 and PD1 are used to form an inverter (Inverter-1 shown in Fig. 4B). PU-2 and PD2 are used to form another inverter (Inverter-2 shown in Fig. 4B). Inverter Inverter-1 and Inverter-2 are coupled across each other to form a memory cell of SRAM cell 202. Figure 4A shows the word line (WL), the bit line (BL), and the inverted phase element ( ), a storage unit for accessing the SRAM cell 202.

In fact, the SRAM cell 202 (e.g., layout) of Figure 4A can be physically implemented using a number of methods. Three layouts of the SRAM cell 202, referred to as SRAM cell 202A, SRAM cell 202B, and SRAM cell 202C, will be described below in accordance with various aspects of the present disclosure. Those skilled in the art should understand that the three embodiments are only for explanation, and are not intended to limit the scope of the present invention.

Figure 5 shows a top view of a partial layout of an SRAM macro 102 with SRAM cells 202A. Referring to FIG. 5, the SRAM cell 202A has a rectangular boundary (shown by a dashed line) having a first size (X pitch) 204A and a second size (Y pitch) 206A. The layout includes an N-well active zone and two P-well active zones, and the two P-well active zones are respectively disposed on the X-direction side of the active zone of the N-well. This layout further includes two fin active lines 222A and 224A. The two-fin active lines 222A and 224A are respectively disposed in the active areas of the two P-wells and extend longitudinally in the Y direction and overlap the SRAM cells 202A. The layout further includes two fin active lines 226A and 228A, each of which is disposed in the active region of the N well and extends longitudinally in the Y direction and overlaps a portion of the SRAM cell 202A. The edge-to-edge gap between the finned active lines 222A, 226A, 228A, and 224A is twice the fin spacing 214. In some embodiments, the gap between the finned active lines is set between 2 and 2.5 times the fin pitch 214 to provide sufficient design space and processing space when forming the SRAM finned line. In this example, the X pitch 204A may still be maintained at an integer multiple of the fin pitch 214. Additionally, this layout includes two gate features 232A and 234A and two gate features 236A and 238A. The two gate features 232A and 234A extend lengthwise in the X direction and overlap a portion of the SRAM cell 202 and are shared by the SRAM cell 202A with an adjacent SRAM cell (not shown). The two gate features 236A and 238A extend lengthwise in the X direction in the SRAM cell 222A. The above-described gate features together with the fin active line define the six transistors PU-1/2, PD-1/2, and PG-1/2 of FIG. The Y pitch 206A is approximately equal to the sum of the pitches of the pass gate transistor (PG-1 or PG-2) and the pull-down transistor (PD-1 or PD-2), wherein the spacing of one transistor is its source and drain the distance between.

In an embodiment, the X pitch 204A is set to be approximately between fins At a distance of 8, 8.5 or 9 from 214 (Fig. 3), the Y pitch 206A is set to be approximately twice the gate pitch 216 (Fig. 3). Such a setting considers the characteristic arrangement between the SRAM cell 202A and the peripheral logic circuit 210, and the feature arrangement between the SRAM cell 202A and the peripheral logic circuit 210 is to improve the semiconductor device 100 having the SRAM macro 102 (1st and 2nd) Figure) The overall manufacture. For example, a single fin pitch rule in SRAM cell 202A and peripheral circuitry 210 assists in improving the important dimensions of the unified fin active line during lithography. For its simple layout, the density of the SRAM cell 202A in the SRAM product can be increased. In one embodiment, if a high density of memory cells is desired, the SRAM macro 102 (Fig. 2) has only SRAM cells of this type, and the X pitch 204A is set to be approximately the fin spacing 214 (Fig. 3). 8 times. In another embodiment, the X pitch 204A is set to be approximately 9 times the fin pitch 214. In some embodiments, the X pitch 204A is set to a non-integer multiple of the fin pitch 214, such as 8.5 times. In SRAM macro 102 (Fig. 2), the architecture of SRAM cell 202A may be four adjacent SRAM cells 202A having an X dimension that is an integer multiple (e.g., 34 times) of fin pitch 214. After the SRAM cell 202A is placed, the fin active line between the SRAM cell 202A and the peripheral logic circuit 210 can still be maintained in an appropriate arrangement. Such flexibility is one of many benefits of the present disclosure.

Figure 6 shows a partial layout of the SRAM cell 202B, and Figure 7 shows a partial layout of the SRAM cell 202C. SRAM cells 202B and 202C are similar in many respects to SRAM cell 202A, and the description thereof is omitted for the sake of brevity.

Referring to FIG. 6, the SRAM cell 202B is represented by a rectangular boundary (as indicated by a broken line) having a first size (X pitch) 204B and a second size (Y pitch) 206B. One difference between the SRAM cells 202B and 202A is that in the SRAM cell 202B, each P-well active region has a two-fin active line 222B-1/2 and 224B-1/2. In fact, the transistors PG-1/2 and PD-1/2 of the SRAM cell 202B have a double-fin active line for increasing the amount of current source. The edge-to-edge of the two fins 222B-1 and 222B-2 is separated by a fin spacing 214, as are the two fins 224B-1 and 224B-2. In the present embodiment, the X pitch 204B is approximately twice the fin pitch 214 (Fig. 3), and is therefore larger than the X pitch 204A (Fig. 5). A similar situation to FIG. 5 includes that the Y pitch 206B is approximately twice the pole pitch 216. In one embodiment, the ratio between the X pitch 204B and the Y pitch 206B is about 2.7 to 2.9.

A similar portion of the SRAM cell 202C of Fig. 7 is that the transistors PG-1/2 and PD-1/2 of the SRAM cell 202C have three-fin active lines 222C-1/2/3 and 224C-1/2/. 3, respectively, to increase the current source amount; X spacing 204C is 4 times the fin spacing 214 (Fig. 3), greater than the X spacing 204A (Fig. 5); and the Y spacing 206C is approximately the gate spacing 216 (3rd) Figure) 2 times. The edge-to-edge of the three-fin 222C-1, 222C-2, and 222C-3 is separated by a fin spacing 214, as are the three-fin 224C-1, 224C-2, and 224C-3.

Figure 8 shows a top view of two SRAM cells 202D, which can be used as SRAM cells 202 of Figure 2. As shown in FIG. 8, the SRAM cell 202D has a write port portion 802 and a read port portion 804. The write buffer portion 802 is actually a six transistor 單埠SRAM cell as shown in FIG. The read buffer portion 804 has a read pull-down transistor R_PD and a read pass gate transistor R_PG.

In fact, the SRAM cell 202D shown in Figure 8 can be fabricated physically (e.g., in a layout) in a number of ways. Figure 9 is a top view of a partial layout of the SRAM cell 202D'. Referring to FIG. 9, when the layout of the read 埠 portion 804 has the transistors R_PD and R_PG, the layout of the read 埠 portion 802 is substantially the same as that of the SRAM cell 202B (Fig. 6), and the transistors R_PD and R_PG are double fins. Fin field effect transistor body. The edge-to-edge of the two-fin active lines 902-1 and 902-2 is separated by a fin spacing 214. Many of the features of SRAM cell 202D are similar to those previously discussed in Figures 5-7 and will not be described in detail. In one embodiment, to improve the process and circuit density of the SRAM macro 102 having the SRAM cell 202D, the Y-spacing 206D is set to be approximately when the X-pitch 204D is an integer multiple (eg, 15 times) the fin pitch 214. Double the gate pitch 216.

Figures 10A and 10B show metal traces of SRAM cells in accordance with some embodiments. Figure 10A shows the power supply line (Cvdd), the bit line (BL), and the inverted phase element ( ), each of which is disposed on the first metal layer, and the word line (WL) and the ground line (Vss) are both disposed on the second metal layer. FIG. 10B shows that the word line (WL) is disposed on the first metal layer, and the power supply line (Cvdd), the bit line (BL), and the inverted phase element line ( And the ground line (Vss) is disposed on the second metal layer. In an embodiment, the first metal layer is between the second metal layer and the active regions of the respective SRAM cells. In one embodiment, the first and second metal layers are connected together through the inner layer vias.

In some applications, a semiconductor device may have a complex SRAM macro. Care must be taken to ensure that each SRAM macro is at the device level and the circuit density. The current disclosure is to solve such problems. FIG. 11 shows the semiconductor device 100. The semiconductor device 100 has other SRAM macros 104 in addition to the SRAM macro 102. Although the two SRAM macros in FIG. 11 are disposed adjacent to each other, in fact, two SRAM macros may be disposed anywhere in the semiconductor device 100. Additionally, the two SRAM macros 102 and 104 may have the same or different types of SRAM cells. For example, SRAM macro 102 has an array of SRAM cells 202A, while SRAM macros 104 have SRAM cells 202A, 202B, An array of 202C or 202D. The following are some embodiments of semiconductor device 100 in which the SRAM macro and peripheral logic can be placed in a number of sizes to improve full wafer layout automation, homogenize fin active line main dimensions, and manufacturability of the overall device.

In one embodiment, SRAM macro 102 includes an array of SRAM cells 202A (Fig. 5), and SRAM macro 104 includes an array of SRAM cells 202B (Fig. 6). The X pitch 204B is set to be approximately X pitch 204A plus twice the fin pitch 214 (Fig. 3). In one embodiment, the X pitch 204A is set to approximately eight times the fin pitch 214, and the X pitch 204B is set to approximately ten times the fin pitch 214. In another embodiment, the X pitch 204A is set to approximately 8.5 times the fin pitch 214, and the X pitch 204B is set to approximately 10.5 times the fin pitch 214. In other embodiments, the X pitch 204A is set to approximately 9 times the fin pitch 214, and the X pitch 204B is set to approximately 11 times the fin pitch 214. The Y pitches 206A and 206B are each set to approximately 2 times the gate pitch 216. In addition, the ratio of the X pitch 204B to the Y pitch 206B is between about 2.7 and 2.9, such as 2.8, and the ratio of the X pitch 204A to the Y pitch 206A is between about 2.25 and 2.28, such as 2.2667.

In one embodiment, SRAM macro 102 includes SRAM cell 202B (Fig. 6), while SRAM macro 104 includes an array of SRAM cells 202D (Fig. 8). The X pitch 204B is set to approximately 10 times the fin pitch 214 (Fig. 3), and the X pitch 204D is set to approximately 15 times the fin pitch 214. The Y pitches 206B and 206D are each set to approximately 2 times the gate pitch 216.

In one embodiment, SRAM macro 102 includes SRAM cell 202B (Fig. 6), while SRAM macro 104 includes SRAM cell 202C (Fig. 7). An array of them. The X pitch 204C is set to be about the X pitch 204B plus twice the fin pitch 214 (Fig. 3). For example, the X pitch 204B is set to approximately 10 times the fin pitch 214, and the X pitch 204C is set to approximately 12 times the fin pitch 214. For example, the X pitch 204B is set to approximately 10.5 times the fin pitch 214, and the X pitch 204C is set to approximately 12.5 times the fin pitch 214.

Figure 12A shows a fin active line of group 203 (Fig. 2) comprising four adjacent SRAM cells 202A (Fig. 5), Cell-R0, Cell-My, Cell-Mx, and Cell-R180. The four adjacent SRAM cells are arranged in 2 rows and 2 columns. The dotted line A-A indicates the boundary of the four adjacent SRAM cells in the X direction, and the broken line B-B indicates the boundary of the four adjacent SRAM cells in the Y direction. Regarding the structure of the fin active line (shape, size, and position in the cell), according to the dotted line AA, Cell-R0 and Cell-My are the mapped images of Cell-Mx and Cell-R180, and according to the broken line BB, Cell -R0 and Cell-Mx are mapped images of Cell-My and Cell-R180. In the present disclosure, the formation of these finned active lines is etched using three masks (or mesh lines), such as 1202, 1204, and 1206 shown in FIG. 12B.

Referring to FIG. 12B, the three masks 1202, 1204, and 1206 are three layers of the design layout of the SRAM macro 102 (the SRAM macro 102 in the semiconductor device 100). The mask 1202 defines a mandrel pattern for forming a void, the mask 1204 defines a virtual fin cut pattern for removing virtual voids (or virtual fin lines), and the mask 1206 defines a fin tail cut pattern, such as The pull-up transistors (such as PU-1 and PU-2 in Figure 5) have short fin lines. Each mandrel pattern has a rectangular shape (upper view) extending longitudinally in the Y direction. In one embodiment, although not shown, each mandrel pattern extends over at least one of the SRAM cells 202A (see Figure 2). In an embodiment, there are four mandrel patterns extending overlapping each SRAM cell 202A. Regarding the structure of the mandrel pattern (the shape, size and position of the mandrel pattern of each cell), Cell-R0 and Cell-My are the mapping positions of Cell-Mx and Cell-R180 on the dotted line AA, and Cell-R0 And Cell-Mx is a copy of Cell-My and Cell-R180, such as Cell-My and Cell-R180 displacement X are spaced 204A in the X-direction position. Each of the virtual fin cut patterns 1204 is also rectangular (upper view) and extends longitudinally in the Y direction. The fin tail resection pattern 1206 is located at the boundary of the SRAM cell in the Y direction for cutting the fin lines, such as reducing the active areas of the transistors PU-1 and PU-2. Separating the layout of the 12A into three masks as shown in FIG. 12B for allowing density and/or regular patterns with the masks 1202, 1204, and 1206 to substantially improve the important dimensions of the pattern during photolithography Homogenize.

Figure 12C shows the gate features of group 203 that overlap over the finned active lines of the group. Each gate feature has a rectangular shape and extends longitudinally in the X direction. The gate features are separated from the gate features in the Y direction by an interval that is half of the Y interval 206A. The gate features overlap the fin active lines to form a plurality of P-fin field effect transistors and N-fin field effect transistors. Regarding the structure of the gate feature (the shape, size, and position of the gate feature in each cell), according to the dotted line AA, Cell-R0 and Cell-My are the mapped images of Cell-Mx and Cell-R180, and according to Dotted line BB, Cell-R0 and Cell-Mx are mapped images of Cell-My and Cell-R180.

Figure 13 is an embodiment of a method 1300 of forming a finned active line of group 203 (Fig. 12A) using masks 1202, 1204, 1206 (Fig. 12B). Additional operations may be performed before, during, or after execution of method 1300, and portions of operations of method 1300 may be replaced, deleted, or removed to achieve other additional embodiments of the method. Method 1300 will be described below using Figures 14-24C.

In operation 1302, method 1300 (FIG. 13) deposits dielectric layers 1404 and 1406 for overlapping a substrate 1402 (eg, a semiconductor wafer). Please refer to FIG. 14, which shows a germanium substrate 1402 and a first dielectric layer 1404 (such as germanium oxide) disposed over the germanium substrate 1402 and a second dielectric layer 1406 (such as tantalum nitride). Materials that can serve as dielectric layers 1404 and 1406 include tantalum oxide, tantalum nitride, polycrystalline germanium, germanium tetrazide (Si ₃ N ₄ ), bismuth oxynitride (SiON), tetraethyl orthosilicate (TEOS). ), tantalum nitride oxide, nitric oxide, high K material (K>5) or a combination thereof, but is not limited thereto. Dielectric layers 1404 and 1406 are formed by a process that includes deposition. For example, the first dielectric layer 1404 of tantalum oxide is formed by thermal oxidation. The second dielectric layer 1406 of germanium nitride (SiN) is formed by chemical vapor deposition (CVD). For example, the tantalum nitride layer is chemically used by CVD, such as hexachlorodisilane (HCD or Si ₂ C ₁₆ ), ethylene dichlorosilane (DCS or SiH ₂ C ₁₂ ), Bis (Tertiary Butyl Amino) Silane (BTBAS or C ₈ H ₂₂ N ₂ Si) and disilane (DS or Si2H6). In one embodiment, the dielectric layer 1406 has a thickness between approximately 20 nm and 200 nm.

Method 1300 (Fig. 13) then performs operation 1304 to form a mandrel pattern 1502 in dielectric layer 1406. Referring to Fig. 15A (top view) and Fig. 15B (cross-sectional view taken along line A-A shown in Fig. 15), the mandrel pattern 1502 is evenly distributed in the X direction. By performing a process for patterning the interface layer 1406 for forming a mandrel pattern 1502, the process includes a lithography process and an etch process. In this embodiment, a photoresist layer is formed over the dielectric layer 1406 by a spin coating process and a soft bake process. Then, the photoresist layer is exposed by the mask 1202 (Fig. 12B). The exposed photoresist layer is formed over the dielectric layer 1406 by post-exposure bake (PEB), exposure, and hard bake of the exposed photoresist layer. Connect The dielectric layer 1406 is etched through the openings of the patterned photoresist layer to form a patterned interface layer 1406. The patterned photoresist layer is then removed using a suitable procedure, such as wet stripping or plasma ashing. In one embodiment, the etching process includes applying a dry (or plasma) etch to remove the opening in the interface layer 1406 with the patterned photoresist layer. In another embodiment, the etching process includes applying a wet etch process with hydrofluoric acid (HF) to remove the SiO layer 1406 having openings. In the light development process described above, the regular optical axis pattern 1502 can help to improve the pattern size uniformity under consideration of the optical proximity effect.

Method 1300 (Fig. 13) continues with operation 1306 to form a void 1602. Referring to FIG. 16A (top view) and FIG. 16B (cross-sectional view along line AA), a void 1602 formed in the sidewall of the mandrel pattern 1502 is shown. The void 1602 includes one or more materials other than the mandrel pattern 1502. In one embodiment, the void 1602 may have an interface material such as titanium nitride, tantalum nitride or titanium oxide. The void 1602 may also have materials such as polycrystalline germanium, germanium dioxide (SiO ₂ ), germanium tetranitride (Si ₃ N ₄ ), germanium oxynitride (SiON), tetraethyl orthosilicate (TEOS), nitrogen. The antimony oxide, the nitrogen oxide, the high K material (K>5) or a combination thereof is not limited thereto. The voids 1602 can be formed in a number of ways, such as a deposition process and an etch process. For example, the deposition process includes a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) process. For example, the etching process includes an anisotropic etch such as plasma etching.

Method 1300 (Fig. 13) continues with operation 1308 to remove the mandrel pattern 1502. Referring to FIG. 17A (top view) and FIG. 17B (cross-sectional view along line AA), after the mandrel pattern 1502 is removed, the void 1602 is still maintained over the interface layer 1404, for example by an etching process. Selectively remove interface material 1406, but does not remove void material. The etching process can be a wet etch, a dry etch, or a combination thereof.

Method 1300 (Fig. 13) continues with operation 1310 for forming finned lines 1802 in the crucible substrate 1402. Please refer to FIG. 18B, which is a cross-sectional view taken along line A-A of FIG. 18A. The void 1602 serves as an etch mask for etching the germanium substrate 1402. The void 1602 and the interfacial layer 1404 are sequentially removed, so in the crucible substrate 1402 (Fig. 18C), the fin line 1802 is formed.

The method 1300 (Fig. 13) continues with operation 1312 for performing a first fin cut process using the mask 1204 (Fig. 12B), thereby removing the virtual fin line. Referring to FIG. 19A (top view) and 19B (cross-sectional view taken along line A-A), the virtual fin line 1802D is removed, thus leaving the fin line 1802A over the crucible substrate 1402. In the present embodiment, the virtual fin line 1802D is removed by a program that includes a lithography process and an etch process. For example, a photoresist layer is formed over the germanium substrate by a spin coating process and a soft bake process. Then, the photoresist layer is exposed by the mask 1204 shown by the broken line in Fig. 19A, and the mask 1204 shown by the broken line in Fig. 19A indicates the opening to be generated. The exposed photoresist layer is sequentially unrolled and peeled off, thereby forming a patterned photoresist layer. The fin line 1802A is protected by a patterned photoresist layer, while the dummy fin line 1802D is not protected by a photoresist layer. Next, the dummy fin line 1802D is removed by patterning the opening of the photoresist layer. The patterned photoresist layer is removed by a suitable process, such as a wet strip or a plasma ash.

The method 1300 (Fig. 13) continues with operation 1314 for masking 1206 (Fig. 12B) to perform a second fin resection process, thereby cutting the fin line of the pull up transistor, such as PU-1 of Fig. 5. With PU-2. Please refer to Figure 20A (top view) And in FIG. 20B (a cross-sectional view taken along line AA of FIG. 20A), the fin line 1802A partially crossing the boundary of the SRAM cell 202A is removed, thereby making the pull-up transistors PU-1 and PU-2 shorter. Fin line. In the present embodiment, the second fin resection process is similar to the first fin resection process described in the foregoing FIGS. 19A and 19B, except that the second fin resection process utilizes the mask 1206.

Method 1300 (Fig. 13) continues with operation 1316 to form a final device having finned line 1802A. For example, operation 1316 may implant dopants for doping well and channel doping, forming a gate dielectric layer, forming a lightly doped source/drain, forming a gate stack, and the like.

21 shows a method 2100 of forming a finned active line of group 203 (FIG. 12A), as shown in FIG. 12B, with groups 203 having three masks 1202, 1204, and 1206, in accordance with an embodiment. Additional operations may be performed before, during, or after performing method 2100, and in other embodiments, portions of operations of method 2100 may be replaced, eliminated, or interchanged. Part of the operation of method 2100 is similar to the operation of method 1300 and, therefore, will not be described again for the sake of brevity.

After operation 1308, method 2100 (FIG. 21) forms voids 1602A and 1602D (22A and 22B), wherein void 1602A will be used to form the finned active line, while void 1602D (virtual void) is not.

In operation 2110, method 2100 (FIG. 21) removes dummy void 1602D using mask 1204, such as by photolithography and an etch process as described in FIGS. 19A and 19B, wherein the etch process is selected The void material is removed sexually (Fig. 22C).

In operation 2112, method 2100 (FIG. 21) cuts the space across the boundary of SRAM cell 202A by the aid of mask 1206 (FIGS. 23A and 23B). Gap 1602A. Operation 2112 can be accomplished by a process similar to the photolithography and etching processes described in FIGS. 20A and 20B, wherein the void material is selectively removed at the etch (FIG. 23B).

In operation 2114, method 2100 (FIG. 21) etches germanium substrate 1402 using the remaining voids 1602A as an etch mask (24A and 24B). The void 1602A and the dielectric layer 1404 are sequentially removed, thereby forming the TFTs PU-1/2, PD-1/2 and PG-1/2 fin lines 1802A in the germanium substrate 1402 (24C) Figure).

Method 2100 (FIG. 21) continues with operation 1316 to form the final device described above with finned line 1802A.

25A shows a fin active line of group 203 (FIG. 2), and group 203 has four adjacent SRAM cells 202B (FIG. 6), such as Cell_R0, Cell_My, Cell_Mx, and Cell_R180. The four cells are arranged in two columns and two rows. The dotted line A-A is the boundary of the SRAM cells in the X direction, and the broken line B-B is the boundary of the SRAM cells in the Y direction. Regarding the fin active line structure (shape, size, and position), Cell_R0 and Cell_My are the mapped images of Cell_Mx and Cell_R180 along the dotted line A-A, and Cell_R0 and Cell_Mx are the mapped images of Cell_My and Cell_R180 along the broken line B-B. In the present embodiment, these finned active lines can be formed by using the void lithography and the three masks 2502, 2504, and 2506 shown in FIG. 25B.

Referring to FIG. 25B, masks 2502, 2504, and 2506 are similar to masks 1202, 1204, and 1206 of FIG. 12B, and masks 2502, 2504, and 2506 are designed for SRAM macro 102 (in semiconductor device 100). The third floor. The mask 2502 defines a mandrel pattern for forming a void, and the mask 2504 defines a virtual A quasi-fin cut pattern to remove dummy fin lines (or virtual voids), and a mask 2506 defines a fin tail switching pattern for pulling up the transistor (eg, PU-1 and PU of Figure 5) -2) has a shorter fin line. As shown in Fig. 25B, the mandrel pattern is distributed flat in the X direction. Each mandrel pattern has a rectangular shape (top view) extending longitudinally in the Y direction. In one embodiment, although not shown, each mandrel pattern extends at least four SRAM cells 202B (see Figure 2). In this embodiment, the layout includes a five-mandrel pattern that extends across each of the SRAM cells 202B. Regarding the structure of the mandrel pattern (the shape, size and position of the mandrel pattern of each cell), Cell-R0 and Cell-My are the mapped images of Cell-Mx and Cell-R180 on the dotted line AA, and Cell-R0 And Cell-Mx is a copy of Cell-My and Cell-R180, such as Cell-My and Cell-R180 displacement X are spaced 204A in the X-direction position. Each of the virtual fin cut patterns is also rectangular (upper view) and extends longitudinally in the Y direction. The fin tail resection pattern is located at the boundary of the SRAM cell 202B in the Y direction for cutting the fin line, such as reducing the active areas of the transistors PU-1 and PU-2. The layout of the 25A is divided into three masks as shown in Fig. 25B to allow density and/or regular patterns to substantially improve the uniform size of the important dimensions of the pattern during photolithography. The fin active line of Fig. 25A can be formed by the embodiment of the method 1300 (Fig. 13) or the method 2100 (Fig. 21) described above.

Figure 25C shows the gate features of group 203, which overlap the fin active lines of the same group (Fig. 25A). Each gate feature is a rectangular shape that extends in the X direction. The pitch of the gate features in the Y direction is approximately half of the Y pitch 206B. The gate feature extends over the finned active line to form a plurality of P-fin field effect transistors and N-fin field effect transistors. Regarding the structure of the gate features (the shape, size and position of the gate features in each cell), according to the dotted line A-A, Cell-R0 And Cell-My is a mapped image of Cell-Mx and Cell-R180, and according to the dotted line B-B, Cell-R0 and Cell-Mx are mapped images of Cell-My and Cell-R180.

Although not intended to be limiting, the present disclosure provides many advantages. For example, the present disclosure defines an implanted field-effect transistor SRAM macro structure for arranging respective characteristics between SRAM cells and peripheral logic circuits (eg, fin active lines, gate features, etc.) . For example, such an arrangement facilitates a highly dense fin active line structure as well as a single fin pitch design. The implanted FinFET SRAM macromechanics is flexible, which may include high density SRAM cells, high current SRAM cells, single 埠SRMA packets, double 埠SRAM cells, or a combination thereof. Therefore, it can be installed in many application fields such as computers, communications, mobile phones, and automation electronics. The current disclosure further teaches the layout design and method of the fin active area of the SRAM cell. In some embodiments, the fin active region is divided into a mandrel pattern layer (single mask) and two ablation pattern layers (complex mask). In the light development process, these mandrel patterns are dense, parallel, rectangular, and add important size uniformity.

In one embodiment, the present disclosure is an integrated circuit (IC) layout. The IC layout includes a first rectangular region, wherein the first rectangular region has a longer side in a first direction and a shorter side in a second direction, the first direction being perpendicular to the second direction a first dotted line and a second broken line are divided into a first sub-area, a second sub-area, a third sub-area, a fourth sub-area, and a first sub-area according to an inverse clock sequence Positioned in a first rectangular upper right position, the first dashed line passes through a plurality of center points of the first rectangular area in the first direction, and the second broken line passes through the plurality of center points of the first rectangular area in the second direction. The IC layout further includes at least 8 first patterns in the IC In the first layer of the layout, each of the first patterns is a rectangular shape extending longitudinally in the second direction and overlapping the first rectangular regions, the first patterns being separated from each other in the first direction; the first pattern The first, second, third, and fourth portions partially overlap the first, second, third, and fourth sub-regions, respectively; according to the first dashed line, the first and second portions of the first pattern are respectively the first pattern The fourth and third portions of the mapped image; the first and fourth portions of the first pattern are copies of the second and third portions of the first case, respectively. The IC layout further includes at least eight second patterns, which are located in the second layer of the IC layout, wherein each of the second patterns is a rectangular shape and extends longitudinally in the second direction, and the second pattern is in the first direction. Separated from each other, when the first and second layers are stacked together, each of the second patterns partially overlaps one of the first patterns and completely overlaps the longer sides of the first pattern. The IC layout further includes a plurality of third patterns located in the third layer of the IC layout, wherein each of the third patterns is a rectangular shape, and the third patterns are separated from each other when the first, second, and third layers are stacked together Each of the third patterns partially overlaps one of the first patterns and overlaps a portion of the longer side of the first pattern that does not overlap the second pattern. In the above IC layout, the entirety of the first, second, and third patterns is used to define a plurality of active regions for forming a transistor; and when the first, second, and third layers are stacked together, according to The longer sides of the first pattern overlapping the second and third patterns define the active regions.

In another embodiment, the present disclosure is a semiconductor device. The semiconductor device has a first SRAM macro set, wherein the first SRAM macro includes a plurality of first SRAM cells and a plurality of second peripheral logic circuits, the first SRAM cells being arranged to have a first direction a pitch and a second pitch in the second direction, the first direction being perpendicular to the second direction, the first 單埠SRAM The cell has a plurality of fin field effect transistors having a first gate feature and a first fin active line, the second peripheral logic circuit having a fin field effect transistor having a second gate feature and a second fin active line The second gate features are arranged to have a third pitch in the second direction, and the second fin active lines are arranged to have a fourth pitch in the first direction. The semiconductor device further includes a second SRAM macro set, wherein the second SRAM macro has a plurality of third SRAM cells and a plurality of fourth peripheral logic circuits, the third SRAM cell having a fifth pitch in the first direction, and Having a sixth pitch in the second direction, the third 單埠SRAM cell has a plurality of fin field effect transistors having a third gate feature and a third fin active line, and the fourth peripheral logic circuit has a fin field effect a crystal having a fourth gate feature and a fourth fin active line, the fourth gate feature being arranged to have a third pitch in the second direction, the fourth fin active line being arranged to have the first direction Fourth spacing. In the above semiconductor device, the second pitch is approximately twice the third pitch; the sixth pitch is approximately equal to the second pitch; and the fifth pitch is greater than the first pitch, the first pitch being approximately twice the fourth pitch.

In another embodiment, the present disclosure is a semiconductor device. The semiconductor device has a first SRAM macro set, wherein the first SRAM macro includes a plurality of first SRAM cells and a plurality of second peripheral logic circuits, the first SRAM cells being arranged to have a first direction in a first direction a pitch and a second pitch in the second direction, the first direction being perpendicular to the second direction, the first 單埠SRAM cell having a first fin field effect transistor having a first gate feature and a first fin active a second peripheral logic circuit having a second fin field effect transistor having a second gate feature and a second fin active line, the second gate feature being arranged to have a third pitch in the second direction, The second fin active line is arranged in the first There is a fourth pitch in one direction. The semiconductor device further includes a second SRAM macro set, wherein the second SRAM macro has a plurality of third dual-SRAM cells and a plurality of fourth peripheral logic circuits, and the third dual-SRAM cells are arranged to have a fifth direction in the first direction. a pitch, and having a sixth pitch in the second direction, the third double-sided SRAM cell having a third fin field effect transistor having a third gate feature and a third fin active line, the fourth peripheral logic circuit having a fourth fin field effect transistor having a fourth gate feature and a fourth fin active line, the fourth gate feature being arranged to have a third pitch in the second direction, the fourth fin active line being arranged There is a fourth pitch in the first direction. In the above semiconductor device, the second pitch is approximately twice the third pitch; the sixth pitch is approximately equal to the second pitch; the ratio between the first and fourth pitches is not an integer; and at the fifth and fourth pitches The ratio between the ones is an integer.

The disclosure of the present invention has been disclosed in the above preferred embodiments, so that those skilled in the art can understand the present disclosure more clearly. However, those of ordinary skill in the art should understand that the invention can be readily practiced in the light of the disclosure. Therefore, the scope of protection of this disclosure is subject to the definition of the scope of the patent application.

Claims (20)

An integrated circuit layout comprising: a first rectangular region, wherein the first rectangular region has a longer side in a first direction and a shorter side in a second direction, the second direction being vertical The first direction, and a first dashed line passes through a geometric center point of the first rectangular area in the first direction, and a second broken line passes the geometric center point in the second direction, according to an inverse clock order, The first and second broken lines divide the first rectangular area into a first sub-area, a second sub-area, a third sub-area and a fourth sub-area, wherein the first sub-area is located in the first rectangular area a top right position; at least eight first patterns, located in a first layer of the integrated circuit layout, wherein each of the first patterns is a rectangular shape extending lengthwise in the second direction and overlapping the first rectangle The first patterns are separated from each other in the first direction; a first portion, a second portion, a third portion, and a fourth portion of the first patterns each partially overlap the first and second portions And a third sub-region; the first and second portions of the first patterns are respectively mapped images of the fourth and third portions of the first pattern; and the first pattern is The first and fourth portions are respectively a copy of the second and third portions of the first pattern; at least eight second patterns are located in a second layer of the integrated circuit layout, wherein each of the second patterns is a rectangular shape extending longitudinally in the second direction, the second patterns being spaced apart from each other in the first direction; when the first and second layers are stacked together, each second pattern partially overlapping the same One of the first patterns and completely overlapping a longer side of the respective first pattern; And a plurality of third patterns, which are located in a third layer of the integrated circuit layout, wherein each of the third patterns is a rectangular shape, and the third patterns are separated from each other when the first and second And when the third layer is superimposed, each of the third patterns partially overlaps one of the first patterns, and overlaps a portion of the longer side of the first pattern that does not overlap the second patterns The first, second, and third patterns are used to define a plurality of active regions for forming a transistor; and when the first, second, and third layers are stacked together, according to the non-overlapping The longer sides of the first patterns of the second and third patterns define the active regions. The integrated circuit layout as described in claim 1, wherein the active regions are fin active lines for forming a fin field effect transistor type of transistor. The integrated circuit layout as described in claim 1, further comprising: a plurality of gate features, a gate layer located in the integrated circuit region, wherein each of the gate features is a rectangle Extending longitudinally in a first direction; in the second direction, the gate features have a gate spacing therebetween; a first portion, a second portion, and a third portion of the gate features And partially overlapping the first, second, third and fourth sub-regions with a fourth portion; according to the first dashed line, the first and second portions of the gate features are respectively characterized by the gates The fourth and third portions of the mapped image; according to the second dotted line, the first and fourth portions of the gate features are respectively mapped images of the second and third portions of the gate features; The gate feature and the opposite active region form a P-type transistor; and a portion of the gate feature and the opposite active region form an N-type transistor. The integrated circuit layout of claim 3, wherein in each region, the gate features and the active regions are used to form at least six transistors, and in each region, the at least six The transistor is used to form an SRAM cell. The integrated circuit layout of claim 4, wherein in each of the regions, the at least six transistors are fin field effect transistors. The integrated circuit layout of claim 1, further comprising a second rectangular area, the second rectangular area being substantially the same as the first rectangular area, extending in the second direction, and the first The rectangular regions are arranged side to side, wherein the first and second patterns extend over at least one of the first and second rectangular regions. The integrated circuit layout of claim 1, wherein the eight first patterns extend over the first rectangular area, and when the first and second layers are superposed together, the eight first patterns Each of them partially overlaps one of the second patterns. The integrated circuit layout of claim 1, wherein the ten first patterns extend over the first rectangular region, and when the first and second layers are stacked together, the ten first pattern The two do not partially overlap any of the second patterns. A semiconductor device comprising: a first SRAM macro, wherein the first SRAM macro comprises a plurality of first SRAM cells and a plurality of second peripheral logic circuits, the first The SRAM cells are arranged to have a first pitch in a first direction and a second pitch in a second direction, the first direction being perpendicular to the second direction, the first 單埠SRAM cells having a plurality of a fin field effect transistor having a plurality of first gate features and a plurality of first fin active lines, the second peripheral logic circuit having a plurality of fin field effect transistors having a plurality of second gate features and a plurality of second a fin active line, the second gate features are arranged to have a third pitch in the second direction, and the second fin active lines are arranged to have a fourth pitch in the first direction; And a second SRAM macro set, wherein the second SRAM macro has a plurality of third SRAM cells and a plurality of fourth peripheral logic circuits, the third SRAM cells having a fifth pitch in the first direction And having a sixth pitch in the second direction, the third 單埠SRAM cells having a plurality of fin field effect transistors having a plurality of third gate features and a plurality of third fin active lines, the Four peripheral logic circuits have complex fins a field effect transistor having a plurality of fourth gate features and a plurality of fourth fin active lines, the fourth gate features being arranged to have the third pitch in the second direction, the fourth fins The drive line is arranged to have the fourth pitch in the first direction, wherein the second pitch is approximately twice the third pitch; the sixth pitch is approximately equal to the second pitch; and the fifth pitch is greater than The first pitch is about twice the fourth pitch. The semiconductor device of claim 9, wherein the ratio between the first and fourth pitches is 8, 8.5 or 9. The semiconductor device of claim 9, wherein the ratio between the first and fourth pitches is 10, 10.5 or 11. The semiconductor device of claim 9, wherein the ratio between the first and second pitches is between about 2.25 and 2.28. The semiconductor device of claim 9, wherein the ratio between the first and fourth pitches is not an integer, and the integer is twice an integer. The semiconductor device of claim 9, wherein a first metal layer of the first 單埠SRAM cells has a plurality of power supply lines, a plurality of bit lines, and a plurality of inverted phase lines; a second metal layer of the SRAM cell has a complex digital line and a plurality of ground lines; and the first metal layer is between the second metal layer and a layer of the semiconductor device, the layer of the semiconductor device having the same The first fin type active line. The semiconductor device of claim 9, wherein the complex digital lines of the first 單埠SRAM cells are disposed in a first metal layer; the plurality of power supply lines of the first 單埠SRAM cells, a plurality of bit lines, a plurality of anti-phase elements, and a plurality of ground lines are disposed in a second metal layer; and the first metal layer is between the second metal layer and a layer of the semiconductor, the layer of the semiconductor device There are these first fin active lines. A semiconductor device comprising: a first SRAM macro, wherein the first SRAM macro comprises a plurality of first SRAM cells and a plurality of second peripheral logic circuits, the first The SRAM cells are arranged to have a first pitch in a first direction and a second pitch in a second direction, the first direction being perpendicular to the second direction, the first 單埠SRAM cells having a plurality of a first fin field effect transistor having a plurality of first gate features and a plurality of first fin active lines, the second peripheral logic circuits having a plurality of second fin field effect transistors having a plurality of second gate features And a plurality of second fin active lines, the second gate features being arranged to have a third pitch in the second direction, the second fin active lines being arranged to have a first direction a fourth pitch; and a second SRAM macro, wherein the second SRAM macro has a plurality of third dual-slice SRAM cells and a plurality of fourth peripheral logic circuits, the third dual-SRAM cells being arranged at the first Having a fifth pitch in the direction and a sixth pitch in the second direction, the third double 埠SRAM cells having a plurality of third fin field effect transistors having a plurality of third gate features and a plurality of Tri-fin active line, the fourth perimeter The logic circuit has a plurality of fourth fin field effect transistors having a plurality of fourth gate features and a plurality of fourth fin active lines, the fourth gate features being arranged to have the third pitch in the second direction The fourth fin active lines are arranged to have the fourth pitch in the first direction; wherein the second pitch is approximately twice the third pitch; the sixth pitch is approximately equal to the second pitch A first ratio between the first and fourth pitches is not an integer; and a second ratio between the fifth and fourth pitches is an integer. The semiconductor device of claim 16, wherein the first ratio An example is 10.5 and the second ratio is 15. The semiconductor device of claim 16, wherein a gate feature overlaps a fin active line for forming one of the first fin field effect transistors. The semiconductor device of claim 16, wherein one of the gate features overlaps both of the fin active lines to form both of the first fin field effect transistors. The semiconductor device of claim 16, wherein the double-sided SRAM cells comprise a write buffer portion and a read buffer portion; and the write buffer portion is substantially identical to the top SRAM cell.