TWI690056B - Static random-access memory (sram)cell array and forming method thereof - Google Patents
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本發明係關於一種靜態隨機存取記憶體單元陣列及其形成方法,且特別係關於一種應用犧牲鰭狀結構的靜態隨機存取記憶體單元陣列及其形成方法。 The invention relates to a static random access memory cell array and a method for forming the same, and particularly relates to a static random access memory cell array using a sacrificial fin structure and a method for forming the same.
隨機存取記憶體(RAM:Random Access Memory)使用時可以讀取資料也可以寫入資料,當電源關閉以後資料立刻消失。由於隨機存取記憶體的資料更改容易,所以一般應用在個人電腦做為暫時儲存資料的記憶體。隨機存取記憶體又可以細分為「動態(Dynamic)」與「靜態(Static)」兩種。 Random access memory (RAM: Random Access Memory) can be used to read data or write data, the data disappears immediately after the power is turned off. Since the data of the random access memory is easy to change, it is generally used in a personal computer as a memory for temporarily storing data. Random access memory can be subdivided into "Dynamic" and "Static".
「動態隨機存取記憶體(DRAM:Dynamic RAM)」是以1個電晶體加上1個電容來儲存1個位元(1bit)的資料,而且使用時必須要週期性地補充電源來保持記憶的內容,故稱為「動態(Dynamic)」。動態隨機存取記憶體構造較簡單(1個電晶體加上1個電容來儲存1個位元的資料)使得存取速度較慢(電容充電放電需要較長的時間),但是成本也較低,因此一般都製作成對容量要求較高但是對速度要求較低的記憶體,例如:個人電腦主機板上通常使用的主記憶體(main memory)。 "Dynamic Random Access Memory (DRAM: Dynamic RAM)" is a transistor plus a capacitor to store 1 bit (1bit) of data, and when using it must periodically replenish power to maintain memory The content is called "Dynamic". The structure of dynamic random access memory is relatively simple (1 transistor plus 1 capacitor to store 1 bit of data), which makes the access speed slower (capacitor charging and discharging takes longer time), but the cost is also lower Therefore, it is generally made into a memory with a high capacity requirement but a low speed requirement, such as a main memory (main memory) commonly used on a motherboard of a personal computer.
「靜態隨機存取記憶體(SRAM:Static RAM)」是以6個電晶體來儲存 1個位元(1bit)的資料,而且使用時不需要週期性地補充電源來保持記憶的內容,故稱為「靜態(Static)」。靜態隨機存取記憶體的構造較複雜(6個電晶體儲存1個位元的資料)使得存取速度較快,但是成本也較高,因此一般都製作成對容量要求較低但是對速度要求較高的記憶體,例如:個人電腦的中央處理器(CPU)內建256KB或512KB的快取記憶體(Cache Memory)。由於中央處理器的速度決定了電腦運算數據及處理資訊的快慢,主記憶體的容量則決定了電腦可以儲存資訊的多寡,因此快取記憶體是用來儲存一些經常使用到的資訊,把這些經常用到的資訊放在速度較快的快取記憶體中可以使中央處理器很快的取得這些資訊,而不需要再到速度較慢的主記憶體中去尋找,如此一來可使中央處理器處理的速度加快。 "Static Random Access Memory (SRAM: Static RAM)" is stored with 6 transistors One bit (1bit) of data, and when using it does not need to periodically supplement the power to maintain the contents of the memory, so it is called "Static". The structure of static random access memory is more complicated (6 transistors store 1 bit of data), which makes the access speed faster, but the cost is also higher, so it is generally made to have lower capacity requirements but speed requirements Higher memory, for example, the central processing unit (CPU) of the personal computer has a built-in 256KB or 512KB cache memory. Because the speed of the central processor determines how fast the computer can calculate data and process information, the capacity of the main memory determines how much information the computer can store, so the cache memory is used to store some frequently used information. Frequently used information is placed in the faster cache memory to enable the central processor to quickly obtain this information, without having to go to the slower main memory to find, so that the central The processing speed of the processor is accelerated.
本發明提出一種靜態隨機存取記憶體單元陣列及其形成方法,能促進製程可靠度,並提升靜態隨機存取記憶體的性能。 The invention provides a static random access memory cell array and a method for forming the same, which can promote the reliability of the manufacturing process and improve the performance of the static random access memory.
本發明提供一種形成靜態隨機存取記憶體(static random-access memory,SRAM)單元陣列的方法,包含有下述步驟。首先,圖案化而形成複數個鰭狀結構於一基底上,其中此些鰭狀結構包含複數個主動鰭狀結構以及複數個犧牲鰭狀結構,各通道電晶體(PG FinFET)與對應的一降壓電晶體(PD FinFET)至少共享一主動鰭狀結構,在一記憶體單元中二相鄰的升壓電晶體(PU FinFET)跨設的二主動鰭狀結構之間設置有至少一犧牲鰭狀結構。接著,移除此些犧牲鰭狀結構的至少一部份。 The invention provides a method for forming a static random-access memory (SRAM) cell array, which includes the following steps. First, patterning to form a plurality of fin structures on a substrate, wherein the fin structures include a plurality of active fin structures and a plurality of sacrificial fin structures, each channel transistor (PG FinFET) and a corresponding drop The piezoelectric crystal (PD FinFET) at least shares an active fin structure, and at least one sacrificial fin structure is disposed between two active fin structures spanned by two adjacent boost transistors (PU FinFET) in a memory cell structure. Next, at least a portion of these sacrificial fin structures are removed.
本發明提供一種靜態隨機存取記憶體(static random-access memory, SRAM)單元陣列,包含有複數個鰭狀結構位於一基底上。此些鰭狀結構包含複數個主動鰭狀結構以及矮於此些主動鰭狀結構的複數個剩下的犧牲鰭狀結構,其中各通道電晶體(PG FinFET)與對應的一降壓電晶體(PD FinFET)至少共享一主動鰭狀結構,在一記憶體單元中二相鄰的升壓電晶體(PU FinFET)跨設的二主動鰭狀結構之間設置有至少一剩下的犧牲鰭狀結構。 The invention provides a static random-access memory (static random-access memory, SRAM) cell array, including a plurality of fin-like structures on a substrate. These fin-shaped structures include a plurality of active fin-shaped structures and a plurality of remaining sacrificial fin-shaped structures shorter than these active fin-shaped structures, wherein each channel transistor (PG FinFET) and the corresponding one of the reduced piezoelectric crystals ( PD FinFET) at least share an active fin structure, at least one remaining sacrificial fin structure is arranged between two active fin structures spanned by two adjacent boost transistors (PU FinFET) in a memory cell .
基於上述,本發明提出一種靜態隨機存取記憶體單元陣列及其形成方法,其先圖案化而形成複數個鰭狀結構於一基底上,其中此些鰭狀結構可包含複數個主動鰭狀結構以及複數個犧牲鰭狀結構,接著再移除至少部份的犧牲鰭狀結構,如此即可藉由在所需之主動鰭狀結構佈局中加入犧牲鰭狀結構,俾使各鰭狀結構之間的間距相同,或近乎相同,如此可使各鰭狀結構的輪廓相近。因此,本發明所形成之各形狀相近的鰭狀結構,可促進製程穩定性以及裝置的可靠度。再者,本發明在一靜態隨機存取記憶體單元中二相鄰的升壓電晶體跨設的二主動鰭狀結構之間設置有至少一犧牲鰭狀結構,以使(通常具有較大間距的)二主動鰭狀結構之間的間距可近似於其他主動鰭狀結構之間的間距(,包括例如邏輯區等其他區域中的鰭狀結構之間的間距)。 Based on the above, the present invention proposes a static random access memory cell array and a method of forming the same, which is first patterned to form a plurality of fin-like structures on a substrate, wherein the fin-like structures may include a plurality of active fin-like structures And a plurality of sacrificial fin structures, and then at least part of the sacrificial fin structures are removed, so that by adding sacrificial fin structures to the desired active fin structure layout, between the fin structures The spacing is the same, or nearly the same, so that the contours of the fin-like structures can be similar. Therefore, the fin-like structures formed in the present invention having similar shapes can promote the process stability and the reliability of the device. Furthermore, the invention is provided with at least one sacrificial fin structure between two active fin structures straddling two adjacent boost transistors in a static random access memory cell, so that (usually with a larger pitch) The spacing between the two active fin structures may be similar to the spacing between other active fin structures (including the spacing between fin structures in other regions such as logic regions).
10:硬遮罩層 10: Hard mask layer
12:氧化層 12: oxide layer
14:氮化層 14: Nitride layer
20、30:遮罩 20, 30: mask
22、32:有機介電層 22, 32: Organic dielectric layer
24、34:含矽硬遮罩底抗反射層 24, 34: Anti-reflective layer with silicon-containing hard mask bottom
26、36:光阻 26, 36: photoresist
40:絕緣結構 40: Insulation structure
110:基底 110: base
110’:塊狀底材 110’: massive substrate
112、112a、112b、112c、112d:鰭狀結構 112, 112a, 112b, 112c, 112d: fin structure
112e、112f、112g、112h、112h1、112h2、112i、112i1、112i2、112j、112j1、112j2:主動鰭狀結構 112e, 112f, 112g, 112h, 112h1, 112h2, 112i, 112i1, 112i2, 112j, 112j1, 112j2: active fin structure
112k、112k’、112l、112l’、112m、112m’、112n、112n’、112o、112o’:犧牲鰭狀結構 112k, 112k’, 112l, 112l’, 112m, 112m’, 112n, 112n’, 112o, 112o’: sacrificial fin structure
112a’、112b’、112c’、112d’:剩餘部分 112a’, 112b’, 112c’, 112d’: the rest
120:多晶矽閘極 120: Polysilicon gate
130:內連線金屬 130: interconnection metal
140:接觸插塞 140: contact plug
A:靜態隨機存取記憶體單元區 A: Static random access memory unit area
C1:第一鰭狀結構裁切 C1: Cutting the first fin structure
C2:第二鰭狀結構裁切 C2: Cutting the second fin structure
E:尾端 E: tail
P、P1、P2、P3、P4:間距 P, P1, P2, P3, P4: pitch
P1:蝕刻製程 P1: Etching process
PD1、PD2:降壓電晶體 PD1, PD2: step-down piezoelectric crystal
PG1、PG2:通道電晶體 PG1, PG2: channel transistor
PU1、PU2:升壓電晶體 PU1, PU2: boost transistor
U1:(1,1,1)型的靜態隨機存取記憶體單元 U1: (1,1,1) type static random access memory unit
U2:(1,2,2)型的靜態隨機存取記憶體單元 U2: (1,2,2) type static random access memory unit
w:寬度 w: width
θ:角度 θ: angle
第1-7圖繪示本發明一實施例之形成靜態隨機存取記憶體單元陣列的方法之俯視及剖面示意圖。 1-7 are schematic top and cross-sectional views of a method for forming a static random access memory cell array according to an embodiment of the invention.
第8圖繪示本發明另一實施例之形成靜態隨機存取記憶體單元陣列的方法之俯視及剖面示意圖。 FIG. 8 is a schematic top and cross-sectional view of a method for forming a static random access memory cell array according to another embodiment of the invention.
第1-7圖繪示本發明一實施例之形成靜態隨機存取記憶體單元陣列的方法之俯視及剖面示意圖。如第1-2圖所示,圖案化而形成複數個鰭狀結構112於一基底110上。如第1圖所示,提供一塊狀底材110’,在其上形成硬遮罩層10,並將其圖案化以定義出其下之塊狀底材110’中欲對應形成之鰭狀結構112的位置。在本實施例中,硬遮罩層10由下而上可分別為一氧化層12和一氮化層14的堆疊結構,但本發明不以此為限。接著,如第2圖所示,進行一蝕刻製程P1,於塊狀底材110’中形成鰭狀結構112。如此,完成鰭狀結構112於基底110上之製作。在一實施例中,形成鰭狀結構112後即可移除硬遮罩層10,而於後續製程中形成三閘極場效電晶體(tri-gate MOSFET)。如此一來,由於鰭狀結構112與後續形成之介電層之間具有三直接接觸面(包含二接觸側面及一接觸頂面),因此被稱作三閘極場效電晶體(tri-gate MOSFET)。相較於平面場效電晶體,三閘極場效電晶體可藉由將上述三直接接觸面作為載子流通之通道,而在同樣的閘極長度下具有較寬的載子通道寬度,俾使在相同之驅動電壓下可獲得加倍的汲極驅動電流。而在另一實施例中,亦可保留硬遮罩層10,而於後續製程中形成另一具有鰭狀結構之多閘極場效電晶體(multi-gate MOSFET)-鰭式場效電晶體(fin field effect transistor,Fin FET)。鰭式場效電晶體中,由於保留了硬遮罩層10,鰭狀結構112與後續將形成之介電層之間僅有兩接觸側面。
1-7 are schematic top and cross-sectional views of a method for forming a static random access memory cell array according to an embodiment of the invention. As shown in FIGS. 1-2, a plurality of fin-
此外,如前所述,本發明亦可應用於其他種類的半導體基底,例如在另一實施態樣中,提供一矽覆絕緣基底(未繪示),並以蝕刻暨微影之方法蝕刻矽覆絕緣基底(未繪示)上之單晶矽層而停止於氧化層,即可完成鰭狀結構於矽覆絕緣基底上的製作。此外,為簡化並清晰揭示本發明,本實施例之鰭狀結構112為15個,但本發明所能應用之鰭狀結構112亦可為其他複數個可形成靜態
隨機存取記憶體單元陣列的數量。
In addition, as mentioned above, the present invention can also be applied to other types of semiconductor substrates. For example, in another embodiment, a silicon-clad insulating substrate (not shown) is provided, and the silicon is etched by etching and lithography. The single crystal silicon layer on the insulating substrate (not shown) stops at the oxide layer, and the fabrication of the fin structure on the silicon coating insulating substrate can be completed. In addition, in order to simplify and clearly disclose the present invention, there are 15
如第3-6圖所示,裁切此些鰭狀結構112,以形成所需之靜態隨機存取記憶體單元陣列的佈局。裁切鰭狀結構112的方法以及靜態隨機存取記憶體單元陣列的佈局視所需之製程需要以及裝置需求而定。在本實施例中,裁切此些鰭狀結構112的方法包含一第一鰭狀結構裁切C1以及一第二鰭狀結構裁切C2,其中第3-4圖繪示本實施例之第一鰭狀結構裁切C1方法,而第5-6圖繪示本實施例之第二鰭狀結構裁切C2方法。本發明形成鰭狀結構112的方法可包含以側壁影像轉移(Sidewall Image Transfer,SIT)技術形成,而第一鰭狀結構裁切C1或/及第二鰭狀結構裁切C2則可結合側壁影像轉移(Sidewall Image Transfer,SIT)技術。意即,第一鰭狀結構裁切C1或/及第二鰭狀結構裁切C2可為側壁影像轉移(Sidewall Image Transfer,SIT)技術其中的步驟,故第一鰭狀結構裁切C1或/及第二鰭狀結構裁切C2可包含一併切除用以定義並轉移其圖像至基底110而形成為鰭狀結構112的側壁。
As shown in FIGS. 3-6, these
詳細而言,如第3圖所示,先依序覆蓋並圖案化一遮罩20,以遮蓋不須移除的部份的鰭狀結構112,並暴露出部分待移除的鰭狀結構112。在本實施例中,覆蓋之遮罩20為由下至上堆疊的一有機介電層(organic dielectric layer,ODL)22、一含矽硬遮罩底抗反射層(Silicon-containing Hardmask Bottom anti-reflection coating,SHB)24以及一光阻26。此遮罩20完全暴露出兩端的一鰭狀結構112a及一鰭狀結構112b,並僅暴露出鰭狀結構112a及鰭狀結構112b之間的鰭狀結構112的尾端E,因此可解決例如側壁影像轉移(Sidewall Image Transfer,SIT)技術中鰭狀結構的連接及線末短縮(line-end shortening)等問題。接著,進行第一鰭狀結構裁切C1,完全移除暴露出的鰭狀結構112a及鰭狀結構112b,以及鰭狀結
構112a及鰭狀結構112b之間的鰭狀結構112的尾端E,如第4圖所示,虛線部分為第一鰭狀結構裁切C1的裁切範圍。裁切後,鰭狀結構112a及鰭狀結構112b可仍保留剩餘部分112a’/112b’,鰭狀結構112a及鰭狀結構112b之間的鰭狀結構112的尾端E亦仍保留剩餘部分(未繪示),其中剩餘部分112a’/112b’會突出於鰭狀結構112之間的基底110。第一鰭狀結構裁切C1可為多方向裁切,或僅以一第一方向裁切。在本實施例中,第一鰭狀結構裁切C1大致以y方向裁切,並選擇性加入x方向裁切以移除鰭狀結構112a及鰭狀結構112b,但本發明不以此為限。在其他實施例中,第一鰭狀結構裁切C1可僅沿y方向裁切,而保留鰭狀結構112a及鰭狀結構112b。進行第一鰭狀結構裁切C1之後,隨即移除光阻26、含矽硬遮罩底抗反射層24以及有機介電層22。
In detail, as shown in FIG. 3, a
接著,進行第二鰭狀結構裁切C2。如第5圖所示,先依序覆蓋並圖案化一遮罩30,以遮蓋不須移除的部份的鰭狀結構112,並暴露出部分待移除的鰭狀結構112。在本實施例中,覆蓋之遮罩30為由下至上堆疊的一有機介電層(organic dielectriclayer,ODL)32、一含矽硬遮罩底抗反射層(SiO-based Hard Mask,SHB)34以及一光阻36。此遮罩30完全暴露出邊緣的一鰭狀結構112c及一鰭狀結構112d。接著,進行第二鰭狀結構裁切C2,移除暴露出的鰭狀結構112c及鰭狀結構112d,如第6圖所示,虛線部分為第二鰭狀結構裁切C2的裁切範圍。裁切後,鰭狀結構112c及鰭狀結構112d可仍保留剩餘部分112c’/112d’,其中剩餘部分112c’/112d’亦會突出於鰭狀結構112之間的基底110。在本實施例中,第二鰭狀結構裁切C2沿一第二方向裁切,即x方向裁切,是以第一鰭狀結構裁切C1的第一方向裁切垂直第二鰭狀結構裁切C2的第二方向裁切,但本發明不以此為限。進行第二鰭狀結構裁切C2之後,可隨即移除光阻36、含矽硬遮罩底抗反射層34以及有機介電層32。在本實施例中,旋即移除硬遮罩層10。
Next, the second fin-shaped structure is cut C2. As shown in FIG. 5, a
以下提出二實施例,分別形成二靜態隨機存取記憶體單元陣列。第7圖為一(1,1,1)型的靜態隨機存取記憶體單元陣列,即靜態隨機存取記憶體單元陣列中各通道電晶體(PG FinFET)與對應的一降壓電晶體(PD FinFET)共享單一主動鰭狀結構。第8圖為另一(1,2,2)型的靜態隨機存取記憶體單元陣列,即靜態隨機存取記憶體單元陣列中各通道電晶體(PG FinFET)與對應的一降壓電晶體(PD FinFET)共享二主動鰭狀結構。此外,本發明亦可應用在其他型的靜態隨機存取記憶體單元陣列,或者其他具有鰭狀結構的裝置中。 Two embodiments are proposed below to form two static random access memory cell arrays, respectively. Figure 7 is a (1,1,1) type static random access memory cell array, that is, each channel transistor (PG FinFET) in the static random access memory cell array and the corresponding one buck piezoelectric crystal ( PD FinFET) share a single active fin structure. Figure 8 is another (1,2,2) type static random access memory cell array, that is, each channel transistor (PG FinFET) in the static random access memory cell array and the corresponding one piezoelectric crystal (PD FinFET) shares two active fin structures. In addition, the present invention can also be applied to other types of static random access memory cell arrays, or other devices with fin structures.
接著,在完成第6圖之第二鰭狀結構裁切C2步驟之後,移除部分的鰭狀結構112,以形成用以跨設靜態隨機存取記憶體單元陣列之電晶體組的鰭狀結構佈局,如第7圖所示。更進一步而言,先如第6圖所示,鰭狀結構112可包含複數個主動鰭狀結構112e/112f/112g/112h/112i/112j以及複數個犧牲鰭狀結構112k’/112l’/112m’/112n’/112o’,本發明移除至少一部份的犧牲鰭狀結構112k’/112l’/112m’/112n’/112o’,以獲得所需之鰭狀結構佈局,並形成相同形狀的鰭狀結構。詳細而言,本實施例在移除部分的犧牲鰭狀結構112k’/112l’/112m’/112n’/112o’之後,形成五個犧牲鰭狀結構112k/112l/112m/112n/112o,其中犧牲鰭狀結構112k/112l/112m/112n/112o會突出於鰭狀結構112之間的基底110,如第7圖之左圖所示,但本發明不以此為限。如此一來,此主動鰭狀結構112e/112f/112g/112h的分佈即可形成第7圖之右圖所示的其中一(1,1,1)型的靜態隨機存取記憶體單元U1。再者,主動鰭狀結構112i/112j分別位於(1,1,1)型的靜態隨機存取記憶體單元U1的兩側,此二主動鰭狀結構112i/112j可例如分別作為其他靜態隨機存取記憶體單元中的主動鰭狀結構。五個犧牲鰭狀結構112k/112l/112m/112n/112o則分別位於各主動鰭狀結構
112e/112f/112g/112h/112i/112j之間。在本實施例中,係根據主動鰭狀結構112e/112f/112g/112h/112i/112j之間距,在各主動鰭狀結構112e/112f/112g/112h/112i/112j之間分別設置犧牲鰭狀結構112k/112l/112m/112n/112o,俾使各鰭狀結構112之間距彼此相同且與其他區域之鰭狀結構的間距相同,但本發明不以此為限。例如,一般而言,邏輯區中的各主動鰭狀結構之間距小於靜態隨機存取記憶體單元U1中的各主動鰭狀結構之間距,故本發明在靜態隨機存取記憶體單元U1中的各主動鰭狀結構112e/112f/112g/112h/112i/112j之間加入犧牲鰭狀結構112k/112l/112m/112n/112o,俾使靜態隨機存取記憶體單元U1中的各鰭狀結構112之間距相等或近似於邏輯區中的各主動鰭狀結構之間距。
Next, after completing the second fin structure trimming step C2 of FIG. 6, part of the
因此,本發明之精神係加入至少一犧牲鰭狀結構於主動鰭狀結構之間,俾使相同區域或不同區域之各鰭狀結構之間距相近,甚至可達相同,進而使所形成之各鰭狀結構的寬度、輪廓或形狀相近,因而能提升製程穩定性及裝置可靠度等性能。因為,當鰭狀結構的寬度不同時,會影響所形成之靜態隨機存取記憶體的性能;當鰭狀結構的形狀不同時,會影響製程穩定性。再者,各鰭狀結構中的一最大間距勢必小於各鰭狀結構中的一最小間距的兩倍(,否則即可在最大間距之間再加入一犧牲鰭狀結構)。再者,本實施例之圖示僅繪示靜態隨機存取記憶體單元區A,而靜態隨機存取記憶體單元U1位於靜態隨機存取記憶體單元區A中,但基底110可另包含一邏輯區,而在靜態隨機存取記憶體單元區A中的各鰭狀結構112的間距較佳小於在邏輯區中的鰭狀結構的間距的兩倍(,否則當在靜態隨機存取記憶體單元區A中的各鰭狀結構112的間距大於或等於在邏輯區中的鰭狀結構的間距的兩倍時,即可在鰭狀結構112的間距之間再加入至少一犧牲鰭狀結構),俾使在靜態隨機存取記憶體單元區U1中的鰭狀結構
112的寬度、形狀及輪廓與在邏輯區中的鰭狀結構的寬度、形狀及輪廓相同,或近似相同。
Therefore, the spirit of the present invention is to add at least one sacrificial fin-like structure between the active fin-like structures, so that the fin-like structures in the same area or different areas are close to each other, or even reach the same, so that the fins formed The width, contour or shape of the structure are similar, which can improve the stability of the process and the reliability of the device. Because, when the width of the fin structure is different, it will affect the performance of the formed static random access memory; when the shape of the fin structure is different, it will affect the stability of the process. Furthermore, a maximum pitch in each fin structure is bound to be less than twice the minimum pitch in each fin structure (otherwise, a sacrificial fin structure can be added between the maximum pitch). Furthermore, the illustration of this embodiment only shows the static random access memory unit area A, and the static random access memory unit U1 is located in the static random access memory unit area A, but the
(1,1,1)型的靜態隨機存取記憶體單元U1包含二升壓電晶體(PU FinFET)PU1、二通道電晶體(PG FinFET)PG1以及二降壓電晶體(PD FinFET)PD1。(1,1,1)型的靜態隨機存取記憶體單元U1中各通道電晶體PG1與對應的一降壓電晶體PD1共享單一主動鰭狀結構112h/112g,二相鄰的升壓電晶體PU1跨設的二主動鰭狀結構112e/112f之間設置有單一犧牲鰭狀結構112k。在一最佳的實施例中,各鰭狀結構112之間的間距P相等。相同地,各通道電晶體PG1與對應的一降壓電晶體PD1共享的單一主動鰭狀結構112h/112g與最接近此單一主動鰭狀結構112h/112g的二升壓電晶體PU1跨設的主動鰭狀結構112f/112e之間分別設置犧牲鰭狀結構112l/112m;二相鄰的記憶體單元中的共享的主動鰭狀結構之間,意即主動鰭狀結構112h/112j之間以及主動鰭狀結構112g/112i之間,分別設置犧牲鰭狀結構112o/112n。
The static random access memory unit U1 of (1,1,1) type includes two boost transistors (PU FinFET) PU1, two channel transistors (PG FinFET) PG1, and two step-down piezoelectric crystals (PD FinFET) PD1. In the static random access memory unit U1 of the (1,1,1) type, each channel transistor PG1 shares a single
在此強調,各鰭狀結構112之間的間距P會直接影響所形成之鰭狀結構112的寬度w與形狀。具體來說,當各鰭狀結構112之間的間距P越大,則所形成之鰭狀結構112的剖面輪廓斜度越大,意即角度θ越大;當各鰭狀結構112之間的間距P越小,則所形成之鰭狀結構112的剖面輪廓斜度越陡,意即角度θ越小。因此,當各鰭狀結構112之間的間距P不相同時,會造成所形成的各鰭狀結構112之寬度與剖面輪廓傾斜度不相同。當各鰭狀結構112之寬度與剖面輪廓不均勻,則會劣化製程穩定度及所形成之裝置的可靠度等性能。在本實施例中,同時在主動鰭狀結構112e/112f/112g/112h/112i/112j之間補上犧牲鰭狀結構112k/112l/112m/112n/112o,用以調整鰭狀結構112之間的間距P,俾使各鰭狀結構
112之間距P與其他區域(例如邏輯區)之鰭狀結構之間距盡可能相同。在本實施例中,僅在主動鰭狀結構112e/112f/112g/112h/112i/112j之間補上單一條犧牲鰭狀結構112k/112l/112m/112n/112o,但本發明不以此為限。本發明亦可在主動鰭狀結構112e/112f/112g/112h/112i/112j之間選擇性補上犧牲鰭狀結構112k/112l/112m/112n/112o,或者在二相鄰的主動鰭狀結構112e/112f/112g/112h/112i/112j之間補上兩條及以上的犧牲鰭狀結構112k/112l/112m/112n/112o,視各鰭狀結構112之間的間距P與相對其他區域的鰭狀結構之間的間距而定。
It is emphasized here that the pitch P between the
更進一步而言,(1,1,1)型的靜態隨機存取記憶體單元U1又可包含一多晶矽閘極120跨設鰭狀結構112,內連線金屬130連接各電晶體包含通道電晶體PG1、降壓電晶體PD1與升壓電晶體PU1,接觸插塞140則物理性連接多晶矽閘極120及內連線金屬130。(1,1,1)型的靜態隨機存取記憶體單元U1之結構與運作方法為本領域所熟知,故不再詳細贅述。
Furthermore, the (1,1,1) type static random access memory unit U1 may further include a
另外,本發明亦可應用於一(1,2,2)型的靜態隨機存取記憶體單元陣列,如第8圖所示。(1,2,2)型的靜態隨機存取記憶體單元U2與(1,1,1)型的靜態隨機存取記憶體單元U1的差別在於:(1,1,1)型的靜態隨機存取記憶體單元U1中的主動鰭狀結構112h取代成為兩條主動鰭狀結構112h1/112h2,而(1,2,2)型的靜態隨機存取記憶體單元U2中一通道電晶體(PG FinFET)PG2與對應的一降壓電晶體(PD FinFET)PD2共享此二主動鰭狀結構112h1/112h2;(1,1,1)型的靜態隨機存取記憶體單元U1中的主動鰭狀結構112g取代成為兩條主動鰭狀結構112g1/112g2,而(1,2,2)型的靜態隨機存取記憶體單元U2中另一通道電晶體(PG FinFET)PG2與對應的一降壓電晶體(PD FinFET)PD2共享此二主動鰭狀結構112g1/112g2。(1,1,1)
型的靜態隨機存取記憶體單元U1側邊的主動鰭狀結構112i取代成為兩條主動鰭狀結構112i1/112i2,且(1,1,1)型的靜態隨機存取記憶體單元U1側邊的主動鰭狀結構112j取代成為兩條主動鰭狀結構112j1/112j2。二相鄰的升壓電晶體PU2跨設的二主動鰭狀結構112e/112f之間仍設置有單一犧牲鰭狀結構112k。
In addition, the present invention can also be applied to a (1,2,2) type static random access memory cell array, as shown in FIG. 8. The difference between (1,2,2) type static random access memory unit U2 and (1,1,1) type static random access memory unit U1 is: (1,1,1) type static random The active fin structure 112h in the access memory unit U1 is replaced by two active fin structures 112h1/112h2, and the (1,2,2) type static random access memory unit U2 has a channel transistor (PG FinFET) PG2 shares the two active fin structures 112h1/112h2 with the corresponding PD FinFET PD2; the active fin structure in the (1,1,1) type static random access memory unit U1 112g is replaced by two active fin structures 112g1/112g2, and another channel transistor (PG FinFET) PG2 in the (1,2,2) type static random access memory unit U2 and a corresponding buck piezoelectric crystal (PD FinFET) PD2 shares the two active fin structures 112g1/112g2. (1,1,1)
The active fin structure 112i on the side of the static random access memory unit U1 is replaced with two active fin structures 112i1/112i2, and the side of the (1,1,1) type static random access memory unit U1 The active fin structure 112j is replaced by two active fin structures 112j1/112j2. A single
由於此二主動鰭狀結構112h1/112h2之間的間距P1、此二主動鰭狀結構112i1/112i2之間的間距P2以及此二主動鰭狀結構112j1/112j2之間的間距P3小於其他鰭狀結構112之間的間距P4,故除了此二主動鰭狀結構112h1/112h2之間、此二主動鰭狀結構112i1/112i2之間以及此二主動鰭狀結構112j1/112j2之間無設置犧牲鰭狀結構之外,其他鰭狀結構112之間皆設置有犧牲鰭狀結構112k/112l/112m/112n/112o。因此,本實施例可調整各鰭狀結構112之間的間距,俾使各鰭狀結構112之間距盡可能相同。如此一來,即可使所形成之各鰭狀結構112具有相同寬度及形狀,因而能促進製程可靠度,進而提升靜態隨機存取記憶體的性能。
Because the pitch P1 between the two active fin structures 112h1/112h2, the pitch P2 between the two active fin structures 112i1/112i2, and the pitch P3 between the two active fin structures 112j1/112j2 are smaller than other fin structures There is no P4 between the two active fin structures 112h1/112h2, between the two active fin structures 112i1/112i2, and between the two active fin structures 112j1/112j2 In addition,
另外,在形成主動鰭狀結構112e/112f/112g(112g1/112g2)/112h(112h1/112h2)/112i(112i1/112i2)/112j(112j1/112j2)以及犧牲鰭狀結構112k/112l/112m/112n/112o之後,可形成絕緣結構40於主動鰭狀結構112e/112f/112g(112g1/112g2)/112h(112h1/112h2)/112i(112i1/112i2)/112j(112j1/112j2)之間,其中主動鰭狀結構112e/112f/112g(112g1/112g2)/112h(112h1/112h2)/112i(112i1/112i2)/112j(112j1/112j2)突出絕緣結構40,但絕緣結構40覆蓋全部的犧牲鰭狀結構112k/112l/112m/112n/112o。
In addition,
綜上所述,本發明提出一種靜態隨機存取記憶體單元陣列及其形成 方法,其先圖案化而形成複數個鰭狀結構於一基底上,其中此些鰭狀結構可包含複數個主動鰭狀結構以及複數個犧牲鰭狀結構,接著再移除至少部份的犧牲鰭狀結構,如此即可藉由在所需之主動鰭狀結構佈局中加入犧牲鰭狀結構,俾使各鰭狀結構之間的間距相同,或近乎相同,如此可使各鰭狀結構的寬度與形狀相同。本發明所形成之寬度與形狀相同的各鰭狀結構,可促進製程穩定性以及裝置的可靠度。 In summary, the present invention proposes a static random access memory cell array and its formation A method of patterning a plurality of fin-like structures on a substrate, wherein the fin-like structures may include a plurality of active fin-like structures and a plurality of sacrificial fin-like structures, and then at least part of the sacrificial fins are removed In this way, the sacrificial fin structure can be added to the desired active fin structure layout so that the spacing between the fin structures is the same, or nearly the same, so that the width of each fin structure can be Same shape. The fin structures with the same width and shape formed by the invention can promote the stability of the manufacturing process and the reliability of the device.
詳細而言,本發明所形成之靜態隨機存取記憶體單元陣列中的各靜態隨機存取記憶體包含二升壓電晶體、二通道電晶體以及二降壓電晶體。各通道電晶體(PG FinFET)與對應的一降壓電晶體(PD FinFET)至少共享一主動鰭狀結構,例如本發明可形成一(1,1,1)型的靜態隨機存取記憶體單元陣列,其各通道電晶體與對應的降壓電晶體僅共享單一主動鰭狀結構,或者本發明可形成一(1,2,2)型的靜態隨機存取記憶體單元陣列,其各通道電晶體與對應的降壓電晶體僅共享二主動鰭狀結構。在此強調,本發明在一靜態隨機存取記憶體單元中二相鄰的升壓電晶體跨設的二主動鰭狀結構之間設置有至少一犧牲鰭狀結構,以使(通常具有較大間距的)二主動鰭狀結構之間的間距可近似於靜態隨機存取記憶體單元中的其他主動鰭狀結構之間的間距,或者其他區域(例如邏輯區)中的鰭狀結構之間的間距。以本發明之方法,各鰭狀結構中的一最大間距勢必小於各鰭狀結構中的一最小間距的兩倍(,否則即可在最大間距之間再加入一犧牲鰭狀結構)。以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 In detail, each static random access memory in the static random access memory cell array formed by the present invention includes two boost transistors, two channel transistors, and two drop piezoelectric crystals. Each channel transistor (PG FinFET) and the corresponding one of the reduced piezoelectric crystal (PD FinFET) share at least an active fin structure, for example, the present invention can form a (1,1,1) type static random access memory unit Array, each channel transistor and the corresponding step-down crystal only share a single active fin structure, or the invention can form a (1,2,2) type static random access memory cell array, each channel The crystal and the corresponding voltage-reducing crystal share only two active fin structures. It is emphasized here that the present invention is provided with at least one sacrificial fin structure between two active fin structures straddling two adjacent boost transistors in a static random access memory cell, so that (usually having a larger The spacing between the two active fin structures can be similar to the spacing between other active fin structures in the static random access memory unit, or between the fin structures in other regions (such as logic regions) spacing. According to the method of the present invention, a maximum pitch in each fin structure is bound to be less than twice the minimum pitch in each fin structure (otherwise, a sacrificial fin structure can be added between the maximum pitch). The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.
40:絕緣結構 40: Insulation structure
110:基底 110: base
112e、112f、112g、112h、112i、112j:主動鰭狀結構 112e, 112f, 112g, 112h, 112i, 112j: active fin structure
112k、112l、112m、112n、112o:犧牲鰭狀結構 112k, 112l, 112m, 112n, 112o: sacrificial fin structure
112a’、112b’、112c’、112d’:剩餘部分 112a’, 112b’, 112c’, 112d’: the rest
120:多晶矽閘極 120: Polysilicon gate
130:內連線金屬 130: interconnection metal
140:接觸插塞 140: contact plug
A:靜態隨機存取記憶體單元區 A: Static random access memory unit area
P:間距 P: pitch
PD1:降壓電晶體 PD1: step-down piezoelectric crystal
PG1:通道電晶體 PG1: channel transistor
PU1:升壓電晶體 PU1: Boost transistor
U1:(1,1,1)型的靜態隨機存取記憶體單元 U1: (1,1,1) type static random access memory unit
w:寬度 w: width
θ:角度 θ: angle
Claims (19)
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US15/635,190 US9941288B2 (en) | 2016-04-27 | 2017-06-27 | Static random-access memory (SRAM) cell array |
US15/635,165 US9953988B2 (en) | 2016-04-27 | 2017-06-27 | Method of forming static random-access memory (SRAM) cell array |
US15/686,169 US9947674B2 (en) | 2016-04-27 | 2017-08-25 | Static random-access memory (SRAM) cell array |
US15/691,764 US10050046B2 (en) | 2016-04-27 | 2017-08-31 | Static random-access memory (SRAM) cell array and forming method thereof |
US16/028,442 US10468420B2 (en) | 2016-04-27 | 2018-07-06 | Method of forming static random-access memory (SRAM) cell array |
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US20150206890A1 (en) * | 2012-11-14 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell Layout for SRAM FinFET Transistors |
US9257439B2 (en) * | 2014-02-27 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET SRAM |
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US20140097499A1 (en) * | 2008-05-05 | 2014-04-10 | Micron Technology, Inc. | Semiconductor Structures |
US8942030B2 (en) * | 2010-06-25 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for SRAM cell circuit |
US8669186B2 (en) * | 2012-01-26 | 2014-03-11 | Globalfoundries Inc. | Methods of forming SRAM devices using sidewall image transfer techniques |
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