TWI762425B - Method of adjusting signal to noise ratio of sram and invertor structure - Google Patents

Abstract

An inverter structure includes a first fin structure disposed within a P-type transistor region on a substrate. A second fin structure is disposed within an N-type transistor region on the substrate. A gate line is disposed within the P-type transistor region and the N-type transistor region. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are respectively disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A first distance between the first end and the first fin structure is greater than a third end between the third end and the first fin structure. The second distance between the second end and the second fin structure is smaller than a fourth distance between the fourth end and the second fin structure.

Description

The Adjustment Method of Signal-to-Noise Ratio of Static Random Access Memory and the Structure of Inverter

The present invention relates to a method for adjusting the signal-to-noise ratio of a static random access memory and an inverter structure, especially a method and structure for improving the signal-to-noise ratio and the performance of the inverter by adjusting the gate length.

In a static random access memory (SRAM) composed of six transistors, each bit is stored in two cross-coupled inverters composed of four field effect transistors. The other two field effect transistors are the control switches of the bit line (Bit Line) of the static random access memory. The SRAM itself is a volatile memory cell (MC), that is, when the power supplied to the SRAM disappears, the stored data will be erased at the same time. The way of storing data in static random access memory is achieved by using the conductive state of the transistor in the memory cell. Its design is based on the use of mutually coupled transistors, there is no problem of capacitor discharge, and it does not need to be continuously charged to keep the data from being lost. That is, no memory update operation is required, which is different from the dynamic random access memory (DRAM), which is also a volatile memory, using the charged state of the capacitor to store data. SRAM is used as a cache memory in computer systems. However, as the speed of electronic components increases, the performance and read/write speed of SRAM are also required. improve.

In view of this, the present invention utilizes varying gate lengths to increase the threshold voltage, read current and signal-to-noise ratio of the transistor to improve the performance of inverters and SRAMs.

According to a preferred embodiment of the present invention, an inverter structure includes: a substrate includes a P-type transistor region and an N-type transistor region, a first fin structure is disposed in the P-type transistor region, A second fin structure is disposed in the N-type transistor region, wherein the second fin structure is parallel to the first fin structure, and a gate line is disposed in the P-type transistor region and the N-type transistor region and is parallel to the first fin structure The structure is vertical, wherein the gate line includes a first end located in the P-type transistor region and a second end located in the N-type transistor region, and two first dummy gate lines are located on both sides of the gate line respectively and the second end is located in the N-type transistor region. A dummy gate line is perpendicular to the first fin structure, the first dummy gate line includes a third end located in the P-type transistor region and a fourth end located in the N-type transistor region, wherein the first end A first distance from the first fin structure is greater than a third distance between the third end and the first fin structure, and a second distance between the second end and the second fin structure is smaller than the third distance. a fourth distance between the four ends and the second fin structure.

According to a preferred embodiment of the present invention, a method for adjusting the signal-to-noise ratio of a static random access memory includes firstly providing a substrate, and a first long fin structure and a second long fin structure are disposed on the substrate , a first short fin structure and a second short fin structure are arranged on the substrate and located between the first long fin structure and the second long fin structure, a first gate line and the first long fin The first short fin structure and the second long fin structure are interlaced, and a second gate line is interlaced with the first long fin structure, the second short fin structure and the second long fin structure, wherein the first The long fin structure includes a first side and a second side, the second side faces the first short fin structure, the first side and the second side are opposite, and the second long fin structure includes a third side and a fourth side side, the fourth side faces the second short fin structure, the third side and the fourth side are opposite, and then a gate line truncation step is performed, and the gate line truncation step includes placing the first long fin structure and the second short fin structure. The second gate line between the fin structures is removed by a first length, the first gate line located between the second long fin structure and the first short fin structure is removed by the first length, and the first gate line located between the second long fin structure and the first short fin structure is removed by a first length. The first gate line on the first side of an elongated fin structure is removed by a second length, and the second gate line on the third side of the second long fin structure is removed by a second length. It is worth noting that: When the first length is greater than the second length, the SNR of the SRAM is greater than that of the SRAM when the first length is equal to the second length.

FIGS. 1 to 2 illustrate a method for fabricating a static random access memory according to a first preferred embodiment of the present invention.

As shown in FIG. 1, a substrate 10 is first provided, and a first long fin structure 12a, a second long fin structure 12b, a first short fin structure 14a and a second short fin structure 14b are disposed on the On the substrate 10, the first short fin structure 14a and the second short fin structure 14b are located between the first long fin structure 12a and the second long fin structure 12b, the first long fin structure 12a, the second long fin structure 12a, the second long fin structure The fin structures 12b, the first short fin structures 14a and the second short fin structures 14b are parallel to each other. In addition, a first gate line 16a intersects with the first long fin structure 12a, the first short fin structure 14a and the second long fin structure 12b, and a second gate line 16b and the first long fin structure 12a , The second short fin structure 14b and the second long fin structure 12b are staggered, the first gate line 16a and the second gate line 16b are parallel to each other, it is worth noting that the first short fin structure 14a The two gate lines 16b are overlapped or interlaced, and the second short fin structures 14b are not overlapped or interlaced with the first gate lines 16a. In detail, the first long fin structure 12a includes a first side 18 and a second side 20, the second side 20 faces the first short fin structure 14a, the first side 18 and the second side 20 are opposite, and the second side 20 faces the first short fin structure 14a. The two long fin structures 12b include a third side 22 and a fourth side 24, the fourth side 24 faces the second short fin structure 14b, and the third side 22 and the fourth side 24 are opposite to each other. The substrate 10 can be a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate or a silicon carbide substrate. The first long fin structure 12a, the second long fin structure 12b, the first short fin structure 14a and the second short fin structure 14b may be extended from the base 10 and have the same material as the base 10, the first gate Line 16a and second gate line 16b may include a conductive polysilicon and a gate dielectric layer.

Next, a gate line cutting step is performed to provide a basic length L, the basic length L, the first gate line 16a and the second gate line 16b being parallel. At the same time, the second gate line 16b located between the first long fin structure 12a and the second short fin structure 14b, the second gate line 16b located between the second long fin structure 12b and the first short fin structure 14a A gate line 16a, the first gate line 16a located on the first side 18 of the first elongated fin structure 12a, and the second gate line 16b located on the third side 22 of the second elongated fin structure 12b are removed The basic length L, that is to say, the first gate line 16a and the second gate line 16b are respectively removed by two discontinuous basic lengths L at the same time. As shown in FIG. 2, after the gate line cutting step, the first gate line 16a is cut into three first gate line segments 116a, and the second gate line 16b is cut into three second gate line segments 116b Finally, a dielectric layer 26 is formed to cover the end of each first gate line segment 116a and the end of each second gate line segment 16b.

The gate line truncation step can be completed by a lithography process and an etching process. For example, a photoresist (not shown) can be formed to cover the substrate 10, the first long fin structure 12a, the second long fin structure 12b, The first short fin structure 14a, the second short fin structure 14b, the first gate line 16a and the second gate line 16b, and then a photomask (not shown) is used to pattern the photoresist and define on the photoresist The region 19 to be removed later includes the positions of the first gate line 16a and the second gate line 16b to be removed, and then part of the first gate line 16a and part of the second gate line 16a are simultaneously removed by etching process. 16b removes several base lengths L to form several first gate line segments 116a and several second gate line segments 116b.

Please continue to refer to FIG. 2, the completed first gate line segments 116a, the second gate line segments 116b, the first long fin structure 12a, the second long fin structure 12b, and the first short fin The fin-like structure 14a and the second short fin-like structure 14b together form a static random access memory 100, and the static random access memory 100 has an initial signal-to-noise ratio and an initial read current value.

Figures 3 to 4 illustrate a method for adjusting the signal-to-noise ratio of a static random access memory according to a second preferred embodiment of the present invention, wherein components with the same function and location are given as the first The same reference numerals in the preferred embodiment.

As shown in FIG. 3, the substrate 10, the first long fin structure 12a, the second long fin structure 12b, the first short fin structure 14a, the second short fin structure 14a, the second short fin structure 14a and the second short fin structure are first provided as described in the first preferred embodiment. The detailed materials and positions of the fin structure 14b, the first gate line 16a and the second gate line 16b can be referred to in the first preferred embodiment, which will not be repeated here.

Next, a gate line truncation step is performed to provide a first length L ₁ and a second length L ₂ , wherein the first length L ₁ is greater than the basic length L in the first preferred embodiment, and the second length L ₂ is less than the first length L 2 In a preferred embodiment, the basic length L, that is, the first length L ₁ is greater than the second length L ₂ . The first length L ₁ , the second length L ₂ and the base length L are parallel. The first length L1 on the _first gate line 16a and the second gate line 16b is increased by a first adjustment length in the direction of the first long fin structure 12a and the second long fin structure 12b respectively from the basic length L d ₁ , the second length L ₂ on the first gate line 16a and the second gate line 16b is reduced by a second adjustment length d from the basic length L in the direction away from the first side 18 and the third side 22, respectively _2. The first adjustment length d ₁ and the second adjustment length d ₂ may be the same or different. As taught in the first preferred embodiment, the gate line breaking step can be accomplished using a lithography process plus an etching process.

In the gate line truncation step, the gate line is located between the first long fin structure 12a and the second short fin structure 14b, is close to the first short fin structure 14a and the first long fin structure 12a, and is close to the first long fin structure 14a and the first long fin structure 12a The second gate line 16b that is farther from the two short fin structures 14b is removed by the first length L ₁ and will be located between the second long fin structure 12b and the first short fin structure 14a and away from the second short fin structure The first gate line 16a, which is closer to the second long fin structure 12b and farther from the first short fin structure 14a, is located at the first gate line 16a of the first long fin structure 12a with the first length L ₁ removed. The first gate line 16a on side 18 and the second gate line 16b on the third side 22 of the second elongated fin structure 12b are removed by a _second length L2.

As shown in FIG. 4, after the gate line cutting step, the first gate line 16a is cut into three first gate line segments 116a, and the second gate line 16b is cut into three second gate line segments 116b , two first gate line segments 116a, two second gate line segments 116b, a first long fin structure 12a, a second long fin structure 12b, a first short fin structure 14a and a second short fin structure 14b A static random access memory 200 is formed together, and a dielectric layer 26 is formed to cover the end of each first gate line segment 116a and the end of each second gate line segment 116b. The dielectric layer 26 may be nitrided Silicon, silicon oxide and other insulating materials.

A first pull-down transistor PD1 is formed where the first long fin structure 12a and the first gate line segment 116a overlap, and the first long fin structure 12a and the second gate line segment 116b intersect A first pass gate transistor PG1 is formed at the overlap, and a first pull-up transistor PU1 is formed at the overlap of the first short fin structure 14a and the first gate line segment 116a , a second pull-up transistor PU2 is formed where the second short fin structure 14b and the second gate line segment 116b overlap, and a second pull-up transistor PU2 is formed where the second long fin structure 12b and the first gate line segment 116a overlap. Two access transistors PG2, a second pull-down transistor PD2 is formed where the second long fin structure 12b and the second gate line segment 116b overlap. The difference between the first preferred embodiment and the second preferred embodiment is that the length of the gate line to be removed is different. The first access transistor PG1 and the second access transistor produced by the second preferred embodiment are The gate line segment in the transistor PG2 is shorter than the gate line segment at the same position fabricated in the first preferred embodiment, and the first pull-down transistor PD1 and the first pull-down transistor PD1 fabricated in the second preferred embodiment The gate line segment in the two pull-down transistors PD2 is longer than the gate line segment at the same position fabricated in the first preferred embodiment. And because the dielectric layer 26 contains stress, it will be applied to the first gate line segment 116a and the second gate line segment 116b from the end of the first gate line segment 116a and the end of the second gate line segment 116b stress, resulting in the stress on the first access transistor PG1, the second access transistor PG2, the first pull-down transistor PD1 and the second pull-down transistor PD2 in the second preferred embodiment In the preferred embodiment, the threshold voltage of each transistor in the second preferred embodiment will be different from that in the first preferred embodiment, and finally the signal-to-noise ratio of the SRAM 200 will be better. Static random access memory is 100 large.

FIG. 5 is an equivalent circuit diagram of the SRAM in FIG. 4 . Please refer to FIG. 4 and FIG. 5 at the same time, the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1 and the second pull-down transistor PD2 form a latch circuit (latch), so that Data can be latched on Storage Node 28 or 30 . The first pull-up transistor PU1 and the first pull-down transistor PD1 together form an inverter, and both ends of the series circuit formed by the two are respectively coupled to a voltage source Vcc and a The voltage source Vss; similarly, the second pull-up transistor PU2 and the second pull-down transistor PD2 form another inverter, and the two ends of the series circuit formed by the two are also respectively coupled to the voltage source Vcc and Voltage source Vss. The two inverters are coupled to each other to store data.

In one embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 are composed of P-type transistors, and the first pull-down transistor PD1 , the second pull-down transistor PD2 and the first access transistor The transistor PG1 and the second access transistor PG2 are composed of N-type transistors, but the invention is not limited thereto. In addition, the source of the first access transistor PG1 is electrically connected to the storage node 30 ; similarly, the source of the second access transistor PG2 is electrically connected to the storage node 28 . The gates of the first access transistor PG1 and the second access transistor PG2 are respectively coupled to the word line WL, and the drains of the first access transistor PG1 and the second access transistor PG2 are respectively Coupled to the corresponding bit lines BL1 and BL2.

Fig. 6 to Fig. 7 show a method for adjusting the read current value of a static random access memory according to the third preferred embodiment of the present invention, wherein elements with the same function and position are given The same reference number in a preferred embodiment. The third preferred embodiment differs from the second preferred embodiment in that the first length L ₁ in the second preferred embodiment is replaced by a third length L ₃ in the third preferred embodiment, and the third The preferred embodiment extends the second length L ₂ of the second preferred embodiment at the same location. In detail, the third length is reduced by a third adjustment length d ₃ in the direction away from the first long fin structure 12 a and the second long fin structure 12 b respectively from the basic length L, that is, the third length L ₃ If it is smaller than the basic length L, the read current value of the SRAM 300 fabricated in this way will be larger than that of the SRAM 100 .

FIG. 8 is a structure of an inverter according to a fourth preferred embodiment of the present invention. The structure of the inverter of the present invention can be applied to a static random access memory. The structure of the inverter includes A substrate 50, the substrate includes a P-type transistor region 52 and an N-type transistor region 54, a first fin structure 56a is disposed in the P-type transistor region 52, and a second fin structure 56b is disposed in the N-type transistor region The crystal region 54 in which the second fin structure 56b is parallel to the first fin structure 56a. A gate line 58 is disposed in the P-type transistor region 52 and the N-type transistor region 54 and is perpendicular to the first fin structure 56a and the second fin structure 56b, wherein the gate line 58 includes a first end 158 located in the P-type transistor region 52 and a second end 258 are located in N-type transistor region 54 . The two first dummy gate lines 60 are respectively located on both sides of the gate line 58 and the first dummy gate lines 60 are perpendicular to the first fin structure 56a and the second fin structure 56b, and the two first dummy gate lines The pole lines 60 each include a third end 160 in the P-type transistor region 52 and a fourth end 260 in the N-type transistor region 54, it is worth noting that the first end 158 and the first fin structure 56a A first distance S ₁ is greater than a third distance S ₃ between the third end 160 and the first fin structure 56a, and a second distance between the second end 258 and the second fin structure 56b S ₂ is less than a fourth distance S ₄ between the fourth end 260 and the second fin structure 56b. The first distance S ₁ , the second distance S ₂ , the third distance S ₃ , and the fourth distance S ₄ are parallel to the gate line 58 .

In addition, the overlapping region of the gate line 58 and the first fin structure 56a forms a P-type gate, and P-type source/drain doped regions are disposed in the first fin structure 56a on both sides of the P-type gate (not shown), a P-type transistor 62 is formed by the P-th gate, the P-type source/drain doped regions and the first fin structure 56a; on the gate line 58 and the second fin structure The overlapping region of the structure 56b forms an N-type gate, and an N-type source/drain doped region (not shown) is arranged in the second fin structure 56b on both sides of the N-type gate, and the N-type gate is formed by the N-type gate. The electrode, the N-type source/drain doped regions and the second fin structure 56b together form an N-type transistor 64 . An inverter is formed by the N-type transistor 62 and the P-type transistor 64 together.

In addition, a dielectric layer 66 covers the first end 158 , the second end 258 , the third end 160 and the fourth end 260 . The dielectric layer 66 can be silicon nitride, silicon oxide or other insulating materials, and contains stress in the dielectric layer 66, so the stress in the dielectric layer 66 can be applied to the first end 158, the second end 258, The third end 160 and the fourth end 260 in turn change the stress in the fin structure directly below the N-type gate or P-type gate. The stress in the dielectric layer 66 is tensile stress. Therefore, in the P-type transistor 62, when the first end 158 of the gate line 58 of the P-type gate of the P-type transistor 62 is separated from the first end of the P-type transistor 62 The farther a fin structure 56a is, the better the performance of the P-type transistor 62; the second end 258 of the gate line 58 of the N-type gate in the N-type transistor 64 The closer the fin structure 56b is, the better the performance of the N-type transistor 64 is.

According to a preferred embodiment of the present invention, the structure of the inverter may further include two second dummy gate lines 68 , and each second dummy gate line 68 is respectively disposed on each first dummy gate electrode one side of line 60 and not between first dummy gate line 60 and gate line 58 . The first dummy gate line 60 and the second dummy gate line 68 are both floating, only the gate line 58 has an external voltage, and the first dummy gate line 60 and the second dummy gate line 68 are in the The gate line 58 is formed in order to avoid a loading effect.

In addition, each of the second dummy gate lines 68 has a fifth end 168 in the P-type transistor region 52 and a sixth end 268 in the N-type transistor region 54, and the _third distance S3 is greater than the fifth end A _fifth distance S5 between 168 and the first fin structure 56a, and a _fourth distance S4 is smaller than a sixth distance S6 between the _sixth end 268 and the second fin structure 56b. Likewise fifth end 168 and sixth end 268 are also encapsulated by dielectric layer 66 . The distance between the ends of the first dummy gate line 60 and the second dummy gate line 68 and the adjacent fin structures will affect the stress on the P-type transistor 62 and the N-type transistor 64. The dummy gate line that is closer to the gate line 58 has a greater impact on the performance of the P-type transistor 62 and the N-type transistor 64 , that is, the third end 160 of the first dummy gate line 60 and the first fin. The influence of the third distance S ₃ between the fin structures 56a on the P-type transistor 62 is greater than that of the fifth distance S ₅ between the fifth end 168 of the second dummy gate line 68 and the first fin structure 56a to P The influence of the N-type transistor 62; the same, the fourth distance S ₄ between the fourth end 260 of the first dummy gate line 60 and the second fin structure 56b has a greater influence on the N-type transistor 64 than the second dummy The effect of the sixth distance S ₆ between the sixth end 268 of the gate line 68 and the second fin structure 56b on the N-type transistor 64 . The distance between the end of the first dummy gate line 60 and the second dummy gate line 68 and the fin structure is in accordance with the distance between the dummy gate line and the gate line 58, and the distance between the dummy gate line It is used as a dummy gate line next to the N-type transistor 64 or the P-type transistor 62 to determine the distance between its end and the fin structure. Therefore, the distances from the first end 158 , the third end 160 and the fifth end 168 in the P-type transistor region 52 to the first fin structure 56 a are the first distance S ₁ the largest, and the third distance S ₃ the second , and the _fifth distance S5 is the smallest; the distance between the second end 258, the fourth end 260 and the sixth end 268 in the N-type transistor region 54 to the second fin structure 56b is the sixth distance _S6 is the largest, The fourth distance S ₄ is the next, and the second distance S ₂ is the smallest.

FIG. 9 shows an N-type transistor structure according to a fifth preferred embodiment of the present invention, wherein elements having the same functions and positions will be given the same reference numerals as in the fourth preferred embodiment. The difference from the fourth preferred embodiment is that in the fifth preferred embodiment, only one second fin structure 56b is located in the N-type transistor region 54 and there is no P-type transistor region, so the second fin structure of the gate line 58 is The end 258 , the fourth end 260 of the first dummy gate line 60 and the sixth end 268 of the second dummy gate line 68 are in accordance with the sixth distance S of the N-type transistor region 54 in the fourth preferred embodiment ₆ is the largest, the _fourth distance S is the second, and the _second distance S is the smallest. In addition, the gate line 58 , the first dummy gate line 60 and the second dummy gate line 68 may only have one end arranged according to the above principle, and the other end may be aligned. As shown in Figure 9, both ends can be arranged according to the above principles. If both ends are arranged according to the above principles, the efficiency will be doubled compared to the efficiency of only one end arranged according to the above principles.

FIG. 10 shows a P-type transistor structure according to a sixth preferred embodiment of the present invention, wherein elements with the same functions and positions will be given the same reference numerals as in the fourth preferred embodiment. The difference from the fourth preferred embodiment is that in the sixth preferred embodiment, only one first fin structure 56a is located in the P-type transistor region 52 and there is no N-type transistor region, so the first fin structure of the gate line 58 is The end 158, the third end 160 of the first dummy gate line 60 and the fifth end 168 of the second dummy gate line 68 are in accordance with the first distance within the P-type transistor region in the fourth preferred embodiment S1 is the largest, the third distance S is the _third , and the _fifth distance S5 is the smallest. In addition, the gate line 58, the _first dummy gate line 60 and the second dummy gate line 68 may have only one end The ends are arranged according to the above principles, and the ends of the other end are cut evenly, or as shown in Figure 10, the ends of both ends are arranged according to the above principles. The performance of the above principle arrangement is increased by a factor of 2. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Base 12a: First long fin-like structure 12b: Second long fin-like structure 14a: First short fin-like structure 14b: Second short fin-like structure 16a: first gate line 16b: Second gate line 18: First side 19: Area 20: Second side 22: Third side 24: Fourth side 26: Dielectric layer 28: Storage Node 30: Storage Node 50: base 52: P-type transistor region 54: N-type transistor region 56a: first fin structure 56b: Second fin structure 58: gate line 60: The first dummy gate line 62: P-type transistor 64: N-type transistor 66: Dielectric layer 68: The second dummy gate line 100: Static random access memory 116a: first gate line segment 116b: second gate line segment 158: First End 160: Third End 168: Fifth End 200: Static random access memory 258: Second End 260: Fourth End 268: Sixth End 300: Static random access memory BL1: bit line BL2: bit line d1: the first adjustment length d2: the second adjustment length d3: the third adjustment length L: basic length L1: first length L2: second length L3: third length PD1: The first pull-down transistor PD2: Second pull-down transistor PG1: first access transistor PG2: Second access transistor PU1: The first pull-up transistor PU2: Second pull-up transistor S1: first distance S2: Second distance S3: The third distance S4: Fourth distance S5: Fifth distance S6: Sixth distance Vcc: voltage source Vss: voltage source WL: word line

FIGS. 1 to 2 illustrate a method for fabricating a static random access memory according to a first preferred embodiment of the present invention. FIG. 3 to FIG. 4 illustrate a method for adjusting the signal-to-noise ratio of a static random access memory according to the second preferred embodiment of the present invention. FIG. 5 is an equivalent circuit diagram of the SRAM in FIG. 4 . FIGS. 6 to 7 are diagrams illustrating an adjustment method of a read current value of a SRAM according to a third preferred embodiment of the present invention. FIG. 8 shows the structure of an inverter according to a fourth preferred embodiment of the present invention. FIG. 9 shows an N-type transistor structure according to a fifth preferred embodiment of the present invention. FIG. 10 is a P-type transistor structure according to a sixth preferred embodiment of the present invention.

12a: First long fin-like structure

12b: Second long fin-like structure

14a: First short fin-like structure

14b: Second short fin-like structure

18: First side

20: Second side

22: Third side

24: Fourth side

26: Dielectric layer

100: Static random access memory

116a: first gate line segment

116b: second gate line segment

Claims (9)

A method for adjusting the signal-to-noise ratio of static random access memory, including: Provide a base, a first long fin structure and a second long fin structure are arranged on the base, a first short fin structure and a second short fin structure are arranged on the base and located on the first Between a long fin structure and the second long fin structure, a first gate line is interlaced with the first long fin structure, the first short fin structure and the second long fin structure, a first Two gate lines are interlaced with the first long fin structure, the second short fin structure and the second long fin structure, wherein the first long fin structure includes a first side and a second side, the The second side faces the first short fin structure, the first side is opposite to the second side, the second long fin structure includes a third side and a fourth side, the fourth side faces the second short a fin structure, the third side and the fourth side are opposite; and A gate line truncation step is performed, including: The second gate line located between the first long fin structure and the second short fin structure is removed by a first length, and the second gate line located between the second long fin structure and the first short fin structure The first gate line between the structures is removed by the first length, and the first gate line located on the first side of the first long fin structure is removed by a second length to be located in the second the second gate line on the third side of the elongated fin structure has the second length removed; When the first length is greater than the second length, the SNR of the SRAM is greater than that of the SRAM when the first length is equal to the second length. The signal-to-noise ratio adjustment method of a static random access memory as claimed in claim 1, wherein the first long fin structure, the second long fin structure, the first short fin structure and the second short fin structure The fin structures are parallel to each other, the first gate line and the second gate line are parallel to each other, and the first gate line is perpendicular to the first long fin structure. The method for adjusting the signal-to-noise ratio of the static random access memory as claimed in claim 1, wherein when the gate line truncation step is performed, the second gate line with the first length removed is also separated from the first gate line at the same time. A long fin structure is closer and farther from the second short fin structure, and the first gate line with the first length removed is closer to the second long fin structure and farther from the first short fin structure structure is far away. The signal-to-noise ratio adjustment method of the static random access memory as claimed in claim 3, wherein the first short fin structure does not overlap with the second gate line, and the second short fin structure does not overlap with the first short fin structure. A gate line overlaps. The method for adjusting the signal-to-noise ratio of the static random access memory as described in claim 1, further comprising: After performing the gate line truncation step, the first gate line is truncated into three first gate line segments, and the second gate line is truncated into three second gate line segments; and A dielectric layer is formed to cover the ends of each of the first gate line segments and the ends of each of the second gate line segments. The signal-to-noise ratio adjustment method of the static random access memory according to claim 5, wherein a first pull-down transistor is formed at the overlap of the first long fin structure and the first gate line segment, and the first long fin structure and the first gate line are overlapped. A first access transistor is formed at the overlap of the fin structure and the second gate line segment, a first pull-up transistor is formed at the overlap of the first short fin structure and the first gate line segment, and the second short fin structure overlaps with the first gate line segment. A second pull-up transistor is formed at the overlap of the fin structure and the second gate line segment, and a second access transistor is formed at the overlap of the second long fin structure and the first gate line segment. A second pull-down transistor is formed where the fin structure and the second gate line section overlap. The signal-to-noise ratio adjustment method of the static random access memory according to claim 6, wherein the first pull-down transistor, the second pull-down transistor, the first pull-up transistor, the second pull-up transistor, The first access transistor and the second access transistor together form the SRAM. The method for adjusting the signal-to-noise ratio of the static random access memory as claimed in claim 1, wherein the first short fin structure is located between the first long fin structure and the second short fin structure. The method for adjusting the signal-to-noise ratio of a static random access memory as claimed in claim 1, wherein the second gate line between the first long fin structure and the second short fin structure is removed by removing the The first length, the first gate line located between the second long fin structure and the first short fin structure is removed by the first length, and the first gate line will be located in the first long fin structure of the first long fin structure. The steps of removing the second length from the first gate line on one side, and removing the second length from the second gate line on the third side of the second long fin structure are performed simultaneously.

Images