CN106887249A - Static RAM and its operating method - Google Patents
Static RAM and its operating method Download PDFInfo
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- CN106887249A CN106887249A CN201510931662.5A CN201510931662A CN106887249A CN 106887249 A CN106887249 A CN 106887249A CN 201510931662 A CN201510931662 A CN 201510931662A CN 106887249 A CN106887249 A CN 106887249A
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Abstract
The invention discloses a kind of static RAM and the method for operating on it.The static RAM includes：Latch units, are connected between first node and Section Point；First transmission transistor, its first end is connected to the first bit line, and the second end is connected to the first node, and first grid is connected to the first wordline, and second grid is connected to the second wordline；And second transmission transistor, its first end is connected to the Section Point, and the second end is connected to the second bit line, and first grid is connected to the first wordline, and second grid is connected to the second wordline.The transmission transistor has two kinds of mode of operations of electronic conduction or hole conduction, by adjusting transmission transistor electronic conduction or the mode of operation of hole conduction described in the lever selection of the first wordline and the second wordline, and the state that the transmission transistor is turned on or off in relevant work pattern can be controlled.Driving force is adjustable when the transmission transistor is turned on, and leakage current is very low during disconnection, so that power consumption when reducing latch units holding data.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of static RAM
And its operating method (SRAM).
Background technology
All the time, semiconductor integrated circuit field continues to develop according to the rule of Moore's Law always.
Wherein, with advances in technology, in SRAM the characteristic size of cmos device from micron order
Deep-submicron is narrowed down to.However, after devices scale to nanoscale, giving SRAM bands
Carried out many severe challenges, such as process complexity raising, short ditch performance degradation, reliability decrease,
Leakage Current and power consumption rise high.Short channel effect wherein, in device and various Leakage Currents (and
Its caused power consumption) have become the significant obstacle of SRAM technology development.Generally, it is difficult to
Make the performance indications such as capacity, speed, area and power consumption in the design of SRAM memory while obtaining
Optimize simultaneously and then meet the limitation of the performance in terms of various application requirements, power consumption well, in certain journey
Also cause that the further miniaturization of cmos device in SRAM becomes more and more difficult on degree.Meanwhile,
The development of the aspect such as battery-driven movement and the increase of wearable device demand also causes that SRAM sets
The power demand of meter becomes important all the more.
The storage of data, reading and write-in are largely dependent upon the crystalline substance in SRAM in SRAM
The relative driving force of body pipe.For example, in traditional 6 pipe SRAM structures, whole unit tool
There is symmetry, trombone slide constitutes bistable circuit under trombone slide and two NMOS on two of which PMOS,
For latching one-bit digital signal, two other nmos pass transistor is transmission transistor, they
Memory is read out or SRAM is attached or disconnected with peripheral circuit during write operation.
In order to keep read operation stabilization, it should make the driving force of transmission transistor weaker than lower trombone slide, and
In order to keep write operation stabilization, it should make the driving force of transmission transistor stronger than upper trombone slide.Cause
How this, reduce Leakage Current and thereby reduce power consumption as far as possible under conditions of noise margin is not influenceed
While when meeting read operation and write operation driving tube driving force limitation, be SRAM
Problem demanding prompt solution in design.
The content of the invention
In order to solve the above-mentioned problems in the prior art, the present invention propose following SRAM with
And it is kept, read and write operation method.
According to an aspect of the invention, there is provided a kind of SRAM.The SRAM includes：Latch
Unit, is connected between first node and Section Point；First transmission transistor, its first end connects
The first bit line is connected to, the second end is connected to the first node, and first grid is connected to the first wordline,
Second grid is connected to the second wordline；And second transmission transistor, its first end is connected to described
Section Point, the second end is connected to the second bit line, and first grid is connected to the first wordline, second gate
Pole is connected to the second wordline.
Preferably, the latch units include：Memory module, including the first memory transistor and
Two memory transistors, the first end of first memory transistor is connected to the first node, control
End processed is connected to the Section Point, and the second end of second memory transistor is connected to described
Two nodes, control end is connected to the first node, the second end of first memory transistor and
The first end of second memory transistor is grounded.
Preferably, the latch units may include：Load blocks, including the first load transistor and
Second load transistor, the first end of first load transistor is connected to the first node,
Control end is connected to the Section Point, and the second end of second load transistor is connected to described
Section Point, control end is connected to the first node, the second end of first load transistor
First end with second load transistor connects supply voltage.
Alternatively, the latch units may include：Load blocks, including first resistor and second
Resistance, the first end of the first resistor is connected to the first node, the of the second resistance
Two ends are connected to the Section Point, the second end of the first resistor and the of the second resistance
One end connects supply voltage.
Preferably, the first grid of first transmission transistor and second transmission transistor point
The mode of operation of the first transmission transistor and the second transmission transistor Yong Yu not be selected, described first passes
The second grid of defeated transistor and second transmission transistor is respectively used to be selected by first grid
The first transmission transistor and second transmission transistor are controlled in the mode of operation selected leads on and off
Open.
Preferably, the mode of operation includes electronic conduction pattern and hole conduction pattern.
Preferably, the channel material of first transmission transistor and second transmission transistor is
At least one of the following：CNT, intrinsic silicon, low-doped silicon, Graphene.
Preferably, the first end and of first transmission transistor and second transmission transistor
The material at two ends is the forbidden band central metal compound such as metal silicide.
Preferably, the first end of first transmission transistor is in source electrode and drain electrode, institute
The second end for stating the first transmission transistor be source electrode and drain electrode in another；Second transmission is brilliant
The first end of body pipe is in source electrode and drain electrode, and the second end of second transmission transistor is
Source electrode and drain electrode in another.
Preferably, the first end of first memory transistor is in source electrode and drain electrode, institute
The second end for stating the first memory transistor be source electrode and drain electrode in another；Second storage is brilliant
The first end of body pipe is in source electrode and drain electrode, and the second end of second memory transistor is
Source electrode and drain electrode in another.
Preferably, the first end of first load transistor is in source electrode and drain electrode, institute
The second end for stating the first load transistor be source electrode and drain electrode in another；Second load is brilliant
The first end of body pipe is in source electrode and drain electrode, and the second end of second load transistor is
Source electrode and drain electrode in another.
Preferably, first memory transistor and second memory transistor are NMOS crystal
Pipe.
Preferably, first load transistor and second load transistor are PMOS crystal
Pipe.
Preferably, by adjusting the level of the first wordline and the second wordline, the first transmission is enabled to
Transistor and the second transmission transistor disconnect or turn on.
Preferably, by adjusting the level of the first wordline and the second wordline, the first transmission is enabled to
Transistor and the second transmission transistor are turned on, and cause the driving energy of first transmission transistor
Power be weaker than the first memory transistor driving force and/or the second transmission transistor driving force it is weak
In the driving force of the second memory transistor.
Preferably, by adjusting the level of the first wordline and the second wordline, the first transmission is enabled to
Transistor and the second transmission transistor are turned on, and cause the driving energy of first transmission transistor
Power be better than the first load transistor driving force and/or the second transmission transistor driving force it is strong
In the driving force of the second load transistor.
According to another aspect of the invention, it is proposed that a kind of carry out keeping operation to above-mentioned SRAM
Method.Methods described includes：By adjusting the level of the first wordline, the first transmission transistor is selected
With the mode of operation of the second transmission transistor；It is brilliant according to the first transmission transistor and second transmission
The mode of operation of body pipe, by adjust the second wordline level, make first transmission transistor and
Second transmission transistor disconnects.
Above-mentioned SRAM is read according to another aspect of the invention, it is proposed that a kind of
Method.Methods described includes：By the level for adjusting the first wordline and the second wordline so that first
Transmission transistor and the second transmission transistor are turned on, and cause the drive of first transmission transistor
Kinetic force is weaker than the driving force of the first memory transistor and/or the driving energy of the second transmission transistor
Power is weaker than the driving force of the second memory transistor；And by adjusting the first bit line and the second bit line
Level, read stored data from the latch units.
Write operation is carried out to above-mentioned SRAM according to another aspect of the invention, it is proposed that a kind of
Method.Methods described includes：By the level for adjusting the first wordline and the second wordline so that first
Transmission transistor and the second transmission transistor are turned on, and cause the drive of first transmission transistor
Kinetic force is better than the driving force of the first load transistor and/or the driving energy of the second transmission transistor
Power is better than the driving force of the second load transistor；And by adjusting the first bit line and the second bit line
Level, to the latch units write the data to be stored.
In SRAM proposed by the present invention and its operating method, the pipe number in SRAM is not increased
In the case of amount, the very low transmission crystal of adjustable and leakage current is programmed by using driving force
Pipe (such as, restructural field-effect transistor), when being not only able to reduce sram cell holding data
Leakage current and thereby reduce power consumption, but also apply appropriate programming grid by two wordline
Voltage and control-grid voltage adjust the design side that the driving force of transmission transistor optimizes SRAM
Case.
Brief description of the drawings
Fig. 1 shows the structural representation of SRAM according to an embodiment of the invention；
Fig. 2 shows a kind of structural representation of exemplary restructural FET device；
Fig. 3 shows a kind of exemplary restructural FET device when applied voltage works
Current characteristics figure；
Fig. 4 shows the side for SRAM keep operation a kind of according to an embodiment of the invention
The flow chart of method；
Fig. 5 shows the side being read to SRAM a kind of according to an embodiment of the invention
The flow chart of method；
Fig. 6 shows the side that write operation is carried out to SRAM a kind of according to an embodiment of the invention
The flow chart of method；
Fig. 7 shows the structural representation of 6 pipe SRAM exemplary according to an embodiment of the invention；
Fig. 8 A and Fig. 8 B show the pressure that 6 pipe SRAM as shown in Figure 7 keep with operation
Situation schematic diagram；
Fig. 9 shows that the pressure situation being read to 6 pipe SRAM as shown in Figure 7 is illustrated
Figure；
Figure 10 A and Figure 10 B show carries out applying for write operation to 6 pipe SRAM as shown in Figure 7
Pressure situation schematic diagram.
Specific embodiment
The present invention is specifically described below with reference to accompanying drawing.
First, Fig. 1 shows the structural representation of SRAM 100 according to an embodiment of the invention.
The SRAM 100 includes that latch units 110, the first transmission transistor 120-1 (R1) and second are passed
Defeated transistor 120-2 (R2).The latch units 110 are connected to first node A1 and Section Point
Between A2.In the first transmission transistor 120-1, first end is connected to the first bit line BL, the
Two ends are connected to the first node A1, and first grid is connected to the first wordline WL1, second grid
It is connected to the second wordline WL2.In the second transmission transistor 120-2, first end is connected to described
Section Point A2, the second end is connected to the second bit line BLB, and first grid is connected to the first wordline
WL1, second grid is connected to the second wordline WL2.
The latch units 110 include memory module.The memory module includes the first memory transistor
With the second memory transistor.The first end of first memory transistor is connected to the first node
A1, control end is connected to the Section Point A2.The second end connection of second memory transistor
To the Section Point A2, control end is connected to the first node A1.First storage crystal
The first end of the second end of pipe and second memory transistor is grounded.
Preferably, the first end of first memory transistor is in source electrode and drain electrode, institute
The second end for stating the first memory transistor be source electrode and drain electrode in another；Second storage is brilliant
The first end of body pipe is in source electrode and drain electrode, and the second end of second memory transistor is
Source electrode and drain electrode in another.
Preferably, first memory transistor and second memory transistor are NMOS crystal
Pipe.
In some preferred embodiments, the latch units may also include load blocks.The load
Module includes the first load transistor and the second load transistor.The of first load transistor
One end is connected to the first node A1, and control end is connected to the Section Point A2.Described second
Second end of load transistor is connected to the Section Point A2, and control end is connected to the first segment
Point A1.The first end of the second end of first load transistor and second load transistor is equal
Connect supply voltage.
Preferably, the first end of first load transistor is in source electrode and drain electrode, institute
The second end for stating the first load transistor be source electrode and drain electrode in another；Second load is brilliant
The first end of body pipe is in source electrode and drain electrode, and the second end of second load transistor is
Source electrode and drain electrode in another.
Preferably, first load transistor and second load transistor are PMOS crystal
Pipe.
In other preferred embodiments, the latch units may include load blocks.The load
Module includes first resistor and second resistance.The first end of the first resistor is connected to described first
Node A1, the second end of the second resistance is connected to the Section Point A2, the first resistor
The second end and the first end of the second resistance connect supply voltage.
In an embodiment of the present invention, the first transmission transistor 120-1 and second transmission are brilliant
It is brilliant that the first grid of body pipe 120-2 is respectively used to the transmission of the first transmission transistor 120-1 of selection and second
The mode of operation of body pipe 120-2.Preferably, the mode of operation includes electronic conduction pattern and hole
Conduction mode.
In an embodiment of the present invention, the first transmission transistor 120-1 and second transmission are brilliant
The second grid of body pipe 120-2 is respectively used to be controlled in the mode of operation selected by first grid
The conducting and disconnection of the first transmission transistor 120-1 and the second transmission transistor 120-2.It is preferred that
Ground, by the level for adjusting the first wordline WL1 and the second wordline WL2 so that the first transmission crystal
Pipe 120-1 and the second transmission transistor 120-2 disconnects or turns on.
In an embodiment of the present invention, can be by adjusting the first wordline WL1 and the second wordline WL2
Level so that the first transmission transistor 120-1 and the second transmission transistor 120-2 are turned on, and
So that the driving force of the first transmission transistor 120-1 is weaker than the driving of the first memory transistor
The driving force of ability and/or the second transmission transistor 120-2 is weaker than the driving of the second memory transistor
Ability.
In an embodiment of the present invention, can be by adjusting the first wordline WL1 and the second wordline WL2
Level so that the first transmission transistor 120-1 and the second transmission transistor 120-2 are turned on, and
So that the driving force of the first transmission transistor 120-1 is better than the driving of the first load transistor
The driving force of ability and/or the second transmission transistor 120-2 is better than the driving of the second load transistor
Ability.
Preferably, in embodiments of the invention the first transmission transistor 120-1 and second transmission
The channel material of transistor 120-2 is at least one of the following：CNT, intrinsic silicon, low-mix
Miscellaneous silicon, Graphene.
Preferably, in embodiments of the invention the first transmission transistor 120-1 and second transmission
The material at the first end of transistor 120-2 and the second end is forbidden band central metal compound, such as metal
Silicide.Metal silicide resistivity is low, and metal silicide fermi level near silicon sheet
Fermi level is levied, driving force when being conducive to adjusting transmission transistor read operation and write operation.
Preferably, the first end of the first transmission transistor 120-1 is in source electrode and drain electrode, institute
The second end for stating the first transmission transistor 120-1 be source electrode and drain electrode in another；Described second passes
The first end of defeated transistor 120-2 is in source electrode and drain electrode, second transmission transistor
Second end of 120-2 be source electrode and drain electrode in another.
Preferably, in embodiments of the invention the first transmission transistor 120-1 and second transmission
Transistor 120-2 is restructural field-effect transistor.Fig. 2 shows a kind of exemplary restructural effect
Answer the structural representation of transistor device.The structure uses the heterogeneous nanometer of metal-semiconductor-metal
Cable architecture, and (correspond to first grid with two independent grids, programming grid and control gate
And second grid).Programming grid (i.e. first grid) is operated in N-shaped (electronics for selection transistor
It is conductive) or p-type (hole conduction) mode of operation, control gate (i.e. second grid) control into
The injection of electronics or hole needed for entering transistor channel, adjusts the conductance of transistor channel.Can
Reconstruct transistor device has extremely low Leakage Current, and driving force can be by control gate
Programming with programming grid is adjusted.
Fig. 3 shows a kind of exemplary restructural FET device when applied voltage works
Current characteristics figure.As shown in figure 3, when grid voltage is programmed and drain-source voltage is positive voltage, restructural
Field-effect transistor is operated in the mode of operation of N-shaped (electronic conduction), and off-state leakage current is extremely low.
When grid voltage is programmed and drain-source voltage is negative voltage, it is (empty that restructural field-effect transistor is operated in p-type
Cave is conductive) mode of operation, off-state leakage current is also extremely low.
The method for below describing to operate SRAM as shown in Figure 1.Wherein, Fig. 4 shows
The flow chart of the method 400 for SRAM keep operation a kind of according to an embodiment of the invention.
Fig. 5 shows the method 500 being read to SRAM a kind of according to an embodiment of the invention
Flow chart.Fig. 6 shows and a kind of according to an embodiment of the invention carries out write operation to SRAM
Method 600 flow chart.
In fig. 4, it is described that SRAM is carried out to keep the method 400 of operation to start from S410, wherein
By adjusting the level of the first wordline WL1, the transmission of the first transmission transistor 120-1 of selection and second is brilliant
The mode of operation of body pipe 120-2.Then, in S420, according to the first transmission transistor 120-1 and
The mode of operation of the second transmission transistor 120-2, by adjusting the level of the second wordline WL2,
Disconnect the first transmission transistor 120-1 and the second transmission transistor 120-2.
In method 400, by by the first transmission transistor 120-1 and second transmission transistor
120-2 disconnects so that in latch units 110 (that is, at first node A1 and Section Point A2)
The data of storage are isolated from the outside, so as to be maintained.
In Figure 5, the method 500 being read to SRAM starts from S510, wherein
By the level for adjusting the first wordline WL1 and the second wordline WL2 so that the first transmission transistor
120-1 and the second transmission transistor 120-2 is turned on, and causes the first transmission transistor 120-1
Driving force be weaker than the driving force and/or the second transmission transistor 120-2 of the first memory transistor
Driving force be weaker than the driving force of the second memory transistor.Then, in S520, by adjusting
The level of the first bit line BL and the second bit line BLB is saved, is read from the latch units 110 and is stored
Data.
In method 500, by by the first transmission transistor 120-1 and second transmission transistor
120-2 is turned on, enabling the data of storage are read from latch units 110.
In figure 6, the method 600 that write operation is carried out to SRAM starts from S610, wherein
By the level for adjusting the first wordline WL1 and the second wordline WL2 so that the first transmission transistor
120-1 and the second transmission transistor 120-2 is turned on, and causes the first transmission transistor 120-1
Driving force be better than the driving force and/or the second transmission transistor 120-2 of the first load transistor
Driving force be better than the driving force of the second load transistor.Then, in S620, by adjusting
The level of the first bit line BL and the second bit line BLB is saved, to be stored to the write-in of the latch units 110
Data.
In method 600, by by the first transmission transistor 120-1 and second transmission transistor
120-2 is turned on, enabling in latch units 110 (that is, first node A1 and Section Point A2
Place) the write-in data to be stored.
Above technical scheme is shown in order to clearer, hereafter figure 7 illustrates a kind of exemplary
The structural representation of 6 pipe SRAM, and the SRAM structures in Fig. 7 are combined in figs. 8-10 to above-mentioned
Keep, read, write operation is specifically described.
In the figure 7, six shown pipe SRAM structures include six transistors, wordline (WL1,
) and bit line (BL, BLB) WL2.6 transistors include two load transistors (on PMOS
Trombone slide P1, P2), two memory transistors (trombone slide N1, N2 under NMOS) and two transmission it is brilliant
Body pipe (restructural field-effect transistor R1, R2).Wherein tetra- transistors of P1, P2, N1 and N2
Corresponding to the latch units 110 in Fig. 1, R1 and R2 corresponds to the first transmission transistor in Fig. 1
120-1 and the second transmission transistor 120-2, node 1 and node 2 correspond to A1 and A2.R1 and R2
Include programming grid and control gate (i.e. first grid and second grid), programming grid is connected to wordline
WL1, control gate is connected to wordline WL2.Whole SRAM has a symmetry, wherein P1 and P2 with
And N1 and N2 constitutes bistable circuit, for latching one-bit digital signal.R1 and R2 are by restructural
Field-effect transistor is constituted, and they are being read out or during write operation by SRAM and periphery electricity
Road is turned on or off.
As shown in figs. 8 a and 8b, when the SRAM in Fig. 7 will keep data, to wordline WL1 and
WL2 applies appropriate programming gate voltage and control-grid voltage, so that it is guaranteed that transmission transistor is in closing
Disconnected state.As shown in Figure 8 A, when the current potential at node 1 is low level " 0 ", the electricity at node 2
Position is exactly high level " 1 ", and now wordline WL1 meets supply voltage Vdd, wordline WL2 ground connection (Gnd),
So that restructural field-effect transistor is turned off, reduce as the restructural field-effect of transmission transistor
The Leakage Current of transistor.As shown in Figure 8 B, when the current potential at node 1 is high level " 1 ", knot
Current potential at point 2 is exactly low level " 0 ", now wordline WL1 ground connection (Gnd), and wordline WL2 connects electricity
Source voltage Vdd, so that restructural field-effect transistor is turned off, reduces as transmission transistor
The Leakage Current of restructural field-effect transistor.
As shown in figure 9, when the SRAM in Fig. 7 is read, to wordline WL1 and WL2
Apply appropriate programming gate voltage and control-grid voltage, so that it is guaranteed that transmission transistor is turned on, make institute
To bit line BL, the inverted signal of the data for being stored is delivered to bit line BLB to the data transfer of storage, from
And, peripheral circuit reads data by BL and BLB.In the read operation of SRAM, wordline
(WL1 and WL2) and bit line (BL and BLB) are while meet supply voltage Vdd.As shown in figure 9,
Voltage at node 1 can be from " 0 " electricity due to the partial pressure of trombone slide N1 and transmission transistor R1 under NMOS
It is flat to be increased to a certain current potential.In order to avoid the change of data storage, should by wordline WL1 and
The appropriate programming gate voltage of WL2 applyings and control-grid voltage make the driving of transmission transistor R1 and R2
Ability is weaker than lower trombone slide N1 and N2.
As illustrated in figs. 10 a and 10b, when the SRAM in Fig. 7 carries out write operation, SRAM
Peripheral circuit deliver a voltage on BL and BLB as input, to wordline WL1 and WL2 apply
Appropriate programming gate voltage and control-grid voltage are so that it is guaranteed that transmission transistor conducting, data write-in
SRAM.In the write operation of SRAM, two wordline WL1 and WL2 connect supply voltage simultaneously
Vdd, and data are driven on bit line.As shown in Figure 10 A, the current potential at node 1 is low
During level " 0 ", the current potential at node 2 is exactly high level " 1 ", and the voltage at node 2 is due to PMOS
The partial pressure of upper trombone slide P2 and transmission transistor R2 can drop to a certain current potential from level"1".In order to add
The change of fast data storage, should apply appropriate programming gate voltage by wordline WL1 and WL2
It is stronger than upper trombone slide P2 with the driving force that control-grid voltage makes transmission transistor R2.As shown in Figure 10 B,
Appropriate programming gate voltage and control-grid voltage similarly can be applied by wordline WL1 and WL2
Make the driving force of transmission transistor R1 stronger than upper trombone slide P1.Therefore work as and row write is entered to this SRAM
When entering to operate, appropriate programming gate voltage and control gate should be applied by wordline WL1 and WL2
Voltage makes the driving force of transmission transistor R1 and R2 stronger than upper trombone slide P1 and P2.
In the present invention, " the first element is connected with the second element " or similar description can refer to the first element
Be directly connected to the second element, it is also possible to refer to the first element and the second element by other elements or in
Between medium be indirectly connected with.
Although below combined the preferred embodiments of the present invention show the present invention, this area
Technical staff will be understood that, without departing from the spirit and scope of the present invention, can be right
The present invention carries out various modifications, replacement and changes.Therefore, the present invention should not be come by above-described embodiment
Limit, and should be limited by appended claims and its equivalent.
Claims (20)
1. a kind of static RAM, including：
Latch units, are connected between first node and Section Point；
First transmission transistor, its first end is connected to the first bit line, and the second end is connected to described
One node, first grid is connected to the first wordline, and second grid is connected to the second wordline；And
Second transmission transistor, its first end is connected to the Section Point, and the second end is connected to
Two bit lines, first grid is connected to the first wordline, and second grid is connected to the second wordline.
2. static RAM according to claim 1, wherein, it is described latch it is single
Unit includes：
Memory module, including the first memory transistor and the second memory transistor, first storage
The first end of transistor is connected to the first node, and control end is connected to the Section Point, institute
The second end for stating the second memory transistor is connected to the Section Point, and control end is connected to described
The first end of one node, the second end of first memory transistor and second memory transistor
It is grounded.
3. static RAM according to claim 2, wherein, it is described latch it is single
Unit also includes：
Load blocks, including the first load transistor and the second load transistor, first load
The first end of transistor is connected to the first node, and control end is connected to the Section Point, institute
The second end for stating the second load transistor is connected to the Section Point, and control end is connected to described
The first end of one node, the second end of first load transistor and second load transistor
Connect supply voltage.
4. static RAM according to claim 2, wherein, it is described latch it is single
Unit also includes：
Load blocks, including first resistor and second resistance, the first end connection of the first resistor
To the first node, the second end of the second resistance is connected to the Section Point, described
Second end of one resistance and the first end of the second resistance connect supply voltage.
5. static RAM according to claim 1, wherein, described first passes
The first grid of defeated transistor and second transmission transistor is respectively used to selection first and transmits crystal
The mode of operation of pipe and the second transmission transistor,
The second grid of first transmission transistor and second transmission transistor is respectively used to
By controlling the first transmission transistor and second transmission brilliant in the mode of operation that first grid is selected
The conducting and disconnection of body pipe.
6. static RAM according to claim 1, wherein, the Working mould
Formula includes electronic conduction pattern and hole conduction pattern.
7. static RAM according to claim 1, wherein, described first passes
The channel material of defeated transistor and second transmission transistor is at least one of the following：Carbon is received
Mitron, intrinsic silicon, low-doped silicon, Graphene.
8. static RAM according to claim 1, wherein, described first passes
The material of the first end and the second end of defeated transistor and second transmission transistor is forbidden band center gold
Category compound.
9. static RAM according to claim 8, wherein, in the forbidden band
Centre metallic compound is metal silicide.
10. according to the static RAM that any one of claim 1-9 is described, wherein,
The first end of first transmission transistor is in source electrode and drain electrode, and described first passes
Second end of defeated transistor be source electrode and drain electrode in another；
The first end of second transmission transistor is in source electrode and drain electrode, and described second passes
Second end of defeated transistor be source electrode and drain electrode in another.
11. according to any one of claim 2-4 described static RAM, wherein,
The first end of first memory transistor is in source electrode and drain electrode, and described first deposits
Store up transistor the second end be source electrode and drain electrode in another；
The first end of second memory transistor is in source electrode and drain electrode, and described second deposits
Store up transistor the second end be source electrode and drain electrode in another.
12. static RAMs according to claim 3, wherein,
The first end of first load transistor is in source electrode and drain electrode, and described first is negative
Carry transistor the second end be source electrode and drain electrode in another；
The first end of second load transistor is in source electrode and drain electrode, and described second is negative
Carry transistor the second end be source electrode and drain electrode in another.
13. according to any one of claim 2-4 described static RAM, wherein,
First memory transistor and second memory transistor are nmos pass transistors.
14. static RAMs according to claim 3, wherein,
First load transistor and second load transistor are PMOS transistors.
15. static RAMs according to claim 1, wherein,
By adjusting the level of the first wordline and the second wordline, enable to the first transmission transistor and
Second transmission transistor disconnects or turns on.
16. according to any one of claim 2-4 described static RAM, wherein,
By adjusting the level of the first wordline and the second wordline, enable to the first transmission transistor and
Second transmission transistor is turned on, and causes that the driving force of first transmission transistor is weaker than the
The driving force of the driving force of one memory transistor and/or the second transmission transistor is weaker than second and deposits
Store up the driving force of transistor.
17. static RAMs according to claim 3, wherein,
By adjusting the level of the first wordline and the second wordline, enable to the first transmission transistor and
Second transmission transistor is turned on, and causes that the driving force of first transmission transistor is better than the
It is negative that the driving force of the driving force of one load transistor and/or the second transmission transistor is better than second
Carry the driving force of transistor.
18. is a kind of to according to any one of claim 1-17 described static random access memory
Device carries out the method for keeping operation, including：
By adjusting the level of the first wordline, the first transmission transistor and the second transmission transistor are selected
Mode of operation；
According to the first transmission transistor and the mode of operation of second transmission transistor, by regulation
The level of the second wordline, disconnects first transmission transistor and second transmission transistor.
19. is a kind of to according to any one of claim 1-17 described static random access memory
The method that device is read, including：
By the level for adjusting the first wordline and the second wordline so that the first transmission transistor and second
Transmission transistor is turned on, and causes that the driving force of first transmission transistor is weaker than first and deposits
It is brilliant that the driving force of the driving force and/or the second transmission transistor of storing up transistor is weaker than the second storage
The driving force of body pipe；And
By adjusting the level of the first bit line and the second bit line, read from the latch units and stored
Data.
20. is a kind of to according to any one of claim 1-17 described static random access memory
The method that device carries out write operation, including：
By the level for adjusting the first wordline and the second wordline so that the first transmission transistor and second
Transmission transistor is turned on, and causing the driving force of first transmission transistor, to be better than first negative
It is brilliant that the driving force of the driving force and/or the second transmission transistor that carry transistor is better than the second load
The driving force of body pipe；And
By adjusting the level of the first bit line and the second bit line, to be stored to latch units write-in
Data.
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| CN201510931662.5A CN106887249A (en) | 2015-12-15 | 2015-12-15 | Static RAM and its operating method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766493A (en) * | 2018-05-23 | 2018-11-06 | 上海华力微电子有限公司 | A kind of adjustable WLUD applied to SRAM reads and writes auxiliary circuit |
| CN111161775A (en) * | 2019-11-26 | 2020-05-15 | 华东师范大学 | Static random access memory |
| CN116206643A (en) * | 2022-07-25 | 2023-06-02 | 北京超弦存储器研究院 | Dynamic random access memory unit, memory device and reading method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103201797A (en) * | 2010-11-04 | 2013-07-10 | 高通股份有限公司 | Stable SRAM bitcell design utilizing independent gate FinFET |
| JP5278971B2 (en) * | 2010-03-30 | 2013-09-04 | 独立行政法人産業技術総合研究所 | SRAM device |
| CN104882444A (en) * | 2014-02-27 | 2015-09-02 | 台湾积体电路制造股份有限公司 | Structure and method for finfet sram |
-
2015
- 2015-12-15 CN CN201510931662.5A patent/CN106887249A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5278971B2 (en) * | 2010-03-30 | 2013-09-04 | 独立行政法人産業技術総合研究所 | SRAM device |
| CN103201797A (en) * | 2010-11-04 | 2013-07-10 | 高通股份有限公司 | Stable SRAM bitcell design utilizing independent gate FinFET |
| CN104882444A (en) * | 2014-02-27 | 2015-09-02 | 台湾积体电路制造股份有限公司 | Structure and method for finfet sram |
Non-Patent Citations (3)
| Title |
|---|
| JUNCHENG WANG等: "Invetigation of reconfigurable silicon nanowire Schottky Barrier transistors-based logic gate circuits and SRAM cell", 《2015 SILICON NANOELECTRONICS WORKSHOP(SNW)》 * |
| M. DE MARCHI等: "Polarity control in Double-Gate, Gate-all-around vertically stacked silicon nanowire FETs", 《2012 INTERNATIONAL ELECTRON DEVICES MEETING》 * |
| 毛永毅等: "《数字系统设计基础》", 31 May 2010 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766493A (en) * | 2018-05-23 | 2018-11-06 | 上海华力微电子有限公司 | A kind of adjustable WLUD applied to SRAM reads and writes auxiliary circuit |
| CN108766493B (en) * | 2018-05-23 | 2021-04-02 | 上海华力微电子有限公司 | Adjustable WLUD read-write auxiliary circuit applied to SRAM |
| CN111161775A (en) * | 2019-11-26 | 2020-05-15 | 华东师范大学 | Static random access memory |
| CN116206643A (en) * | 2022-07-25 | 2023-06-02 | 北京超弦存储器研究院 | Dynamic random access memory unit, memory device and reading method |
| CN116206643B (en) * | 2022-07-25 | 2024-03-15 | 北京超弦存储器研究院 | Dynamic random access memory unit, memory device and reading method |
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Application publication date: 20170623 |