CN111161775A - Static random access memory - Google Patents
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- CN111161775A CN111161775A CN201911170922.6A CN201911170922A CN111161775A CN 111161775 A CN111161775 A CN 111161775A CN 201911170922 A CN201911170922 A CN 201911170922A CN 111161775 A CN111161775 A CN 111161775A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
The invention discloses a static random access memory, which comprises a pull-up transistor, a transmission transistor and a pull-down transistor. The pull-up transistor and the transmission transistor comprise a channel, a source end and a drain end which are arranged at two sides of the channel, a control grid and a polar grid which are arranged at the outer side of a grid oxide, and an electrically isolated side wall which is arranged between the control grid and the source end; the pull-down transistor comprises a channel, a source end and a drain end which are arranged on two sides of the channel, a control grid and a polarity grid which are arranged on the outer side of a grid oxide, and an electrically isolated side wall which is arranged between the control grid and the drain end. The invention utilizes the difference of the asymmetric reconfigurable field effect transistor structure to achieve the inconsistency of conduction currents, realizes higher reading static noise tolerance and writing capability required by the static random access memory unit, effectively improves the reading and writing stability of the static random access memory unit, and further improves the performance of the static memory circuit.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a novel static random access memory.
Background
With the continuous progress of semiconductor technology, the deep nano technology era is entered, and a fin field effect transistor (FinFET) becomes one of the core devices of the deep nano technology by virtue of its excellent gate control capability. Research on the application of finfets as core devices is also widely spread, and the memory circuit has the most promising application prospect.
However, in the case of a FinFET, this characteristic of the FinFET is very significant for a Static Random Access Memory (SRAM) due to the fact that the width-to-length ratio of the device cannot be arbitrarily adjusted. As the process dimensions of integrated circuits shrink to near nanometer scale, moore's law faces significant challenges, reaching its physical limits in the next decade. Therefore, it is necessary to develop new devices with higher flexibility and apply them to solve the design contradiction of six-transistor SRAM cells. In recent years, the concept of Reconfigurable Field Effect Transistors (RFETs) has been proposed and rapidly became a focus of research, and device-level reconfigurability promises to realize more complex and lower device count circuits. Many novel structures have been proposed to achieve reconfigurability of the device. In the reconfigurable field effect transistors, the polarity of a device channel carrier is adjusted by applying different voltage biases to the double gates, so that the rotation of an n-type device and a p-type device is realized, and meanwhile, the electrical doping characteristics of the reconfigurable transistor bring great convenience in the manufacturing process. However, when the conventional symmetric reconfigurable field effect transistor is simply used and applied to the SRAM, the read/write contradiction cannot be solved well because the pass transistor and the pull-down transistor have the same conductivity. In past research, we found that the existence of the double gate for the RFET can dynamically adjust the schottky barrier between the source and drain terminals, thereby selecting the type of on-carriers and influencing the tunneling probability of the carriers. Therefore, the reconfigurable field effect transistor with the asymmetric structure can not only realize the optimization of the device performance, but also bring great improvement on the performance by utilizing the inconsistency of the conduction current and flexibly applying the reconfigurable field effect transistor to a microcircuit unit.
Based on the research of RFET, it is necessary to design and realize a 6T-SRAM with excellent performance for SRAM, if the read stability is enhanced, the gain factor β of the transmission transistorPGA gain factor β smaller than the pull-down transistor is requiredPDAnd to enhance the write capability of the six-transistor SRAM cell, the gain factor β of the pass transistorPGA gain factor β greater than the pull-up transistor is requiredPUWithin reasonable limits, β is satisfiedPD>βPG>βPUThe six-transistor SRAM cell with high read stability and high write capability can be obtained simultaneously. Therefore, in order to improve the performance of the memory circuit, the six-transistor SRAM cell needs to adopt a lower conductivity pass transistor to improve the read stability, and simultaneously needs a higher conductivity pass transistor to enhance the write capability.
Disclosure of Invention
The invention aims to provide a new storage circuit structure of a six-tube SRAM based on a reconfigurable field effect transistor by utilizing different conduction currents caused by the asymmetric characteristic of an asymmetric reconfigurable field effect transistor.
The specific technical scheme for realizing the purpose of the invention is as follows:
a static random access memory, comprising: the reconfigurable field effect transistor comprises a first pull-up transistor PU1, a second pull-up transistor PU2, a first transmission transistor PG1, a second transmission transistor PG2, a first pull-down transistor PD1 and a second pull-down transistor PD2, wherein the first pull-up transistor PU1, the second pull-up transistor PU2, the first transmission transistor PG1 and the second transmission transistor PG2 are asymmetric reconfigurable field effect transistors with side walls between source ends and control gates; the first pull-down transistor PD1 and the second pull-down transistor PD2 are asymmetric reconfigurable field effect transistors with side walls between drain terminals and polar gates; the first pull-up transistor PU1 and the first pull-down transistor PD1 form a first inverter, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter; the output end of the first inverter forms a first storage node, and the output end of the second inverter forms a second storage node; the first inverter is cross-coupled with a second inverter; wherein:
the source end of the first transfer transistor PG1 is connected with the first storage node, the polarity gate is connected with a power supply VDD, the control gate is connected with a bit line WL, and the drain end is connected with a first bit line BL;
a source terminal of the second pass transistor PG2 is connected to the second storage node, a polarity gate is connected to a power supply VDD, a control gate is connected to a bit line WL, and a drain terminal is connected to a second bit line BLB;
the first pull-up transistor PU1 is connected with the drain terminal of the first pull-down transistor PD1 to form the first storage node; the control gate of the first pull-up transistor PU1 is connected with the control gate of the first pull-down transistor PD1 to a node; the polarity gate of the first pull-up transistor PU1 is connected to ground; the polarity gate of the first pull-down transistor PD1 is connected to a power supply VDD;
the second pull-up transistor PU2 is connected to the drain terminal of the second pull-down transistor PD2 to form the second storage node; the control gate of the second pull-up transistor PU2 and the control gate of the second pull-down transistor PD2 are connected to a node; the polarity gate of the second pull-up transistor PU2 is connected to ground; the polarity gate of the second pull-down transistor PD2 is connected to the power supply VDD.
The asymmetric reconfigurable field effect transistor with the side wall between the source end and the control grid comprises:
a channel;
the drain end is arranged at one end of the channel, and the source end is arranged at the other end of the channel;
a gate oxide disposed outside the channel; a control gate and a polarity gate respectively disposed outside the gate oxide;
and the electrical isolation side wall is arranged between the control grid and the source end.
The asymmetric reconfigurable field effect transistor with the side wall between the drain end and the polar grid comprises:
a channel;
the drain end is arranged at one end of the channel, and the source end is arranged at the other end of the channel;
a gate oxide disposed outside the channel; a control gate and a polarity gate respectively disposed outside the gate oxide;
and the electrical isolation side wall is arranged between the polar grid and the drain terminal.
The data writing of the static random access memory comprises the following steps:
step 1: when data "0" or "1" needs to be written, the bit line BL is set to be at a low level or a high level, the bit line BLB is set to be at a high level or a low level, and a potential difference exists at both sides of the source terminals and the drain terminals of the first transfer transistor PG1 and the second transfer transistor PG 2;
step 2: current flows from the source terminal of the first pull-up transistor PU1 or the second pull-up transistor PU2 to the first pass transistor PG1 or the second pass transistor PG2 and the first bit line BL or the second bit line BLB;
and step 3: the first storage node becomes a low level or a high level, and the second storage node becomes a high level or a low level.
The data reading of the static random access memory comprises the following steps:
step 1: setting a first bit line BL and a second bit line BLB to be at a high level; when the first storage node is at a low level or a high level and the second storage node is at a high level or a low level, there is no potential difference between the source terminal and the drain terminal of the second pass transistor PG2 or the first pass transistor PG 1;
step 2: current flows from the drain terminal of the first pass transistor PG1 or the second pass transistor PG2 to the first pass transistor PG1 or the second pass transistor PG2 and the first pull-down transistor PD1 or the second pull-down transistor PD2 from the first bit line BL or the second bit line BLB;
and step 3: the first bit line BL or the second bit line BLB becomes a low level, and the second bit line BLB or the first bit line BL remains a high level.
The polarity grid of an SRAM unit pull-up transistor consisting of asymmetric reconfigurable field effect transistors keeps a low level '0' state all the time, the control grid of the SRAM unit pull-up transistor is connected with the control grid of a pull-down transistor, the source end of the SRAM unit pull-down transistor is connected with a power supply VDD, and the drain end of the SRAM unit pull-up transistor is connected with the drain end of the pull-down transistor and the source end of a transmission transistor; for the pull-down transistor, the drain terminal of the pull-down transistor is connected with the drain terminal of the pull-up transistor and the drain terminal of the transmission transistor, the source terminal of the pull-down transistor is connected with the ground and is set to be in a low level, and the polarity grid of the pull-down transistor always keeps in a high level state; for the pass transistor, its drain terminal is connected to the drain terminal of the pull-up transistor and the drain terminal of the pull-down transistor, its source terminal is connected to the bit line "BL" or "BLB", its control gate is connected to the bit line "WL", and the polarity gate will always remain at the high level VDD. Wherein:
the pull-up transistor and the transmission transistor comprise a channel, a drain end arranged at one end of the channel, a source end arranged at the other end of the channel, a grid oxide arranged outside the channel, a control grid and a polar grid which are respectively arranged outside the grid oxide, and an electrical isolation side wall arranged between the control grid and the source end; the pull-down transistor comprises a channel, a drain end arranged at one end of the channel, a source end arranged at the other end of the channel, a grid oxide arranged outside the channel, a control grid and a polarity grid which are respectively arranged outside the grid oxide, and an electrical isolation side wall arranged between the control grid and the source end. Wherein:
the channel is a silicon nanowire, a germanium-silicon nanowire, a gallium arsenide nanowire, a gallium nitride nanowire, an indium phosphide nanowire or a carbon nanotube;
the grid oxide is silicon dioxide, hafnium oxide or silicon oxynitride deposited and wrapped on the outer side of the channel;
the drain end or the source end extending towards the interior of the channel is titanium silicide, nickel silicide, cobalt silicide, titanium nitride, tantalum nitride or a combination of a plurality of titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride deposited at the two ends or the interior of the channel;
the control grid and the polar grid are aluminum, copper, polysilicon or titanium nitride which are deposited at two ends of the channel and are formed by photoetching and etching the outer side of the grid oxide;
the side wall is silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass or borophosphosilicate glass deposited on the outer sides of two ends of the channel and at one end of the control grid and the polar grid.
For the conventional SRAM device, the stability of the read-write state is regulated by the conduction capability of each transistor, when the read operation is involved, the conduction current capability of a transmission transistor is required to be weaker than that of a pull-down transistor so as to obtain higher read stability, and when the write operation is involved, the conduction capability of a pull-up transistor is required to be weaker than that of the transmission transistor, namely βPD>βPG>βPU. The problem to be solved by the invention is to utilize the difference of the asymmetric reconfigurable field effect transistor structure to achieve the inconsistency of conduction currents, thereby realizing higher reading static noise tolerance and writing capability required by the SRAM memory cell, effectively improving the reading and writing stability of the SRAM, and further improving the performance of the static memory circuit.
Drawings
FIG. 1 is a schematic diagram of a pull-up transistor and pass transistor according to the present invention;
FIG. 2 is a top view of FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along line A-A of FIG. 1;
FIG. 4 is a schematic diagram of a pull-down transistor according to the present invention;
FIG. 5 is a top view of FIG. 4;
FIG. 6 is a schematic cross-sectional view taken along line A-A of FIG. 4;
FIG. 7 is a schematic structural view of the present invention;
FIG. 8 is a graph comparing ID-VG1 of individual tubes of the present invention;
fig. 9 is a comparison graph of ID-VG1 for each single tube based on a conventional symmetrical structure.
Detailed Description
The invention is described in detail below with reference to the figures and examples.
Referring to fig. 7, the present invention includes: the reconfigurable field effect transistor comprises a first pull-up transistor PU1, a second pull-up transistor PU2, a first transmission transistor PG1, a second transmission transistor PG2, a first pull-down transistor PD1 and a second pull-down transistor PD2, wherein the first pull-up transistor PU1, the second pull-up transistor PU2, the first transmission transistor PG1 and the second transmission transistor PG2 are asymmetric reconfigurable field effect transistors with side walls between source ends and control gates; the first pull-down transistor PD1 and the second pull-down transistor PD2 are asymmetric reconfigurable field effect transistors with side walls between drain terminals and polar gates; the first pull-up transistor PU1 and the first pull-down transistor PD1 form a first inverter, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter; the output of the first inverter forms a first storage node 8 and the output of the second inverter forms a second storage node 11; the first inverter is cross-coupled with a second inverter; wherein:
the source end of the first transfer transistor PG1 is connected to the first storage node 8, the polarity gate is connected to the power supply VDD, the control gate is connected to the bit line WL, and the drain end is connected to the first bit line BL;
a source terminal of the second pass transistor PG2 is connected to the second storage node 11, a polarity gate is connected to a power supply VDD, a control gate is connected to a bit line WL, and a drain terminal is connected to a second bit line BLB;
the first pull-up transistor PU1 is connected with the drain terminal of the first pull-down transistor PD1 to form the first storage node 8; the control gate of the first pull-up transistor PU1 and the control gate of the first pull-down transistor PD1 are connected to the node 9; the polarity gate of the first pull-up transistor PU1 is connected to ground; the polarity gate of the first pull-down transistor PD1 is connected to a power supply VDD;
the second pull-up transistor PU2 is connected to the drain terminal of the second pull-down transistor PD2 to form the second storage node 11; the control gate of the second pull-up transistor PU2 and the control gate of the second pull-down transistor PD2 are connected to the node 10; the polarity gate of the second pull-up transistor PU2 is connected to ground; the polarity gate of the second pull-down transistor PD2 is connected to the power supply VDD.
Referring to fig. 1 to 3, the asymmetric reconfigurable field effect transistor including a side wall between a source terminal and a control gate of the present invention includes:
a channel 1;
a drain terminal 3 arranged at one end of the channel 1 and a source terminal 4 arranged at the other end of the channel 1;
a gate oxide 2 disposed outside the channel 1; a control gate 6 and a polarity gate 5 respectively disposed outside the gate oxide 2;
an electrically isolating side wall 7 is provided between the control gate 6 and the source terminal 4.
Referring to fig. 4 to 6, the asymmetric reconfigurable field effect transistor including the sidewall between the drain terminal and the polar gate of the present invention includes:
a channel 1;
a drain terminal 3 arranged at one end of the channel 1 and a source terminal 4 arranged at the other end of the channel 1;
a gate oxide 2 disposed outside the channel 1; a control gate 6 and a polarity gate 5 respectively disposed outside the gate oxide 2;
and an electrical isolation sidewall 7 disposed between the polar gate 5 and the drain terminal 3.
The pull-up transistors PU1 and PU2 and the transmission transistors PG1 and PG2 are asymmetric reconfigurable field effect transistors with side walls between source ends and control gates, and the pull-down transistors PD1 and PD2 are asymmetric reconfigurable field effect transistors with side walls between drain ends and polar gates. For the pull-up transistor, the polarity gate G2 will always keep a low level "0" state, and its control gate G1 is connected to the pull-down transistor control gate G1, its source terminal is connected to the power VDD, and its drain terminal is connected to the drain terminal of the pull-down transistor and the source terminal of the pass transistor; for the pull-down transistor, the drain terminal of the pull-down transistor is connected with the drain terminal of the pull-up transistor and the drain terminal of the transmission transistor, the source terminal of the pull-down transistor is connected with the ground and is set to be in a low level, and the polarity grid G2 of the pull-down transistor keeps in a high level state all the time; for the pass transistor, its drain terminal is connected to the drain terminal of the pull-up transistor and the drain terminal of the pull-down transistor, its source terminal is connected to the bit line "BL" or "BLB", its control gate G1 is connected to the bit line "WL", and the polarity gate G2 will always remain high VDD.
When the static random access memory is used for writing operation, the method comprises the following steps:
step 1: when data "0" or "1" needs to be written, the bit line BL is set to be at a low level or a high level, the bit line BLB is set to be at a high level or a low level, and a potential difference exists at both sides of the source terminals and the drain terminals of the first transfer transistor PG1 and the second transfer transistor PG 2;
step 2: current flows from the source terminal of the first pull-up transistor PU1 or the second pull-up transistor PU2 to the first pass transistor PG1 or the second pass transistor PG2 and the first bit line BL or the second bit line BLB;
and step 3: the first storage node 8 becomes a low level or a high level, and the second storage node 11 becomes a high level or a low level.
When the static random access memory is used for reading, the method comprises the following steps:
step 1: setting a first bit line BL and a second bit line BLB to be at a high level; when the first storage node 8 is at a low level or a high level and the second storage node 11 is at a high level or a low level, there is no potential difference between the source terminal and the drain terminal of the second pass transistor PG2 or the first pass transistor PG 1;
step 2: current flows from the drain terminal of the first pass transistor PG1 or the second pass transistor PG2 to the first pass transistor PG1 or the second pass transistor PG2 and the first pull-down transistor PD1 or the second pull-down transistor PD2 from the first bit line BL or the second bit line BLB;
and step 3: the first bit line BL or the second bit line BLB becomes a low level, and the second bit line BLB or the first bit line BL remains a high level.
Referring to FIGS. 8 to 9, as shown in FIG. 8, the pull-up transistor current (1.74E-5A) at the turn-on time of the device can be seen from the comparison graph of ID-VG1 of each single transistor of six-transistor SRAM built based on asymmetric reconfigurable transistors>Pass transistor current (5.69E-7A)>Pull-down transistor current (3.18E-7A), condition β for optimization of SRAM cellPD>βPG>βPUFor the conventional symmetric transistor, as shown in FIG. 9, the pull-up transistor current (2.33E-7A) at the turn-on time of the device is approximately equal to the pass transistor current (4.09E-7A) and the pull-down transistor current (3.18E-7A), and the condition β for optimizing the SRAM memory cell is not satisfiedPD>βPG>βPUCompared with the symmetrical reconfigurable field effect transistor, the novel device is characterized in that a side wall expansion area is added at a source end/drain end, when the saturation current of the drain end at a high level is compared with the saturation current of the source end at a high level, IDS and ISD are found to be unequal in size, because when high voltage is applied to one side with the side wall expansion area, the extra barrier (EPB) existing in the expansion area is remarkably reduced under the action of the high voltage, and by utilizing the characteristic, the asymmetrical reconfigurable field effect transistor with the side wall expansion area is placed at different positions in a six-tube SRAM, so that β is formedPD>βPG>βPU。
The invention utilizes the difference of the asymmetric reconfigurable field effect transistor structure to achieve the inconsistency of conduction currents, realizes higher reading static noise tolerance and writing capability required by the static random access memory unit, effectively improves the reading and writing stability of the static random access memory unit, and further improves the performance of the static memory circuit.
Claims (5)
1. A static random access memory, comprising: the reconfigurable field effect transistor comprises a first pull-up transistor PU1, a second pull-up transistor PU2, a first transmission transistor PG1, a second transmission transistor PG2, a first pull-down transistor PD1 and a second pull-down transistor PD2, wherein the first pull-up transistor PU1, the second pull-up transistor PU2, the first transmission transistor PG1 and the second transmission transistor PG2 are asymmetric reconfigurable field effect transistors with side walls between source ends and control gates; the first pull-down transistor PD1 and the second pull-down transistor PD2 are asymmetric reconfigurable field effect transistors with side walls between drain terminals and polar gates; the first pull-up transistor PU1 and the first pull-down transistor PD1 form a first inverter, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter; the output end of the first inverter forms a first storage node (8), and the output end of the second inverter forms a second storage node (11); the first inverter is cross-coupled with a second inverter; wherein:
the source end of the first transmission transistor PG1 is connected with the first storage node (8), the polarity grid is connected with a power supply VDD, the control grid is connected with a bit line WL, and the drain end is connected with a first bit line BL;
the source end of the second pass transistor PG2 is connected to the second storage node (11), the polarity gate is connected to a power supply VDD, the control gate is connected to a bit line WL, and the drain end is connected to a second bit line BLB;
the first pull-up transistor PU1 is connected with the drain terminal of the first pull-down transistor PD1 to form the first storage node (8); the control gate of the first pull-up transistor PU1 is connected to the control gate of the first pull-down transistor PD1 at node (9); the polarity gate of the first pull-up transistor PU1 is connected to ground; the polarity gate of the first pull-down transistor PD1 is connected to a power supply VDD;
the second pull-up transistor PU2 is connected with the drain terminal of the second pull-down transistor PD2 to form the second storage node (11); the control gate of the second pull-up transistor PU2 and the control gate of the second pull-down transistor PD2 are connected to a node (10); the polarity gate of the second pull-up transistor PU2 is connected to ground; the polarity gate of the second pull-down transistor PD2 is connected to the power supply VDD.
2. The SRAM of claim 1, wherein the asymmetric reconfigurable FET with a spacer between the source terminal and the control gate comprises:
a channel (1);
a drain terminal (3) arranged at one end of the channel (1) and a source terminal (4) arranged at the other end of the channel (1);
a gate oxide (2) disposed outside the channel (1); a control gate (6) and a polarity gate (5) respectively disposed outside the gate oxide (2);
and the electrical isolation side wall (7) is arranged between the control grid (6) and the source end (4).
3. The SRAM of claim 1 wherein the asymmetric reconfigurable FET with a spacer between the drain and the polarity gate comprises:
a channel (1);
a drain terminal (3) arranged at one end of the channel (1) and a source terminal (4) arranged at the other end of the channel (1);
a gate oxide (2) disposed outside the channel (1); a control gate (6) and a polarity gate (5) respectively disposed outside the gate oxide (2);
and the electrical isolation side wall (7) is arranged between the polar grid (5) and the drain terminal (3).
4. The static random access memory according to claim 1, wherein the data writing thereof comprises the steps of:
step 1: when data "0" or "1" needs to be written, the bit line BL is set to be at a low level or a high level, the bit line BLB is set to be at a high level or a low level, and a potential difference exists at both sides of the source terminals and the drain terminals of the first transfer transistor PG1 and the second transfer transistor PG 2;
step 2: current flows from the source terminal of the first pull-up transistor PU1 or the second pull-up transistor PU2 to the first pass transistor PG1 or the second pass transistor PG2 and the first bit line BL or the second bit line BLB;
and step 3: the first storage node (8) becomes low level or high level, and the second storage node (11) becomes high level or low level.
5. The static random access memory according to claim 1, wherein its data reading comprises the steps of:
step 1: setting a first bit line BL and a second bit line BLB to be at a high level; when the first storage node (8) is at a low level or a high level and the second storage node (11) is at a high level or a low level, no potential difference exists between the source terminal and the drain terminal of the second transmission transistor PG2 or the first transmission transistor PG 1;
step 2: current flows from the drain terminal of the first pass transistor PG1 or the second pass transistor PG2 to the first pass transistor PG1 or the second pass transistor PG2 and the first pull-down transistor PD1 or the second pull-down transistor PD2 from the first bit line BL or the second bit line BLB;
and step 3: the first bit line BL or the second bit line BLB becomes a low level, and the second bit line BLB or the first bit line BL remains a high level.
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