CN110197680B - MRAM memory chip adopting fully-depleted silicon-on-insulator FD-SOI field effect transistor - Google Patents

MRAM memory chip adopting fully-depleted silicon-on-insulator FD-SOI field effect transistor Download PDF

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CN110197680B
CN110197680B CN201810157448.2A CN201810157448A CN110197680B CN 110197680 B CN110197680 B CN 110197680B CN 201810157448 A CN201810157448 A CN 201810157448A CN 110197680 B CN110197680 B CN 110197680B
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potential
back gate
field effect
mram
effect transistor
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CN110197680A (en
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叶力
戴瑾
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Shanghai Information Technologies Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

Disclosure of the inventionThe field effect transistor of each MRAM storage unit of the MRAM storage array chip adopts a fully depleted silicon-on-insulator (FD-SOI) field effect transistor and comprises an individual potential control unit. Value V of back grid potential V _ body of FD-SOI field effect transistor in working statebAnd can be flexibly configured to any value within an appropriate range. When the design method writes the 0 direction: the source line potential V _ SL is set to V0+VbThe bit line potential V _ BL is set to 0, and the gate (word line) potential V _ G is set to Vdd+Vb. When writing the 1 direction: the source line potential V _ SL is set to VbThe bit line potential V _ BL is set to V1+VbThe gate (word line) potential V _ G is set to Vdd+Vb. The invention can eliminate the latch-up effect of the bulk silicon field effect transistor, adjust the back grid potential and solve the problem of insufficient driving current provided by a writing circuit.

Description

MRAM memory chip adopting fully-depleted silicon-on-insulator FD-SOI field effect transistor
Technical Field
The invention belongs to the technical field of semiconductor chip storage, and particularly relates to an MRAM (magnetic random access memory) storage chip adopting a fully depleted silicon-on-insulator (FD-SOI) field effect transistor.
Background
Magnetic Random Access Memory (MRAM) is an emerging non-volatile memory technology. It has high read-write speed and high integration and can be written repeatedly for unlimited times. MRAM can be read and written randomly as fast as SRAM/DRAM, and can also permanently retain data after power-off as Flash memory.
MRAM has very good economy and performance, and its unit capacity occupies silicon area which is much more advantageous than SRAM, and also more advantageous than NOR Flash which is often used in such chips, and much more advantageous than embedded NOR Flash. The MRAM read-write time delay is close to the best SRAM, and the power consumption is the best in various memories and storage technologies; MRAM is compatible with standard CMOS semiconductor technology, DRAM and Flash are incompatible with standard CMOS semiconductor technology; the MRAM can also be integrated with the logic circuit in one chip.
MRAM is based on MTJ (magnetic tunnel junction) architecture. Consisting of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1: the lower layer of ferromagnetic material is a reference layer with a fixed magnetization direction and the upper layer of ferromagnetic material is a memory layer with a variable magnetization direction, which may be parallel or anti-parallel to the fixed magnetization layer. Due to quantum physical effects, current can pass through the middle tunnel barrier layer, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The former case has a low resistance and the latter case has a high resistance.
The process of reading the MRAM is to measure the resistance of the MTJ. Writing MRAM uses a relatively new STT-MRAM technology to write through MTJs using a stronger current than reading. A bottom-up current places the variable magnetization layer in a direction parallel to the fixed layer, and a top-down circuit places it in an anti-parallel direction.
As shown in fig. 2, each memory cell of the MRAM is composed of an MTJ and a field effect transistor. Each memory cell needs to be connected to three wires:
● the gate of the FET is connected to the Word Line of the chip to turn on or off the cell;
● the Source electrode of the field effect transistor is connected to Source Line;
● the drain of the field effect transistor is connected to one end of the MTJ, and the other end of the MTJ is connected to the Bit Line;
● the back gate body potential body of the FET is connected to ground.
A typical MRAM memory array arrangement is shown in fig. 3 (only a 2 x 2 matrix is representatively shown). The word line is vertical to the source line and the bit line, and the source line and the bit line are parallel to each other. Write drive current and read current are generated by a voltage difference between a source line and a bit line, and read-write switch control is realized through a word line. The transistor connected with the MTJ can adopt a CMOS field effect transistor or a fully depleted silicon-on-insulator SOI field effect transistor.
The MTJ memory cell requires two directions of current to implement the writing of 0, 1, where writing 0 corresponds to a transition from a low resistance state to a high resistance state and writing 1 corresponds to a transition from a high resistance state to a low resistance state. When writing 1, BL is at high potential and SL is at low potential. When writing 0, BL is at low potential and SL is at high potential. Under the same condition of V _ g, V _ gs when 1 is written is larger than V _ gs when 0 is written, so that the field effect transistor can provide asymmetry of driving current in two directions, and the current when 1 is written is larger than that when 0 is written. MTJ memory cell, on the other handThe characteristic of (1) is that less current is required to write the 1, which results in a mismatch between the current supplied by the circuit and the required drive current. One solution to this problem is to increase the V _ g (wl) voltage applied to the fet when a larger driving current is required, i.e., to use a higher V _ g-Vdd+VbAnd simultaneously increasing the bias voltage of the back gate Body potential Body to V to relieve the pressure of the MOS tube while increasing V _ gb。
The prior art uses bulk silicon fets as shown in fig. 4. The latch-up effect is generated by increasing the bias voltage of the back gate Body potential Body under the circuit working state. The current is generated in the back grid of the back grid once the potential of the back grid body of the bulk silicon field effect transistor is raised, and two groups of source, drain and back grids of two adjacent NMOS and PMOS transistors can form a group of NPN and PNP triode loops to carry out positive feedback amplification on the current of the back grid, so that the field effect transistor cannot normally work and even has the risk of burning. In addition, when the back gate potential is raised, if the source or the drain is at 0 potential, the forward conduction of the PN junction between the source or the drain and the back gate can be generated, so that the field effect transistor cannot normally operate.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an MRAM memory chip using fully depleted silicon-on-insulator FD-SOI fet, which can eliminate the latch-up effect of bulk silicon fet, adjust the bulk back gate potential, and solve the problem of insufficient driving current provided by the write circuit.
In order to achieve the above object, the present invention provides an MRAM memory chip using fully depleted silicon-on-insulator FD-SOI field effect transistors, where the field effect transistor of each MRAM memory cell of the MRAM memory chip uses fully depleted silicon-on-insulator FD-SOI field effect transistors; the MRAM chip also comprises an individual potential control unit for regulating and controlling the back gate body potential of the memory chip.
The invention also provides a design method for adjusting the back gate electrode body potential by adopting the MRAM memory chip of the fully depleted silicon-on-insulator FD-SOI field effect transistor, which comprises the following specific design modes:
the specific design mode of the method is as follows:
the back gate electrode potential is set to V _ body ═ VbAnd in the read operation, take Vb＝0。
Further, the specific method for adjusting the back gate body potential of the MRAM memory chip is as follows:
when writing the 0 direction:
the source line potential V _ SL is set to V0+VbThe bit line potential V _ BL is set to 0, and the gate (word line) potential V _ G is set to Vdd+Vb(ii) a Wherein, V0+VbIs a voltage signal, V, that the read driving circuit needs to generate and apply to the source linedd+VbThe read driving circuit needs to generate and apply a voltage signal, V, to the gatebIs the voltage signal to be applied to Body;
when writing the 1 direction:
the source line potential V _ SL is set to VbThe bit line potential V _ BL is set to V1+VbThe gate (word line) potential V _ G is set to Vdd+Vb(ii) a Wherein, V1+VbIs the voltage signal that the read driver circuit needs to generate and apply to the bit line.
Further, the back gate body potential V _ body can be flexibly set according to design requirements.
Further, the back-gate body potential V _ body is set by a back-gate body potential control circuit that can appropriately adjust the back-gate body potential V _ body under different operations.
The invention adopts the fully depleted silicon-on-insulator FD-SOI field effect transistor as the storage unit of the MRAM, can eliminate the latch-up effect of the bulk silicon field effect transistor, can adjust the back gate body potential, and solves the problem of insufficient drive current provided by a write circuit.
Drawings
FIG. 1 is a schematic diagram of a prior art MTJ.
FIG. 2 is a schematic diagram of a prior art MRAM memory cell architecture.
Fig. 3 is a prior art MRAM memory array layout.
Fig. 4 is a schematic diagram of a bulk silicon fet structure used in one prior art technique.
FIG. 5 is a schematic diagram of an MRAM memory chip having a fully depleted silicon-on-insulator FD-SOI field effect transistor according to a preferred embodiment of the invention.
Fig. 6 is a flow chart illustrating the direction of writing 0 according to another preferred embodiment of the present invention, wherein the MRAM memory chip using fully depleted silicon-on-insulator FD-SOI field effect transistor is designed by adjusting the back gate body potential.
Fig. 7 is a schematic flow chart of the direction of write 1 of the design method for adjusting the back gate body potential of the MRAM memory chip using the fully depleted silicon-on-insulator FD-SOI field effect transistor according to another preferred embodiment of the present invention.
Detailed Description
The following detailed description of the preferred embodiments of the present invention is provided to enable those skilled in the art to more readily understand the advantages and features of the present invention, and to clearly and unequivocally define the scope of the present invention.
EXAMPLE 1
An MRAM memory chip using fully depleted silicon-on-insulator (FD-SOI) field effect transistors is disclosed, wherein the field effect transistors of each MRAM memory cell of the MRAM memory chip are fully depleted silicon-on-insulator (FD-SOI) field effect transistors, as shown in FIG. 5. The MRAM chip also comprises an individual potential control unit for regulating and controlling the back gate body potential of the memory chip.
Because the back grid body, the source and the drain of the fully depleted silicon-on-insulator FD-SOI field effect transistor are isolated by a layer of silicon oxide dielectric layer, when the potential of the back grid body is raised, the MRAM chip can not form PNP and NPN type triode structures, latch-up effect does not exist, and area and cost are not brought.
Example 2
A design method for adjusting the back gate body potential of an MRAM memory chip adopting a fully depleted silicon-on-insulator (FD-SOI) field effect transistor is disclosed, as shown in fig. 6 and 7, and the specific design method is as follows:
the back gate electrode potential is set to V _ body ═ Vb，VbThe value can be flexibly set according to design requirements. Preferably, the back gate electrode body potential control circuit can be used for controlling the back gate electrode body potential under different operationsAnd reasonably adjusting the body potential of the back gate.
In read operation, take Vb＝0。
The specific method for adjusting the back gate body potential of the MRAM memory chip is as follows:
when writing the 0 direction:
the source line potential V _ SL is set to V0+VbThe bit line potential V _ BL is set to 0, and the gate (word line) potential V _ G is set to Vdd+Vb. Wherein, V0+VbIs a voltage signal, V, that the read driving circuit needs to generate and apply to the source linedd+VbThe read driving circuit needs to generate and apply a voltage signal, V, to the gatebIs the voltage signal to be applied to Body.
When writing the 1 direction:
the source line potential V _ SL is set to VbThe bit line potential V _ BL is set to V1+VbThe gate (word line) potential V _ G is set to Vdd+Vb(ii) a Wherein, V1+VbIs the voltage signal that the read driver circuit needs to generate and apply to the bit line.
The embodiment can adjust the back grid potential and solve the problem of insufficient driving current provided by the writing circuit.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims (4)

1. A design method for adjusting the potential of a back gate electrode body of an MRAM (magnetic random access memory) storage chip adopting a fully depleted silicon-on-insulator (FD-SOI) field effect transistor is adopted as the field effect transistor of each MRAM storage unit of the MRAM storage chip, the MRAM storage chip also comprises an individual potential control unit for regulating and controlling the potential of the back gate electrode body of the storage chip, wherein the back gate electrode, a source electrode and a drain electrode of the fully depleted silicon-on-insulator (FD-SOI) field effect transistor are isolated by a silicon oxide dielectric layer; when the potential of the back gate electrode body of the MRAM memory chip is raised, PNP and NPN triode structures cannot be formed;
the method is characterized by comprising the following specific design modes:
the back gate electrode potential is set to V _ body ═ Vb，Vb≥0，VbIs the voltage signal to be applied to Body and, in a read operation, takes Vb＝0。
2. The design method for regulating the back gate body potential of the MRAM memory chip according to claim 1, wherein the specific method for regulating the back gate body potential of the MRAM memory chip is as follows:
when writing the 0 direction:
the source line potential V _ SL is set to V0+VbThe bit line potential V _ BL is set to 0, and the gate (word line) potential V _ G is set to Vdd+Vb(ii) a Wherein, V0+VbIs a voltage signal, V, that the read driving circuit needs to generate and apply to the source linedd+VbThe read driving circuit needs to generate and apply a voltage signal on the grid;
when writing the 1 direction:
the source line potential V _ SL is set to VbThe bit line potential V _ BL is set to V1+VbThe gate (word line) potential V _ G is set to Vdd+Vb(ii) a Wherein, V1+VbIs the voltage signal that the read driver circuit needs to generate and apply to the bit line.
3. The design method for regulating the potential of the back gate body of the MRAM memory chip according to claim 1, wherein the potential V _ body of the back gate body can be flexibly set according to design requirements.
4. The design method for regulating the potential of the back gate body of the MRAM memory chip according to claim 3, wherein the back gate body potential V _ body is set by a back gate body potential control circuit, and the back gate body potential control circuit can reasonably regulate the back gate body potential V _ body under different operations.
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EP2363862B1 (en) * 2010-03-02 2016-10-26 Crocus Technology MRAM-based memory device with rotated gate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007100626A3 (en) * 2006-02-24 2008-12-24 Grandis Inc Current driven memory cells having enhanced current and enhanced current symmetry
CN102099862A (en) * 2008-08-15 2011-06-15 高通股份有限公司 Gate level reconfigurable magnetic logic
CN102334166A (en) * 2009-03-02 2012-01-25 高通股份有限公司 Reducing source loading effect in spin torque transfer magnetoresitive random access memory (stt-mram)
CN101867015A (en) * 2009-04-16 2010-10-20 台湾积体电路制造股份有限公司 By applying the P-substrate bias and regulating the program current that threshold voltage improves MTJ
EP2363862B1 (en) * 2010-03-02 2016-10-26 Crocus Technology MRAM-based memory device with rotated gate
CN104766623A (en) * 2015-04-20 2015-07-08 北京航空航天大学 Circuit for enhancing STT-MRAM (Spin Transfer Torque-Magnetoresistive Random Access Memory) reading reliability by using substrate bias voltage feedback

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