CN110890115A - Spin orbit torque magnetic memory - Google Patents
Spin orbit torque magnetic memory Download PDFInfo
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- CN110890115A CN110890115A CN201811043623.1A CN201811043623A CN110890115A CN 110890115 A CN110890115 A CN 110890115A CN 201811043623 A CN201811043623 A CN 201811043623A CN 110890115 A CN110890115 A CN 110890115A
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
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Abstract
The invention provides a spin orbit torque magnetic memory, which comprises a magnetic tunnel junction, a metal electrode, a bit line, a source line, a first word line, a second word line, a first field effect tube and a second field effect tube, wherein the magnetic tunnel junction is connected with the metal electrode; the surface of the metal electrode is close to the memory layer of the magnetic tunnel junction; the first field effect transistor is connected with the first word line, the bit line and the first end of the metal electrode, and the second end of the metal electrode is connected with the source line; the second field effect transistor is connected with the second word line, the bit line and the magnetic tunnel junction. The storage units of the magnetic storage adopt field effect transistors with different sizes to respectively control read-write operation, and the read field effect transistors and the write field effect transistors are arranged in a staggered mode, so that the area is saved. When the magnetic memory performs a read operation, a read current passes through the magnetic tunnel junction; when the magnetic memory performs a write operation, a write current partially flows through the magnetic tunnel junction partially through the metal electrode, or completely through the metal electrode. The spin orbit magnetic moment memory provided by the invention is beneficial to simultaneously realizing high-speed read-write operation, long erasing service life and small size of the memory.
Description
Technical Field
The invention relates to a storage device, in particular to a spin orbit torque magnetic memory, and belongs to the technical field of integrated circuit memory chips.
Background
MRAM is a new memory and storage technology, can be read and written randomly as SRAM/DRAM, and can permanently retain data after power failure as Flash memory. The chip has good economy, and the silicon chip area occupied by unit capacity has great advantages compared with SRAM, NOR Flash frequently used in the chips and embedded NOR Flash. Its performance is also quite good, the read-write time delay is close to the best SRAM, and the power consumption is the best difference in various memory and storage technologies. Also MRAM is not compatible with standard CMOS semiconductor processes like DRAM and Flash, and MRAM can be integrated with logic circuits in one chip.
The principle of MRAM is based on a structure called MTJ (magnetic tunnel junction). It consists of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1 and 2. The lower layer of ferromagnetic material is a reference layer 13 with a fixed magnetization direction and the upper layer of ferromagnetic material is a memory layer 11 with a variable magnetization direction, the magnetization direction of the memory layer 11 can be parallel or anti-parallel to the reference layer 13. Due to quantum physical effects, current can pass through the middle tunnel barrier layer 12, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The resistance is low when the magnetization directions of the memory layer 11 and the reference layer 13 are parallel, as shown in FIG. 1; the resistance is high in anti-parallel, as in fig. 2. Whether the stored signal is 0 or 1 is determined by measuring the resistance state of the MTJ.
There are several methods for writing MRAM, and in this way, first generation and third and fourth generation MRAM technologies are distinguished. Currently, the industry is adopting the third generation MRAM technology, i.e. spin torque MRAM (spin transfer torque MRAM). This technique uses a stronger current through the MTJ for writing than for reading. A top-down current places the variable magnetization layer in a direction parallel to the fixed layer and a bottom-up circuit places it in an anti-parallel direction, thereby effecting writing of the memory bit.
Each MRAM memory cell is composed of an MTJ and an NMOS selection tube, and is connected with an external read-write circuit through a bit line and a source line to read and write data. The word line is connected to the grid of the field effect transistor, and the field effect transistor is switched on and off by controlling the grid potential, so that selective writing and reading of the storage unit are realized. Each memory cell needs to be connected to three wires: the gate of the NMOS is connected to the Word Line (Word Line)32 of the chip, which is responsible for switching on or off this cell; one pole of the NMOS is connected to the Source Line (Source Line)34, the other pole of the NMOS is connected to one pole of the magnetic tunnel junction 31, the other pole of the magnetic tunnel junction 31 is connected to the Bit Line (Bit Line)33, a nonmagnetic material isolation layer 36 is disposed between the magnetic tunnel junction 31 and the Bit Line 33, and the body 35 of the NMOS can also be connected to the circuit as needed, as shown in fig. 3. An MRAM chip is made up of one or more arrays of MRAM memory cells, each array having a number of external circuits, such as: a row address decoder: changing the received address to a selection of a word line; a column address decoder: changing the received address to a selection of bit lines; a read-write controller: controlling a read (measure) write (add current) operation on the bit line; input and output control: and exchange data externally.
As shown in fig. 4, the word line 43 and the bit line 44 must be vertical in a memory array, and each memory cell in the memory array is composed of a magnetic tunnel junction 41 and a field effect transistor 42. A relatively simple design is that the bit lines 44 and source lines 45 are parallel. In a write operation, the word line 43 is raised to a higher potential to open a row of memory cells, and then the bit line 44 or the source line 45 is raised to a higher potential according to the need to write a 0 or a1 to each memory cell.
The write operation of the existing spin torque technology needs to apply a write current on the MTJ to flip the magnetic moment of the memory layer, the larger the write current is, the faster the flipping speed is, but because the storage unit MTJ is a tunnel junction and a thin insulating layer is arranged in the middle, the passing current tunnels through the insulating layer, the larger the tunneling current is, and the higher the probability of abrasion and even breakdown of the tunnel junction is. Therefore, the service life of the MRAM memory cell is inversely related to the writing speed, and the reliability of the chip is difficult to meet the requirement in the application scenario that high-speed reading and writing of the MRAM are required.
To solve the above problem, two-direction optimization methods are currently generally adopted to reduce the write current: (1) magnetic materials of the MTJ are optimized through material engineering, the magnetic materials comprise a magnetomotive damping coefficient of a memory layer, and a tunnel junction interface and a reinforced reference layer are optimized to improve the spin torque efficiency; (2) by optimizing the MTJ etching processing technology, the damage to the MTJ in the process of processing is reduced, so that the required overturning current is as close to the principle limit as possible. However, on the premise of no fundamental breakthrough, the two methods face huge difficulty in reducing the overturning current and have limited space.
One way to solve the above problem is to use spin orbit magnetic moment to assist the spin torque or to completely use the spin track pitch for the write operation. The method enables the metal electrode to bear part or all of the driving current, reduces the current flowing through the magnetic tunnel junction, weakens the abrasion on the magnetic tunnel junction and prolongs the erasing service life. Issued patents that employ this approach: CN201410531733 invented a design scheme of spin-orbit pitch memory array, as shown in fig. 12. The invention describes a memory cell composed of a field effect transistor and a magnetic tunnel junction, wherein the read-write operation adopts an SL disconnection mode, when in write operation, because BL applies high voltage SL and applies low voltage, RL has a considerable length and a certain capacitance, the configuration that RL is directly connected to MTJ and the other end of RL is suspended can cause transient current to charge RL end, thereby turning over or breaking down MTJ devices, and the feasibility of practical implementation is not provided. In contrast, according to the design scheme of the invention, the MTJ and the source line bit line are disconnected through the field effect transistor, so that the problem of transient charging on the bit line is solved.
WO 2018/038849a1 describes a spin torque effect magnetic memory based on spin orbit torque assist, the basic memory cell of which comprises a magnetic tunnel junction, a spin hall metal electrode, a field effect transistor, two diodes, one word line for each cell as shown in fig. 13, two bit lines, and one source line. The read-write operation is realized through the control of a diode and a field effect tube: taking a unit at the center of the figure as an example, when writing 1, BL (1) is applied with a writing voltage, BLB (1) is grounded, SL (1) is grounded, a field effect tube on WL (1) is conducted, and at the moment, current flows through an SHM spin Hall metal electrode from left to right and flows through a magnetic tunnel junction from bottom to top. When writing 0, BL (1) is grounded, BLB (1) is applied with writing voltage, SL (1) is grounded, the field effect tube on WL (1) is conducted, and at the moment, current flows through the SHM spin Hall metal electrode from left to right and flows through the magnetic tunnel junction from top to bottom. During reading operation, BL (1) is applied with reading voltage, BLB (1) is grounded, SL (1) is grounded, field effect tube on WL (1) is not conducted, and current flows through magnetic tunnel junction from bottom to top. In the design method, when writing 1 and writing 0, the current flowing through the SHM has the same direction, so that an auxiliary effect is achieved in one direction, a blocking effect is achieved in the other direction, and the writing efficiency in the two directions of 1 and 0 cannot be improved simultaneously. In addition, the design method cannot adjust the size ratio of the spin track pitch auxiliary effect and the spin torque main effect through a control circuit, but can only be realized by adjusting the production process, and the adjustment range is very limited. The invention adopts the method of the double field effect tube without introducing a diode, solves the difficulties and has obvious advantages in comparison.
US20170352702 discloses a unique spin metal electrode, as shown in fig. 14, for spin-track pitch memory, which proposes to use a narrower metal electrode near the magnetic tunnel junction and a wider electrode far from the magnetic tunnel junction, where the narrow metal electrode is beneficial to provide enough spin track pitch or spin current to flip the magnetic moment of the free layer of the magnetic tunnel junction, and the wide metal electrode is beneficial to reduce the total trace resistance, increase the memory operation speed and reduce the power consumption. This patent does not teach a viable memory array cell design nor does it mention the method of read and write operations.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the technical problems to be solved by the present invention are: the magnetic memory reduces or eliminates current flow through the magnetic tunnel junction when performing a write operation. A memory array design is provided which is practical for read and write operations and which occupies as little area as possible.
In order to solve the technical problem, the invention provides a spin orbit torque magnetic memory, which comprises a magnetic tunnel junction, a metal electrode, a bit line, a source line, a first word line, a second word line, a first field effect tube and a second field effect tube, wherein the magnetic tunnel junction is formed by connecting a first magnetic field transistor and a second magnetic field transistor; the surface of the metal electrode is close to the magnetic tunnel junction; the grid of the first field effect transistor is connected with a first word line, one of the source electrode or the drain electrode of the first field effect transistor is connected with a bit line, the other of the source electrode or the drain electrode of the first field effect transistor is connected with the first end of the metal electrode, and the second end of the metal electrode is connected with the source line; the grid of the second field effect transistor is connected with the second word line, one of the source electrode or the drain electrode of the second field effect transistor is connected with the bit line, and the other of the source electrode or the drain electrode of the second field effect transistor is connected with the magnetic tunnel junction. The magnetic tunnel junction sequentially comprises a reference layer, a barrier layer and a memory layer.
Furthermore, the metal electrode is adjacent to the memory layer of the magnetic tunnel junction, and the metal electrode is selected from one of Ta, TaN, Ti, TiN, Pt, Pd, Ir, Hf and W.
Further, the circulation path of the read current and the circulation path of the write current are connected to the source line through the second end point, the circulation path of the read current is connected to the bit line through the third end point, and the circulation path of the write current is connected to the bit line through the first end point.
Further, the first field effect transistor and the second field effect transistor control a flow path of the write current, the second field effect transistor controls a flow path of the read current, and a ratio of the write current flowing through the metal electrode and the write current flowing through the magnetic tunnel junction is adjusted by gate voltages of the first field effect transistor and the second field effect transistor. And during writing operation, the first field effect transistor is turned off, and the second field effect transistor is turned on. When the magnetic tunnel junction is not operated, the first field effect transistor and the second field effect transistor are in an off state. And selecting the first field effect transistor or the second field effect transistor by using a multiplexer.
Furthermore, the first field effect transistor and the second field effect transistor both adopt NMOS. The first field effect transistor and the second field effect transistor adopt NMOS with the same length but different widths, and the width of the first field effect transistor is larger than that of the second field effect transistor. The first field effect transistors and the second field effect transistors are arranged in a staggered mode.
Further, the bit line is perpendicular to the source line, and the second word line, the first word line and the source line are parallel. The first word line and the second word line are capable of interchanging functions:
when the first word line is a write word line, the second word line is a read word line; correspondingly, the first field effect transistor is used as a writing field effect transistor, and the second field effect transistor is used as a reading field effect transistor;
when the second word line is a write word line, the first word line is a read word line; correspondingly, the second field effect transistor is used as a writing field effect transistor, and the first field effect transistor is used as a reading field effect transistor.
Furthermore, when the reading operation is implemented, the high potential of the reading word line controls the switching-on of the reading field effect transistor, and the zero potential of the writing word line controls the switching-off of the writing field effect transistor. The bit line is at a high potential and the source line is at a low potential, and the read current flows from the bit line to the magnetic tunnel junction and then to the source line.
Furthermore, when the writing operation is implemented, the high potential of the reading word line controls the switching on of the reading field effect transistor, and the high potential of the writing word line controls the switching on of the writing field effect transistor.
When the write 0 operation is implemented, the source line is at a high potential, the bit line is at a low potential, and the write current flows into the metal electrode from the source line and then is divided into the following two branches: one branch flows into the bit line through the magnetic tunnel junction, and the other branch flows into the bit line only after flowing through the metal electrode.
When the 1 writing operation is carried out, the bit line is high in potential, the source line is low in potential, and the writing current flows out from the bit line to the source line through the following two branches: one branch circuit flows through the metal electrode through the magnetic tunnel junction and then is merged into the source line, and the other branch circuit directly flows through the metal electrode and then is merged into the source line.
Further, when the above write 0 or write 1 operation is performed, the current distribution on the two branches is controlled by the respective gate voltages of the read word line and the write word line.
The invention has the following beneficial effects: the magnetic memory can regulate and control the applied write current to partially flow through the magnetic tunnel junction, thereby reducing the breakdown abrasion pressure of the current on the magnetic tunnel junction, independently separating the write current and the erasing service life of the MRAM, and theoretically realizing high-speed write and high reliability of a chip simultaneously. The layout method that the first field effect transistors and the second field effect transistors with different widths are alternately arranged is adopted, so that the area occupied by the two field effect transistor-magnetic tunnel junction storage units is reduced to the greatest extent. The area occupied by the storage unit is increased by 25 percent compared with that of a field effect transistor-magnetic tunnel junction storage unit. Still has area comparison advantage compared with SRAM. In addition, the distribution proportion of the write current between the magnetic tunnel junction and the metal electrode can be controlled and adjusted by external voltage through the two field effect transistors, so that subsequent flexible adjustment is facilitated.
Drawings
FIG. 1 is a diagram of a memory layer magnetically parallel to a reference layer when a magnetic tunnel junction is in a low resistance state;
FIG. 2 is a schematic diagram of the memory layer and the reference layer being magnetically antiparallel when the magnetic tunnel junction is in a high resistance state;
FIG. 3 is a schematic diagram of a memory cell comprising a magnetic tunnel junction and a field effect transistor;
FIG. 4 is a schematic diagram of the layout of a memory array of the magnetic memory;
FIG. 5 is a schematic diagram of a three-terminal structure of a magnetic memory in accordance with a preferred embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a magnetic memory in accordance with a preferred embodiment of the present invention;
FIG. 7 is a cross-sectional view of a magnetic memory in accordance with a preferred embodiment of the present invention;
FIG. 8 is a schematic diagram of a staggered arrangement of FETs in a preferred embodiment of the present invention;
FIG. 9 is a schematic circuit diagram of a magnetic memory according to a preferred embodiment of the present invention;
FIG. 10 is a schematic circuit diagram of a magnetic memory for a write 0 operation in accordance with a preferred embodiment of the present invention;
FIG. 11 is a schematic circuit diagram of a magnetic memory according to a preferred embodiment of the present invention for performing a write 1 operation;
FIG. 12 is a schematic circuit diagram of a prior art spin-orbit pitch memory array;
FIG. 13 is a schematic circuit diagram of a prior art spin torque effect magnetic memory based on spin orbit torque assist;
FIG. 14 is a schematic diagram of a unique spin metal electrode of the prior art.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be noted that the drawings are in simplified form and are not to precise scale, which is provided for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention relates to a circuit design of a Magnetic Random Access Memory (MRAM), in particular to a spin orbit torque MRAM (SOT-MRAM) which is one of fourth generation MRAM memories.
FIG. 5 is a schematic diagram of a three-terminal structure formed by a magnetic tunnel junction and a metal electrode in the magnetic memory of the present invention. The magnetic tunnel junction includes a reference layer 51, a barrier layer 52, a memory layer 53, a metal electrode 54 adjacent to the memory layer 53 in this order. The metal electrode is adjacent to the memory layer of the magnetic tunnel junction, and the metal electrode can be made of transition group heavy metal element materials, preferably one of Ta, TaN, Ti, TiN, Pt, Pd, Ir, Hf and W. Topological insulator materials can also be selected, and simple substances or alloy materials such as Bi, BiSb, BiSe, BiSbTe and the like are preferred. Such heavier atomic mass metallic materials or topological insulator materials generally have stronger spin hall effect and high conductivity: the current flowing through the metal electrode deflects carriers of different spin directions in opposite directions, thereby forming a spin current perpendicular to the current direction and the electrode surface. The spin current accumulates carrier spin at the interface of the metal electrode and the magnetic tunnel junction memory layer, and the precession and magnetic moment overturning of the memory layer are excited by the spin track pitch effect. The method of switching the magnetic moment of the memory layer (the method of writing the memory cell) is different from the method of writing the spin torque in that: the former current flows through the metal electrode and the latter current flows through the magnetic tunnel junction. The magnetic tunnel junction comprises one or more thin layers of junction edge materials, so that current flowing through the magnetic tunnel junction has an abrasion effect on the magnetic tunnel junction, and the magnetic tunnel junction is stored to cause breakdown with a certain probability to cause the device to fail. The abrasion effect of the current in the metal electrode on the metal can be ignored, and the power consumption and the erasing service life of the memory can be optimized by combining the two writing methods and mutually-assisted reading and writing methods. A first end 57 of the metal electrode is connected to a bit line, a second end 55 of the metal electrode is connected to a source line, and a terminal 56 of the magnetic tunnel junction remote from the metal electrode is also connected to the bit line. The spin orbit torque magnetic memory used in the present invention is a three-terminal structure, and the end point of the first terminal 57 of the metal electrode is referred to as a first end point, the end point of the second terminal 55 is referred to as a second end point, and the end point of the terminal 56 is referred to as a third end point. Compared with the traditional two-terminal structure self-selection torque magnetic memory, the three-terminal structure spin-orbit torque magnetic memory in the embodiment has fundamental changes in the aspects of writing physical mechanism, circuit design, reading and writing operation and the like.
FIG. 6 is a schematic circuit diagram of a spin-orbit torque magnetic memory. The spin orbit torque magnetic memory includes a magnetic tunnel junction 61, a metal electrode 62, a first field effect transistor 63, a second field effect transistor 64, a first word line 65, a second word line 66, a bit line 67, a source line 68. The surface of the metal electrode 62 is close to the magnetic tunnel junction 61. The gate of the first field effect transistor 63 is connected to a first word line 65, the source (or drain) of the first field effect transistor 63 is connected to a bit line 67, and the drain (or source) of the first field effect transistor is connected to a first end of the metal electrode 62. A second end of metal electrode 62 is connected to source line 68. The gate of the second field effect transistor 64 is connected to the second word line 66, the source (or drain) of the second field effect transistor 64 is connected to the bit line 67, and the drain (or source) of the second field effect transistor 64 is connected to the magnetic tunnel junction 61.
The path for the read current and the path for the write current are connected to source line 68 through the second terminal, the path for the read current is connected to bit line 67 through the third terminal, and the path for the write current is connected to bit line 67 through the first terminal. The first fet 63 controls the path of the write current and the second fet 64 controls the path of the read current. The first field effect transistor and the second field effect transistor control the circulation path of the writing current, the second field effect transistor controls the circulation path of the reading current, and the grid voltage of the field effect transistors can adjust the on-off degree (equivalent resistance) of the field effect transistors. The ratio of the write current flowing through the metal electrode and the write current flowing through the magnetic tunnel junction is adjusted by the gate voltages of the first field effect transistor and the second field effect transistor. The erasing pressure, the writing speed and the power consumption of the magnetic tunnel junction are reasonably optimized. And during reading operation, the first field effect transistor is turned off, and the second field effect transistor is turned on. When the magnetic tunnel junction is not operated, both the first field effect transistor 63 and the second field effect transistor 64 are in an off state. A multiplexer is used to select either the first fet 63 or the second fet 64. Bit line 67 is perpendicular to source line 68 and first word line 65, second word line 66, and source line 68 are parallel. The first word line 65 and the second word line 66 may be functionally interchanged according to different read and write states.
As shown in fig. 7, the overall structure of the magnetic memory in the embodiment of the invention uses four layers of metal interconnects, three layers of through holes and contact electrodes connected with source lines and drain lines. The magnetic tunnel junction 71 and the metal electrode 72 are arranged adjacently, the bit line 73 and the source line 74 are vertical, and the two field effect transistors are NMOS, and respectively have a gate 75, a source 76 and a drain 77. Above the source 76, in order: lead hole 70, metal 78a, via 79a, metal 78b, via 79b, metal 78c, via 79 c. The processing steps are as follows:
1. a Front-end-of-line (FEOL) process forms the gate 75, the source 76, and the drain 77.
2. And a via contact connecting the source and the drain.
3. And etching the bottom electrode groove below the magnetic tunnel junction.
4. And 4, electrochemically depositing a bottom electrode, wherein Wu, Ta, Ti or nitride alloy of the Wu, the Ta and the Ti is selected.
5. And polishing and grinding the bottom electrode by chemical mechanical polishing.
6. And etching the first layer of metal copper M1 groove, and manufacturing a first layer of metal copper M1 by a Damascus process.
7. And growing and etching the magnetic tunnel junction, and backfilling a low-k dielectric medium.
8. And manufacturing a first layer of through holes V1 and a second layer of metal copper M2 by adopting a dual damascene manufacturing process.
9. And etching a groove of the spin Hall metal electrode 72 above the magnetic tunnel junction, electrochemically depositing the metal electrode 72, and selecting one of Ta, TaN, Ti, TiN, Pt, Pd, Ir, Hf and W, or selecting a topological insulator material, preferably a simple substance or an alloy material such as Bi, BiSb, BiSe, BiSbTe and the like.
10. The chemical mechanical polishing planarizes the metal electrode 72.
11. A second layer of through holes V2 and a third layer of copper metal M3, and a dual damascene manufacturing process, wherein a source line is made of M3 metal.
12. And a third layer of through holes and a fourth layer of copper metal M4 are formed, and the bit line is made of M4 metal through a dual damascene manufacturing process.
As shown in fig. 8, the NMOS with the same length but different width is used for the writing fet and the reading fet, and the width of the writing fet is larger than that of the reading fet. The write operation requires a larger drive current, and wider fets 81, 83, 85 are used. The read operation requires only a small drive current, with the use of narrow fets 82, 84, 86. The field effect transistors with different sizes are arranged in a staggered mode, and space is saved. The write current of the magnetic tunnel junction is estimated to be 200 microamperes, the read current is estimated to be 20 microamperes, and by taking a 55-nanometer node as an example, the size of the read field effect transistor is limited by design rules and the size of the write field effect transistor is limited by the capacity of the drive current. The area of the memory cell is increased by 25 percent compared with the area of the memory cell consisting of one field effect transistor and one magnetic tunnel junction of the third generation of spin torque magnetic memories. Still have obvious area advantage compared SRAM.
The same word line can be used as a read word line and a write word line, and a Multiplexer (MUX) is adopted to select the corresponding field effect transistor when the read and write operations are carried out. In fig. 8, fet 81 and fet 84 form a first unit, fet 82 and fet 85 form a second storage unit, and fet 83 and fet 86 form a third storage unit. When the first cell or the third cell needs to be written, the word line 87 is a write word line, and the bit lines 89 at the leftmost end and the rightmost end function; when it is desired to read either the first cell or the third cell, word line 88 is a read word line. When a second cell needs to be written, word line 88 is a write word line, and the middle bit line 89 is active; when a second cell needs to be read, word line 87 is the read word line. Therefore, the write word line and the read word line are not fixed, but alternately switched according to the setting of the Multiplexer (MUX).
Fig. 9 shows a schematic circuit diagram for carrying out a read operation. In FIG. 9, the read word line 93 is high to control the read FETs to turn on, and the write word line 94 is zero to control the write FETs to turn off (shown in gray in FIG. 9). The bit line 95 is at a high potential and the source line 96 is at a low potential, and a read current flows from the bit line 95 into the magnetic tunnel junction 91, through a portion of the metal electrode 92, and into the source line 96, as indicated by the U-shaped arrow in the figure.
The write operation is divided into two cases, a bit write 0 operation and a write 1 operation. Fig. 10 is a schematic circuit diagram of a write 0 operation. When the write 0 operation is implemented, the high potential of the read word line 103 controls the read field effect transistor to be switched on, the high potential of the write word line 104 controls the write field effect transistor to be switched on, the high potential of the source line 106 and the low potential of the bit line 105 are achieved, and the write current flows into the metal electrode 102 from the source line 106 and then is divided into the following two branches: one branch flows into the bit line through the magnetic tunnel junction 101; the other branch flows through the metal electrode 102 only and then flows into the bit line 105, as indicated by the left arrow in the figure.
Fig. 11 is a schematic circuit diagram of the write 1 operation. When the write 1 operation is implemented, the read word line 114 controls the read fet to be turned on at a high potential, the write word line 113 controls the write fet to be turned on at a high potential, the bit line 115 is at a high potential, the source line 116 is at a low potential, and the write current flows from the bit line 115 through the following two branches: one branch passes through the read field effect transistor, then flows through the metal electrode 112 through the magnetic tunnel junction 111, and then is merged into the source line 116; the other branch passes through the write fet, then flows completely through the metal electrode 112, and then flows into the source line 116, as shown by the arrow pointing to the right in the figure.
The invention adopts the fourth generation technology, the writing method does not depend on the magnetic moment of the memory layer to be overturned by current in the magnetic tunnel junction of the memory unit, but the writing current with certain current density flows in the metal electrode contacted below the magnetic tunnel junction, and the memory layer is overturned by the spin-orbit torque effect. The write current applied by the method does not directly pass through the magnetic tunnel junction, so that the breakdown probability of the magnetic tunnel junction is not directly influenced, two factors of the write speed and the service life of the magnetic memory are independently separated, the read operation applies smaller current to the magnetic tunnel junction, the write operation applies larger current to the metal bottom electrode, and high-speed write and high reliability of a chip can be realized simultaneously.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (15)
1. A magnetic memory is characterized by comprising a magnetic tunnel junction, a metal electrode, a bit line, a source line, a first word line, a second word line, a first field effect tube and a second field effect tube; the surface of the metal electrode is close to the magnetic tunnel junction; the grid electrode of the first field effect transistor is connected with the first word line, one of the source electrode or the drain electrode of the first field effect transistor is connected with the bit line, the other of the source electrode or the drain electrode of the first field effect transistor is connected with the first end of the metal electrode, and the second end of the metal electrode is connected with the source line; the grid electrode of the second field effect transistor is connected with the second word line, one of the source electrode or the drain electrode of the second field effect transistor is connected with the bit line, and the other of the source electrode or the drain electrode of the second field effect transistor is connected with the magnetic tunnel junction.
2. A magnetic memory according to claim 1, wherein said first fet controls the path of the write current and said second fet controls the path of the read current, at most only one of said first fet and said second fet being on at the same time; when the magnetic tunnel junction is not operated, the first field effect transistor and the second field effect transistor are in an off state.
3. A magnetic memory as claimed in claim 2, wherein a multiplexer is used to select the switching on and off of said first fet or said second fet.
4. A magnetic memory according to claim 1, wherein the first fet and the second fet are each NMOS.
5. A magnetic memory according to claim 4 wherein the first FET and the second FET are NMOS of the same length but different widths, the width of the first FET being greater than the width of the second FET.
6. A magnetic memory according to claim 5, wherein said first field effect transistors and said second field effect transistors are staggered.
7. A magnetic memory according to claim 1, wherein said bit line and said source line are perpendicular, and said second word line, said first word line and said source line are parallel.
8. The magnetic memory of claim 1, wherein the magnetic tunnel junction comprises a reference layer, a barrier layer, and a memory layer in that order, and the metal electrode is adjacent to the memory layer.
9. A magnetic memory according to claim 1, wherein the first word line and the second word line are functionally interchangeable:
when the first word line is a write word line, the second word line is a read word line; correspondingly, the first field effect transistor is used as a writing field effect transistor, and the second field effect transistor is used as a reading field effect transistor;
when the second word line is a write word line, the first word line is a read word line; correspondingly, the second field effect transistor is used as a writing field effect transistor, and the first field effect transistor is used as a reading field effect transistor.
10. A method as claimed in claim 9, wherein when performing a read operation, the read word line high potential controls the read fet to turn on, and the write word line zero potential controls the write fet to turn off.
11. A method of claim 9, wherein when performing a read operation, the bit line is high and the source line is low, and wherein a read current flows from the bit line to the magnetic tunnel junction and then to the source line.
12. A method as claimed in claim 9, wherein when performing a write operation, the read word line high voltage controls the read fet to turn on, and the write word line high voltage controls the write fet to turn on.
13. The method of claim 12, wherein when performing a write 0 operation, the source line is high, the bit line is low, and a write current flows from the source line to the metal electrode and then splits into two branches: one branch flows into the bit line through the magnetic tunnel junction, and the other branch flows into the bit line only after flowing through the metal electrode.
14. A method of claim 12, wherein when performing a write 1 operation, the bit line is high, the source line is low, and a write current flows from the bit line to the source line in two branches: one branch circuit flows through the metal electrode through the magnetic tunnel junction and then is merged into the source line, and the other branch circuit directly flows through the metal electrode and then is merged into the source line.
15. A method of claim 13 or 14, wherein the current distribution in the two branches is controlled by the gate voltages of the read word line and the write word line when writing is performed.
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