TW201312693A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

A method for manufacturing semiconductor device includes a pillar-shaped semiconductor forming step for simultaneously forming first and second pillar-shaped semiconductors (2, 3) on a substrate (1) with the same height, a pillar-shaped semiconductor bottom connection step for doping a donor or receptor impurity in a bottom region of the first pillar-shaped semiconductor (2) to form a first semiconductor layer (5) and connecting the first semiconductor layer and the second pillar-shaped semiconductor (3) with each other, a circuit element forming step for doping a donor or receptor impurity in an upper region of the first pillar-shaped semiconductor to form an upper semiconductor region (11), and forming a circuit element having the upper semiconductor region, a conductor layer forming step for forming a first conductor layer (13) inside the second pillar-shaped semiconductor, a contact hole forming step for forming first and second contact holes (16a, 16b) respectively connected to the first and second pillar-shaped semiconductors, and a wiring metal layer forming step for forming a wiring metal layer connected to the upper semiconductor region and the first conductor layer via the first and second contact holes.

Description

Semiconductor device manufacturing method, and semiconductor device

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a transistor in which a channel region is formed in a semiconductor having a columnar structure, and a semiconductor device therefor.

For example, in a CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging device in which a pixel is formed in a columnar semiconductor or a semiconductor device in which a MOS transistor is formed in a columnar semiconductor, further requirements are required. Performance.

Solid-state imaging devices are widely used in video cameras, still cameras, and the like. Further, performance improvement such as high resolution, high speed, and high sensitivity of the solid-state imaging device is also required.

A solid-state imaging device of a conventional example will be described below with reference to FIGS. 17A to 17D. As shown in FIG. 17A to FIG. 17D, a solid-state imaging device in which one pixel is formed in a column 115 (hereinafter referred to as Si) belonging to one semiconductor (see, for example, Patent Document 1) is known. Fig. 17A is a cross-sectional structural view of a single pixel. In this pixel structure, a flat signal line N ⁺ layer (which is an N-type Si semiconductor layer containing a large amount of donor impurities) is formed on the yttrium oxide substrate 114, hereinafter referred to as "N ⁺ layer". ) 116. A mast 115 is formed on this signal line N ⁺ layer 116. The signal line N ⁺ layer 116 is formed further below the mast 115 by diffusion. A P layer 117 (which is a "P-type Si semiconductor layer containing a large amount of acceptor impurities", hereinafter simply referred to as a "P layer") is connected to the signal line N ⁺ layer 116, and surrounds the P layer 117. A gate insulating layer 118 is formed, and a gate conductor layer 119 is formed outside the gate insulating layer 118. In a region adjacent to the gate conductor layer 119, a P layer 117 and an N layer 120 located on the outer periphery of the P layer 117 are formed. Further, on the P layer 117 and the N layer 120, a pixel-selective P ⁺ layer { is a P-type Si semiconductor layer containing a large amount of acceptor impurities, hereinafter abbreviated as a P ⁺ layer} 121. Furthermore, a pixel selection line conductor layer 122 is connected to the pixel selection P ⁺ layer.

The light incident from the top of the mast 115 is absorbed in the photoelectric conversion region of the P layer 117 and the N layer 120 on which the photo diode is formed, and generates a signal charge (free electron). Furthermore, most of the generated signal charge is stored in the N layer 120 of the photodiode. In the pixel column 115, a N layer 120 of the photodiode is used as a gate, a P layer 117 surrounded by the N layer 120 is used as a channel, and a P ⁺ layer 121 is selected as a source by a pixel. The P layer 117 near the signal line N ⁺ layer 116 is a bonding transistor of a drain. The signal current corresponding to the amount of signal charge stored in the N layer 120 of the photodiode is selected by the application of a plus voltage to the pixel to select the P ⁺ layer 121, and a ground voltage is applied to the signal line N ⁺ layer 116. And read. A reset MOS transistor having a N-layer 120 as a source, a signal line N ^{+ a} layer 116 as a drain, and a gate conductor layer 119 surrounding the gate insulating layer 118 as a gate is formed and stored in The signal charge of the N layer 120 of the photodiode is removed via the signal line N ⁺ layer 116 by applying a positive voltage to the gate conductor layer 119 and applying a positive voltage to the signal line N ⁺ layer 116 belonging to the drain. external.

As described above, the basic operation of the pixel in the conventional solid-state imaging device is composed of the following operations: photoelectric conversion operation of the light absorption/signal charge generation in the photodiode portion of the P layer 117 and the N layer 120; The N-layer 120 of the body stores a signal charge storage operation of the signal charge; by using the photodiode N layer 120 as a gate, the P ⁺ layer 121 as a source by a pixel, and the P layer near the signal line N ⁺ layer 116 117 is a gate electrode assembly for reading a signal current corresponding to the stored signal charge amount; and the stored signal charge is obtained by using the N layer 120 as a source and a signal line N ^{The +} layer 116 is a reset operation in which the drain electrode and the gate electrode layer 119 surrounding the gate insulating layer 118 are gate-replaced MOS transistors and removed to the signal line N ⁺ layer 116.

The pixel of the solid-state imaging device is composed of a pixel region arranged in a two-dimensional shape and a peripheral driving/output circuit region for driving a pixel signal and performing signal extraction processing on the pixel signal. 17B shows a mast 115 and a signal line N ⁺ layer 116 which constitute one pixel in the pixel region, and the pixel selection line conductor layer 122 is electrically connected to the upper wiring metal layer 124a, 124b of the peripheral driving/output circuit region. Sectional structure diagram. This pixel structure is characterized in that a signal line N ⁺ layer 116 and a pixel selection P ⁺ layer 121 are formed in the lower region of the mast 115, respectively. The signal line N ⁺ layer 116 extends from the mast 115 constituting the pixel to the peripheral drive output circuit, and is connected to the signal line metal layer 124a via a contact hole 123a in the peripheral drive/output circuit region. Further, the pixel selection line conductor layer 122 connected to the pixel selection P ⁺ layer 121 extends from the mast 115 constituting the pixel to the peripheral driving/output circuit, and in the peripheral driving/output circuit region, via the contact hole 123b Connected to the pixel selection line metal layer 124b. The contact hole 123a on the signal line N ⁺ layer 116 is formed by etching the SiO ₂ layers 125a, 125b, 125c deposited on the N ⁺ layer 116. Further, the contact hole 123b is formed by etching only the SiO ₂ layer 125c on the pixel selection line conductor layer 122. Thereby, in the depths of the contact hole 123a and the contact hole 123b, a difference in the degree of height corresponding to the mast 115 constituting the pixel is inevitably generated.

The height of the mast 115 is mainly determined by the height of the N layer 120 of the photodiode. The light system is incident on the upper surface of the P ⁺ layer 121 from the pixels on the mast 115. The signal charge generation rate caused by the light irradiation thus has a characteristic of decreasing the exponential function with respect to the Si depth from the pixel selection P ⁺ layer 121. In the solid-state imaging device that detects visible light, in order to efficiently take out signal charges that contribute to sensitivity, the depth of the photoelectric conversion region needs to be 2.5 to 3 μm (refer to, for example, Non-Patent Document 1). Therefore, the height of the N layer 120 of the photoelectric conversion photodiode needs to be at least 2.5 to 3 μm. The height of the gate conductor layer 119 of the reset MOS transistor located under the N layer 120 can also operate at 0.1 μm or less. Therefore, the height of the pixel mast 115 needs to be at least 2.5 to 3 μm.

Fig. 17C is a plan view showing a solid-state imaging device of a conventional example. In the figure, the cross-sectional structure diagram along the G-G' line corresponds to the 17B chart. As shown in Fig. 17C, the masts P ₁₁ to P ₃₃ constituting the pixels are arranged, and the masts P ₁₁ to P ₃₃ are formed to extend in the longitudinal direction (column) of the drawing to the peripheral driving/output. The signal lines N ⁺ layers 116a, 116b, 116b, 116c are formed in the circuit regions. The signal line N ⁺ layers 116a (116), 116b, 116c are connected to the signal line metal layers 128a (124a), 128b, 128c via contact holes 126a (123a), 126b, 126c in the peripheral drive/output circuit region. The reset MOS gate conductor layers 119a (119), 119b, 119c and the pixel selection line conductor layers 122a (122), 122b, 122c connected in the column of each of the pillars P ₁₁ to P ₃₃ constituting the pixel are convex. The horizontal (row) direction extends to the peripheral drive/output circuit area. The pixel selection line conductor layers 122a (122), 122b, and 122c are connected to the pixel selection line metal layers 129a (124b), 129b, and 129c via the contact holes 127a (123b), 127b, and 127c in the peripheral driving/output circuit region.

In Fig. 17C, although the contact holes 126a, 126b, and 126c on the signal line N ⁺ layers 116a, 116b, and 116c are formed in the peripheral driving/output circuit region on the outer side of the pixel region, it is necessary to cooperate with the pixel column. The case where P ₁₁ to P _{33 are} adjacent to each other is formed. Referring to Fig. 17C, the signal current in the signal charge reading operation and the stored charge removal current in the reset operation are via the contact holes 126a, 126b, and 126c at the terminals of the signal line N ⁺ layers 116a, 116b, and 116c. It is taken out from the signal line metal layers 128a, 128b, and 128c. When the contact of the signal line N ⁺ layers 116a, 116b, 116c with the signal line metal layers 128a, 128b, 128c is performed in the drive-output circuit region, the pixel posts P ₁₁ to P ₃₃ and the contact holes 126a, 126b, 126c The resistance values of the signal line N ⁺ layers 116a, 116b, 116c between them limit the response time of signal current extraction and storage charge removal. Therefore, in order to speed up, the resistance value of the signal line needs to be reduced.

Fig. 17D is a plan view showing the solid-state imaging device which reduces the resistance value of the signal line. In the figure, the cross-sectional structural diagram along the line H-H' corresponds to Fig. 17B. As shown on FIG. 17D, in the pixel region, and the silicon-based column P ₁₁ to P ₃₃ adjacent to the contact hole CH ₁₁ CH ₃₃ to be formed. The masts P ₁₁ to P ₃₃ have the configuration shown by the mast 115 in Fig. 17B, and the contact holes CH ₁₁ to CH ₃₃ have the configuration shown by the contact hole 123a in Fig. 17B. The columns P ₁₁ to P ₃₃ and the contact holes CH ₁₁ to CH ₃₃ are formed on the signal line N ⁺ layers 130a, 130b, 130c extending in the longitudinal (row) direction of the drawing. N ⁺ layer signal lines 130a, 130b, 130c via the line to the contact hole CH ₁₁ CH ₃₃ is connected to the figures toward the longitudinal (row) of the signal line extending in the direction of the metal layer 135a, 135b, 135c. The reset MOS gate conductor N ⁺ layers 131a, 131b, 131c and the pixel selection line conductor N ⁺ layers 132a, 132b, 132c extending along the column of each of the pillars P ₁₁ to P ₃₃ constituting the pixel are evasively contacted The holes CH ₁₁ to CH ₃₃ extend in the lateral (column) direction of the drawing to the peripheral drive/output circuit area. The pixel selection line conductors N ⁺ layers 132a, 132b, and 132c are connected to the pixel selection line metal layers 134a, 134b, and 134c via the contact holes 133a, 133b, and 133c in the peripheral driving/outputting circuit region.

Connecting the pixel from the signal line to the peripheral driving/output circuit via the contact holes CH ₁₁ to CH ₃₃ with the signal line metal layers 135a, 135b, and 135c connected to the signal line N ⁺ layers 130a, 130b, and 130c. A low resistance of the signal line is achieved. This is because the resistivity (Ωm) with respect to the signal line N ⁺ layers 130a, 130b, 130c is about 10 ^-5 Ωm, and the resistivity of the signal line metal layers 135a, 135b, 135c is when aluminum (Al) is used. It is about 3 × 10 ^-8 Ωm, and when copper (Cu) is used, it is about 1.5 × 10 ^-8 Ωm, which is extremely small. At this time, among the pixel regions, it is necessary to form the masts P ₁₁ to P ₃₃ constituting the pixels, and the contact holes CH ₁₁ to CH ₃₃ . Furthermore, in order to prevent short-circuiting of the signal line metal layers 135a, 135b, 135c, the pixel selection line conductor N ⁺ layers 132a, 132b, 132c, and the reset MOS gate conductor N ⁺ layers 131a, 131b, 131c, the contact holes CH ₁₁ to The CH ₃₃ is formed so as to avoid the pixel selection line conductor N ⁺ layers 132a, 132b, and 132c and the reset MOS gate conductor N ⁺ layers 131a, 131b, and 131c. Further, since the contact holes CH ₁₁ to CH ₃₃ are formed adjacent to the pillars P ₁₁ to P _{33 of the} individual constituent pixels, it is necessary to secure the masts P ₁₁ to P ₃₃ and the contact holes CH ₁₁ to CH constituting the individually formed pixels. A mask of ₃₃ is formed by a registration margin. Thus, in order to reduce the signal line resistance value, the contact holes CH ₁₁ to CH ₃₃ are formed adjacent to the pillars P ₁₁ to P ₃₃ constituting the pixel, and the signal line metal layers 135a, 135b, and 135c are used to perform the pixel-to-periphery. Drive/output circuit connection. As a result, a decrease in the pixel integration degree of the pixel region occurs.

At present, a pitch of pixels arranged in a two-dimensional shape in a pixel region, a product having a minimum of 1.4 μm, and a pitch of 0.9 μm have been published (see, for example, Non-Patent Document 2). When the design rule (minimum design size) is 0.2 μm (200 nm), the planar shape of the contact hole is usually formed with this minimum design size. At this time, the aspect ratio (depth length ratio with respect to the width length of the contact hole) of the contact hole 123a on the signal line N ⁺ layer 116 shown in FIG. 17B is at least 12.5 to 15. In order to reduce the cost of the solid-state imaging device, it is required to further reduce the area of the pixel region. In this respect, although the reduction in the minimum processing size is required, the height of the mast 115 is set to 2.5 to 3 μm due to the requirement of photoelectric conversion characteristics, and therefore it is required to form the contact hole 123a having a higher aspect ratio.

In the solid-state imaging device shown in FIGS. 17C and 17D, as shown in FIG. 17B, it is necessary to form two contact holes 123a and 123b having different depths corresponding to at least the height of the mast 115 constituting the pixel. Usually, the formation of the contact holes 123a, 123b is performed individually, so the number of steps is increased. Furthermore, since the mask alignment margin when the contact hole 123a and the contact hole 123b are formed is separately ensured, the pixel accumulation degree is lowered. Alternatively, when two contact holes 123a and 123b are formed at the same time, in order to form a contact hole by RIE (Reactive Ion Etching) or the like, the signal line N ⁺ layer 116 is accurately stopped. The aforementioned pixels select the surface of the line conductor layer 122, which causes manufacturing difficulty. Furthermore, when two contact holes are formed at the same time, after the etching of the contact holes 123b reaches the bottom pixel selection line conductor layer 122, the etching of the contact holes 123a is additionally exposed to the etching before reaching the surface of the signal line N ⁺ layer 116. gas. Therefore, the pixel selection line conductor layer must be thickened. Further, since the etching time is long, the removal of the etching mask layer after RIE or the removal of the etching residue is difficult. Such difficulty in the manufacturing step becomes larger as the aspect ratio of the contact hole becomes higher.

Similar to such a solid-state imaging device, an SGT (Surrounding Gate Transistor) is known as a semiconductor device in which a circuit element is formed on a mast. The SGT forms a gate conductor layer on the outer periphery of the mast layer via a gate insulating layer, and further has a source or drain impurity in a portion of the mast located above and below the gate conductor layer. a diffusion layer, and a column between the source and the drain impurity diffusion layer constitutes a channel of the MOS transistor (refer to, for example, Patent Document 2) 32, 33, 34).

Hereinafter, a CMOS inverter circuit using the conventional SGT will be described with reference to FIGS. 18A, 18B, and 18C. Figure 18A is a circuit diagram of an inverter circuit using SGT. It consists of two P channels SGT125a, 125b and one N channel SGT125c. The gates of all SGT125a, 125b, and 125c are connected to the input terminal Vi, and the drains of the P channels SGT125a and 125b are connected to the power supply terminal Vcc, P channel. The source of the SGTs 125a and 125b and the source of the N-channel SGT 125c are connected to the output terminal Vo, and the drain of the N-channel SGT 125c is connected to the ground terminal Vss. In this circuit, the signal voltage input to the input terminal Vi is inverted and output from the output terminal Vo. Further, the input terminal Vi is connected to the gate terminal Vi1 of the P channels SGT 125a, 125b and the gate terminal Vi2 of the N channel SGT 125c.

Fig. 18B is a plan view showing a state in which a CMOS inverter circuit shown in Fig. 18A is formed on a ruthenium oxide substrate 131 by a known technique. The source P ⁺ layer 126a of the P channels SGT 125a, 125b is formed in contact with the source N ⁺ layer 126b of the N channel SGT 125c. Further, the masts 127a and 127b forming the P-channels SGT 125a and 125b on the source P ⁺ layer 126a are formed. Further, a mast 127c of the N-channel SGT 125c is formed on the source N ⁺ layer 126b. The gate conductor layer 128a of the SGTs 125a and 125b surrounds the pillars 127a and 127b and is continuously formed, and the gate conductor layer 128a is connected to the input wiring metal layer 130a (Vi1) via the contact hole 129a. The gate conductor layer 128b of the SGT 125c is formed to continuously surround the mast 127c, and the gate conductor layer 128b is connected to the input wiring metal layer 130e (Vi2) via the contact hole 129f. The drains of the P channels SGT 125a and 125b are connected to the power supply wiring metal layer 130b (Vcc) via the contact holes 129b and 129c formed on the masts 127a and 127b. The P ⁺ layer 126a and the N ⁺ layer 126b are connected to the output wiring metal layer 130c (Vo) via a contact hole 129d formed on the boundary portion between the two. The source of the N-channel SGT 125c is connected to the ground wiring metal layer 130d (Vss) via a contact hole 129e formed on the mast 127c.

Fig. 18C is a cross-sectional structural view taken along line J-J' of Fig. 18B. As shown in Fig. 18C, a planar germanium layer 132 is formed on the buried oxide film 131, and the flat germanium layer 132 is composed of a source P ⁺ layer 126a and a source N ⁺ layer 126b, in the drain P ⁺ A surface near the boundary between the layer 126a and the drain N ⁺ layer 126b is formed with a silicide layer 133 for directly connecting the drain P ⁺ layer 126a and the drain N ⁺ layer 126b to each other. The pillars 127a, 127b on the drain P ⁺ layer 126a are formed with P channels SGT 125a, 125b, and the masts 127c on the drain N ⁺ layer 126b are formed with N channels SGT 125c. A gate insulating film 136a, 136b, 136c composed of a High-k (high dielectric constant) film of HfO ₂ or the like is formed so as to surround the pillars 127a, 127b, and 127c, and surrounds the gate insulating film 136a, In the manner of 136b and 136c, gate conductor layers 128a and 128b made of a metal film such as TaN or TiN are formed. A drain N ⁺ layer 139 is formed in an upper portion of the stem 127c forming the N-channel SGT 125c, and a drain P ⁺ layer 138a, 138b is formed in an upper region of the stems 127a, 127b forming the P-channels SGT 125a, 125b. Further, a contact stopper SiN layer 140 is formed to cover the source P ⁺ layers 138a, 138b, and an interlayer SiO ₂ layer 141 is formed on the SiN layer 140. Further, contact holes 129a, 129b, 129c, 129d, 129e, and 129f are formed to penetrate the planarized SiO ₂ layer 141.

The vaporized layer 133 at the boundary between the source P ⁺ layer 126a and the source N ⁺ layer 126b is connected to the output wiring metal layer 130c (Vo) via the contact hole 129d. The drain N ⁺ layer 139 in the upper region of the mast 127c is connected to the ground wiring metal layer 130d (Vss) via the contact hole 129e. The drain P ⁺ layers 138a and 138b forming the upper region of the pillars 127a and 127b of the P-channels SGT 125a and 125b are connected to the power supply wiring metal layer 130b (Vcc) via the contact holes 129b and 129c. The gate conductor layer 128a surrounding the masts 127a and 127b is connected to the input wiring metal layer 130a (Vi1) via the contact hole 129a, and the gate conductor layer 128b surrounding the mast 127c is connected to the input wiring via the contact hole 129f. Metal layer 130e (Vi2).

As can be understood from Fig. 18C, the contact holes 129a, 129b, 129c, 129d, 129e connected to the input wiring metal layers 130a (Vi1), 130e (Vi2), 130b (Vcc), 130c (Vo), 130d (Vss), The height of 129f is the same as that of the contact holes 129b, 129c, and 129e, and is deepened in the order of the contact holes 129d, 129a, and 129f. Further, gate conductor N ⁺ layers 128a, 128b, drain P ⁺ layers 138a, 138b, source N ⁺ layer 139, germanide layer connected at the bottom of each contact hole 129a, 129b, 129c, 129d, 129e, 129f The material of 133 is different. Therefore, as in the case of the above-described solid-state imaging device, an increase in the number of steps due to the formation of the contact holes individually, and a circuit due to the mask matching margin when the contact holes are formed are generated. The reduction in the degree of accumulation. Alternatively, when the contact holes 129a, 129b, 129c, 129d, 129e, and 129f are formed by RIE or the like, it is necessary to have good controllability on the gate conductor layers 128a, 128b, the drain P ⁺ layers 138a, 138b, 汲The surface of the pole N ⁺ layer 139 and the vaporized layer 133 is stopped, and the manufacturing of the etching mask layer after the RIE etching or the removal of the etching residue is difficult. Further, since the contact hole 129d is provided between the masts 127a and 127b of the P-channels SGT 125a and 125b and the mast 127c of the N-channel SGT 125c, the gate conductor layers 128a and 128b cannot be formed on the contact hole 129d. The gate conductor layer 128a of the P channels SGT 125a and 125b and the gate conductor layer 128b of the N channel SGT 125c are connected to the individual input wiring metal layers 130a (Vi1) and 130e (Vi2) via the individual contact holes 129a and 129f. Due to this connection configuration, the degree of accumulation of the CMOS inverter circuit as shown in Fig. 18A is lowered.

[Previous Technical Literature] [Patent Literature]

Patent Document 1: International Publication No. 2009/034623

Patent Document 2: US Patent Application Publication No. 2010/0213539

[Non-patent literature]

Non-Patent Document 1: G. Agranov, R. Mauritzson; J. Ladd, A. Dokoutchaev, X. Fan, X. Li, Z. Yin, R. Johnson, V. lenchenko v, S. Nagaraja, W. Gazeley, J. Bai, H. Lee, Takizawa Yoshihide; "Pixel Size Reduction and Feature Comparison of CMOS Image Sensors", Image Information Media Society Report, ITE Technical Report Vol. 33, No. 38, pp. 9-12 (Sept. 2009).

Non-Patent Document 2: S.G. Wuu, C.C. Wang, B.C. Hseih, Y.L. Tu, CHTseng,THHsu,RSHsiao,S.Takahashi,RJLin,CSTsai,YPChao,KYChou,PSChou,HYTu,FLHsueh,L.Tran;"A Leading-Edge 0.9μm Pixel CMOS Image Sensor Technology With Backside Illumination: Future Challenges for Pixel Scaling", IEDM 2010 Digest Papers, 14.1.1 (2010).

In the semiconductor device using the pixels of the solid-state imaging device shown in FIGS. 17A to 17D and the SGT shown in FIGS. 18A to 18C, a pixel or an SGT is also formed on the mast. As described above, when the pixel or the SGT is formed on the mast, the diffusion layer doped with the donor or acceptor impurity in the upper portion and the lower region of the mast is connected to the upper wiring metal layer via the contact hole. Therefore, at least the depth of the mast is different in the depth of the contact hole connected to the upper portion and the lower portion of the mast. Thus, when the formation of contact holes requiring different depths is required to be formed individually, the number of steps is increased, and the degree of circuit accumulation is lowered in order to ensure individual mask alignment margins at the time of formation of the contact holes. Further, when two contact holes are formed at the same time, when the contact holes are formed by RIE or the like, it is difficult to manufacture the semiconductor layers and the conductor layers with good controllability. Further, when two contact holes are formed at the same time, the etch mask layer for RIE or the like is formed to be thickened by the contact hole, and the etching mask layer after the RTE etching is removed, and even the residue is etched. Removal can become difficult. In contrast, an increase in the number of suppression steps is required, and the circuit accumulation degree is not lowered, and contact A method of manufacturing a semiconductor device and a semiconductor device in which hole formation is easy. Further, since the contact hole formation region in which the diffusion layer doped with the donor or acceptor impurity is not connected to the upper wiring metal layer is prevented from being formed on the lower portion of the mast, the conductor layer wiring is formed on the mast. The peripheral circuit causes a decrease in the degree of circuit accumulation, and therefore it is required to prevent the reduction in the degree of accumulation of this circuit.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of manufacturing a semiconductor device and a semiconductor device capable of preventing a reduction in circuit integration.

In order to achieve the above object, a method of manufacturing a semiconductor device according to a first aspect of the present invention includes a columnar semiconductor forming step of simultaneously forming a first columnar semiconductor and a second columnar semiconductor on the substrate so as to have the same height a columnar semiconductor bottom connection step of doping the donor or acceptor impurity into at least one of a bottom region of the first columnar semiconductor and a region below the bottom region to form a first semiconductor layer And connecting the first semiconductor layer and the second columnar semiconductor to each other; and the circuit element forming step of doping the donor or acceptor impurity in the upper region of the first columnar semiconductor to form an upper semiconductor region, and Forming a circuit element having the upper semiconductor region; forming a conductor layer to form a first conductor layer in the second columnar semiconductor; and forming a contact hole forming step to form a first connection between the first and second columnar semiconductors Contact hole, second contact hole; The wiring metal layer forming step forms a wiring metal layer that is connected to the upper semiconductor region and the first conductor layer via the first and second contact holes.

Further, a step of forming a second conductor layer on the same surface as the upper semiconductor region so as to be connected to the upper semiconductor region; and the step of forming the contact hole in the second conductor layer and the aforementioned The first columnar semiconductor is formed with the first and second contact holes so as to be connected to the second conductor layer and the second columnar semiconductor, and the first and second contact holes are formed in the wiring metal layer forming step. a wiring metal layer connected to the second conductor layer and the first conductor layer in the second contact hole.

The conductor layer forming step may include a step of doping the donor or acceptor impurity into the second columnar semiconductor to form the first semiconductor layer, or a step of doping the second columnar semiconductor in the second columnar semiconductor A step of forming the first semiconductor layer by embedding any one of a polycrystalline semiconductor layer, a vaporized layer, and a metal layer mixed with a donor or a receptor.

The step of forming the first insulating layer and the second insulating layer so as to surround the first and second columnar semiconductors, and the first and second insulating layers may be connected to the first and second insulating layers. The step of forming the gate conductor layer in the form of the second columnar semiconductor.

Further, a step of forming a conductor layer so as to surround the first and second insulating layers and to connect the first and second columnar semiconductors may be provided above the gate conductor layer.

The columnar semiconductor bottom connection step may be performed by doping a donor or acceptor impurity into at least one of a bottom region of the first columnar semiconductor and a region below the bottom region to form a first semiconductor. And a step of connecting the first semiconductor layer and the second columnar semiconductor to each other by forming a fourth conductor layer on the substrate.

The second insulating layer may be formed of an insulating material having a lower capacitance than the first insulating layer.

The step of simultaneously forming the first and third columnar semiconductors at the same height as each other may be provided, and an impurity diffusion layer, a vaporized layer or a metal layer containing a donor or acceptor impurity may be formed in the foregoing a step in the third columnar semiconductor; and extending the gate conductor layer to the third columnar semiconductor via the gate insulating layer on the outer circumference of the first columnar semiconductor, and surrounding the third columnar semiconductor And a step of forming the impurity diffusion layer, the vaporization layer, or the metal layer formed in the third columnar semiconductor and containing the donor or acceptor impurity in a region below the third columnar semiconductor .

Further, a semiconductor device according to a second aspect of the present invention includes: a substrate; and first and second columnar semiconductors formed on the substrate and having the same height; and a bottom region of the first columnar semiconductor and At least one of the regions below the aforementioned bottom region is doped with a donor or acceptor a first semiconductor layer is formed with impurities, and the first semiconductor layer and the second columnar semiconductor are connected to each other; and the upper portion of the first columnar semiconductor is doped with a donor or acceptor impurity. a circuit element in the upper semiconductor region; a first conductor layer formed in the second columnar semiconductor; and a first contact hole and a second contact hole respectively connected to the first and second columnar semiconductors a wiring metal layer connected to the upper semiconductor region and the first conductor layer via the first and second contact holes.

The first insulating layer and the second insulating layer may be formed to surround the first and second columnar semiconductors, respectively, and the third conductive layer may surround at least the first insulating layer of the first and second insulating layers. The method extends over the second insulating layer; the height of the third conductor layer on the outer circumference of the second columnar semiconductor is lower than the height of the third conductor layer on the outer circumference of the first columnar semiconductor. The thickness of the third conductor layer is higher.

Further, the solid-state imaging device may include the first and second columnar semiconductors and include the circuit element, and the pixel may have a bottom portion formed on the substrate as the first semiconductor layer. a semiconductor layer; the second semiconductor layer is formed over the bottom semiconductor layer in the first columnar semiconductor, and includes a phase opposite to the bottom semiconductor layer a reverse conductivity type semiconductor or an intrinsic type semiconductor; the gate conductor layer is formed on the outer periphery of the second semiconductor layer via the first insulating layer so as to be positioned above the bottom semiconductor layer; and the third semiconductor The layer is formed on the outer peripheral portion of the second semiconductor layer so as to be located above the gate conductive layer, and has the same conductivity type as the first semiconductor layer; and is connected to the fourth semiconductor layer of the upper semiconductor region. The second semiconductor layer is formed above the third semiconductor layer and has a conductivity type opposite to the bottom semiconductor layer; a bottom region of the first columnar semiconductor and the second columnar semiconductor The first conductor layers are connected to each other by the bottom semiconductor layer.

The SGT may be a semiconductor device; the SGT may be formed as the circuit element in the first columnar semiconductor; and the SGT may include a bottom semiconductor region formed as the first semiconductor layer on the substrate; a channel semiconductor layer connected to the upper portion of the bottom semiconductor region and including a semiconductor or an intrinsic semiconductor belonging to a conductivity type opposite to the bottom semiconductor region; an insulating layer formed on an outer periphery of the channel semiconductor layer; and a conductor layer interposed therebetween a gate insulating layer formed on the channel semiconductive The outer peripheral layer of the bulk layer; the upper semiconductor layer is connected to the upper portion of the channel semiconductor layer and has the same conductivity type as the bottom semiconductor region, and the bottom semiconductor region functions as a source of the SGT On the other hand, when the bottom semiconductor region functions as the drain of the SGT, it functions as a source, and the bottom semiconductor region and the second columnar semiconductor are used. The first conductor layers are connected to each other.

The solid-state imaging device may be arranged in a pixel region in which a plurality of the pixels are arranged, and the first and second columnar semiconductor systems constituting each of the pixels are arranged in two dimensions in the vertical (row) direction and the horizontal (column) direction. shape.

A solid-state imaging device may be used. The bottom semiconductor layer of the first semiconductor layer may be connected to the plurality of first columnar semiconductors in the row in a row in which the first columnar semiconductors are arranged in the vertical direction. a bottom region extending in a vertical direction (row direction) to form a first semiconductor layer connection conductor layer; wherein the first semiconductor layer connection conductor layer is connected to the first semiconductor layer connection conductor layer and each of the first a bottom region of the second columnar semiconductor adjacent to the columnar semiconductor; and the gate conductor layer of the first columnar semiconductor is shielded from light incident between the first columnar semiconductors adjacent in the column direction Ways are connected to each other, thereby forming a second semiconductor layer extending in the lateral (column) direction And the fourth layer of the first columnar semiconductor is connected to the first columnar semiconductor so as to shield the light incident between the first columnar semiconductors adjacent to each other in the row direction a third semiconductor layer connecting conductor layer of the semiconductor layer; and a plurality of the second columnar semiconductors are formed in a region in which at least one of the second and third semiconductor layer connecting conductor layers is formed, and A contact hole is formed in the columnar semiconductor, and the first semiconductor layer connection conductor layer and the wiring metal layer are connected to each other via the contact holes and the first conductor layer in each of the second columnar semiconductors.

In the pixel region in which the pixels are arranged, the bottom semiconductor layer as the first semiconductor layer is arranged in the vertical direction in the vertical direction of the first columnar semiconductor. a direction in which the first semiconductor layer connection conductor layer is formed, and the gate conductor layers of the first columnar semiconductor are connected to each other, thereby forming a second semiconductor layer connection conductor layer extending in the lateral (row) direction And a third semiconductor layer connecting conductor layer connected to the fourth semiconductor layer of the first columnar semiconductor and extending in a lateral (column) direction; and the second and third semiconductor layer connecting conductor layers from electromagnetic energy ( The energy is formed in a direction in which the waves are incident, and is formed to have a portion overlapping each other; and the second columnar semiconductor is formed on the first semiconductor layer On the conductor layer, between the first columnar semiconductors adjacent in the lateral (column) direction.

Further, in the semiconductor device having the SGT, a plurality of the first columnar semiconductors may be arranged, and the gate conductor layer of the first columnar semiconductor may be extended by connecting a plurality of the first columnar semiconductors to each other. a second columnar semiconductor formed in a region where the gate conductor layer is formed, a second insulating layer formed to surround the second columnar semiconductor, and the second insulating layer via the gate conductor layer It is formed on the outer circumference of the second columnar semiconductor.

The first columnar semiconductor and the third columnar semiconductor covered by the third insulating layer may be formed on the substrate, and the sixth semiconductor layer may be formed on the first columnar semiconductor. a seventh semiconductor layer is formed in a region below the first columnar semiconductor; a first insulating layer and a second insulating layer are formed to surround the first columnar semiconductor and the second columnar semiconductor, respectively; A first conductor layer is surrounded by the outer circumference of the first columnar semiconductor, and a fifth conductor layer composed of at least one layer is formed so as to surround the second insulating layer on the outer circumference of the second columnar semiconductor. The fifth conductor layer is connected to the upper surface of the third columnar semiconductor, and is connected to the third columnar semiconductor, the sixth semiconductor layer of the first columnar semiconductor, and the second columnar semiconductor. A contact hole is formed, and a wiring metal layer connected to any one of the sixth semiconductor layer, the seventh semiconductor layer, and the fifth conductor layer via the contact hole is provided.

The first insulating layer and the second insulating layer may be formed to surround the first columnar semiconductor and the second columnar semiconductor, respectively, and the seventh conductive layer may be formed to surround the first insulating layer. The seventh conductor layer extends to the second columnar semiconductor; the seventh conductor layer is formed on the outer circumference of the second columnar semiconductor via the second insulating layer, and is on the upper portion of the second columnar semiconductor. Connected to the first conductor layer.

The first and third columnar semiconductors may be formed to have the same height, and an impurity diffusion layer or a telluride layer containing a donor or acceptor impurity may be formed in the third columnar semiconductor. a metal layer; a gate conductor layer is formed on the outer periphery of the first columnar semiconductor via a gate insulating layer; the gate conductor layer extends to the third columnar semiconductor and surrounds the third columnar semiconductor Further, an impurity diffusion layer, a vaporization layer or a metal layer containing a donor or acceptor impurity formed in the third columnar semiconductor is connected to a lower region of the third columnar semiconductor.

According to the method of manufacturing a semiconductor device and the semiconductor device of the present invention, the upper and lower regions of the columnar semiconductor constituting the circuit element are matched It is easy to connect the wiring layer placed above the columnar semiconductor, and it is possible to achieve high integration, high-speed driving, and stable operation of the semiconductor device having the circuit element.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention and a semiconductor device manufactured by the method of the present invention will be described with reference to the drawings.

(First embodiment)

Hereinafter, a solid-state imaging device according to a first embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS. 1A, 1B, 2A, and 2F.

Fig. 1A is a plan view showing the solid-state imaging device of the embodiment. In the pixel region of the solid-state imaging device, the masts P ₁₁ to P ₃₃ constituting the pixels are arranged in a two-dimensional (matrix) shape in the vertical (row) direction and the horizontal (column) direction. The columns P ₁₁ to P ₃₃ are formed on the yttrium oxide substrate 1 and formed on the signal line N ⁺ layers 5a, 5b, 5c extending in the longitudinal (row) direction of the first A-picture to the peripheral driving/outputting circuit region. on. The signal line N ⁺ layers 5a, 5b, and 5c are in the peripheral drive/output circuit region provided in the upper portion and the left portion of the first A-A through the contact hole SCa formed on the second masts Ca, Cb, and Cc. The SCb and SCc are connected to the signal line metal layers 26a, 26b, and 26c.

The masts P ₁₁ to P ₃₃ are surrounded by the reset MOS gate conductor layers 7a, 7b, 7c extending in the lateral (column) direction.

The pixel selection line conductor layers 14a, 14b, 14c extend in the lateral (column) direction of the first AA to the peripheral drive/output circuit region, and are driven/outputted at the periphery. In the circuit region, the pixel selection line metal layers 17aa, 17ab, and 17ac are connected via the contact holes 16aa, 16ab, and 16ac.

Fig. 1B is a cross-sectional structural view taken along line A-A' shown in Fig. 1A. A flat signal line N ⁺ layer 5 (5a) is formed on the ruthenium oxide substrate 1. On the signal line N ⁺ layer 5 (5a), a first mast 2 (P ₁₁ ) constituting a pixel and a second mast 3 (Ca) constituting a contact are formed. The signal line N ⁺ layer 5 (5a) is formed in a lower region of the first and second masts 2 (P ₁₁ ) and 3 (Ca) by thermal diffusion of donor impurities.

Insulating layers 4b and 4c made of yttrium oxide (SiO ₂ ) are formed so as to cover the first and second masts 2 (P ₁₁ ) and 3 (Ca) and the signal line N ⁺ layer 5 (5a). The insulating layer 4b here is a gate insulating layer. Further, an SiO ₂ layer 6 is formed on the yttrium oxide substrate 1, and a reset MOS gate is formed on the SiO ₂ layer 6 and the outer periphery of the gate insulating layer 4b of the first pillar 2 (P ₁₁ ). Conductor layer 7 (7a). The photodiode N layer 9 is formed on the outer peripheral portion of the P layer 8a in the upper portion of the first mast 2 (P ₁₁ ) so as to be adjacent to the reset MOS gate conductor layer 7 (7a). Further, an SiO ₂ layer 10 is formed on the SiO ₂ layer 6.

In the upper region of the first mast 2 (P ₁₁ ), a pixel selection P ⁺ layer 11 is formed. Further, in the second column 3 (Ca), the conductor N ⁺ layer 13 is formed by introducing a donor impurity. Further, a pixel selection line conductor layer 14 (14a) connected to the pixel selection P ⁺ layer 11 is formed. Further, the SiO ₂ layer 15 is deposited in such a manner as to cover the entirety of the structures.

Further, in the SiO ₂ layer 15, contact holes 16a (16aa) and 16b (SCa) are formed. The pixel selection line conductor layer 14 (14a) and the pixel selection line metal layer 17a (17aa) are connected via the contact hole 16a (16aa), and the conductor N ⁺ layer 13 and the signal line metal layer 17b are connected via the contact hole 16b (SCa) (26a). Here, contact holes 16a (16aa) and 16b (SCa) having the same depth are formed on the first and second masts 2 (P ₁₁ ) and 3 (Ca).

Hereinafter, a method of manufacturing the solid-state imaging device according to the embodiment will be described with reference to FIGS. 2A to 2F. This manufacturing method is a method of manufacturing the solid-state imaging device of the cross-sectional structure diagram shown in FIG. 1B.

The method of manufacturing a solid-state imaging device according to the present embodiment includes a columnar semiconductor forming step of forming a flat layer of germanium layer 5S on the tantalum oxide substrate 1, and forming pixels of the solid-state imaging device on the flat layered layer 5S. The first column 2 and the second column 3 constituting the contact window are formed at the same height and simultaneously; the columnar semiconductor bottom connection step is performed by doping the donor or acceptor impurity into the bottom region of the first column 2 and Forming a signal line N ⁺ layer 5 at least one of the regions adjacent to the bottom region, and connecting the signal line N ⁺ layer 5 and the second mast 3 to each other; the circuit element forming step, the donor or the receiving The bulk impurity is doped in the upper region of the first mast 2 to form the P ⁺ layer 11 and the circuit component having the P ⁺ layer 11 is formed; the conductor layer forming step forms the conductor N ⁺ layer 13 in the second mast 3 a pixel selection line conductor layer forming step of connecting to the P ⁺ layer 11 formed on the upper portion of the first mast 2 and forming a pixel selection line conductor layer 14 on the same surface as the P ⁺ layer 11; the contact hole is formed Steps, forming respectively connected to the first column 2 or pixel selection 14, the second silicon column line contact hole 3 of the conductor layers 16a, 16b; step of forming a wiring metal layer, 16a 2 is formed connected to the upper region of the first silicon pillar 11 of the P ⁺ layer or P ⁺ layer via the contact hole 11 connected pixel selection line conductor layer 14 of pixel selection line metal layer 17a, and via contact hole 16b formed with signal line metal layer 17b connected to conductor N ⁺ layer 13 of second mast 3; respectively, to surround the first mast 2. a step of forming the SiO ₂ layers 4b, 4c in the manner of the second column 3; and forming a gate conductor layer composed of at least one layer so as to surround at least the SiO ₂ layer 4b of the SiO ₂ layers 4b, 4c 7 is a step of connecting to the SiO ₂ layer 4c.

Here, a pixel as a circuit element is formed by the gate conductor layer 7 and the photodiode, and the gate conductor layer 7 is formed on the outer periphery of the P layer 8a via the SiO ₂ layer 4b, and the photodiode system The N layer 9 formed on the outer peripheral portion of the P layer 8a so as to be adjacent to the P layer 8a and the gate conductor layer 7 formed on the signal line N ⁺ layer 5 is included.

Hereinafter, a method of manufacturing the solid-state imaging device according to the present embodiment will be described in more detail with reference to FIGS. 2A to 2F.

As shown in FIG. 2A, in the pixel region of the solid-state imaging device of the present embodiment, a flat ruthenium layer 5S is formed on the ruthenium oxide substrate 1, and the first constituting pixel is formed on the flat ruthenium layer 5S.矽柱2. Further, in the peripheral drive/output circuit region, the second mast 3 constituting the contact window is formed. Thereby, the first mast 2 and the second mast 3 are connected via the flat layer 5S.

Next, as shown in FIG. 2A, the tantalum layer having the heights of the first and second masts 2, 3 on the tantalum oxide substrate 1 is made of a Si oxide film (SiO ₂ mill) and a Si nitride film. (Si ₃ N ₄ film) is etched to the height of the flat ruthenium layer 5S by the Si etching performed by the RIE of the mask, and the first mast 2 and the second mast 3 are at the same height as each other. form.

Next, as shown in FIG. 2B, the SiO ₂ layer 4a is formed on the surfaces of the first and second columns 2, 3 and the first and second columns 2 and 3.

Next, as shown in FIG. 2B, the ruthenium layer between the first column 2 and the second column 3 is ion-implanted with, for example, As, P, etc., and is thermally diffused, and is in a flat shape. The 矽 layer 5S and the lower region of the first and second masts 2, 3 form an N ⁺ layer 5 as a signal line.

Next, as shown in FIG. 2B, the SiO ₂ layer 4a is deposited by CVD (Chemical Vapor Deposition), and by performing etch back, the first mast 2 and the second crucible are used. An SiO ₂ layer 6 is formed on the yttrium oxide substrate 1 between the pillars 3.

Next, the SiO ₂ layer 4a is removed, and as shown in FIG. 2C, the surface of the first mast 2 and the second mast 3 is oxidized and the gate SiO ₂ layer of the MOS transistor is formed in the first mast 2 4b, and forming an SiO ₂ layer 4c on the surface of the second column 3, and forming a MOS transistor using tungsten (W), nickel (Ni), cobalt (Co), titanium (Ti) or the like Gate conductor layer 7.

Next, as shown in FIG. 2D, a CVDSiO ₂ film ion-implanted or doped with a donor impurity such as arsenic (As) is used as a diffusion source, and adjacent to the gate conductor layer 7, On the outer peripheral portion of the P layer 8 of the mast 2, an N layer 9 constituting the photodiode is formed.

Next, as shown in FIG. 2D, the SiO ₂ film 10 is deposited by CVD, and the plane of the SiO ₂ layer 10 is planarized by etching, and then over the P layer 8a and the N layer 9 by Ion implantation of bulk impurities forms a pixel-selective P ⁺ layer 11 in the upper region of the first mast 2 .

Next, as shown in FIG. 2E, a photo resist layer 12 having a through hole is formed in a region above the second mast 3 by photolithography, and phosphorus (P) or the like is applied. The bulk impurities are ion-implanted into the second column 3 to form the conductor N ⁺ layer 13. Here, since it is preferable to form the conductor N ⁺ layer 13 as a whole in the second column 3 in this manner, in the ion implantation here, it is preferable to use the same acceleration voltage to introduce impurities into the Si. The ion implantation method of the channeling phenomenon.

Next, the photoresist layer 12 is removed, and an activation heat treatment of the donor impurities by ion implantation is performed.

Next, as shown in FIG. 2F, the pixel selection line conductor layer 14 connected to the pixel selection P ⁺ layer 11 of the first mast 2 is formed.

Next, as shown in FIG. 2F, on the SiO ₂ film 10, the SiO ₂ layer 15 is formed by CVD, and the contact holes 16a, 16b are formed in the SiO ₂ layer 15.

Next, as shown in FIG. 2F, the pixel selection line conductor layer 14 and the pixel selection line metal layer 17a are connected via the contact hole 16a, and the conductor N ⁺ layer 13 and the signal line metal layer 17b are connected via the contact hole 16b. Here, the signal line N ⁺ layer 5 located in the lower region of the first mast 2 is connected to the signal line metal layer 17b via the conductor N ⁺ layer 13 formed in the second mast 3 .

Thereby, the pixel located in the upper portion of the first mast 2 constituting the pixel selects the P ⁺ layer 11 and the signal line N ⁺ layer 5 located in the lower region of the first mast 2, that is, via the contact holes of the same depth to each other. 16a and 16b are connected to the pixel selection line metal layer 17a and the signal line metal layer 17b.

Connected to the first silicon pillar P 2 of the pixel selection line ⁺ layer 11 of the conductor layer 14, formed in the upper two lines in the region of the first silicon pillar P ⁺ layer 11 is connected to the side surface of the P ⁺ layer 11. The contact hole 16a on the pixel selection line conductor layer 14 and the contact hole 16b on the second mast 3 are formed to have substantially the same depth.

According to the present embodiment, the pixels constituting the solid-state image pickup apparatus of (circuit element) of the first silicon pillar 2, P ₁₁ to P _33, and forming the contact windows of the second silicon pillar 3, Ca (3), Cb , Cc, based in The way to become the same height of each other and at the same time. Thereby, the signal line N ⁺ layers 5, 5a, 5b, 5c located in the lower region of the first mast 2, P ₁₁ to P ₃₃ , and the pixel located in the upper region can be selected as the P ⁺ layer 11 ( Contacted in the first column 2, P ₁₁ to P ₃₃ in FIG. 1A) is connected to the contact of the signal line metal layers 17b, 26a, 26b, 26c and the pixel selection line metal layers 17a, 17aa, 17ab, 17ac. The holes 16a, 16b, SCa, SCb, SCc, 16aa, 16ab, 16ac are set to have the same depth. Further, the contact holes 16b, SCa (16b), SCb, and SCc do not need to be set to a deep contact hole as the contact hole 123a of the conventional example shown in Fig. 17B. Thereby, the signal lines N ⁺ layers 5, 5a (5), 5b, 5c located in the upper and lower regions of the first mast 2 via the contact holes 16a, 16b can be easily realized, and the pixel selection P ⁺ layer 11 (in the first 1A is located above the first masts P ₁₁ to P ₃₃ ), and is connected to the signal line metal layers 17b, 26a, 26b, and 26c and the pixel selection line metal layers 17a, 17aa, 17ab, and 17ac.

Generally, in order to enhance the sensitivity of the solid imaging device of a red wavelength, the need to form a first silicon pillar of the pixel 2, the height P ₁₁ to P ₃₃ increases, and the need to belong to the photoelectric conversion region of the diode length is increased. This is because the red wavelength light is absorbed by the light in the deeper Si than the blue and green wavelength light, and the signal charge is generated. Therefore, when the light diode is to absorb more of the incident red wavelength light, At the time, the first mast 2, P ₁₁ to P _{33 must be} increased. However, in the prior art, the depth of the contact hole 123a for connecting the signal line N ⁺ layer 116 and the signal line metal layer 124a may become larger. On the other hand, the solid-state imaging device obtained in the present embodiment is connected to the signal line metal layers 17b, 26a, 26b, and 26c, and the contact holes 16a and 16b of the pixel selection line metal layers 17a, 17aa, 17ab, and 17ac, SCa, SCb, SCc, 16aa, 16ab, 16ac are always formed in such a manner that the height is small and the heights are the same as each other. Therefore, the solid-state imaging device of the present embodiment is particularly effective when obtaining a solid-state imaging device having high red wavelength sensitivity.

(Second embodiment)

3A to 3C are views showing a method of manufacturing the solid-state imaging device according to the embodiment. In the present embodiment, the signal line N ⁺ layer 5 and the signal line metal layer are formed by forming the germanide layer 23 in place of the conductor N ⁺ layer 13 of the second column 3 constituting the contact window in FIG. 1B. The resistance value between 17b is reduced.

In the present embodiment, first, the steps shown in Figs. 2A to 2D in the first embodiment are performed.

Next, as shown in FIG. 3A, the pixel selection line conductor layer 14 connected to the P ⁺ layer 11 of the first column 2 is formed, and the SiO ₂ layer 18 and the photoresist layer 19 are formed by CVD, and by light. Through holes 20 are formed in the second mast 3 by lithography and etching.

Next, as shown in FIG. 3A, ions are implanted into the second column 3 by impurities such as cerium (Si) or hydrogen (H) which are not donors or acceptors, and the second column 3 is After the formation of the amorphous or porous tantalum layer 21, the photoresist layer 19 is removed.

Next, as shown in FIG. 3B, the metal layer 22 of nickel (Ni), cobalt (Co), tantalum (Ta), tungsten (W), titanium (Ti) or the like is covered and heat-treated by a vapor deposition method. After the formation of the amorphous or porous tantalum layer 21 via the vaporized telluride layer 23, the metal layer 22 is removed. The vaporized layer 23 is formed of a material such as NiSi ₂ , CoSi ₂ , TaSi ₂ , WSi ₂ , or TiS ₂ .

Next, as shown in FIG. 3C, contact holes 16a, 16b are formed in the SiO ₂ layer 18, and a pixel selection line metal layer 17a in which the pixel selection line conductor layer 14 is connected via the contact hole 16a is formed. Further, a signal line metal layer 17b connected to the vaporized layer 23 via the contact hole 16b of the second column 3 is formed.

According to the present embodiment, since the conductor N ⁺ layer 13 formed in the second mast 3 of the first embodiment has the vaporized layer 23 having a low resistance value, the signal line N ⁺ layer 5 and the signal line metal layer 17b can be lowered. The resistance value between. Since the wiring resistance value R between each of the signal lines between the N ⁺ layer 5 and the signal line metal layer 17b, and a signal line from the N ⁺ layer 5 to the signal line metal layer 17b of the capacitor C of the RC product is smaller, a pixel driving speed is The larger the size, the higher the driving speed of the solid-state imaging device can be achieved by the telluride layer 23.

(Third embodiment)

Hereinafter, a method of manufacturing the solid-state imaging device according to the embodiment will be described with reference to FIGS. 4A to 4D and 5 . In the present embodiment, the metal layer 70a, 70b such as tungsten (W) or copper (Cu) is formed instead of the conductor N ⁺ layer 13 of the second column 3 constituting the contact window in Fig. 1B. The resistance value between the signal line N ⁺ layer 5 and the signal line metal layer 73b is reduced.

In the present embodiment, first, the steps shown in Figs. 2A to 2C in the first embodiment are performed.

Next, as shown in FIG. 4A, an N layer 9 constituting a photodiode is formed on the outer peripheral portion of the first mast 2, and the first mast 2, the second mast 3, and the SiO ₂ layer are formed by CVD. A nitrided Si (SiN) layer 64 is formed over 6.

Next, as shown in FIG. 4A, the entire structure is covered by the SiO ₂ layer 65, and the surface of the SiO ₂ layer 65 is polished to the first column 2 by CMP (Chemical Mechanical Polishing). And the surface of the SiN layer 64 on the second column 3.

Next, as shown in FIG. 4B, the SiO ₂ layer 65 is etched back by RIE until the upper portion of the first mast 2 and the second post are exposed, and the exposed first post is covered by etching. The SiO ₂ layer 4b of ₂ and the SiN layer 64 are removed to form a pixel selective P ⁺ layer 11.

Next, as shown in FIG. 4B, the pixel selection line conductor layer 14 is formed in such a manner as to be connected to the pixel selection P ⁺ layer 11, and the SiO ₂ layer 66 is formed by CVD to cover the entire structure.

Next, as shown in FIG. 4B, the SiO ₂ layer 66 is polished to the surface of the SiN layer 64 on the second column 3 by CMP.

Next, as shown in FIG. 4B, a through hole 68 is formed on the second mast 3 by the photolithography method using the photoresist layer 67, and the photoresist layer 67 is used as an etching mask, and the second layer is formed. The layer of the SiN layer 64, the SiO ₂ layer 4c, and the second column 3 on the column 3 is etched to form a through hole 68a.

Next, as shown in FIG. 4C, the photoresist layer 67 is removed, and a titanium nitride (TiN) layer 69 is formed on the surface of the SiO ₂ layer 4c at the bottom and sidewalls of the through hole 68a, and the TiN layer 69 is formed by CVD. A tungsten (W) layer 70 is deposited thereon.

Next, as shown in Fig. 4D, the W layer 70 is polished to the surface of the SiO ₂ layer 66 by CMP, and the SiO ₂ layer 71 is deposited as a whole by CVD, and contact holes 72a, 72b are formed.

Next, as shown in FIG. 4D, the pixel selection line conductor layer 14 and the pixel selection line metal layer 73a are connected via the contact hole 72a, and the W layer 70a and the signal line metal layer 73b are connected via the contact hole 72b.

Thereby, the conductor layer formed on the second mast 3 is the conductor N ⁺ layer 13 in the structure shown in FIG. 2F, and the vaporized layer 23 in the structure shown in FIG. 3C. Here, in the present embodiment, the W layer 70a having a lower electric resistance is used.

Fig. 5 shows a copper (Cu) layer 70b formed in place of the aforementioned W layer 70a as a conductor layer formed in the second mast 3. Although the W layer 70a described above is formed by a CVD method, the Cu layer 70b is formed by an electro-chemical plating method (Electrochemical Deposition) method. Further, in the formation of the W layer 70a, in order to make the adhesion between the SiO ₂ layers 66, 4b and the W layer 70 good in the aforementioned W layer 70, the TiN layer 69 is used as a primer. When the Cu layer 70b is formed, a barrier seed layer 69a is used as an undercoat layer of the Cu layer 70b, and the barrier seed layer 69a is included to prevent Cu from diffusing to the SiO ₂ layer. A barrier layer made of TiN, TaN, or the like of 4b, 65, and 66, and a seed layer formed of Cu formed by a sputtering method as an electrode for Cu electric field plating. Further, the SiO ₂ layer 71 is deposited by CVD, and the contact holes 72a and 72b are formed in the SiO ₂ layer 71. Then, the pixel selection line conductor layer 14 is connected to the pixel selection line metal layer 73a via the contact hole 72a, and the Cu layer 70b is connected to the signal line metal layer 73b via the contact hole 72b.

(Fourth embodiment)

Hereinafter, a method of manufacturing the solid-state imaging device according to the embodiment will be described with reference to Fig. 6. In the cross-sectional structure of Fig. 1B of the first embodiment, the first mast 2 and the second mast 3 are formed on the signal line N ⁺ layer 5 (5a), whereas in the present embodiment, The signal line N ⁺ layer 5 (5a) is a metal material such as W, Co, or Ti formed on the yttrium oxide substrate 1, or a conductor layer containing the metal material.

Fig. 6 is a cross-sectional structural view of the solid-state imaging device corresponding to Fig. 1B.

Referring to Fig. 6, first, a signal line conductor layer 28 is formed on a ruthenium oxide substrate 1 by CVD, a metal material such as W, Co, or Ti, or a material containing the same.

Next, the first column 2a constituting the pixel and the second column 3a constituting the contact window are formed on the signal line conductor layer 28, and the first column 2a and the second column 3a are surrounded to form the SiO ₂ layer 29a. 29b.

Next, the gate conductor layer 30a is formed via the SiO ₂ layer 29a in the lower region of the first mast 2a so as to surround the first mast 2a, and is in the first mast 2a and the second mast 3a. In the lower region, N ⁺ layers 31a, 31b connected to the signal line conductor layer 28 are formed.

Next, an N layer 32 constituting the photodiode is formed on the outer peripheral portion of the first mast 2a above the gate conductor layer 30a.

Next, between the first column 2a and the second column 3a, the SiO ₂ layer 10a is formed by CVD, and a pixel selective P ⁺ layer is formed above the N layer 32 and above the first column 2a. 33.

Next, the pixel selection line conductor layer 14 is formed in such a manner that the P ⁺ layer 33 is selected in connection with the pixel.

Next, the donor or acceptor impurity is doped to the inside of the upper side of the second column 3a, or the germanide-formed conductor layer 35 is formed.

Next, an SiO ₂ layer 15 is formed in an upper region of the SiO ₂ layer 10a, the first column 2a, and the second column 3a, and a contact hole 16a and a second column are formed on the pixel selection line conductor layer 14, respectively. A contact hole 16b is formed on 3a.

Next, the pixel selection line metal layer 17a is formed to be connected to the pixel selection line conductor layer 14 via the contact hole 16a, and the signal line metal layer 17b is formed to be connected to the conductor layer 35 via the contact hole 16b.

In the step shown in FIG. 1B, the first mast 2 of the pixel region and the second mast 3 which forms a contact window existing in the peripheral drive/output circuit region are connected to each other via the signal line N ⁺ layer 5. On the other hand, in the present embodiment, the signal line N ⁺ layer 31a located in the lower region of the first mast 2a is made of a metal such as W, Ni, Co, or the like having a lower electric resistance than the N ⁺ layer 5. Since the signal line conductor layer 28 is connected, the resistance for connecting the drive-output circuit provided at the periphery of the pixel region and the signal line between the pixels located in the pixel region can be reduced. As a result, high-speed driving of the solid-state imaging device can be achieved.

(Fifth Embodiment)

The solid-state imaging device according to the embodiment will be described below with reference to FIGS. 7A to 7D. According to the present embodiment, the problem of high-speed driving in the solid-state imaging device of the conventional example shown in FIG. 17C and the problem of high pixel integration in the solid-state imaging device of the conventional example shown in FIG. 17D are improved. .

Fig. 7A is a view showing a cross-sectional structure formed by the same steps as the manufacturing steps shown in Figs. 2A to 2C. In the present embodiment, the second mast 3a constituting the contact window is formed adjacent to the first mast 2 constituting the pixel in the pixel region, and the third mast constituting the contact window is formed in the peripheral drive/output circuit region. 3b. This third column 3b is formed by being separated from the signal line N ⁺ layer. The gate conductor layer 7a is formed so as to surround the SiO ₂ layers 4b, 4c, and 4d which are formed to cover the first to third pillars 2, 3a, and 3b. The gate conductor layer 7a is formed to connect the first to third masts 2, 3a, and 3b to each other, and is formed to cover the third mast 3b.

Fig. 7B is a view showing a cross-sectional structure formed by the same steps as those of the 2D, 2E, and 2F. In the second F diagram, the pixel selection line conductor layer 14 is separated from the second mast 3 constituting the contact window. However, in the present embodiment, as shown in Fig. 7B, the pixel selection line conductor layer 14d is from the first The pixel on the mast 2 is formed so that the P ⁺ layer 11 extends so as to be formed on the outer circumference of the SiO ₂ layer 4c surrounding the second mast 3a. The pixel selection line conductor layer 14d is connected to the pixel selection line metal layer 17a via the contact hole 16a. The signal line N ⁺ layer 5 is connected to the signal line metal layer 17b via the conductor layer 23 (21) of the second column 3a constituting the contact window and the contact hole 16b. Further, the gate conductor layer 7a surrounds the outer circumference of the second mast 3a, and extends to the third mast 3b, and further extends to the upper surface of the third mast 3b. Further, the gate conductor layer 7a is connected to the gate conductor layer 17c from the third mast 3b via the contact hole 16c.

Fig. 7C is a plan view showing a state in which the gate conductor layer 7a is formed on the outer circumference of the second mast 3a constituting the contact window shown in Fig. 7B. Along the 7C The cross-sectional structural diagram of the B-B' line in the figure corresponds to Fig. 7B.

In the pixel region shown in Fig. 7B, only the first column P ₁₁ of the first pixel constituting the B-B' line which is repeatedly arranged in the horizontal (column) direction of the seventh drawing is shown (the seventh column) 1 column 2), and the second column C ₁₁ constituting the contact window (the second column 3a of Fig. 7B). In an actual solid-state imaging device, the first mast P ₁₁ constituting the pixel and the second mast C ₁₁ constituting the contact window are paired, and the pair is in the vertical (row) and the horizontal (column). The directions are arranged in a two-dimensional shape. In the solid-state imaging device of the present embodiment, the signal line N ⁺ layers 5a (5), 5b, and 5c are formed to extend in the vertical (row) direction. On the signal line N ⁺ layers 5a (5), 5b, and 5c, the first masts P ₁₁ to P _{33 are formed} , and the first masts P ₁₁ to P _{33 are} adjacent to each other and arranged in the horizontal (column). In this manner, the second cylinders C ₁₁ to C ₃₃ constituting the contact window are formed. At the same time, the third masts 36a (3b), 36b, and 36c are formed in the peripheral drive/output circuit region so as to be connected to the gate conductor layers 7aa (7a), 7ab, and 7ac. The lower regions of the first and second masts P ₁₁ to P ₃₃ and C ₁₁ to C ₃₃ are connected to the signal line N ⁺ layers 5a (5), 5b, and 5c. The gate conductor layers 7aa (7a), 7ab, and 7ac are formed on the outer circumferences of the first to second masts P ₁₁ to P ₃₃ and C ₁₁ to C _{33 so as} to extend in the lateral (column) direction. Further, the gate conductor layers 7aa (7a), 7ab, and 7ac extend to the third masts 36a (3b), 36b, and 36c in the peripheral drive/output circuit region. Similarly, the pixel selection line conductor layers 14a (14d), 14b, and 14c are formed on the first to second masts P ₁₁ and C ₁₁ to C _{33 so as} to extend in the lateral (column) direction in FIG. 7C. Outside the week. Pixel selection line conductor layer 14a (14d), 14b, 14c in line (column) extending in the transverse direction is formed in the first and the second silicon pillar P ₁₁ to P _33, C ₁₁ to C ₃₃ outside weeks. Further, in the peripheral driving circuit region, the pixel selection line metal layers 17aa (17a), 17ab, and 17cc are connected via the contact holes 16aa (16a), 16ab, and 16ac. The gate conductor layers 7aa (7a), 7ab, and 7ac are connected to the gate conductor layer 38a (17c) via contact holes 37a (16c), 37b, 37c formed on the third masts 36a (3b), 36b, 36c. , 38b, 38c. The signal line N ⁺ layers 5a, 5b, 5c are connected to the signal line metal layer 26a (17b) via contact holes SC ₁₁ to SC ₂₃ formed on the second pillars C ₁₁ to C ₃₃ constituting the contact window. ), 26b. As a result, in the solid-state imaging device of the conventional example shown in FIG. 17C, the pixel region is formed via the signal line N ^{+ which} is formed at the lowest position of the first pillars P ₁₁ to P ₃₃ constituting the pixel. In the layers 116a, 116b, and 116c, the signal lines are taken out in the peripheral driving/outputting circuit region. In contrast, in the present embodiment, the signal line metal layers 26a (17b) and 26b are provided with low resistance. Take out the signal line. As a result, according to the solid-state imaging device of the present embodiment, high-speed driving can be realized as compared with the solid-state imaging device of the conventional example.

Furthermore, according to the present embodiment, the pixel integration degree of the pixel region can be improved.

That is, in the conventional technique shown in Fig. 17D, the signal line N ⁺ layers 130a, 130b, 130c formed at the lowest of the first masts P ₁₁ to P ₃₃ constituting the pixel are connected to the most The contact holes CH ₁₁ to CH _{33 of the} upper signal line metal layers 135a, 135b, and 135c cannot be formed to be reset with the MOS transistors formed above the signal line N ⁺ layers 130a, 130b, and 130c in plan view. The MOS gate conductor layers 131a, 131b, and 131c and the pixel selection line conductor N ⁺ layers 132a, 132b, and 132c overlap. Therefore, the reset MOS gate conductor N ⁺ layers 131a, 131b, 131c and the pixel selection line conductor N ⁺ layers 1323, 132b, 132c are wired so as to avoid the contact holes CH ₁₁ to CH ₃₃ . On the other hand, in the present embodiment, the gate conductor layers 7aa (7a), 7ab, 7ac, and the pixel selection line conductor layers 14a (14d), 14b, and 14c are along the second mast C ₁₁ constituting the contact window. The outer circumference to C ₃₃ is formed to overlap in plan view. As a result, according to the solid-state imaging device of the present embodiment, the pixel accumulation degree of the pixel region can be improved as compared with the solid-state imaging device of the conventional example.

In the cross-sectional structure shown in FIG. 7B, the insulating layer 4c formed on the outer periphery of the second mast 3a constituting the contact window is made of the same material layer as the gate insulating layer 4b formed on the outer periphery of the first mast 2 And formed. Generally, in the gate insulating layer 4b, a high dielectric constant (High-K) material layer is used. Therefore, the bonding capacitance of the gate conductor layer 7a and the pixel selection line conductor layer 14b formed on the outer circumference of the second mast 3a constituting the contact window and the conductor layer 23 (21) in the second mast 3a constituting the contact window Will get bigger. Due to the increase in the combined capacitance between the gate line/signal line and the pixel selection line/signal line, the effect of high-speed driving of the solid-state imaging device is impaired. Further, in this case, the mutual drive pulse noise is mixed between the gate line/signal line and the pixel selection line/signal line to impair the stable driving of the solid-state imaging device. Therefore, in order to drive the high-speed driving/stabilization of the solid-state imaging device, it is required to reset the capacitance between the gate line-signal line and the capacitance between the pixel selection line and the signal line.

Fig. 7D is a cross-sectional structural view showing the solid-state imaging device in which the capacitance between the gate line and the signal line is reset and the capacitance between the pixel selection line and the signal line is further reduced. The structure shown in Fig. 7D is the same as the structure shown in Fig. 7B except that the conductor layer 23 (21) constituting the second mast 3a of the contact window is formed to form the low-capacitance insulating layer 4e. The low-capacitance insulating layer 4e is a low dielectric constant (Low-k) insulating layer of a fluorine-containing (F) or carbon (C) oxide film (SiOF, SiOC), a porous SiO ₂ film, or the like, and a thick SiO. _A film or a combination of an insulating film such as a SiO ₂ film and a low dielectric constant insulating film is formed. The bonding capacitance formed between the gate conductor layer 7a and the pixel selection line conductor layer 14d and the conductor layer 23 (21) connected to the signal line N ⁺ layer 5 is lowered by the low capacitance insulating layer 4e. Thereby, high-speed driving and stable driving of the solid-state imaging device can be achieved.

(Sixth embodiment)

Hereinafter, the solid-state imaging device according to the embodiment will be described with reference to Figs. 8A and 8B. In the fifth embodiment, the resolution of the solid-state imaging device is lowered, the color mixing characteristics in the color image pickup device are further improved, and the manufacturing process of the contact hole is facilitated.

Fig. 8A is a plan view showing the solid-state imaging device of the embodiment. The signal line N ⁺ layers 80a, 80b, and 80c are formed to extend in the vertical (row) direction. In the pixel region, this N ⁺ layer signal lines such as 80a, 80b, 80c on, a first silicon pillar constituting the pixel P ₁₁ to P _{33 is} of the second silicon pillar and the contact window ₁₁ constituting the C to C ₃₃ are formed. Simultaneously with the masts, the third masts 40a, 40b, and 40c constituting the contact windows are formed in the flat-plate layers 39a, 39b, and 39c formed in the peripheral drive/output circuit region. The first masts P ₁₁ to P ₃₃ and the second masts C ₁₁ to C ₃₃ constituting the contact window are alternately arranged in the vertical (row) direction in the pixel region. Gate conductor layers 81a, 81b, 81c based formed on the outer periphery ₁₁ to P _{33 is} composed of the first silicon pillar P pixels of, and side surround is formed first between the first silicon pillar P extending the in towards the column direction ₁₁ to P _{33 is} The two columns C ₁₁ to C ₃₃ are formed to extend in the lateral (column) direction. The gate conductor layers 81a, 81b, and 81c are connected to the gate via contact holes 41a, 41b, and 41c formed in the third masts 40a, 40b, and 40c of the peripheral drive/output circuit region constituting the contact window. Conductor layers 42a, 42b, 42c. And the same, the pixel selection line extending each conductor layer 82a, 82b, 82c toward a column direction line by a first silicon pillar P ₁₁ to P _33, FIG. 8A to the horizontal toward the second formation (column) extending in the direction of the way. The pixel selection line conductor layers 82a, 82b, 82c are extended to the outside of the pixel region, and are connected to the pixel selection line metal layers 17aa, 17ab via the contact holes 16aa, 16ab, 16ac in the peripheral driving/output circuit region. 17ac. The gate conductor layers 81a, 81b, and 81c are formed along the outer circumferences of the first masts P ₁₁ to P ₃₃ constituting the pixels and the second masts C ₁₁ to C ₃₃ constituting the contact window, and are selected from pixels. The line conductor layers 82a, 82b, and 82c are alternately formed to extend in the lateral (column) direction. The signal line N ⁺ layer 80a and the signal line metal layer 83a, the signal line N ⁺ layer 80b and the signal are respectively connected via the contact holes H ₁₁ to H ₃₃ formed on the second masts C ₁₁ to C ₃₃ constituting the contact window. The line metal layer 83b, the signal line N ⁺ layer 80c, and the signal line metal layer 83c. The pixel regions are shielded light gate conductor layers 81a, 81b, 81c and pixel selection line conductor layers 82a, 82b, 82c, except for the first pillars P ₁₁ to P ₃₃ constituting the pixels, viewed from the light incident surface side. Covered.

8B is a cross-sectional structural view of the C-C' line shown in FIG. 8A (in FIG. 8B, only the pixel region is formed in the first column P ₁₁ constituting the pixel, and is formed in the P ₁₁ constituting the bottom of the contact hole of the first silicon pillar of the second silicon column C _11, and the contact window column C _12, C ₁₃ shown will be omitted.). The first mast 2 (P ₁₁ ) constituting the pixel and the bottom of the second mast 3a (C ₁₁ ) constituting the contact window are connected via a signal line N ⁺ layer 5 (80a). The gate conductor layer 81a formed on the outer periphery of the P layer 8a of the first mast 2 (P ₁₁ ) via the gate insulating layer 4b is connected to the first and second masts 2 (P ₁₁ ), 3a (C _{11 )} The outer circumference and the first and second masts 2 (P ₁₁ ) and 3a (C ₁₁ ) are formed. The gate conductor layer 81a on the second silicon pillar 3a (C ₁₁₎ are formed on the outer periphery of the insulating-based layer 4c. Adjacent to the first silicon pillar 2 (P ₁₁₎ of the gate conductor layer 81a, and the photo-diode line N layer 9 formed on the outer peripheral portion P layer 8a. A pixel selection line conductor layer 14e (82a) is connected to the P ⁺ layer 11 forming the upper portion of the N layer 9. In the pixel selection line conductive layers 14e (82a) on the second silicon pillar 3a (C _11), another contact hole is formed with the same depth of 16a (16aa), 16b (H 11). Further, the pixel selection line conductor layer 14e (82a) and the pixel selection line metal layer 17a (17aa) are connected via the contact hole 16a (16aa), respectively, and the second layer is further connected via the contact hole 16b (H ₁₁ ). The conductor layer 23 (21) of the pillar 3a (C ₁₁ ) and the signal line N ⁺ layer 80a.

As described above, the present embodiment has the following five features.

1. The signal current or the reset current of the pixel is transmitted from the pixel region to the peripheral drive/output circuit through the low-resistance signal line metal layers 83a, 83b, and 83c, thereby realizing high-speed driving of the solid-state imaging device.

2. The light incident on the pixel region between the first masts P ₁₁ to P ₃₃ is shielded by the shielded light gate conductor layers 81a, 81b, 81c and the pixel select line conductor layers 82a, 82b, 82c. Thereby, the arrival of the signal line N ⁺ layers 80a, 80b, and 80c is prevented, and the resolution is improved and the color mixing characteristics in color imaging are improved. This reduction in resolution and color mixing characteristics is because the light originally incident on one pixel reaches the signal line N ⁺ layers 80a, 80b, 80c, and is multi-layered with the material layer surrounding the signal line N ⁺ layers 80a, 80b, 80c. It is generated by reflection or the like and incident on the photoelectric conversion region of the adjacent pixel.

3. The second pillars C ₁₁ to C ₃₃ constituting the contact frame are formed in the region of the gate conductor layers 81a, 81b, and 81c, and are not improved by reducing the pixel accumulation degree. The arrangement of the wirings of the gate conductor layers 81a, 81b, and 81c of the resolution and the color mixture characteristics and the pixel selection line conductor layers 82a, 82b, and 82c.

4, the pixel selection line conductive layers 82a, 82b, 82c are not formed in the system by forming the contact windows of the second silicon pillar ₁₁ to C than C ₃₃ weeks provided on the second silicon column C is a contact window ₁₁ to C ₃₃ The formation of the contact holes H ₁₁ to H ₃₃ becomes easy.

5. Since the contact holes 16aa, 16ab, 16ac, H ₁₁ to H ₃₃ , 41a, 41b, 41c are on the first to third masts P ₁₁ to P ₃₃ , C ₁₁ to C ₃₃ , 40 a , 40 b , 40 c The height is small and the same depth is formed, so it is easy to manufacture.

(Seventh embodiment)

The solid-state imaging device for color imaging of the present embodiment will be described below with reference to FIGS. 9A and 9B.

Fig. 9A is a plan view showing the solid-state imaging device of the embodiment. The signal line N ⁺ layers 84a, 84b, 84c, and 84d are formed to extend in the vertical (row) direction, and are connected thereto to form the first masts R1, R2, R3, and R4 constituting the pixels for red signals. (hereinafter referred to as R1 to R4), the first masts G1, G2, G3, and G4 (hereinafter abbreviated as G1 to G4) constituting the pixels for green signals, and the first masts B1 and B2 constituting the pixels for blue signals. B3, B4 (hereinafter referred to as B1 to B4). The second masts CC ₁ , CC ₂ , CC ₃ , and CC ₄ (hereinafter abbreviated as CC ₁ to CC ₄ ) constituting the contact window formed simultaneously with the first masts are connected to the signal line N ⁺ layers 84a and 84b. 84c, 84d, and the third masts 43a, 43b, 43c, 43d constituting the contact window are formed on the flat-plate layers 84da, 84db, 84dc, 84dd provided in the peripheral drive/output circuit region. The second columns CC ₁ and CC ₂ constituting the contact window are formed between the row directions of the first columns R1 and R2 constituting the red signal pixels arranged in the horizontal (column) direction and are originally formed by the pixels. . Similarly, the second masts CC ₃ and CC ₄ constituting the contact window are formed between the rows of the first masts R3 and R4 constituting the red signal pixels arranged in the horizontal (column) direction. The area in which the pixels are formed. Gate conductor layers 85a, 85b, 85c, 85d line formed on the configuration of the first silicon pillar pixel of R1 to R4, G1 to G4, B1 to B4, and forming the contact windows of the second silicon pillar CC ₁ to CC than ₄ weeks Moreover, it is formed in a direction toward the horizontal (column). And the same, the pixel selection line conductive layers 86a, 86b, 86c, 86d line formed on the configuration of the first silicon pillar pixel of R1 to R4, G1 to G4, B1 to B4, and forming the contact windows of the second silicon pillar CC ₁ to It is formed outside the CC ₄ and extends in the direction of the horizontal (column). Signal line N ⁺ layer 84a and signal line metal layer 87a, signal line N ⁺ layer 84b and signal line metal layer 87b, signal line N ⁺ layer 84c and signal line metal layer 87c, signal line N ⁺ layer 84d and signal line metal layer 87d, lines were formed via the contact window constituting the second silicon pillar CC ₁ over to the contact hole ₄ CC CH ₁ to CH ₄ are connected. The gate conductor layers 85a, 85b, 85c, and 85d are connected to the gate conductor layer 45a via contact holes 44a, 44b, 44c, and 44d provided in the third pillars 43a, 43b, 43c, and 43d constituting the contact window. 45b, 45c, 45d. The signal line N ⁺ layers 84a, 84b, 84c, and 84d are connected to the signal line metal layers 87a, 87b, 87c, and 87d in the horizontal direction by the first masts R1 to R4 constituting the red signal pixels in the pixel region. Since each row formed by the arrangement is performed, high-speed driving of the solid-state imaging device can be achieved.

Fig. 9B is a cross-sectional structural view of the DD' line shown in Fig. 9A. In an actual solid-state imaging device, the first masts R1 to R4, G1 to G4, B1 to B4 constituting the pixel, and the second masts CC ₁ , CC ₂ , and CC ₃ constituting the contact window are further in two dimensions. The first and second masts are arranged in a row. Here, it is explained that only the first masts R1 and R3 along the DD′ line and the second masts CC ₁ and CC ₂ constituting the contact window are formed. In Fig. 9A, flat-shaped signal lines N ⁺ layers 84a, 84b, 84c, 84d and flat ruthenium layers 84e formed in the longitudinal direction are formed on the yttria substrate 1. On the signal line N ⁺ layers 84a, 84b, 84c, and 84d, the first masts R1 and R3 constituting the pixels, and the second masts CC ₁ and CC ₂ constituting the contact windows are formed, and in the flat corrugated layer 84e. A third mast 43a constituting a contact window is formed thereon. P layers 8a and 8c are formed on the signal line N ⁺ layers 84a and 84c constituting the bottoms of the first pillars R1 and R3 of the pixel, and the gate insulating layers 4b and 4d are interposed between the outer layers of the P layers 8a and 8c. A gate conductor layer 85a is formed. This gate conductor layer constituting the contact window 85a is also the second silicon pillar of the CC _1, the outer periphery of the CC ₂ extends and is connected by a first sequence, the second silicon pillar _{R1, CC 1, R3, CC} 2 of. The N layers 9, 9a of the photodiode are formed on the outer periphery of the P layers 8a and 8c so as to be adjacent to the gate conductor layer 85a of the first pillars R1 and R3. Formed on the P ⁺ diode light pixel selection line conductive layers 86a to 11,11a layer, comprising a first line, the second silicon pillar R1, CC _1, R3, CC extends beyond _two weeks. This pixel selection line conductor layer 86a surrounds the insulating layers 4c and 4e in the second columns CC ₁ and CC ₂ . The pixel selection line conductor layer 86a is extended to a drive-output circuit region located outside the pixel region, and is connected to the pixel selection line metal layer 17aa via the contact hole 16aa. Contact holes SH ₁ , SH ₂ , and 44a are formed simultaneously on the conductor layers 23a and 23b of the second column CC ₁ and CC ₂ and on the third column 43a so as to have the same depth as the contact hole 16aa. Conductor layers 23a, 23b via a contact hole line SH _1, SH ₂ is connected to the signal line metal layer 87b, 87d. In Fig. 9A, the signal line metal layers 87a, 87b, 87c, and 87d are formed to extend in the vertical (row) direction.

In the solid-state imaging device for color imaging of the present embodiment, the second pupils CC ₁ , CC ₂ , CC ₃ , and CC ₄ constituting the contact window can be processed as suspected pixels by pixel signal processing. For example, the second column CC ₁ is a signal similar to the signal of the pixels R1 arranged in the same column, and the second column CC ₂ is a signal similar to the signal of the pixels R2 arranged in the same column. Since the signal band of the red signal is lower than the signal band of the green signal, the resolution for using the red signal can be lower than the resolution for the green signal. In the solid-state imaging device of the present embodiment, by providing the second pupils CC ₁ to CC ₄ constituting the contact window in the pixel region, high-speed driving can be realized without lowering the pixel integration degree.

(Eighth embodiment)

Hereinafter, a semiconductor device using the P channel SGT of the present embodiment will be described with reference to FIGS. 10A to 10C.

Figure 10A is a circuit diagram of a P-channel SGT. This P-channel SGT is constituted by a gate 56, a source 53, and a drain 57. Further, the gate 56 is connected to the gate terminal G, the source 53 is connected to the source terminal S, and the gate 57 is connected to the gate terminal D.

Fig. 10B is a plan view of the P-channel SGT shown in Fig. 10A. A source P ⁺ layer 53a constituting the source 53 is formed in the flat layer 50. On the source P ⁺ layer 53a, a first column 51b constituting the SGT and a second column 51c constituting a contact window are formed. The third mast 51a constituting the contact window is formed adjacent to the gate conductor layer 56a of the gate 56 so as to be adjacent to the first mast 51b constituting the SGT. The gate conductor layer 56a surrounds the outer circumference of the first mast 51b constituting the SGT, and is formed to cover the third mast 51a constituting the contact window. Further, the drain P ⁺ layer 57a formed on the first column 51b constituting the SGT is connected to the drain wiring metal layer 63b (D) via the contact hole 62b, and the source P ⁺ layer 53a is in contact with the composition. The conductor layer 59 of the second mast 51c of the window is connected to the source wiring metal layer 63c (S) via the contact hole 62c, and the gate conductor layer 56a is contacted from the third mast 51a constituting the contact window. The hole 62a is connected to the gate metal layer 63a (G).

Fig. 10C is a cross-sectional structural view taken along the line EE' of the plan view shown in Fig. 10B. A flat ruthenium layer 50 is formed on the ruthenium oxide substrate 1. A first mast 51b constituting the SGT, a second mast 51c and a third mast 51a constituting the contact window are formed on the flat layer 50. The flat layer 58 of the flat layer 50 and the first layer 51b are N-type or intrinsic semiconductors. Further, insulating layers 54a, 54b, and 54c are formed so as to cover the exposed portions of the flat ruthenium layer 50 and the first to third masts 51a, 51b, and 51c. Further, the gate conductor layer 56a is formed on the outer periphery of the first mast 51b via the insulating layer 54b, and the entire structure extends over the third mast 51a covered by the insulating layer 54a. A source P ⁺ layer 53a is formed in the flat ruthenium layer 50 in the region below the first mast 51b and the second mast 51c. Further, in the upper region of the first mast 51b, a gate P ⁺ layer 57a is formed adjacent to the gate conductor layer 56a. Further, the entire structure is covered with the insulating layer 60, and the conductor layer 59 connected to the upper surface of the second column 51c is formed from the source P ⁺ layer 53a of the second column. Further, the insulating layer 61 is covered, and the contact hole 62a is formed on the third mast 51a, and the contact hole 62b is formed on the first mast 51b, and the contact hole 62c is formed in the second On the mast 51c. Furthermore, the gate conductor layer 56a is connected to the gate metal layer 63a (G) via the contact hole 62a, and the gate P ⁺ layer 57a and the gate wiring metal layer 63b (D) are connected via the contact hole 62b. The source P ⁺ layer 53a and the source wiring metal layer 63c (S) are connected via the conductor layer 59 formed in the contact hole 62c and the second column 51c. Thereby, the contact holes 62b, 62c, and 62a formed on the first mast 51b, the second mast 51c, and the third mast 51a are formed at the same depth (the same height).

The manufacturing method of the P channel SGT is composed of the following steps: a first to third column forming step, which is connected to the flat layer 50 on the yttrium oxide substrate 1 so as to form the first column 51b constituting the SGT, The second mast 51c and the third mast 51a constituting the contact window are simultaneously formed at the same height; the first and second mast bottom connection forming steps surround the bottom of the first mast 51b to the SGT The P ⁺ layer 53a is formed on the flat layer 50, and the source P ⁺ layer 53a is connected to the bottom of the second column 51c. The first column SGT forming step is formed on the outer periphery of the first column 51b. The insulating layer 54b and the insulating layer 54c are formed on the outer periphery of the second mast 51c, and the gate conductor layer 56a is formed by surrounding the insulating layer 54b, and the gate conductor layer 56a is formed to be extended to the contact layer covered by the insulating layer 54a. The third pillar 51a of the window is formed on the upper portion of the first mast 51b adjacent to the gate conductor layer 56a to form the drain P ⁺ layer 57a, and the drain P ⁺ layer 57a and the source P ⁺ layer are to be formed. The layer 58 of the first column 51b sandwiched by 53a is set as the channel of the SGT; the second column conductor layer forming step is formed in the second layer of the contact window. 51c forms a conductive layer 59 of ion-implanted acceptor impurity Si or germanium; a contact hole forming step of forming the insulating layer 60 so as to cover the first mast 51b, the second mast 51c, and the third stub 51a And a contact hole 62a is formed in the third column 51a constituting the contact frame, a contact hole 62b is formed in the first column 51b constituting the SGT, and a contact hole is formed in the second column 51c constituting the contact window. 62c; a wiring metal layer forming step of, via the contact holes 62a, 62b, 62c, the gate conductor layer 56a and the gate metal layer 63a (G), the drain P ⁺ layer 57a, and the drain wiring metal layer 63b (D), The conductor layer 59 and the source wiring metal layer 63c (S) are connected to each other.

Further, in the SGT, when the drain P ⁺ layer 57a functions as a source, the source P ⁺ layer 53a functions as a drain. Further, in the N-channel SGT, the drain-source is composed of an N ⁺ layer, and the channel is composed of a P-type or an intrinsic semiconductor.

(Ninth Embodiment)

Hereinafter, a semiconductor device using the SGT of the present embodiment will be described with reference to FIGS. 11A to 11G.

Figure 11A is a 3-phase CMOS inverter circuit diagram using SGT. The initial stage inverter circuit is composed of two P channels SGT88aa, 88ab and one N channel SGT89a. The gates of SGT88aa, 88ab, and 89a are connected to the input terminal Vi, and the P channels SGT88aa and 88ab are connected to the power terminal Vcc, and the sources of the P channels SGT88aa and 88ab are connected to the source of the N channel SGT89a to form the initial output. The terminal is connected to the input terminal of the second stage inverter circuit. Furthermore, the drain of the N-channel SGT89a is connected to the ground terminal Vss. In the same manner as the first-stage inverter circuit, a second-stage inverter circuit composed of P-channels SGT88ba, 88bb, and N-channel SGT89b, and a third-stage consisting of P-channel SGT88ca and N-channel SGT89c are connected. Inverter circuit. The drains of the P channels SGT88ba, 88bb, 88ca, and 88cb of the second and third inverter circuits are connected to the power supply terminal Vcc, and the drains of the N channels SGT89b and 89c are connected to the ground terminal Vss. In the three-stage CMOS inverter circuit, the signal voltage input to the input terminal Vi is delayed by three clocks, and is output as an inverted signal from the output terminal Vo.

Fig. 11B is a plan view showing a three-stage CMOS inverter circuit of Fig. 11A formed on a substrate by a known technique. From the lower side of Fig. 11B, an initial stage, a second stage, and a third stage inverter circuit are formed. The early part of the inverter circuit based P-channel SGT88aa, 88ab source electrode and the P ⁺ source layer 90ca SGT89a extreme N-channel N ⁺ layer connected to each other to form 90cb. The masts 91ac and 91bc forming the P-channels SGT88aa and 88ab are formed on the source P ⁺ layer 90ca, and the mast 91cc constituting the N-channel SGT 89a is formed on the N ⁺ layer 90cb. The gate conductor layer 93c of SGT88aa, 88ab, and 89a is continuously formed so as to surround the pillars 91ac, 91bc, and 91cc forming the SGT. The gate conductor layer 93c is connected to the first input wiring metal layer 95ca via the contact hole 94ac. The drains of the P channels SGT88aa and 88ab are connected to the first power supply wiring metal layer 95a via the contact holes 94bc and 94cc formed on the masts 91ac and 91bc. The P ⁺ layer 90ca and the source N ⁺ layer 90cb are respectively connected to the first output wiring metal layer 95cb via the contact holes 94dc formed in the boundary portion between the two. The source of the N-channel SGT 89a is connected to the first ground wiring metal 95c via a contact hole 94ec formed in the mast 91cc. The second input wiring metal layer 101ac (Vi) is formed on the first input wiring metal layer 95ca by being connected to the first input wiring metal layer 95ca. The first output wiring metal layer 95cb is connected to the first output wiring metal layer 95cb, and a second output wiring metal layer 101ab connected to an input terminal of the second-stage inverter circuit is formed. In this initial stage inverter circuit, the gate conductor layer 93c is wired so as to avoid the contact hole 94dc.

The second output wiring metal layer 101ab of the first-stage inverter circuit is connected to the first input wiring metal layer 95ba of the second-stage inverter circuit. Paragraph inverter circuit 2 in the same system configuration as the initial stage of the inverter circuit is formed, and a P-channel SGT88ba, 88bb source of the P ⁺ layer 90 BA electrode, the source electrode of the N-channel SGT89b N ⁺ layer 90bb, 91ab silicon column 91bb, 91cb, gate conductor layer 93b, contact holes 94ab, 94bb, 94cb, 94db, 94eb, first input wiring metal layer 95ba, first power wiring metal layer 95a, first ground wiring metal 95c, and first output The wiring metal layer 95bb is formed. The first output wiring metal layer 95bb is connected to the second output wiring metal layer 101aa, and is connected to the first input wiring metal layer 95aa of the third-stage inverter circuit. Paragraph inverter circuit 3 based manner as to be the initial stage / para inverter circuit 2 of the same configuration, the P-channel SGT88ca, 88cb source electrode of the P ⁺ layer 90 aa, the N-channel source electrode SGT89c the N ⁺ layer 90 BA, The masts 91aa, 91ba, 91ca, the gate conductor layer 93a, the contact holes 94aa, 94ba, 94ca, 94da, 94ea, the first input wiring metal layer 95aa, the first power wiring metal layer 95a, the first ground wiring metal 95c, and The first output wiring metal layer 95ab is formed. The first output wiring metal layer 95ab is connected to the second output wiring metal layer 101c (Vo). In addition, the first power supply wiring metal layer 95a is connected to the second power supply wiring metal layer 101b (Vcc) via the contact hole 94fa, and the first ground wiring metal 95c is connected to the second ground wiring metal layer via the contact hole 94fb. 101d (Vss).

Fig. 11C is a cross-sectional structural view taken along line X1-X1' of Fig. 11B. The X1-X1' line is connected in the lateral (column) direction to the contact holes 94aa, the columns 91aa, 91ba of the P channels SGT88ca, 88cb, and is bent there to be connected to the contact hole 94da, and further connected to constitute the N channel SGT. The mast 91ca. The 11Cth diagram corresponds to the cross-sectional structure of the inverter circuit of the third stage. A flat crucible layer 108 is formed on the hafnium oxide substrate 1, and the crucibles 91aa and 91ba of the P channels SGT88ca and 88cb and the mast 91ca of the N channel SGT89c are formed on the flat crucible layer 108. The planar ruthenium layer 108 below the masts 91aa and 91ba forms the source P ⁺ layer 90aa, and the flat ruthenium layer 108 below the mast 91ca forms the source P ⁺ layer 90ba. A gate insulating layer 110b is formed on the outer circumference of the masts 91aa and 91ba, and a gate insulating layer 110d is formed on the outer circumference of the mast 91ca. A gate conductor layer 93b connected to each other is formed to surround the gate insulating layers 110b and 110d. The stopper SiN layer 112 is formed to cover the gate conductor layer 93b. A vaporized layer 133a is formed at a boundary portion between the source P ⁺ layer 90aa and the source P ⁺ layer 90ba. Contact holes 94da are formed in the germanide layer 133a, contact holes 94aa are formed on the gate conductor layer 93a, and contact holes 94ba, 94ca, and 94ea are formed on the masts 91aa, 91ba, and 91ca. The gate conductor layer 93a, the first input wiring metal layer 95aa, the drain P ⁺ layer 111a, the first power supply wiring metal layer 95a, the germanide layer 133a, and the first via wiring holes 94aa, 91ba, 94da, and 91ca are respectively connected. 1 output wiring metal layer 95ab, drain N ⁺ layer 111b, and first ground wiring metal 95c. Further, the first input wiring metal layer 95aa is connected to the second output wiring metal layer 101aa of the second-stage inverter circuit, and the first output wiring metal layer 95ab is connected to the second output wiring metal layer 101c (Vo). . The second output wiring metal layer 101aa of the second-stage inverter circuit and the second output wiring metal layer 101c (Vo) of the third-stage inverter circuit are copper formed by a dual damascene technique ( Cu) wiring layer.

Fig. 11D is a cross-sectional structural view taken along line Y1-Y1' shown in Fig. 11B. Telluride layers 133a, 133b, and 133c are formed at the boundary between the source P ⁺ layers 90aa, 90ba, 90ca and the source P ⁺ layers 90ba, 90bb, 90cb of each inverter circuit (Y1-Y1' line It is located on the source P ⁺ layer 90aa, 90ba, 90ca side). An insulating layer 101b is formed to cover the source P ⁺ layers 90aa, 90ba, 90ca and the source P ⁺ layers 90ba90bb, 90cb. Gate conductor layers 93a, 93b, and 93c are formed on the insulating layer 110b. Further, an insulating layer 113a is deposited on the entire structure. Further, contact holes 94da, 94db, and 94dc are formed on the vapor layers 133a, 133b, and 133c. The contact holes 94da, 94db, and 94dc are formed apart from the gate conductor layers 93a, 93b, and 93c. The vaporized layers 133a, 133b, and 133c and the first input wiring metal layers 95ca, 95cb, and 95cc are connected via the contact holes 94da, 94db, and 94dc. Further, the insulating film 113b is deposited on the entire structure, and the second output wiring metal layers 101c (Vo), 101aa, and 101ab connected to the first input wiring metal layers 95ca, 95cb, and 95cc are, for example, Cu double damascene. Formed by technology.

As shown in FIG. 11B, in the CMOS inverter circuit formed by the conventional technique, the contact holes 94da, 94db, and 94dc connected to the first output wiring metal layers 95ab, 95bb, and 95cb are formed in a plan view. In order not to overlap the gate conductor layers 93a, 93b, and 93c, this may cause a decrease in the circuit integration degree. Further, in the prior art, as shown in Fig. 11C, the contact holes 94ba, 94ca, 94ea on the masts 91aa, 91ba, 91ca, and the telluride layer 133a connected to the bottoms of the masts 91aa, 91ba, 91ca The difference in depth between the contact holes 94da necessarily results in a height corresponding to the masts 91aa, 91ba, and 91ca. Further, although the depth of the contact hole 94da on the vaporized layer 133a is different from the contact hole 94aa on the gate conductor layer 93a (Fig. 11C), it is difficult to form the contact hole.

Fig. 11E is a plan view showing a case where a three-stage CMOS inverter circuit shown in Fig. 11A of the present embodiment is formed on a substrate. From the lower side of Fig. 11E, an initial stage, a second stage, and a third stage inverter circuit are formed. The initial phase inverter circuit P channel SGT88aa, the source P ⁺ layer 96ac of 88ab and the source N ⁺ layer 96bc of the N channel SGT89a are connected to each other, and a P channel is formed on the source P ⁺ layer 96ac. SGT88aa, 88ab column 97cb, 97cc, and a column 97ce forming an N-channel SGT89a on the N ⁺ layer 96bc are formed. Simultaneously with these columns, the pillars 97cd constituting the contact window are formed at the boundary portion between the source P ⁺ layer 96ac and the source N ⁺ layer 96bc, respectively, and are in contact with the source P ⁺ layer 96ac. A mast 97ca constituting a contact window is formed on the layer 108c. The gate conductor layer 93bc of SGT88aa, 88ab, and 89a is formed continuously around the masts 97ca, 97cb, 97cd, and 97ce. The gate conductor layer 93bc is connected to the first input wiring metal layer 47ca via a contact hole 100ca formed in the mast 97ca constituting the contact window. The drains of the P channels SGT88aa and 88ab are connected to the first power supply wiring metal layer 107b via the contact holes 100cb and 100cc formed on the masts 97cb and 97cc. The P ⁺ layer 96ac and the N ⁺ layer 96bc are connected to the first output wiring metal layer 47cb via a contact hole 100cd formed on the mast 97cd formed on the boundary portion between the two. The source of the N-channel SGT 89a is connected to the first ground wiring metal layer 107d via a contact hole 100ce formed in the mast 97ce. The second input wiring metal layer 107aa (Vi) is formed on the first input wiring metal layer 47ca by being connected to the first input wiring metal layer 47ca. The first output wiring metal layer 47cb is connected to the first output wiring metal layer 47cb to form a second output wiring metal layer 107cc connected to an input terminal of the second-stage inverter circuit.

The second output wiring metal layer 107cc of the initial stage inverter circuit is connected to the first input wiring metal layer 47ba of the second-stage inverter circuit. Paragraph inverter circuit 2 based manner as to be the same configuration as the initial stage of the inverter circuit, the nature of the silicon layer 108b, P-channel SGT88ba, the source electrode of the P ⁺ layer 88bb 96ab, the source electrode of the N-channel SGT89b N ⁺ layer 96bb , masts 97ba, 97bb, 97bc, 97bd, 97be, gate conductor layer 93bb, contact holes 100ba, 100bb, 100bc, 100bd, 100be, first input wiring metal layer 47ba, first power wiring metal layer 107b, first ground The wiring metal layer 107d and the first output wiring metal layer 47bb are formed. The first output wiring metal layer 47bb is connected to the second output wiring metal layer 107cb, and is connected to the first input wiring metal layer 47aa of the third-stage inverter circuit. The inverter circuit of the third stage is the same as the initial stage and the second stage inverter circuit, and is composed of the source of the P channel SGT88ca, 88cb, the source layer 108a, the source P ⁺ layer 96aa, and the source of the N channel SGT89c. N ⁺ layer 96ba, mast 97aa, 97ab, 97ac, 97ad, 97ae, gate conductor layer 93ba, contact holes 100aa, 100ab, 100ac, 100ad, 100ae, first input wiring metal layer 47aa, first power wiring metal layer 107b The first ground wiring metal layer 107d and the first output wiring metal layer 47ab are formed. The first output wiring metal layer 47ab is connected to the second output wiring metal layer 107ca (Vo).

Fig. 11F is a cross-sectional structural view taken along the line X2-X2' shown in Fig. 11E. This cross-sectional structure diagram shows the cross-sectional structure of the inverter circuit of the third stage. A flat ruthenium layer 108a is formed on the ruthenium oxide substrate 1, and on the flat ruthenium layer 108a, the masts 97ab and 97ac of the P channels SGT88ca and 88cb and the masts 97ae of the N-channel SGT89c are formed, and the contact window is formed. 97 97aa, 97ad. The planar ruthenium layer 108a under the masts 97ab, 97ac forms a source P ⁺ layer 96aa, and the planar ruthenium layer 108a below the mast 97ae forms a source P ⁺ layer 96ba. A mast 97ad constituting a contact window is formed on a boundary portion between the source P ⁺ layer 96aa and the source N ⁺ layer 96ba. On the outer circumferences of the masts 97ab, 97ac, and 97ae, gate insulating layers 110b and 110d are formed, and insulating layers 110a and 110c are formed on the outer circumferences of the masts 97aa and 97ad constituting the contact windows. On the outer circumferences of the gate insulating layers 110b and 110d and the insulating layers 110a and 110c, gate conductive layers 93b connected to each other are formed. In the mast 97aa constituting the contact window, the entirety of the structure is covered by the insulating layer 110a. The gate conductor layer 93b is formed to cover the insulating layer 110a of the mast 97aa constituting the contact window. Further, the stopper SiN layer 112a is formed so as to cover the entire structure. Next, the contact holes 100aa, 100ab, 100ac, and 100ae are formed on the masts 97aa, 97ab, 97ac, 97ad, and 97ae. Further, via the contact holes 100aa, 100ab, 100ac, 100ad, and 100ae, the gate conductor layer 93b and the first input wiring metal layer 47aa, the drain P ⁺ layer 111a, and the first power wiring metal layer 107b are respectively connected. The conductor layer 109a formed on the mast 97ad of the contact window, the first output wiring metal layer 47ab, the drain N ⁺ layer 111b, and the first ground wiring metal layer 107d. In addition, the first input wiring metal layer 47aa is connected to the second input wiring metal layer 107aa of the second-stage inverter circuit, and the first output wiring metal layer 47ab is connected to the second output wiring metal layer 107ac. The second input wiring metal layer 107aa of the second-stage inverter circuit and the second output wiring metal layer 107ac of the third-stage inverter circuit are each a copper (Cu) wiring layer formed by a dual damascene technique.

Fig. 11G is a cross-sectional structural view taken along line Y2-Y2' shown in Fig. 11E. On the interface between the source P ⁺ layers 96aa, 96ab, 96ac and the source N ⁺ layers 96ba, 96bb, 96bc of each inverter circuit, the masts 97ad, 97bd, 97cd (Y2-Y2) constituting the contact window are formed. 'The line is located on the source P ⁺ layer 96aa, 96ab, 96ac side). Insulating layers 110cc, 110cb, and 110ac are formed so as to cover the pillars 97ad, 97bd, and 97cd, the source P ⁺ layers 96aa, 96ab, and 96ac and the source N ⁺ layers 96ba, 96bb, and 96bc. Gate conductor layers 93ba, 93bb, and 93bc are formed on the outer circumferences of the insulating layers 110ac, 110cb, and 110cc of the masts 97ad, 97bd, and 97cd. Further, the stopper SiN layers 112a, 112b, and 112c and the insulating layer 113a are stacked as a whole. Further, contact holes 100ad, 100bd, and 100cd are formed in the masts 97ad, 97bd, and 97cd. The conductor layers 109a, 109b, and 109c and the first output wiring metal layers 47ab, 47bb, and 47cb are connected via the contact holes 100ad, 100bd, and 100cd. Further, the insulating film 113b is entirely deposited, and the second output wiring metal layers 107ca, 107cb, and 107cc connected to the first output wiring metal layers 47ab, 47bb, and 47cb are formed by, for example, Cu dual damascene technique.

As shown in FIG. 11B, in the CMOS inverter circuit of the conventional example, the contact holes 94da, 94db, and 94dc connected to the first output wiring metal layers 95ab, 95bb, and 95cb are not formed in a plan view line. It overlaps with the gate conductor layers 93a, 93b, and 93c, but this causes a decrease in the circuit integration degree. On the other hand, in the present embodiment, as shown in Fig. 11E, the gate conductor layers 93ba, 93bb, and 93bc are formed on the masts 97ad, 97bd, and 97cd constituting the contact windows. In the plan view, since the contact holes 100ad, 100bd, and 100cd are formed in the regions of the gate conductor layers 93ba, 93bb, and 93bc, the contact holes of the respective segments (100aa, 100ab, 100ac, 100ad, 100ae), (100ba, 100bb, 100bc, 100bd, 100be), (100ca, 100cb, 100cd, 100ce) are linearly arranged in the horizontal (column) direction. Thereby, the circuit integration degree of the CMOS inverter circuit of this embodiment can be improved. In the present embodiment, as shown in FIG. 11F, the first input wiring metal layer 47aa, the first power wiring metal layer 107b, the first output wiring metal layer 47ab, and the first ground wiring metal layer 107d are connected. The contact holes 100aa, 100ab, 100ac, 100ad, 100ae are formed at the same depth on the masts 97aa, 97ab, 97ac, 97ad, 97ae. Thereby, the CMOS inverter circuit can be easily fabricated.

(Tenth embodiment)

Hereinafter, a semiconductor device according to a tenth embodiment will be described with reference to Fig. 12 .

Fig. 12 is a cross-sectional structural view corresponding to Fig. 11F when the present embodiment is applied to the three-segment CMOS inverter circuit shown in Fig. 11A. This cross-sectional structure is the same except for the gate conductor layer 93b in Fig. 11F. In the present embodiment, the height of the gate conductor layer 93bb formed on the outer periphery of the mast 97ad constituting the contact window is lower than that of the masts 97ab, 97ac, and 97ae in which the SGT is formed, and at least becomes the gate. The thickness of the conductor layer 93bb. Thereby, the coupling capacitance of the gate conductor layer 93bb and the conductor layer 109a of the mast 97ad constituting the contact window can be reduced. Since the conductor layer 109a is connected to the first and second output wiring metal layers 47ab and 107ac, the coupling capacitance between the gate conductor layer 93bb and the output wiring can be reduced. As a result, according to the present embodiment, the SGT circuit can be driven at a high speed compared to the circuit shown in FIG.

The height of the gate conductor layer 93bb formed on the outer periphery of the mast 97ad constituting the contact window can be lowered to the thickness of the gate conductor layer 93bb in accordance with the required performance of the circuit.

(Eleventh embodiment)

The solid-state imaging device according to the embodiment will be described below with reference to FIGS. 13A and 13B.

In the present embodiment, the gate conductor layer 7a and the pixel selection line conductor layer 104a are formed on the entire outer circumference of the second mast 3 which constitutes the contact window of the pixel region, and the gate conductor layer 7a and the pixel are formed. The line conductor layer 104a is selected to pass through the contact holes 105a, 105b, 105c, 105d on the third masts 102a, 102b, 102c, 102d constituting the contact windows of the peripheral driving/outputting circuit regions provided on both sides in the lateral (column) direction. This is characterized by being connected to the gate conductor layers 106a, 106d and the pixel selection line metal layers 106b, 106c. Thereby, in particular, driving of both sides of the pixel selection line conductor layer 104a and the gate conductor layer 7a can be achieved without causing a decrease in the pixel integration degree.

Fig. 13A is a cross-sectional structural view of the solid-state imaging device of the embodiment. The structure in which the first stub 2 constituting the pixel formed in the pixel region and the second mast 3 constituting the contact window are the same as those shown in FIG. 9B except for the pixel selection line conductor layer 104a. In the pixel region, a first mast 2 constituting a pixel and a second mast 3 constituting a contact window are formed. The third masts 102a, 102b, 102c, and 102d constituting the contact window are formed in the flat layered layers 5c and 5d provided in the peripheral driving/outputting region. Insulating layers 4b, 4c, 103a, and 103b are formed on the outer circumferences of the first to third masts 2, 3, 102a, 102b, 102c, and 102d. The gate conductor layer 7a is continuously formed along the outer circumferences of the insulating layers 10b and 4c of the insulating layers 4b and 4c and the third pillars 102b and 102c, and the third masts 102a and 102d are covered with the third mast. The upper portions of 102a and 102d are formed as a whole. The pixel selection line conductor layer 104a connected to the P ⁺ layer 11 formed on the upper portion of the first mast 2 is formed to surround the outer periphery of the photodiode N layer 9 of the first mast 2 . The pixel selection line conductor layer 104a is formed along the insulating layer 4c on the side surface of the second mast 3, and is formed to cover the entire upper portion of the third mast 102b, 102c in the third mast 102b, 102c. In the flat portion formed between the masts 2, 3, 102a, 102b, 102c, and 102d, the gate conductor layer 7a is formed on the SiO ₂ layer 6, and the pixel selection line conductor layer 104a is formed on the SiO ₂ layer 10a. . The signal line N ⁺ layer 5 is connected to the conductor layer 23 (21) of the second mast 3, and is connected to the signal line metal layer 17b via the contact hole 16b. The gate conductor layer 7a is formed in the gate conductor layer 106d via the contact holes 105a and 105d formed in the third pillars 102a and 102d. The pixel selection line conductor layer 104a is connected to the pixel selection line metal layers 106b and 106c via the contact holes 105b and 105c formed on the third pillars 102b and 102c.

Thereby, the signal line N ⁺ layer 5, the gate conductor layer 7a, and the pixel selection line conductor layer 104a can be respectively connected to the signal line metal layer 17b, the gate conductor layers 106a, 106d, and the pixel selection line metal layer. The contact holes 16b, 105a, 105b, 105c, and 105d of 106b and 106c are formed at the same depth above the second and third masts 3, 102a, 102b, 102c, and 102d. Further, since the gate conductor layer 7a and the pixel selection line conductor layer 104a can be wired along the side surface of the mast which constitutes the contact window of the other wiring, the pixel collection degree of the solid-state imaging device can be improved.

According to this embodiment, the solid-state imaging device shown in Fig. 13B can be formed. The cross-sectional structure diagram along the line F-F' in Fig. 13B corresponds to Fig. 13A (in the pixel region of Fig. 13A, only the F-F' line which is repeatedly arranged in the horizontal (column) direction is described. The first mast P ₁₁ constituting the pixel and the second mast C ₁₁ constituting the contact window. In the pixel region, the first masts P ₁₁ (2) to P ₃₃ and the second masts C ₁₁ (3) to C ₂₃ constituting the contact windows are alternately formed in the horizontal (column) direction. These first and second masts P ₁₁ to P ₃₃ and C ₁₁ to C ₂₃ are formed on the signal line N ⁺ layers 5a (5), 5b, and 5c which are continuous in the longitudinal (row) direction. Pixel selection line conductive layers 104a, 104b, 104c line connected to the first, the second silicon pillar P ₁₁ to P _33, C the outer periphery ₁₁ to C _23, and the extension is formed to provided a drive on the periphery of both ends of the I / O circuit area The third masts 102b, 102c, 102bb, 102cb, 102bc, and 102cc. Gate conductive layer 104aa, 104ab, 104ac lines formed in the first, the second silicon pillar P ₁₁ to P _33, the outer periphery of C ₁₁ to C _23, and the extension is formed to provided at the periphery of both ends of the first drive / output circuit area 3 masts 102b, 102c, 102bb, 102cb, 102bc, 102cc. The gate conductor layers 104aa, 104ab, and 104ac are connected to the gate via contact holes 105a, 105bd, 105ac, 105d, 105ab, and 105dc provided on the third masts 102a, 102ab, 102ac, 102d, 102db, and 102dc at both ends. The pole conductor layers 106a, 106ab, 106ac, 106c, 106cb, 106cc. The pixel selection line conductor layers 104a, 104b, and 104c are connected via contact holes 105b, 105bb, 105bc, 105c, 105cb, and 105cc provided on the third masts 102b, 102bb, 102bc, 102c, 102cb, and 102cc at both ends. Gate conductor layers 106b, 106bb, 106bc, 106d, 106db, 106dc. Thereby, the gate conductor layers 104aa, 104ab, 104ac and the pixel selection line conductor layers 104a, 104b, 104c can be driven at both ends, so that the driving pulse voltage can be applied to the gate conductor layers 104aa, 104ab, 104ac and the pixels. The reset operation of the selected line conductor layers 104a, 104b, and 104c and the signal reading operation are speeded up.

In the present embodiment, as shown in Fig. 13A, the pixel selection line conductor layer 104a and the gate conductor layer 7a do not overlap each other vertically. However, the present invention is not limited thereto, and an insulating layer may be formed on the surface of the gate conductor layer 7a, and a portion overlapping the pixel selection line conductor layer 104a may be provided in the vertical direction. Thereby, it is possible to more effectively prevent the light incident between the first masts 2 constituting the plurality of pixels from leaking into the first mast 2 constituting the adjacent pixel, thereby causing a decrease in the resolution due to signal charges. Color mixing in color photography.

(Twelfth embodiment)

Hereinafter, a semiconductor device using the SGT of the present embodiment will be described with reference to FIGS. 14A, 14B, and 14C.

Fig. 14A shows an E/D (reinforced drive/empty load) inverter circuit with a depletion-shaped N-channel SGT 114a as a load and an enhancement-shaped N-channel SGT as a driving transistor. The gate of the N-channel SGT 114b is connected to the input terminal Vi, and the source and the gate of the N-channel SGT 114a are connected to the output terminal Vo. Further, the source of the N-channel SGT 114a and the drain of the N-channel SGT 114b are connected to the output terminal Vo, and the drain of the N-channel SGT 114b is connected to the ground terminal Vss. In this E/D inverter circuit, the signal voltage input to the input terminal Vi is inverted and output from the output terminal.

Fig. 14B is a cross-sectional view showing a region of the N-channel SGT 114a surrounded by a broken line in Fig. 14A. A gate insulating layer 54a is formed on an outer circumference of the third pillar 51a constituting the N-channel SGT, and the gate conductor layer 56b formed on the outer periphery of the gate insulating layer 54a is extended to the mast 51b constituting the contact window, and The conductor layer 59 is connected to the upper portion of the mast 51b constituting the contact window along the insulating layer 54b formed on the outer periphery of the mast 51b constituting the contact window. The drain N ⁺ layer 57 of the N channel SGT 114a is connected to the power wiring metal layer 63a (Vcc) via the contact hole 62a formed in the insulating layer 61, and is connected to the drain N ⁺ layer 53 of the N channel SGT 114a to form a contact window. The conductor layer 59 and the gate conductor layer 56b of the mast 51b are connected to the output wiring metal layer 63b (Vo) via the contact hole 62b via the mast 51b constituting the contact window.

As a result, the connection between the drain N ⁺ layer 53 of the N-channel SGT 114a and the gate conductor layer 56b can be realized without adding a new contact hole on the upper surface of the mast 51b constituting the contact window. Further, contact holes 62a, 62b having the same depth as each other can be formed.

Fig. 14C shows an embodiment in which the gate conductor layer 56b is connected to the conductor layer 59 of the mast 51b constituting the contact window, and is formed on the side surface of the conductor layer 59. The insulating layer 54c formed on the outer periphery of the conductor layer 59 is removed until it is lower than the height of the gate conductor layer 56b formed on the outer periphery of the mast 51a constituting the SGT. Further, the gate conductor layer 56b is formed, and the connection of the gate conductor layer 56b and the conductor layer 59 is performed above the conductor layer 59. The connection of the drain N ⁺ layer 57 of the N channel SGT to the power wiring metal layer 63a (Vcc) on the insulating layer 61 is performed via the contact hole 62a. The connection of the gate conductor layer 56b and the output wiring metal layer 63b (Vo) of the source N ⁺ layer 53 of the N channel SGT 114a is performed via the contact hole 62b.

As a result, in the same manner as the structure shown in FIG. 14B, the connection of the source N ⁺ layer 53 of the N-channel SGT 114a and the gate conductor layer 56b does not require new contact on the top of the mast 51b constituting the contact window. The hole can be achieved. As a result, the contact holes 62a, 62b having the same depth as each other can be formed.

(Thirteenth embodiment)

Hereinafter, the solid-state imaging device according to the embodiment will be described with reference to Figs. 15A and 15B.

Fig. 15A is a cross-sectional structural view showing the same steps as the manufacturing steps shown in Figs. 2A to 2C. In the present embodiment, the second mast 3a constituting the contact window is formed in the pixel region of the solid-state imaging device so as to be adjacent to the first mast 2 constituting the pixel, and is formed in the peripheral drive/output circuit region. There is a third mast 3b constituting a contact window. This third column 3b is formed by being separated from the signal line N ⁺ layer. The SiO ₂ layers 4b, 4c, and 4d are formed to cover the first to third masts 2, 3a, and 3b. Thereafter, the SiO ₂ layer 4d on the outer peripheral portion of the third column 3b is removed. The gate conductor layer 7a is formed by surrounding the SiO ₂ layers 4b and 4c and the third column 3b. The gate conductor layer 7a is formed on the SiO ₂ layer 6 so that the first to third masts 2, 3a, and 3b are connected to each other. Here, the gate conductor layer 7a is directly connected to the P layer 8c of the third mast 3b.

Fig. 15B is a cross-sectional structural view showing a solid-state imaging device formed by the same steps as those of Figs. 3A to 3C. In the third column 3b, when the vaporization layer 23 is formed on the second column 3a The telluride layer 23a is formed in the same manner. Thereafter, the solid-state imaging device is formed in the same manner as the step shown in Fig. 7B.

As shown in Fig. 15B, the gate conductor layer 7a is connected to the vaporized layer 23a at a lower portion of the third mast 3b. Thereby, as shown in Fig. 7B, the present embodiment is formed without connecting the gate conductor layer 7a to the third mast 3b. Since the heights of the gate conductor layers 7a surrounding the first to third masts 2, 3a, and 3b can be set to be the same height, the third mast 3b is not required to be shown in FIG. 7B. The gate conductor layer 7a remains to the upper portion of the third mast 3b.

In Fig. 15A, the case where the gate conductor layer 7a is not reacted with the telluride layer 23a of the third column is described. On the other hand, when the gate conductor layer 7a is formed of a metal layer such as Si or a germanide, for example, a metal layer containing a metal material such as W, Pt, Co, or Ti, heat treatment is performed in the third column 3b. In this manner, the gate conductor layer 7a is reacted with the telluride layer to connect the two.

Further, in the present embodiment, the connection of the drain N ⁺ layer 53 of the N-channel SGT 114a shown in Figs. 14A to 14C to the gate conductor layer 56b can be applied. In this case, the connection can be made by directly connecting the gate conductor layer 56b and the conductor layer 59 to the lower portion of the mast 51b for the contact hole.

(Fourteenth embodiment)

The solid-state imaging device of the present embodiment will be described below with reference to FIGS. 16A and 16B. In the embodiment of Fig. 13, the gate conductor layer 7a and the germanium layer 23a of the third column 3b are directly connected to the third The lower part of the mast 3b. On the other hand, in the present embodiment, the metal conductor layer such as copper (Cu) or tungsten (W) and the gate conductor layer 7a in the third mast 3b are connected instead of the telluride layer 23a. It is characterized by it.

In the present embodiment, as shown in Fig. 16A, unlike the case shown in Fig. 15A, the SiO ₂ layer 4d on the outer periphery of the third mast 3b is not removed and remains. In the present embodiment, the gate conductor layer 7a surrounds the SiO ₂ layers 4b, 4c, and 4d on the outer peripheral portions of the first to third masts 2, 3a, and 3b, and is continuously formed on the first interlayer insulating film 6. .

Thereafter, as shown in Fig. 4B, the P layer 8c of the third column 3b is etched to the lower portion of the third column 3b, and then exposed to the SiO ₂ layer 4c which is exposed inside the hole formed by etching. It is removed and the gate conductor layer 7a is exposed. Next, as shown in FIG. 16B, a barrier layer made of TiN, TaN, Cu, or the like is formed on the P layer 8c of the third pillar 3b to be etched, and on the side surface of the hole formed by etching. The seed layer 141 is then filled with Cu in the hole using a damascene technique. Thereafter, the cross-sectional structure shown in Fig. 16B is obtained through the same steps as those shown in Fig. 4D.

In the present embodiment, as in the thirteenth embodiment, the SiO ₂ layer 4d on the outer peripheral portion of the third mast 3b formed simultaneously with the SiO ₂ layer 4b belonging to the gate insulating layer of the first mast ₂ may be formed. The gate conductor layer 7a is removed before. The removal of the SiO ₂ layer 4d of the third column 3b is performed by covering the other regions with a photoresist layer, further removing the SiO ₂ layer 4d, and removing the photoresist layer. In this step, the SiO ₂ layer 4b belonging to the first column 2 of the gate is likely to be contaminated, but in the present embodiment, the SiO ₂ layer is not formed before the gate conductor layer 7a is formed. 4d is removed, so that the absence of contamination of such gate SiO ₂ layer 4b can be avoided. Further, it is not necessary to form the gate conductor layer 7a to the upper portion of the third mast 3b as in the thirteenth embodiment.

In the above-described first to fourteenth embodiments, Si semiconductors are used, but the same effects can be obtained when other semiconductors such as germanium Si (GeSi) or indium germanium (InSb) are used.

Further, in the present embodiment, the masts 2, 2a constituting the pixel and the masts 51a, 97a, 97b, and 97c constituting the SGT are described by an example in which P-type or N-type Si is formed. However, it can also be formed by an intrinsic type of Si.

In the present embodiment, the gate conductor layers 7, 30a, 43a, 43b, 56b, 7a to 7c, 7ae to 7ac formed on the outer peripheral portions of the first masts 2, 2a, 51a, 97a, 97b, 97c, 51a. 104a to c, 93, 93a, and 93b are formed of a single layer of material layers, but may be formed of a plurality of layers separated by an insulating layer. Furthermore, any of the plurality of layers may also comprise an electrically floating conductor layer.

Further, the pixel selection line conductor layers 14, 14a, 14b, 14c, and 34 may be a metal layer having a small specific resistance or the like, or an ITO (Indium Tin Oxide) layer of a micro transparent conductive film. When the ITO film is used, the solid state imaging device of FIG. 8A, since the pixel selection line conductive layers 82a, 82b, 82c of the contact window will not be silicon constituting the C ₁₁ to C ₃₃ columns vertically overlap, can also cover the first Wiring is performed on the top of the column P ₁₁ to P ₃₃ . Similarly, as shown in FIG. 1A, the ITO film can also be applied to a case where the second pillars Ca, Cb, and Cc constituting the contact window are not present in the pixel region and are formed in the peripheral driving/output circuit region.

In Fig. 6, although the N ⁺ layer 31b remains in the lower portion of the second mast 3a for the contact hole, the telluride layer 35 does not lose the present invention even if it directly contacts the signal line conductor layer 28. The effect achieved by the technical idea. Further, in the present embodiment, the present invention is applied to a solid-state imaging device. However, even when applied to a semiconductor device using the SGT, the wiring is reduced in resistance, which contributes to an increase in the driving speed of the circuit.

Further, in FIGS. 4D and 5, the W layer 70a and the Cu layer 70b are formed by a damascene technique in which a metal material is buried in the hole 68 of the contact window pillar. However, it is not limited thereto, and it may be formed by embedding N ⁺ polycrystalline Si containing a donor impurity.

Further, in Fig. 4B, the tantalum layer of the second column 3 is etched until the SiO ₂ layer 4c is exposed to form a hole 68a. However, the present invention is not limited thereto, and the barrier layer may be exposed in this manner, and the stress caused by the buried metal layer such as the W layer or the Cu layer may be alleviated by leaving the ruthenium layer.

At. 7C, Figure 8A, first. 9A, first Fig. 13B, based in the pixel region constituting the contact holes of the silicon column C ₁₁ to C ₃₃ 2, relative to the first silicon pillar P constituting a pixel of ₁₁ to P ₃₃ each set. However, the present invention is not limited thereto, and is connected to the signal line N ⁺ layers 5a, 5b, 5c, 80a, 80b, and 80c, and each of the plurality of first masts P ₁₁ to P ₃₃ is configured to constitute one contact. The mast of the window can also reduce the resistance of the signal line.

For example, in Fig. 7C, Figure 8A, first. 9A, first Fig. 13B, based in the first silicon pillar P pixels constituting ₁₁ to P _{33 is} present in the pixels constituting the region of the contact window in the second silicon column C ₁₁ Separate to C ₃₃ . That is, in the figures, it is illustrated as being separated into columns that respectively constitute pixels and contact holes. The first column constituting the pixel here is a column including a photoelectric conversion portion having a photodiode, a signal reading portion having a bonded transistor, and a reset portion having a reset transistor.

Further, in Fig. 8A, the wiring arrangement of the gate conductor layers 81a, 81b, and 81c of the MOS transistor and the pixel selection line conductor layers 82a, 82b, and 82c may be replaced. This is because the same effect can be obtained.

In Fig. 12, the technical idea of the present invention is applied to a CMOS inverter circuit using SGT. However, the present invention is not limited to this, and since the reduction in the coupling capacitance contributes to high-speed driving and stable operation of the circuit, the technical idea of the present invention can also be applied to a solid having one or a plurality of conductor layers in the first mast 2 . Camera unit.

In the above embodiment, the technical idea of the present invention is applied to a case where a pixel of a solid-state imaging device or an SGT of a semiconductor device is formed in a columnar semiconductor of Si. However, the technical idea of the present invention can also be widely applied to a solid-state imaging device, and is not limited to the SGT, and the circuit element is formed in a semiconductor device of a columnar semiconductor. That is, the technical idea of the present invention is characterized in that the semiconductor region formed at the bottom of the columnar semiconductor in which the circuit element is formed, and the inside of the columnar semiconductor which constitutes the contact window which is formed simultaneously with the columnar semiconductor constituting the circuit element The formed conductor layer is electrically connected to the columnar semiconductor constituting the circuit element or the semiconductor region formed on the upper portion of the columnar semiconductor constituting the circuit element, and the columnar portion constituting the circuit element formed on the same surface as the region The conductor layer connected to the semiconductor region above the semiconductor and the columnar semiconductor constituting the contact window are substantially identical The upper wiring metal layer is connected to the contact hole formed in depth.

Further, the columnar semiconductor constituting the circuit element and the columnar semiconductor constituting the contact window may not necessarily be formed at the same time.

In the above embodiment, the shape of the signal line N ⁺ layer in the solid-state imaging device is different from the P ⁺ layer or the N ⁺ layer located below the mast constituting the SGT, but this is by the conventional technique. In the solid-state imaging device of FIG. 17A and the shape integration in the semiconductor device using SGT shown in FIG. 18C, the shape of the N ⁺ layer or the P ⁺ layer may be the same as each other, or may be the same as the manufacturing method. Different and different.

As shown in FIG. 1A, the shape of the gate conductor layers 7a, 7b, and 7c of the pixel in the solid-state imaging device is rectangular in plan view, and the SGT gate conductor layers 93ba, 93bb, and 93bc shown in FIG. 11E are Although it is formed in a circular shape by surrounding the masts 97aa, 97ab, 97ac, 97ad, 97ae, etc., it may be any shape. Further, the shape of the gate conductor layers 7a, 7b, and 7c in plan view may be other shapes, and may be, for example, an elliptical shape or a pentagon shape, and may be appropriately different depending on the design of the semiconductor device.

As shown in FIGS. 11A to 11G, the ninth embodiment applies the technical idea of the present invention to a semiconductor device using an SGT, but the tenth embodiment can also be applied to a drive-output-input circuit of a solid-state imaging device. Or other semiconductor devices.

For example, in the 10th and 11th F1, the masts 51a and 97aa constituting the contact window are formed in the flat layer 50 which is connected to the source P ⁺ layers 53a and 96aa and the source N ⁺ layer 96ba. In the case of 108a, similarly to the solid-state imaging device shown in Fig. 7B, it may be formed on the flat Si which forms the active electrode N ⁺ layer 96ba and the separated flat layer.

For example, in the 11Eth, 11th, and 11thth drawings, the gate conductor layer 93ba formed on the outer periphery of the mast 97aa, 97ac forming the P-channel SGT and the mast 97ae forming the N-channel SGT has been described. Although 93bb and 93bc are the same material layers, the gate conductor layers 93ba, 93bb, and 93bc are formed by a material layer different from each other or a conductor layer containing different material layers.

Further, in FIG. 13A, the pixel selection line conductor layer 104a is connected to the P ⁺ layer 11 located in the upper portion of the first mast 2, but may be formed electrically separated from the P ⁺ layer 11, and is The pixel selection line conductor layer 14d shown in FIG. 7B is formed in the same layer as the P ⁺ layer 11 so as to constitute a pixel selection line conductor layer. Further, when the gate conductor layer 7a and the pixel selection line conductor layer 104a located in the first mast 2 are composed of two or more layers, the contact window corresponding to each conductor layer can be formed. The number of the three masts 102a, 102b, 102c, and 102d is increased to improve the circuit integration degree of the solid-state imaging device.

In Fig. 10C, only one gate conductor layer 56 is formed in the first mast 51b. However, the present invention is not limited to this. As in the case of the solid-state imaging device of Fig. 13A, the technical idea of the present invention can also be applied to an SGT having a plurality of gate conductor layers in the height direction of the first mast 51b. At this time, since the height of the first mast 51b is increased, the effect of the present invention is further improved.

In the cross-sectional view of FIG. 1B, the yttrium oxide substrate 1 (SiO ₂ substrate) is used as the substrate, but the substrate may be another insulating material layer or a semiconductor layer. When a semiconductor layer is used, a diffusion layer including a donor or an acceptor that can be operated by a solid-state imaging device is formed by being connected to the N ⁺ region 5 to form a substrate. This is also the same in the solid-state imaging device or the semiconductor device of the other embodiment.

In addition, the present invention can be variously modified and modified without departing from the spirit and scope of the invention. In addition, the above embodiments are intended to describe one embodiment of the invention and are not intended to limit the scope of the invention.

[Industrial availability]

The present invention is also widely applicable to a solid-state imaging device and a semiconductor device in which a circuit element is formed in a columnar semiconductor such as an SGT.

1, 114‧‧‧ oxide substrate

2, 2a, B1, B2, B3, B4, G1, G2, G3, G4, R1 to R4, P ₁₁ to P ₃₃ ‧ ‧ 1st column (1st columnar semiconductor)

3, 3a, 51c, C ₁₁ to C ₃₃ , Ca, Cb, Cc, CC ₁ , CC ₂ , CC ₃ , CC ₄ ‧ ‧ 2nd column (second columnar semiconductor)

3b, 36a, 40a, 40b, 40c, 43a, 43b, 43c, 43d, 102a, 102b‧‧‧3rd column

4a, 4b, 4c, 6‧‧‧ SiO ₂ layer (insulation layer)

4d, 4e‧‧‧ low capacitance insulation

5, 5a, 5b, 5c‧‧‧ signal line N ⁺ layer (bottom semiconductor layer)

6‧‧‧1st interlayer insulating film

7a, 7b, 7c, 131a, 131b, 131c‧‧‧Reset MOS gate conductor

7, 7a, 7aa, 7b, 7c, 30a, 17c, 30a, 38a, 42a, 42b, 42c, 56a, 56b, 81a, 81b, 81c, 85a, 85b, 85c, 85d, 93a, 93b, 93ba, 93bb, 93bc, 93c, 104aa, 106a, 106b, 119‧‧ ‧ gate conductor layer

8a, 117‧‧‧1st column P layer

8b‧‧‧2nd column P layer

9, 32, 120‧‧‧N layers

10, 10a, 15, 18, 29a, 65, 66, 71‧‧ SiO ₂

11, 33, 121‧‧‧P ⁺ layers

12, 19, 67‧‧‧ photoresist layer

13‧‧‧Contact window column N ⁺ layer

14, 14a, 14b, 14c, 14d, 14e, 82a, 82b, 82c, 86a, 86b, 86c, 86d, 104a, 122, 122a, 122b, 122c‧‧‧ pixel selection line conductor layer

16a, 16aa, 16ab, 16ac, 16b, 16c, 37a, 41a, 41b, 41c, 44a, 44b, 44c, 44d, 62a, 62b, 62c, 72a, 72b, 94aa, 94ab, 94ac, 94ba, 94bc, 94da, 94eb, 94ec, 94fa, 94fb, 100aa, 100ad, 100ba, 100ca, 100cb, 100cd, 100ce, 100aa, 100ab, 100ac, 123a, 123b, 126a, 126b, 126c, 129a, 129b, 129c, 129d, 129e, 129f, 133a, 133b, 133c, CH ₁ to CH ₄ , CH ₁₁ to CH ₃₃ , H ₁₁ to H ₃₃ , SC ₁₁ to SC ₂₂ , SCa, SCb, SCc, SH ₁ , SH ₂ ‧ ‧ contact holes

17a, 17aa, 17ab, 17ac, 49a, 73a, 106b, 124b, 134a, 134b, 134c‧‧‧ pixel selection line metal layer

17b, 26a, 26b, 26c, 28, 73b, 83a, 83b, 83c, 87a, 87b, 87c, 87d 124a, 128a, 128b, 128c, 135a, 135b, 135c‧‧‧ signal line metal layer

20, 68, 68a‧‧ holes

21‧‧‧Amorphous or porous layer

22‧‧‧Metal layers of Ni, Co, Ta, W, Ti, etc.

23, 23a, 129‧‧‧ Telluride layer

27‧‧‧Insert substrate

31a, 31b‧‧‧N ⁺ layers

33, 121‧‧‧ pixels select P ⁺ layer

35‧‧‧Contact window pillar conductor layer

37, 39a, 39b, 39c, 50, 84da, 84db, 84dc, 84dd, 126, 108, 108a‧‧‧ flat layer

47aa, 47ba, 47ca, 95aa, 95ca‧‧‧1st input wiring metal layer

47bb, 47cd, 95ab, 95bb, 95cb‧‧‧1st output wiring metal layer

49c‧‧‧Resetting the bungee metal layer

51a‧‧‧ constitutes the pillar of the SGT

51b‧‧‧The pillar that forms the contact window

53, 57a, 111a, 111a, 134a, 134b‧‧‧ bungee P ⁺ layers

53a, 53aa, 57, 90aa, 90ba, 90ca, 96aa, 96ab, 96ac, 138a, 138b‧‧‧ source P ⁺ layers

54c, 100a, 100c‧‧‧Contact window pillar insulation

54a, 54b, 60, 61, 110a, 110ac, 110cc, 103a, 113a, 113b‧‧ Insulation

54, 110b, 110d, 118, 136a, 136b, 136c‧‧‧ gate insulation

56‧‧‧The gate conductor layer forming the SGT

58‧‧‧1st column N layer

59, 109a‧‧‧ conductor layer

63c‧‧‧Source wiring metal layer

63a, 63b, 95c, 101c, 140c‧‧‧ output wiring metal layer

64‧‧‧SiN layer

68, 68a‧‧‧through holes

69‧‧‧TiN layer

69a, 141‧‧ ‧ barrier seed layer

70b‧‧‧Cu layer

70, 70a‧‧‧W layer

80a, 80b, 80c, 84a, 84b, 84c, 84d, 116, 116a, 116b, 116c, 130a, 130b, 130c‧‧‧ signal line N ⁺ layer

88aa, 88ba, 88ca, 125a, 125b‧‧‧P channel SGT

89a, 89b, 89bb, 89c, 89cb, 114a, 114b, 125c‧‧‧N-channel SGT

90ba, 90bb, 96bc, 90cb, 139‧‧‧ source N ⁺ layer

91aa, 91ab, 91ac, 91ca, 91cc, 97aa, 97ab, 97ac, 97ad, 97ae, 97ba, 97ca, 97cb, 97cd, 97ce, 115, 127a, 127b, 127c, P ₁₁ to P ₃₃ ‧ ‧ 矽

95c, 95d, 107d‧‧‧1st grounding wiring metal

95a, 101b, 95b, 107b, 140b‧‧‧1st power wiring metal layer

101d, 107ad‧‧‧2nd grounding wiring metal layer

101b, 107ab‧‧‧2nd power wiring metal layer

101ac, 107aa‧‧‧2nd input wiring metal layer

107ac, 107ca, 107cb, 107cc‧‧‧2nd output wiring metal layer

108b, 108c‧‧‧ Essential layer

111b, 127‧‧ ‧ bungee N ⁺ layer

112, 112a‧‧‧ Stop the SiN layer

117‧‧‧P layer

119a‧‧‧MOS gate conductor layer

125‧‧‧ buried oxide film

132a, 132b, 132c‧‧‧ pixel selection line conductor N ⁺ layer

137a‧‧ ‧ gate conductor N ⁺ layer

138, 140‧‧‧Contact window blocking SiN layer

C‧‧‧ capacitor

C ₁₂ , C ₁₃ ‧ ‧ contact window columns

Vcc‧‧‧ power terminal

Vi‧‧‧ input terminal

Vi1, Vi2‧‧‧ gate extremes

Vo‧‧‧ output terminal

Vss‧‧‧ Grounding terminal

S‧‧‧ source terminal

Fig. 1A is a plan view showing a solid-state imaging device according to a first embodiment of the present invention.

Fig. 1B is a cross-sectional structural view showing the solid-state imaging device according to the first embodiment.

FIG. 2A is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the first embodiment.

FIG. 2B is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the first embodiment.

FIG. 2C is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the first embodiment.

FIG. 2D is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the first embodiment.

FIG. 2E is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the first embodiment.

FIG. 2F is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the first embodiment.

3A is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the second embodiment of the present invention.

3B is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the second embodiment.

3C is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the second embodiment.

Fig. 4A is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the third embodiment of the present invention.

Fig. 4B is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the third embodiment.

Fig. 4C is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the third embodiment.

4D is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the third embodiment (tungsten (W) is used for the conductor layer).

Fig. 5 is a cross-sectional structural view showing a case where copper (Cu) is used for the conductor layer in the method of manufacturing the solid-state imaging device according to the third embodiment.

Fig. 6 is a cross-sectional structural view showing a solid-state imaging device according to a fourth embodiment of the present invention.

Fig. 7A is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the fifth embodiment of the present invention.

Fig. 7B is a cross-sectional structural view for explaining a method of manufacturing the solid-state imaging device according to the fifth embodiment.

Fig. 7C is a plan view for explaining the solid-state imaging device according to the fifth embodiment.

Fig. 7D is a cross-sectional structural view for explaining the solid-state imaging device according to the fifth embodiment.

Fig. 8A is a plan view showing a solid-state imaging device according to a sixth embodiment of the present invention.

Fig. 8B is a cross-sectional structural view for explaining the solid-state imaging device according to the sixth embodiment.

Fig. 9A is a plan view showing a solid-state imaging device according to a seventh embodiment of the present invention.

Fig. 9B is a cross-sectional structural view for explaining the solid-state imaging device according to the seventh embodiment.

Fig. 10A is a circuit diagram of a P-channel SGT according to an eighth embodiment of the present invention.

Fig. 10B is a plan view showing the P channel SGT of the eighth embodiment.

Fig. 10C is a cross-sectional structural view showing the P channel SGT of the eighth embodiment.

Fig. 11A is a circuit diagram showing a CMOS inverter circuit using SGT in the ninth embodiment of the present invention.

Fig. 11B is a plan view showing a CMOS inverter circuit using a conventional SGT of the ninth embodiment.

Fig. 11C is a cross-sectional structural view showing a CMOS inverter circuit using a conventional SGT of the ninth embodiment.

Fig. 11D is a cross-sectional structural view showing a CMOS inverter circuit using a conventional SGT of the ninth embodiment.

Fig. 11E is a plan view showing a CMOS inverter circuit using SGT in the ninth embodiment.

Fig. 11F is a cross-sectional structural view showing a CMOS inverter circuit using SGT in the ninth embodiment.

Fig. 11G is a cross-sectional structural view showing a CMOS inverter circuit using SGT in the ninth embodiment.

Fig. 12 is a cross-sectional structural view showing a CMOS inverter circuit using an SGT according to a tenth embodiment of the present invention.

Fig. 13A is a cross-sectional structural view showing a solid-state imaging device according to an eleventh embodiment of the present invention.

Fig. 13B is a plan view showing the solid-state imaging device of the eleventh embodiment.

Fig. 14A is a plan view showing an E/D inverter circuit using an SGT according to a twelfth embodiment of the present invention.

Fig. 14B is a cross-sectional structural view showing an E/D inverter circuit using SGT in the twelfth embodiment.

Fig. 14C is a cross-sectional structural view showing a load N-channel SGT portion of the E/D inverter circuit using the SGT of the twelfth embodiment.

15A is a cross-sectional structural view of a solid-state imaging device according to a thirteenth embodiment of the present invention.

Fig. 15B is a cross-sectional structural view showing a solid-state imaging device according to a thirteenth embodiment.

Fig. 16A is a cross-sectional structural view showing a solid-state imaging device according to a fourteenth embodiment of the present invention.

Fig. 16B is a cross-sectional structural view showing a solid-state imaging device according to a fourteenth embodiment.

Fig. 17A is a diagram showing a pixel cross-sectional structure of a solid-state imaging device of a conventional example.

Fig. 17B is a cross-sectional structural view showing a solid-state imaging device including a wiring metal layer in a conventional example.

Fig. 17C is a plan view showing a solid-state imaging device of a conventional example.

Fig. 17D is a plan view showing a solid-state imaging device of a conventional example in which a contact hole for connecting a signal line N ⁺ layer and a signal line metal layer is formed in a pixel region.

Fig. 18A is a circuit diagram of a CMOS inverter using a conventional example of SGT.

Fig. 18B is a plan view showing a CMOS inverter circuit of a conventional example using SGT.

Fig. 18C is a cross-sectional structural view showing a CMOS inverter circuit using a conventional example of SGT.

1‧‧‧Oxide substrate

2. P ₁₁ ‧‧‧1st column (1st columnar semiconductor)

3. Ca‧‧‧2nd column (2nd columnar semiconductor)

4b, 4c, 6‧‧‧ SiO ₂ layer (insulation layer)

5, 5a‧‧‧ signal line N ⁺ layer (bottom semiconductor layer)

6‧‧‧1st interlayer insulating film

7, 7a‧‧ ‧ gate conductor layer

8a‧‧‧1st column P layer

9‧‧‧N layer

10, 15‧‧‧ SiO ₂ layer

11‧‧‧P ⁺ layer

13‧‧‧Contact window column N ⁺ layer

14, 14a‧‧‧ pixel selection line conductor layer

16a, 16aa, 16b, SCa‧‧ contact holes

17a, 17aa‧‧‧ pixel selection line metal layer

17h, 26a‧‧‧ signal line metal layer

Claims (19)

A method of manufacturing a semiconductor device, comprising: a columnar semiconductor forming step of forming a first columnar semiconductor and a second columnar semiconductor on a substrate so as to have the same height; and a columnar semiconductor bottom connection step Forming a first semiconductor layer by doping the acceptor or the acceptor impurity in at least one of a bottom region of the first columnar semiconductor and a region in contact with the bottom region, and forming the first semiconductor layer The second columnar semiconductors are connected to each other; and the circuit element forming step of doping the donor or acceptor impurities in the upper region of the first columnar semiconductor to form an upper semiconductor region, and forming a circuit component having the upper semiconductor region a conductor layer forming step of forming a first conductor layer in the second columnar semiconductor; and a contact hole forming step of forming a first contact hole and a second contact hole respectively connected to the first and second columnar semiconductors; a metal layer forming step of forming each of the upper semiconductor region and the first conductor layer via the first and second contact holes a wiring metal layer; a first insulating layer forming step of forming the first insulating layer so as to surround the first columnar semiconductor; and a columnar semiconductor connecting conductor layer forming step to surround the first insulating layer and the second The manner of the columnar semiconductor A columnar semiconductor connecting conductor layer is formed in the first and second columnar semiconductors. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a second conductor layer on the same surface as the upper semiconductor region so as to be connected to the upper semiconductor region; In the hole forming step, the first and second contact holes are formed on the second conductor layer and the second columnar semiconductor so as to be connected to the second conductor layer and the second columnar semiconductor; In the wiring metal layer forming step, a wiring metal layer that is connected to the second conductor layer and the first conductor layer via the first and second contact holes is formed. The method of manufacturing a semiconductor device according to claim 1, wherein the conductor layer forming step includes doping the donor or acceptor impurity into the second columnar semiconductor to form the first semiconductor layer. a step of forming the first semiconductor layer by embedding any one of a polycrystalline semiconductor layer, a vaporized layer, and a metal layer doped with a donor or a acceptor in the second columnar semiconductor. step. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the columnar semiconductor connecting conductor layer, the second insulating layer is further formed to surround the second columnar semiconductor, and Forming the columnar half so as to surround the first and second insulating layers and connecting the first and second columnar semiconductors The conductor is connected to the conductor layer. The method of manufacturing a semiconductor device according to claim 1 or 4, further comprising: connecting the first and second insulating layers above the columnar semiconductor connecting conductor layer and connecting the foregoing The step of forming the columnar semiconductor to the upper conductor layer in the form of the first and second columnar semiconductors. The method of manufacturing a semiconductor device according to claim 1, wherein the columnar semiconductor bottom connection step is performed by doping a donor or acceptor impurity into a bottom region of the first columnar semiconductor and underlying a step of forming a first semiconductor layer in at least one of regions in which the bottom regions are in contact with each other, and connecting the first semiconductor layer and the second columnar semiconductor to each other by forming a fourth conductor layer on the substrate . The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating layer is formed using an insulating material having a lower capacitance than the first insulating layer. The method of manufacturing a semiconductor device according to the first aspect of the invention, further comprising the steps of: forming the first and third columnar semiconductors at the same height to each other; and containing the donor or the acceptor a step of forming an impurity diffusion layer, a vaporization layer, or a metal layer of the bulk impurity in the third columnar semiconductor; and forming the columnar semiconductor connection conductor from the outer periphery of the first columnar semiconductor via the first insulating layer The layer extends to the aforementioned third column The semiconductor is surrounded by the third columnar semiconductor, and is formed in the third columnar semiconductor and is provided with an impurity diffusion layer, a vaporized layer or a metal layer containing a donor or acceptor impurity in the third A step of forming a lower region of the columnar semiconductor. A semiconductor device comprising: a substrate; and first and second columnar semiconductors formed on the substrate and having the same height; and a bottom region of the first columnar semiconductor and a bottom region of the first columnar semiconductor At least one of the regions in the region is doped with a donor or acceptor impurity to form a first semiconductor layer, and the first semiconductor layer and the second columnar semiconductor are connected to each other; and the first columnar shape a semiconductor device having a semiconductor region doped with a donor or acceptor impurity; and a first conductive layer formed in the second columnar semiconductor; a first contact hole and a second contact hole of the first and second columnar semiconductors; and a wiring metal layer connected to the upper semiconductor region and the first conductor layer via the first and second contact holes; The first and second insulating layers formed by the first and second columnar semiconductors; and the first and second insulating layers surround at least the first The insulating layer extends to the columnar semiconductor connecting conductor layer of the second insulating layer. The semiconductor device according to claim 9, wherein the height of the columnar semiconductor connecting conductor layer on the outer circumference of the second columnar semiconductor is higher than the columnar semiconductor connection on the outer circumference of the first columnar semiconductor. The height of the conductor layer is also low and is higher than the thickness of the columnar semiconductor connection conductor layer. The semiconductor device according to claim 9, which is a solid-state imaging device, wherein the pixel of the solid-state imaging device includes the first and second columnar semiconductors, and includes the circuit element; and the pixel system has a shape The substrate is a bottom semiconductor layer of the first semiconductor layer; the second semiconductor layer is formed over the bottom semiconductor layer in the first columnar semiconductor, and includes a conductivity type opposite to the bottom semiconductor layer a semiconductor or a micro semiconductor; the third semiconductor layer is formed on the outer peripheral portion of the second semiconductor layer so as to be located above the columnar semiconductor connection conductor layer, and is of the same conductivity type as the first semiconductor layer, wherein The columnar semiconductor connecting conductor layer is formed on the outer periphery of the second semiconductor layer via the first insulating layer so as to be positioned above the bottom semiconductor layer, and the fourth semiconductor layer as the upper semiconductor region is connected to the foregoing a second semiconductor layer formed on the third semiconductor layer And a conductive type opposite to the bottom semiconductor layer; the bottom region of the first columnar semiconductor and the first conductor layer in the second columnar semiconductor are connected to each other by the bottom semiconductor layer. The semiconductor device according to claim 9, which is a semiconductor device having a Surround Gate Transistor (SGT); wherein the SGT is formed in the first columnar semiconductor as the foregoing a circuit element; the SGT system includes: a bottom semiconductor region formed as the first semiconductor layer on the substrate; and a channel semiconductor layer connected to an upper portion of the bottom semiconductor region and including a conductive region opposite to the bottom semiconductor region a semiconductor or an intrinsic semiconductor; an insulating layer formed on an outer circumference of the channel semiconductor layer; and a conductor layer formed on an outer periphery of the channel semiconductor layer via the insulating layer; and the upper semiconductor layer is connected to the channel semiconductor layer The upper portion is the same conductivity type as the bottom semiconductor region, and functions as a drain when the bottom semiconductor region functions as a source of the SGT. On the other hand, the bottom semiconductor When the region plays a role as the bungee of the aforementioned SGT, it plays a role as a source. ; The bottom semiconductor region and the first conductor layer in the second columnar semiconductor are connected to each other. The semiconductor device according to claim 11, wherein the semiconductor device is a solid-state imaging device; and in the pixel region in which the plurality of pixels are arranged, the first and second columnar semiconductor systems constituting each of the pixels are respectively vertical ( The row direction and the horizontal (column) direction are arranged in a two-dimensional shape. The semiconductor device according to claim 13, wherein the semiconductor device is a solid-state imaging device; and the bottom semiconductor layer of the first semiconductor layer is arranged in a row in the longitudinal direction of the first columnar semiconductor. Connecting the bottom region of the plurality of first columnar semiconductors in the row and extending in the vertical direction (row direction) to form a first semiconductor layer connection conductor layer; the first semiconductor layer connection conductor layer is connected to the first a semiconductor substrate connecting conductor layer on a bottom region of the second columnar semiconductor adjacent to each of the first columnar semiconductors; and the columnar semiconductor connecting conductor layer of the first columnar semiconductor is shielded and incident on Light connecting between the first columnar semiconductors adjacent in the column direction is connected to each other to form a second semiconductor layer connecting conductor layer extending in the lateral direction (column) direction, and is provided to be incident in the row direction by shielding The light between the first columnar semiconductors extends in the horizontal (column) direction and is connected to the third semiconductor layer connecting conductor layer of the fourth semiconductor layer of each of the first columnar semiconductors; A plurality of the second columnar semiconductors are formed in a region in which at least one of the second and third semiconductor layer connection conductor layers is formed, and contact holes are formed in the second columnar semiconductors. The first semiconductor layer connection conductor layer and the wiring metal layer are connected to each other via the contact holes and the first conductor layer in each of the second columnar semiconductors. The semiconductor device according to claim 13, wherein the semiconductor device is a solid-state imaging device; and in the pixel region in which the pixel is arranged, the bottom semiconductor layer as the first semiconductor layer is in accordance with the first columnar semiconductor. Each of the rows arranged in the longitudinal direction extends in the vertical direction (row direction) to form a first semiconductor layer connection conductor layer, and the columnar semiconductor connection conductor layers of the first columnar semiconductor are connected to each other to form a second semiconductor layer connecting conductor layer extending in the horizontal (column) direction; and a third semiconductor layer connecting conductor layer connected to the fourth semiconductor layer of the first columnar semiconductor and extending in the lateral (row) direction; The second and third semiconductor layer connection conductor layers are formed so as to overlap each other when viewed from the direction in which the electromagnetic energy waves are incident, and the second columnar semiconductor is formed on the first semiconductor layer connection conductor layer. Further, between the first columnar semiconductors adjacent to each other in the horizontal (column) direction. The semiconductor device according to claim 12, which is a semiconductor device having an SGT, wherein a plurality of the first columnar semiconductors are arranged, and the columnar semiconductor connecting conductor layer of the first columnar semiconductor is The plurality of first columnar semiconductors are connected to each other, the second columnar semiconductor is formed in a region where the columnar semiconductor connecting conductor layer is formed, and the second columnar semiconductor is surrounded by the second columnar semiconductor. 2. The insulating layer; the columnar semiconductor connecting conductor layer is formed on the outer circumference of the second columnar semiconductor via the second insulating layer. The semiconductor device according to claim 9, wherein the first and second columnar semiconductors and the third columnar semiconductor covered by the third insulating layer are formed on the substrate; a sixth semiconductor layer is formed on the columnar semiconductor, and a seventh semiconductor layer is formed in a region below the first columnar semiconductor; and the first columnar semiconductor and the second columnar semiconductor are surrounded by the first columnar semiconductor. a first insulating layer and a second insulating layer, wherein the columnar semiconductor connecting conductor layer surrounds the first insulating layer on the outer circumference of the first columnar semiconductor, and surrounds the outer circumference of the second columnar semiconductor The second insulating layer is formed in at least one layer, and the columnar semiconductor connecting conductor layer is connected to the foregoing a top surface of the third columnar semiconductor; a contact hole formed in each of the sixth semiconductor layer and the second columnar semiconductor connected to the third columnar semiconductor; and the second columnar semiconductor; The contact hole is connected to the wiring metal layer of any one of the sixth semiconductor layer, the seventh semiconductor layer, and the columnar semiconductor connection conductor layer. The semiconductor device according to claim 9, wherein the first insulating layer and the second insulating layer are formed to surround the first columnar semiconductor, and the columnar semiconductor connecting conductor The layer is connected to the first conductor layer on the upper portion of the second columnar semiconductor. The semiconductor device according to claim 9, wherein the first and third columnar semiconductors are simultaneously formed to have the same height, and the third columnar semiconductor is formed with a coating. An impurity diffusion layer, a vaporization layer, or a metal layer of a bulk or acceptor impurity; wherein the columnar semiconductor connection conductor layer extends to the third columnar semiconductor and surrounds the third columnar semiconductor, and is formed in the foregoing An impurity diffusion layer, a vaporization layer, or a metal layer containing a donor or acceptor impurity in the columnar semiconductor is connected to a lower region of the third columnar semiconductor.