TWI607327B - Semiconductor devices - Google Patents

Description

Semiconductor component

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, and more particularly to a layout between its outermost metal (Top metal), connection pad (Pad) openings, and conductive bumps.

Making as many electronic components as possible within a limited wafer area is one of the important goals of integrated circuit design; there are usually two possible ways to achieve this goal: one is to improve the integrated circuit process technology, and the other is in the circuit. The layout is inked. For semiconductor components that are currently commonly used with conductive bumps, the top metal can be connected to an external circuit through a connection pad (Pad) and conductive bumps. Please refer to FIG. 1 , which is directed to the outermost metal 12 , the connection pad opening 13 and the metal bump 14 of the semiconductor component 10 of the prior art. A schematic diagram of a pad layout for drawing a single conductive bump. As shown, the outermost metal 12 must cover the entire metal bump 14 so that the outermost metal 12 below the location of the metal bump 14 can no longer be used for the Wiring of the semiconductor component 10.

However, for integrated circuit chips, especially liquid crystal panel driving circuits, the number of electronic components is large and the wiring between them is complicated, and there are up to hundreds of connection pads, so that the winding area of the circuit layout is increased. Urgent issues to be solved. Therefore, it is necessary to develop a new pad layout technology for semiconductor components.

Therefore, one of the objects of the present invention is to solve the above problems.

According to an aspect of the invention, an embodiment provides a semiconductor device including: a substrate; a conductive region formed on the substrate, projected onto the substrate to form a first projection, and the first projection The figure has a first side; an insulating layer having a connection pad opening formed on the conductive region; and a metal bump formed on the insulating layer and filling the opening of the connection pad, projected thereon Forming a substrate a second projection; wherein the first side is located within the second projection.

According to another aspect of the present invention, an embodiment of the present invention provides a semiconductor device including: a substrate; a first conductive region and a second conductive region formed on the substrate, which are projected onto the substrate to form a substrate a first projection image and a second projection image, the first projection image having a first side, the second projection having a second side; a first connection pad opening and a second connection pad An opening insulating layer formed on the first conductive region and the second conductive region; and a first metal bump formed on the insulating layer and filling the opening of the first connection pad, projected on the substrate Forming a third projection image; forming a second metal bump formed on the insulating layer and filling the second connection pad opening, and projecting on the substrate to form a fourth projection image; wherein the One side is located within the third projection, and the second side is located within the fourth projection.

10, 100, 200‧‧‧ semiconductor components

12‧‧‧ outermost metal

13‧‧‧Connection pad opening

14‧‧‧Metal bumps

126, 126a‧‧‧ bottom side

126b‧‧‧ top side

110‧‧‧Substrate

120, 120a, 120b‧‧‧ conductive area

120’, 120a’, 120b’‧‧‧ first projection

121, 121a, 121b‧‧‧ first side

122, 122a, 122b‧‧‧ second side

123, 123a, 123b‧‧‧ third side

124, 124a, 124b‧‧‧ fourth side

130‧‧‧Insulation

140, 140a, 140b‧‧‧ metal bumps

140’, 140a’, 140b’‧‧‧ second projection

201, 202‧‧‧ Conductive bump combination

FIG. 1 is a schematic view showing the layout of a connection pad of a conventional semiconductor device.

Fig. 2 is a top view of a semiconductor element in accordance with a first embodiment of the present invention.

Fig. 3 is a cross-sectional view showing the structure of the element taken along the line AA' of Fig. 2.

Fig. 4 is a top view of a semiconductor element in accordance with another embodiment of the present invention.

Fig. 5 is a top view of a semiconductor element in accordance with another embodiment of the present invention.

Fig. 6 is a top view of a semiconductor element in accordance with a second embodiment of the present invention.

Figure 7 is a top plan view of a semiconductor device in accordance with another embodiment of the present invention.

Figure 8 is a top plan view of a semiconductor device in accordance with another embodiment of the present invention.

Figure 9 is a top plan view of a semiconductor device in accordance with another embodiment of the present invention.

Figure 10 is a top plan view of a semiconductor device in accordance with another embodiment of the present invention.

For a better understanding of the features, objects, and functions of the present invention, the embodiments of the invention are described in detail. In all of the specification and the drawings, the same component numbers will be used to designate the same or similar components.

In the description of the various embodiments, when an element is described as being on another element "方/上" or "lower/lower" means a situation directly or indirectly above or below the other element, which may include other elements placed between them; the so-called "directly" means No other mediation elements have been set. The descriptions of "Upper/Upper" or "Bottom/Lower" are based on the schema, but also include other possible direction changes. The so-called "first", "second", and "third" are used to describe different elements that are not limited by such predicates. For the convenience and clarity of the description, the thickness or size of each element in the drawings is expressed in an exaggerated or omitted or schematic manner, and the size of each element is not completely the actual size.

2 is a top view of a semiconductor device 100 according to a first embodiment of the present invention, which may also be referred to as a connection pad layout of the outermost layer of the semiconductor device 100, and FIG. 3 is a line AA along the second diagram. A cross-sectional view of the component structure obtained by cutting. The semiconductor device 100 includes a substrate 110, a conductive region 120 formed on the substrate 110, an insulating layer 130 formed on the conductive region 120, and an insulating layer 130 formed on the insulating layer 130 and connected to the conductive region 120. Metal bumps 140.

The substrate 110 is used to carry or support the integrated circuit process of the semiconductor device 100, and the constituent material thereof may be any semiconductor material such as germanium (Si).

The conductive region 120 is formed on the substrate 110. In this embodiment, it may represent the top metal of the semiconductor device 100, that is, connected through a connection pad (Pad) and/or a bump. To an external circuit. In order to understand the layout of the conductive region 120 on the substrate 110, we can project the conductive region 120 from the top to the bottom of the substrate 110, and the boundary of the conductive region 120 will form a projection image (below It is called the first projection map 120'). As shown in FIG. 2, the first projection image 120' of the present embodiment is a rectangle having four sides: a first side 121 on the south side (S) and a second side on the east side (E). 122. A third side 123 on the north side (N) and a fourth side 124 on the west side (W).

The insulating layer 130 is formed on the conductive region 120. In this embodiment, the outermost layer of the semiconductor device 100 can be protected to protect the semiconductor device 100 and the outermost metal of the semiconductor device 100. The environment is properly electrically isolated; as shown in FIG. 2, the insulating layer 130 has a connection pad opening 131 for exposing a portion of the conductive region 120 to the outside of the cover of the insulating layer 130, or Make A portion of the conductive region 120 is not covered by the insulating layer 130, but can serve as a window for the conductive region 120 to be connected to an external circuit. In order to understand the layout of the connection pad opening 131 on the substrate 110, the connection pad opening 131 can be projected from the top to the bottom of the substrate 110, and the boundary thereof will form the connection pad layout of the semiconductor device 100 of the present embodiment. Figure. In general, the connection pad opening 131 may completely fall within the boundary of the conductive region 120. For example, the connection pad opening 131 may be disposed in a central region of the first projection 120'; as shown in FIG. The connection pad opening 131 of this embodiment is located in the central region of the first projection image 120' in the WE direction, and is located on the south side of the first projection image 120' in the SN direction, but still completely falls on the Within the scope of the first projection map 120'.

The metal bump 140 is formed on the insulating layer 130 to fill the connection pad opening 131; that is, the conductive bump 140 is connected to the conductive region 120 via the connection pad opening 131. In order to understand the layout of the metal bump 140 on the substrate 110, the metal bump 140 can be projected from the top to the bottom of the substrate 110, and the boundary of the metal bump 140 will form a projection image (hereinafter It is called the second projection map 140'). As shown in FIG. 2, the second projection image 140' of the present embodiment is also rectangular, and has four sides: a first side on the south side (S) and a second side on the east side (E). The third side of the north side (N) and the fourth side of the west side (W).

In this embodiment, the first side 121 of the first projection 120 ′ of the conductive region 120 projected on the substrate 110 falls on the second projection 140 ′ of the metal bump 140 projected on the substrate 110 . Inside. Please simultaneously compare FIGS. 1 and 2, assuming that the metal bumps 14 and 140 of the semiconductor component for connecting the external circuit have the same size, the conductive region 120 of FIG. 2 is like the outermost layer of FIG. The bottom side 126 of the metal 12 is retracted upward, so that the second projection 140' caused by the metal bump 140 protrudes beyond the first projection 120' caused by the conductive region 120, or 2nd. The bottom side (the first side 121) of the conductive region 120 is offset from the bottom side 126 of the outermost metal 12 in the first direction, and the opening of the connection pad opening 131 is of course followed. Become smaller. As such, the area of the outermost metal used to connect the external circuitry will be reduced, and the reduced area of the outermost metal will provide for Wiring of the semiconductor component 100. In addition, the first side 121 of the first projection 120' is oriented in the direction In the case of the N retraction, the second side 122, the third side 123, or the fourth side 124 may be retracted to the second projection 140'. The semiconductor element 100 can have the effect of winding area.

In another embodiment, we can simultaneously retract the two or more sides of the first projected image 120' to further increase the wirewable area. For example, the first side 121 of the first projection 120' is retracted in the direction N, and the third side 123 opposite to the first side 121 is simultaneously retracted in the direction S to the second projection. Within the range of 140', as shown in Figure 4. For another example, the first side 121 of the first projection 120 ′ is retracted in the direction N, and the second side 122 adjacent to the first side 121 is simultaneously retracted in the direction W to the second Within the range of the projection map 140', as shown in FIG. The invention does not limit this, and which side is retracted depends on the needs of the actual circuit layout.

6 is a top view of a semiconductor device 200 according to a second embodiment of the present invention, which is a connection pad layout including a plurality of conductive bumps; wherein, a single conductive bump combination includes an outermost metal (conductive region 120), and a connection The pad opening 131 and the metal bump 140 are as shown in FIG. 1 or FIG. Taking FIG. 6 as an example, the semiconductor device 200 has five conductive bump combinations 201 and 202, which are arranged in two columns: a conductive bump combination 201 in the first column and a conductive bump combination 202 in the second column. For the conductive bump assembly 201, the connection pad opening number is 131a, the first projection image 120a' is a projection from the conductive region 120a, and the second projection image 140a' is a projection from the metal bump 140a, and The first projection 120a' is rectangular and has four sides: a first side 121a on the south side (S), a second side 122a on the east side (E), and a third side on the north side (N). 123a is located on the fourth side 124a of the west side (W). For the conductive bump assembly 202, the connection pad opening number is 131b, the first projection image 120b' is a projection from the conductive region 120b, and the second projection image 140b' is a projection from the metal bump 140b, and The first projection map 120b' is rectangular and has four sides: a first side 121b on the south side (S), a second side 122b on the east side (E), and a third side on the north side (N). 123b is located at the fourth side 124b of the west side (W). For the rest of the related description, please refer to the description of the first embodiment, and details are not described herein again.

In the embodiment, for the conductive bump assembly 201, the first projection image 120a' The first side 121a falls within the second projection 140a'. The conventional technique corresponding to this embodiment can be as shown in FIG. 7. Assuming that the metal bumps 14a, 140a, and 140b for connecting the external circuit of the semiconductor element have the same size, the conductive region 120a of FIG. 6 is like The bottom side 126a of the outermost metal 12a of FIG. 7 is upwardly retracted such that the first side 121a of the first projection 120a' is retracted in the direction N and falls within the range of the second projection 140a'. Inside. In addition, for the conductive bump assembly 202, the first side 121b and the third side 123b of the first projected image 120b' fall within the second projected image 140b'. The conductive region 120b of FIG. 6 is upwardly retracted like the bottom side edge 126a of the outermost metal 12a of FIG. 7, and the top side edge 126b thereof is simultaneously retracted downward, so that the first projection pattern 120b' is first. The side edge 121b is retracted in the direction N, and the third side edge 123b is retracted in the direction S to fall within the range of the second projection image 140b'; wherein the first side edge 121b and the third side edge 123b is the opposite side of the first projection 120b', respectively. Thus, in contrast to the prior art of Figure 7, the embodiment of Fig. 6 can be used for the outermost metal to obtain the areas B1 and B2 as shown in the figure as the winding area.

In order to make the semiconductor device 200 of FIG. 6 operate normally, the structural dimension design principles of the conductive bump assemblies 201 and 202 are provided below. However, the exemplary embodiment is merely an embodiment of the present invention and is not intended to be a limitation of the present invention. For the conductive bump assembly 201, the conductive region 120a protrudes from the conductive bump 140a by a minimum distance of 2 μm (ie, as shown in FIG. 1 to 2 μm); whether the conductive region 120a protrudes from the conductive bump 140a or the conductive portion 120a The conductive region 120a is recessed in the conductive bump 140a, and the distance between the conductive bump 140a and the connection pad opening 131a is at least 3 μm (ie, D2≧3μm, D3≧3μm as shown in the figure); if the conductive region 120a is retracted In the conductive bump 140a, the distance between the retracted conductive region 120a and the connection pad opening 131a is greater than or equal to 5 μm (ie, D4≧5 μm as shown in the figure). In addition, for the conductive bump assembly 202, the conductive region 120b protrudes from the conductive bump 140b by a minimum distance of 2 μm (ie, as shown in FIG. D5≧2 μm); whether the conductive region 120b protrudes from the conductive bump 140b or The conductive region 120b is recessed into the conductive bump 140b, and the distance between the conductive bump 140b and the connection pad opening 131b is at least 3 μm (ie, D6≧3μm, D7≧3μm as shown in the figure); if the conductive region 120b When the conductive bump 140b is indented, the distance between the indented conductive region 120b and the connection pad opening 131b is greater than or equal to 5 μm (ie, D8≧5μm, D9≧5μm as shown in the figure).

Further, FIGS. 8 to 10 are also other embodiments of the semiconductor device of the present embodiment. In Fig. 8, for the conductive bump assembly 201, the first side 123a of the first projected image 120a' falls within the second projected image 140a'. Compared with the prior art of FIG. 7, the conductive region 120a of FIG. 8 is retracted downward like the top side edge 126b of the outermost metal 12a of FIG. 7, so that the first projection 120a' is The three side edges 123a are retracted in the direction S and fall within the range of the second projection map 140a'. Moreover, for the conductive bump assembly 202, the first side 121b of the first projected image 120b' falls within the second projected image 140b'. Compared with the prior art of FIG. 7, the conductive region 120b of FIG. 8 is upwardly retracted like the bottom side 126a of the outermost metal 12a of FIG. 7, so that the first projection 120b' is first. The side edge 121b is retracted in the direction N and falls within the range of the second projection map 140b'. Thus, in contrast to the prior art of Figure 7, the embodiment of Figure 8 can be used for the outermost metal to obtain the areas C1 and C2 as shown in the figure as the winding area.

In Fig. 9, for the conductive bump assembly 201, the first side 121a and the third side 123a of the first projection 120a' fall within the second projection 140a' at the same time. Compared with the prior art of FIG. 7, the conductive region 120a of FIG. 9 is upwardly retracted like the bottom side edge 126a of the outermost metal 12a of FIG. 7, and the top side edge 126b thereof is simultaneously downwardly contracted. The first side 121a of the first projection 120a' is retracted in the direction N, and the third side 123a is retracted in the direction S to fall within the range of the second projection 140a'. Moreover, for the conductive bump assembly 202, the first side 121b of the first projected image 120b' falls within the second projected image 140b'. Compared with the prior art of FIG. 7, the conductive region 120b of FIG. 9 is upwardly retracted like the bottom side 126a of the outermost metal 12a of FIG. 7, so that the first projection 120b' is the first The side edge 121b is retracted in the direction N and falls within the range of the second projection map 140b'. Thus, in contrast to the prior art of Figure 7, the embodiment of Fig. 9 can be used for the outermost metal to obtain the areas F1, F2 and F3 as shown in the figure as the winding area.

In Fig. 10, for the conductive bump assembly 201, the first side 121a and the third side 123a of the first projection 120a' fall within the second projection 140a' at the same time. Compared with the prior art of FIG. 7, the conductive region 120a of FIG. 10 is upwardly retracted like the bottom side 126a of the outermost metal 12a of FIG. 7, and its top side 126b At the same time, the first side 121a of the first projection 120a' is retracted in the direction N, and the third side 123a is retracted in the direction S to fall within the range of the second projection 140a'. Inside. In addition, for the conductive bump assembly 202, the first side 121b and the third side 123b of the first projected image 120b' fall within the second projected image 140b'. Compared with the prior art of FIG. 7, the conductive region 120b of FIG. 10 is upwardly retracted like the bottom side edge 126a of the outermost metal 12a of FIG. 7, and the top side edge 126b thereof is simultaneously retracted downward. The first side 121b of the first projection 120b' is retracted in the direction N, and the third side 123b is retracted in the direction S to fall within the range of the second projection 140b'. Thus, compared to the prior art of FIG. 7, the embodiment of FIG. 10 can obtain the outermost metal for the regions G1, G2, and G3 as shown in the figure as the winding area.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto. It is to be understood that the scope of the present invention is not limited by the spirit and scope of the present invention, and should be considered as a further embodiment of the present invention.

100‧‧‧Semiconductor components

120‧‧‧Conducting area

120’‧‧‧ first projection

121‧‧‧ first side

122‧‧‧Second side

123‧‧‧ third side

124‧‧‧ fourth side

131‧‧‧Connection pad opening

140‧‧‧Metal bumps

140’‧‧‧second projection

Claims (11)

A semiconductor device comprising: a substrate; a metal conductive region formed on the substrate, projected onto the substrate to form a first projected image, and the first projected image has a first side; An insulating layer connected to the opening of the pad, formed on the metal conductive region; and a metal bump formed on the insulating layer and filling the opening of the connection pad, which is projected on the substrate to form a second projection The metal bump is used to connect to an external circuit; wherein the first side is located within the second projection. The semiconductor device of claim 1, wherein the first projection further has a second side, and the second side is located within the second projection. The semiconductor component of claim 2, wherein the first side is opposite to the second side. The semiconductor component of claim 2, wherein the first side is adjacent to the second side. A semiconductor device comprising: a substrate; a first metal conductive region formed on the substrate; and a second metal conductive region projected onto the substrate to form a first projected image and a second projected image And the first projection has a first side, the second projection has a second side; an insulating layer having a first connection pad opening and a second connection pad opening formed in the first a metal conductive region and the metal second conductive region; and a first metal bump formed on the insulating layer and filling the opening of the first connection pad, projected on the substrate to form a third projection And the first metal bump is connected to a first external circuit; a second metal bump formed on the insulating layer and filling the opening of the second connection pad is projected on the substrate to form a first Four projections, and the second metal protrusion The block is configured to connect to a second external circuit; wherein the first side is located within the third projection, and the second side is located within the fourth projection. The semiconductor device of claim 5, wherein the first projection further has a third side, and the third side is located within the third projection. The semiconductor device of claim 6, wherein the first side is adjacent to the third side. The semiconductor component of claim 6, wherein the first side is opposite to the third side. The semiconductor device of claim 6, wherein the second projection further has a fourth side, and the fourth side is located within the fourth projection. The semiconductor component of claim 9, wherein the second side is adjacent to the fourth side. The semiconductor component of claim 9, wherein the second side is opposite to the fourth side.