TW201310596A - 堆疊式晶片封裝及其製造方法 - Google Patents

堆疊式晶片封裝及其製造方法 Download PDF

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TW201310596A
TW201310596A TW100130575A TW100130575A TW201310596A TW 201310596 A TW201310596 A TW 201310596A TW 100130575 A TW100130575 A TW 100130575A TW 100130575 A TW100130575 A TW 100130575A TW 201310596 A TW201310596 A TW 201310596A
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semiconductor wafer
semiconductor
wafer
bumps
stacked
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TW100130575A
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Hong-Dyi Chang
Tai-Hung Lin
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Novatek Microelectronics Corp
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Priority to TW100130575A priority Critical patent/TW201310596A/zh
Priority to US13/591,225 priority patent/US20130049192A1/en
Publication of TW201310596A publication Critical patent/TW201310596A/zh

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Abstract

一種半導體封裝結構，用於一堆疊式晶片，包含有一第一半導體晶片，包含有一金屬層；一矽穿孔結構，貫穿該第一半導體晶片之一上表面，並電性連接至該金屬層；一重佈線路層，形成於該第一半導體晶片之該上表面，並電性連接至該矽穿孔結構；以及一第二半導體晶片，設置於該第一半導體晶片之上，並透過該重佈線路層，連接至該第一半導體晶片。

Description

堆疊式晶片封裝及其製造方法
本發明係指一種堆疊式晶片封裝及其製造方法，尤指一種利用矽穿孔實現之堆疊式晶片封裝及其製造方法。
液晶螢幕(Liquid Crystal Display，LCD)具有外型輕薄、低電源消耗以及低輻射等特性，已被廣泛地應用在電腦系統、行動電話、個人數位助理(PDA)、數位相機及平板電腦等資訊產品上。一般而言，液晶螢幕的驅動晶片(Driving chip)一般利用玻璃覆晶(Chip on Glass，CoG)封裝技術將驅動晶片直接安裝至顯示器的玻璃基板上，以縮小所需電路面積。
請參考第1A及1B圖，第1A及1B圖分別為習知一半導體封裝結構10之剖面示意圖及俯視示意圖。半導體封裝結構10用來實現一單晶片式驅動晶片，其係將液晶螢幕的驅動電路(Driving Circuit)和靜態隨機存取記憶體(Static Random Access Memory，SRAM)電路以相同半導體製程設計於一佈局區塊100中，並透過凸塊BMP1～BMPn對外交換訊號。此設計造成半導體封裝結構10面積尺寸較大(即第1B圖中之一晶片高度Y1過大)，並造成製程過程中一片晶圓(wafer)可切割之晶片(chip)數目較少，故產品出貨數量會受限於半導體廠於該半導體製程所能提供的產能，無法滿足客戶訂單須求。此外，單一佈局區塊100同時包含驅動電路和記憶體電路，因此設計上電路複雜度高，亦可能造成製程良率較低。再者，佈局區塊100尺寸較大，內部金屬佈線長度難以有效縮短、電阻值亦難以降低，造成傳輸速度較慢、寄生電容及耗電等問題。
因此，習知單一佈局區塊的設計方式不僅佔據相當大的面積，對於追求將驅動晶片的面積、耗電量最小化、並同時提高良率、傳輸速度的業界來說，實有改進的必要。
因此，本發明之主要目的即在提供一種堆疊式晶片封裝及其製造方法。
本發明揭露一種半導體封裝結構，用於一堆疊式晶片，包含有一第一半導體晶片，包含有一金屬層；一矽穿孔結構，貫穿該第一半導體晶片之一上表面，並電性連接至該金屬層；一重佈線路層，形成於該第一半導體晶片之該上表面，並電性連接至該矽穿孔結構；以及一第二半導體晶片，設置於該第一半導體晶片之上，並透過該重佈線路層，連接至該第一半導體晶片。
本發明另揭露一種形成一半導體封裝結構的方法，該半導體封裝結構用於一堆疊式晶片，該方法包含有形成包含有一金屬層之一第一半導體晶片；形成一矽穿孔結構，其貫穿該第一半導體晶片之一上表面，並電性連接至該金屬層；形成一重佈線路層，其位於該第一半導體晶片之該上表面，並電性連接至該矽穿孔結構；以及於該第一半導體晶片之上，形成一第二半導體晶片，並透過該重佈線路層，連接至該第一半導體晶片。
請參考第2A及2B圖，第2A及2B圖分別為本發明實施例之一半導體封裝結構20之剖面示意圖及俯視示意圖。半導體封裝結構20可實現一堆疊式(stacked)晶片，如第2A圖所示，其係由一第一半導體晶片200、一第二半導體晶片202、一矽穿孔(through-silicon-via)結構208、一重佈線路層(redistribution layer)210及一封裝材料214所組成。第一半導體晶片200包含有一金屬層206，可用以佈置驅動電路。矽穿孔結構208貫穿第一半導體晶片200之一上表面而電性連接至金屬層206。此外，第一半導體晶片200之一下表面形成有複數個凸塊BMP_L1～BMP_Lm，用以連接至一外部裝置(未顯示於第2A、2B圖)。重佈線路層210係形成於第一半導體晶片200之該上表面，用來連接第一半導體晶片200及第二半導體晶片202。第二半導體晶片202可佈置靜態隨機存取記憶體電路，其係堆疊於第一半導體晶片200之上，且於一下表面形成有複數個凸塊BMP_U1～BMP_Un，用來透過重佈線路層210及矽穿孔結構208，電性連接至第一半導體晶片200之金屬層206。封裝材料214係包圍第二半導體晶片202，用來提升半導體封裝結構20之整體晶片強度。
進一步地，如第2B圖所示，半導體封裝結構20之一晶片高度為Y2。相較於習知半導體封裝結構10，半導體封裝結構20之電路面積較小(即半導體封裝結構20之晶片高度Y2小於半導體封裝結構10之晶片高度Y1)，並可透過將第一半導體晶片200及第二半導體晶片202分別由不同半導體製程製作而成，進而提高晶片製作過程之良率及產能。
需注意的是，第2A圖及第2B圖係用以說明本發明之概念，本領域具通常知識者可據以做不同修飾，而不限於此。舉例來說，半導體封裝結構20可為一玻璃覆晶(Chip on Glass，CoG)驅動晶片，且驅動電路和靜態隨機存取記憶體電路可分別設置於第一半導體晶片200及第二半導體晶片202中。在此情形下，第一半導體晶片200及第二半導體晶片202可分別由不同半導體製程製作而成，例如，用於設置驅動電路之第一半導體晶片200可採較低階半導體製程製作而成，而用於設置記憶體電路之第二半導體晶片202可採較高階半導體製程製作而成。如此一來，相較於半導體封裝結構10，第一半導體晶片200及第二半導體晶片202之電路面積皆可縮小(如半導體封裝結構10之40～50%)，故製程中所使用之一片晶圓(wafer)可切割之晶片(chip)數目亦可增加(如增加70～100%)，進而大幅提高產能。再者，由於驅動晶片之驅動電路及記憶體電路被分割為兩獨立晶片分開製作，半導體封裝結構20之電路複雜度亦會低於半導體封裝結構10，因此有助於提升製程良率。此外，由於半導體封裝結構20被分割為第一、第二半導體晶片200、202，故可由兩製程生產線平行製作而成，亦可提升生產速度。
另一方面，矽穿孔結構208及重佈線路層210係用來連接第一半導體晶片200及第二半導體晶片202，其較佳地具有低阻值，藉此，半導體封裝結構20可有效透過縮短金屬導線長度及連線電阻，減少晶片面積，增加資料傳送速度，並具有小體積、高效率、低耗電量及成本之優勢。另外，形成於第一半導體晶片200之下表面的凸塊BMP_L1～BMP_Lm其材質可選自銅、鎳、金或其合金，而形成於第二半導體晶片202之下表面的凸塊BMP_U1～BMP_Un其材質可選自覆晶(Flip-Chip)凸塊、焊錫凸塊(Solder bump)、微凸塊(Micro bump)及銅柱凸塊(Copper pillar)等，但本領域具通常知識者當可據以進行修飾或變化，不限於此。此外，封裝材料214可利用擴散型封裝(Fan-out Package)和晶片切割(die saw)等方法形成，以提升半導體封裝結構20之整體晶片強度並完成最終堆疊式晶片成品。
關於半導體封裝結構20之製作方式，可進一步參考第3圖，第3圖為本發明實施例一半導體封裝流程30之示意圖。半導體封裝流程30包含以下步驟：步驟300：開始。
步驟302：形成包含有金屬層206之第一半導體晶片200。
步驟304：形成一矽穿孔結構208，其貫穿第一半導體晶片200之一上表面，並電性連接至金屬層206。
步驟306：形成一重佈線路層210，其位於第一半導體晶片200之該上表面，並電性連接至該矽穿孔結構。
步驟308：於第一半導體晶片200之上，形成一第二半導體晶片202，並透過重佈線路層210，連接至第一半導體晶片200。
步驟310：結束。
半導體封裝流程30之詳細說明或變化可參考前述，於此不贅述。
需注意的是，本發明之主要精神在於透過將一晶片分割為上、下半導體晶片，再透過矽穿孔及重佈線路層等結構連接上、下半導體晶片以形成堆疊式晶片，凡依此所做之各種變化皆屬本發明之範疇。舉例而言，半導體封裝結構20係分割為第一半導體晶片200及第二半導體晶片202，但亦可分割為三個以上之半導體晶片，只要能透過矽穿孔及重佈線路層等結構將該多個晶片互相連接，達到縮小體積、提高傳輸率、降低耗電量等優勢即可。另外，上述實施例將半導體封裝結構20依照電路功能分割為驅動電路及記憶體電路兩部分，但分割的方式亦不在此限，只要可達到有助利用多種不同導體製程分別製作各部分，以達到提高產能或良率，或降低製程複雜度即可。半導體封裝結構20之製程亦不在此限，本領域具通常知識者當可據以進行修飾或變化。例如，第一半導體晶片200及第二半導體晶片202可由同一片晶圓切割而成，但亦可由不同晶圓切割而成，以達到更高度的異質性整合(heterogeneous integration)。而凸塊BMP_L1～BMP_Lm及凸塊BMP_U1～BMP_Un之材質亦不在上述所限，只要能達到降低阻值、有助於堆疊式晶片之整合度並提高傳輸率之目的即可。
綜上所述，本發明之半導體封裝結構藉由將一驅動晶片分割為兩不同晶片，分別由不同半導體製程製作而成，再將兩晶片組合為一堆疊式晶片。如此一來，可得到較小電路面積、較高傳輸率與低耗電量，而製程過程中之產能及良率也可大幅提高。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10、20．．．半導體封裝結構
100．．．佈局區塊
200．．．第一半導體晶片
202．．．第二半導體晶片
BMP1～BMPn、BMP_L1～BMP_Lm、BMP_U1～BMP_Un．．．凸塊
206．．．金屬層
208．．．矽穿孔
210．．．重佈線路層
214．．．封裝材料
第1A圖為習知一堆疊式晶片之剖面示意圖。
第1B圖為第1A圖中堆疊式晶片之俯視示意圖。
第2A圖為依據一實施例之一堆疊式晶片之剖面示意圖。
第2B圖為第2A圖中堆疊式晶片之俯視示意圖。
第3圖為依據一實施例一流程之示意圖。
20．．．堆疊式晶片
200．．．第一半導體晶片
202．．．第二半導體晶片
BMP_L1～BMP_Lm、BMP_U1～BMP_Un．．．凸塊
206．．．金屬層
208．．．矽穿孔
210．．．重佈線路層
214．．．封裝材料

Claims (16)

  1. 一種半導體封裝結構，用於一堆疊式晶片，包含有：一第一半導體晶片，包含有一金屬層；一矽穿孔結構，貫穿該第一半導體晶片之一上表面，並電性連接至該金屬層；一重佈線路層，形成於該第一半導體晶片之該上表面，並電性連接至該矽穿孔結構；以及一第二半導體晶片，設置於該第一半導體晶片之上，並透過該重佈線路層，連接至該第一半導體晶片。
  2. 如請求項1之堆疊式半導體封裝結構，其中該堆疊式晶片為一玻璃覆晶(Chip on Glass，CoG)晶片。
  3. 如請求項1之堆疊式半導體封裝結構，其中該第二半導體晶片係透過複數個凸塊電性連接至該重佈線路層，以連接至該第一半導體晶片。
  4. 如請求項3之堆疊式半導體封裝結構，其中該複數個凸塊係選自覆晶(Flip-Chip)凸塊、焊錫凸塊(Solder bump)、微凸塊(Micro bump)及銅柱凸塊(Copper pillar)。
  5. 如請求項1之堆疊式半導體封裝結構，其中該第一半導體晶片另包含有複數個凸塊，形成於該第一半導體晶片之一下表面，用以連接至一外部裝置。
  6. 如請求項5之堆疊式半導體封裝結構，其中該第一半導體晶片之該複數個凸塊之材質係選自銅、鎳、金或其合金。
  7. 如請求項1之堆疊式半導體封裝結構，其中該第一半導體晶片及該第二半導體晶片係以不同半導體製程製作而成。
  8. 如請求項1之堆疊式半導體封裝結構，另包含一封裝材料，包圍該第二半導體晶片。
  9. 一種形成一半導體封裝結構的方法，該半導體封裝結構用於一堆疊式晶片，該方法包含有：形成包含有一金屬層之一第一半導體晶片；形成一矽穿孔結構，其貫穿該第一半導體晶片之一上表面，並電性連接至該金屬層；形成一重佈線路層，其位於該第一半導體晶片之該上表面，並電性連接至該矽穿孔結構；以及於該第一半導體晶片之上，形成一第二半導體晶片，並透過該重佈線路層，連接至該第一半導體晶片。
  10. 如請求項9之方法，其中該堆疊式晶片為一玻璃覆晶(Chip on Glass，CoG)晶片。
  11. 如請求項9之方法，其中形成該第二半導體晶片包含形成複數個凸塊，使該第二半導體晶片透過該複數個凸塊電性連接至該重佈線路層，以連接至該第一半導體晶片。
  12. 如請求項11之方法，其中該複數個凸塊係選自覆晶(Flip-Chip)凸塊、焊錫凸塊(Solder bump)、微凸塊(Micro bump)及銅柱凸塊(Copper pillar)。
  13. 如請求項9之方法，其中該第一半導體晶片另包含有複數個凸塊，形成於該第一半導體晶片之一下表面，用以連接至一外部裝置。
  14. 如請求項13之方法，其中該第一半導體晶片之該複數個凸塊之材質係選自銅、鎳、金或其合金。
  15. 如請求項9之方法，其中該第一半導體晶片及該第二半導體晶片係以不同半導體製程製作而成。
  16. 如請求項9之方法，其中該半導體封裝結構另包含一封裝材料，包圍該第二半導體晶片。
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