TW201304198A - Light-emitting diode package structure - Google Patents
Light-emitting diode package structure Download PDFInfo
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- TW201304198A TW201304198A TW100124400A TW100124400A TW201304198A TW 201304198 A TW201304198 A TW 201304198A TW 100124400 A TW100124400 A TW 100124400A TW 100124400 A TW100124400 A TW 100124400A TW 201304198 A TW201304198 A TW 201304198A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
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Abstract
Description
本發明係有關於一種封裝結構，且特別是有關於一種發光二極體封裝結構(light-emitting diode package structure)。The present invention relates to a package structure, and more particularly to a light-emitting diode package structure.
發光二極體具有一P/N接面，而對發光二極體的P/N接面施加電壓可使發光二極體發光。發光二極體元件可廣泛地使用在各種應用中，例如指示器(indicator)、招牌、照明、以及其他種類的照明元件。發光二極體(light-emitting diode,LED)由於體積小、使用壽命長、耗電量低與亮度高等優點，已逐漸取代傳統的燈泡，成為目前最重要的發光元件。The light-emitting diode has a P/N junction, and a voltage is applied to the P/N junction of the light-emitting diode to cause the light-emitting diode to emit light. Light-emitting diode elements are widely used in a variety of applications, such as indicators, signage, lighting, and other types of lighting elements. Light-emitting diodes (LEDs) have gradually replaced traditional light bulbs due to their small size, long service life, low power consumption and high brightness, making them the most important light-emitting components.
傳統上是以表面黏著技術製程(surface mount technology,SMT)製作發光二極體。第1A~1D圖顯示一習知使用表面黏著技術的封裝製程剖面示意圖，其中該封裝結構為一水平式封裝結構。在第1A圖中，首先提供一支架(lead-frame)11，其包括一散熱塊11a、複數個導線腳11b、及一主體部分11c。接著，如第1B圖所示，使用固晶膠將發光二極體晶片21固定於支架11中的散熱塊11a上，其中晶片21包括兩個電性相反之電極21b、21c於晶片21的表面上。在固定晶片21後，進行打線31使晶片21上之電極21a、21b電性連接至複數個導線腳11b，其中導線31如第1C圖所示。完成打線31後，在主體部分11c之其中包括晶片21、導線31、及導線腳11b之凹槽中，灌入封裝膠41以完成封裝，如第1D圖所示。Traditionally, surface mount technology (SMT) has been used to fabricate light-emitting diodes. 1A-1D shows a schematic diagram of a conventional package process using surface mount technology, wherein the package structure is a horizontal package structure. In Fig. 1A, a lead-frame 11 is first provided, which includes a heat sink block 11a, a plurality of wire legs 11b, and a body portion 11c. Next, as shown in FIG. 1B, the light-emitting diode chip 21 is fixed on the heat-dissipating block 11a in the holder 11 by using a solid crystal glue, wherein the wafer 21 includes two opposite-electrode electrodes 21b, 21c on the surface of the wafer 21. on. After the wafer 21 is fixed, the wire 31 is made to electrically connect the electrodes 21a, 21b on the wafer 21 to a plurality of wire legs 11b, wherein the wires 31 are as shown in Fig. 1C. After the wire bonding 31 is completed, in the recess of the main body portion 11c including the wafer 21, the wires 31, and the wire legs 11b, the encapsulant 41 is poured to complete the packaging as shown in Fig. 1D.
以傳統表面黏著技術製程製作發光二極體，需將發光二極體晶片以固晶、打線、點膠等製程製作於支架上，之後再使用銲錫膏經回焊將封裝結構固定於已鋪設線路的電路板上。此製程不僅繁瑣費時，還有斷線、封裝膠剝離、固晶膠散熱不佳等缺點，且製作出的發光二極體封裝結構具有毫米尺寸，無法將尺寸進一步微縮。The light-emitting diode is fabricated by a conventional surface-adhesive technology process, and the light-emitting diode chip is fabricated on the support by a method of solid crystal, wire bonding, dispensing, etc., and then the soldering paste is used for re-welding to fix the package structure to the laid circuit. On the circuit board. This process is not only cumbersome and time consuming, but also has the disadvantages of wire breakage, encapsulation peeling, poor heat dissipation of the solid crystal glue, and the fabricated LED package structure has a millimeter size, and the size cannot be further reduced.
因此，需提出一種改良的發光二極體封裝結構以克服上列缺點。Therefore, an improved light emitting diode package structure needs to be proposed to overcome the above disadvantages.
本發明係有關一種發光二極體封裝結構，包括：一螢光基板；一發光二極體晶片，設置於該螢光基板上，該發光二極體晶片具有一對電極；一線路，設置於該螢光基板上，且電性連接至該發光二極體晶片之該對電極；一保護層，形成於該發光二極體晶片上，且具有一開口露出部分該發光二極體晶片；及一散熱塊，設置於該保護層上且填入該開口。The invention relates to a light emitting diode package structure, comprising: a fluorescent substrate; a light emitting diode chip disposed on the fluorescent substrate, the light emitting diode chip has a pair of electrodes; The phosphor substrate is electrically connected to the pair of electrodes of the LED chip; a protective layer is formed on the LED chip and has an opening to expose a portion of the LED chip; A heat dissipating block is disposed on the protective layer and fills the opening.
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：The above and other objects, features and advantages of the present invention will become more <RTIgt;
以下特舉出本發明之實施例，並配合所附圖式作詳細說明，而在圖式或說明中所使用的相同符號表示相同或類似的部分，且在圖式中，實施例之形狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖式中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形狀。此外，當某一層被描述為在另一層(或基底)”上”時，其可代表該層與另一層(或基底)為直接接觸，或兩者之間另有其他層存在。另外，特定之實施例僅為揭示本發明使用之特定方式，其並非用以限定本發明。The embodiments of the present invention are described in detail below with reference to the drawings, and the same reference numerals are used in the drawings or the description of the same or similar parts, and in the drawings, the shapes of the embodiments or The thickness can be enlarged and simplified or conveniently marked. Further, portions of the various elements in the drawings will be described separately, and it is noted that elements not shown or described in the drawings are shapes known to those of ordinary skill in the art. In addition, when a layer is described as being "an" another layer (or substrate), it can mean that the layer is in direct contact with another layer (or substrate) or otherwise. In addition, the specific embodiments are merely illustrative of specific ways of using the invention, and are not intended to limit the invention.
本發明之發光二極體封裝結構是先將一發光二極體晶片固定於一螢光基板上，再以半導體製程將線路、保護層、散熱塊或散熱基板等製作完成，可形成具有微米等級的超薄發光二極體封裝體。The light emitting diode package structure of the present invention firstly fixes a light emitting diode chip on a fluorescent substrate, and then completes a circuit, a protective layer, a heat dissipating block or a heat dissipating substrate by a semiconductor process, and can be formed into a micron level. Ultra-thin LED package.
第2圖為一根據本發明實施例之發光二極體封裝結構200的剖面圖。首先，提供一螢光基板10，其中螢光基板10可包括陶瓷螢光基板或矽膠螢光基板。螢光基板10的厚度可約為10-40 μm。在一些實施例中，陶瓷螢光基板10的形成可藉由鍛燒螢光粉及陶瓷粉末的混合物，其中陶瓷粉末為例如氧化鋁或氧化矽粉末。在其他實施例中，矽膠螢光基板10的形成可藉由先混煉螢光粉及塑料的混合物，再將混煉後的混合物射出加工處理而得到想要的基板，其中塑料為例如環形嵌段共聚物(cyclic block copolymer,CBC)或環烯烴共聚物(cyclic olefin copolymer,COC)。2 is a cross-sectional view of a light emitting diode package structure 200 in accordance with an embodiment of the present invention. First, a fluorescent substrate 10 is provided, wherein the fluorescent substrate 10 may include a ceramic fluorescent substrate or a silicone fluorescent substrate. The phosphor substrate 10 may have a thickness of about 10 to 40 μm. In some embodiments, the ceramic phosphor substrate 10 can be formed by calcining a mixture of phosphor powder and ceramic powder, such as alumina or cerium oxide powder. In other embodiments, the silicone phosphor substrate 10 can be formed by first mixing a mixture of phosphor powder and plastic, and then ejecting the kneaded mixture to obtain a desired substrate, wherein the plastic is, for example, a ring-shaped embedded layer. A cyclic block copolymer (CBC) or a cyclic olefin copolymer (COC).
接著，設置一發光二極體晶片20於螢光基板10上。發光二極體晶片20具有一對設置於晶片20之上表面的電極20a，其分別為P電極和N電極。在一些實施例中，晶片20的設置方式可藉由先形成一透明膠(未顯示)，包括環氧樹脂或矽膠，於螢光基板10即將設置發光二極體晶片20的區域上，再將晶片20設置於透明膠上，藉此接合晶片20與螢光基板10。發光二極體晶片20可為一水平式晶片，且至少包括一p型半導體層、一主動區域及一n型半導體層，其中主動區域位於p型及n型半導體層之間。另外，在晶片20相反於螢光基板10的一側，可選擇性地形成一金屬反射層，金屬反射層之材質可為Al、Ag、Ni、Ph、Pd、Pt、Ru、Au及上述任意組合。上述p型、n型半導體層可為III-V族半導體材料，例如III-V族GaN材料，並以AlxGayIn(1-x-y)N(0≦x≦1,0≦y≦1)表示。從發光二極體晶片20所發出的光較佳為藍光或紫外光，但也可為其他合適波長，且所發出的光將以第2圖所示之方向為基準，朝螢光基板10向下發出，如箭號15所示。若發光二極體晶片20所發出的光為藍光或紫外光，可選擇合適的螢光基板發光二極體封裝結構200之最終出光顏色混合為白光。在一些實施例中，發光二極體晶片20的厚度可約為70-90 μm。Next, a light emitting diode chip 20 is disposed on the fluorescent substrate 10. The light-emitting diode wafer 20 has a pair of electrodes 20a disposed on the upper surface of the wafer 20, which are respectively a P electrode and an N electrode. In some embodiments, the wafer 20 can be disposed by first forming a transparent adhesive (not shown), including epoxy or silicone, on the area of the fluorescent substrate 10 where the light-emitting diode wafer 20 is to be disposed, and then The wafer 20 is disposed on the transparent adhesive, thereby bonding the wafer 20 and the fluorescent substrate 10. The LED substrate 20 can be a horizontal wafer and includes at least a p-type semiconductor layer, an active region and an n-type semiconductor layer, wherein the active region is between the p-type and n-type semiconductor layers. In addition, a metal reflective layer may be selectively formed on the side of the wafer 20 opposite to the fluorescent substrate 10. The metal reflective layer may be made of Al, Ag, Ni, Ph, Pd, Pt, Ru, Au, and any of the above. combination. The p-type, n-type semiconductor layer may be a III-V semiconductor material, such as a III-V GaN material, and have Al x Ga y In (1-xy) N (0≦x≦1, 0≦y≦1 ) said. The light emitted from the LED chip 20 is preferably blue light or ultraviolet light, but may be other suitable wavelengths, and the emitted light will be directed toward the fluorescent substrate 10 based on the direction shown in FIG. Issued below, as indicated by arrow 15. If the light emitted by the LED substrate 20 is blue light or ultraviolet light, the final light-emitting color of the suitable fluorescent substrate light-emitting diode package structure 200 can be mixed into white light. In some embodiments, the light emitting diode chip 20 can have a thickness of about 70-90 μm.
在設置發光二極體晶片20於螢光基板10上之後，設置一線路30於螢光基板10上。線路30位於螢光基板10的上表面上，此外，線路30更沿晶片20之側壁延伸且電性連接至上述電極20a，因此線路30至少有一部分被設置於晶片20上。線路30之材料可為金、銅或其他具有良好導電性之金屬。線路30之形成可利用沉積、微影、蝕刻等技術，其中沉積可利用化學氣相沉積、物理氣相沉積、電鍍或其他合適之沉積方法，而蝕刻可為乾蝕刻或濕蝕刻。After the light-emitting diode chip 20 is placed on the fluorescent substrate 10, a line 30 is disposed on the fluorescent substrate 10. The line 30 is located on the upper surface of the fluorescent substrate 10. Further, the line 30 extends along the sidewall of the wafer 20 and is electrically connected to the electrode 20a. Therefore, at least a portion of the line 30 is disposed on the wafer 20. The material of line 30 can be gold, copper or other metal with good electrical conductivity. The formation of line 30 may utilize deposition, lithography, etching, etc., where deposition may utilize chemical vapor deposition, physical vapor deposition, electroplating, or other suitable deposition methods, and the etching may be dry etching or wet etching.
接著，形成一保護層40於發光二極體晶片20上，其中保護層40具有一開口40a於晶片20的上方，部分露出發光二極體晶片20。例如可先利用化學氣相沉積或其他合適之沉積方法將保護層40毯覆性地覆蓋在上方，再以微影及蝕刻製程形成開口40a。開口40a的大小或形狀並不限定，且可依需要調整。保護層40的厚度可約為90-110 μm。保護層40之材料可包括聚亞醯胺、苯環丁烯(butylcyclobutene,BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates)或前述之組合。Next, a protective layer 40 is formed on the LED substrate 20, wherein the protective layer 40 has an opening 40a above the wafer 20 to partially expose the LED wafer 20. For example, the protective layer 40 may be blanket-covered above by chemical vapor deposition or other suitable deposition method, and the opening 40a may be formed by a photolithography and etching process. The size or shape of the opening 40a is not limited and can be adjusted as needed. The protective layer 40 may have a thickness of about 90-110 μm. The material of the protective layer 40 may include polyamidamine, butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, acrylates or Combination of the foregoing.
在形成保護層40之後，在一些實施例中，更包括順應性地形成一黏著層50於保護層40之上表面及開口40a中。黏著層50之作用主要在於接合保護層40及即將形成的散熱塊60。黏著層50之材質可包括Ti及Cu。黏著層50的厚度可約為5-10 μm。在其他實施例中，可不形成上述黏著層。After forming the protective layer 40, in some embodiments, it further includes conformingly forming an adhesive layer 50 on the upper surface of the protective layer 40 and in the opening 40a. The adhesive layer 50 functions primarily to bond the protective layer 40 and the heat sink 60 to be formed. The material of the adhesive layer 50 may include Ti and Cu. The thickness of the adhesive layer 50 can be about 5-10 μm. In other embodiments, the above adhesive layer may not be formed.
接著，設置一散熱塊60於保護層40上，且填入該開口40a。散熱塊60的材料可為一般習知之各種散熱材料，例如銅、鋁或鋁合金。散熱塊60最厚部分的厚度t可約為40-60 μm。Next, a heat dissipating block 60 is disposed on the protective layer 40 and filled in the opening 40a. The material of the heat slug 60 may be various conventional heat dissipating materials such as copper, aluminum or aluminum alloy. The thickness t of the thickest portion of the heat slug 60 can be about 40-60 μm.
在散熱塊60形成於保護層40上之後，可形成一共晶層70於散熱塊60上方。共晶層70之材質可為金錫合金(AuSn)或擇自下列材料至少其一：Au、Ti、Ni、Pt、Rh、Al、In及Sn。共晶層70之厚度可約為1-5 μm。共晶層70之作用在於可藉由該層將發光二極體封裝結構200接合至例如一電路板，而使用熔點較低的共晶材質可使之後的接合得以在較低溫度下進行。另外，除散熱塊6所提供良好的導熱外，共晶層也可提供額外的導熱，使發光二極體封裝200的整體導熱性質更加良好。After the heat slug 60 is formed on the protective layer 40, a eutectic layer 70 may be formed over the heat slug 60. The material of the eutectic layer 70 may be gold tin alloy (AuSn) or at least one of the following materials: Au, Ti, Ni, Pt, Rh, Al, In, and Sn. The eutectic layer 70 may have a thickness of about 1-5 μm. The eutectic layer 70 functions to bond the light emitting diode package structure 200 to, for example, a circuit board by using the layer, and the lower bonding temperature of the eutectic material allows the subsequent bonding to be performed at a lower temperature. In addition, in addition to the good thermal conductivity provided by the heat slug 6, the eutectic layer can provide additional thermal conductivity, which makes the overall thermal conductivity of the LED package 200 better.
參見第2圖，根據於本發明之實施例所提供的發光二極體封裝結構200包括螢光基板10，以及在螢光基板10上依序形成的發光二極體晶片20、線路30、保護層40、黏著層50、散熱塊60及共晶層70。發光二極體晶片20設置於螢光基板10上，且具有一對設置於晶片20之上表面的電極20a。線路30設置於螢光基板10上，並沿晶片20之側壁延伸且電性連接至電極20a，因此線路30至少有一部分被設置於晶片20上。保護層40形成於晶片20上，且具有一開口露出部分晶片20。散熱塊60形成於保護層40上，且填入保護層40之開口。Referring to FIG. 2, a light emitting diode package structure 200 according to an embodiment of the present invention includes a fluorescent substrate 10, and a light emitting diode chip 20, a line 30, and a protection formed on the fluorescent substrate 10 in sequence. Layer 40, adhesive layer 50, heat slug 60 and eutectic layer 70. The light emitting diode chip 20 is disposed on the fluorescent substrate 10 and has a pair of electrodes 20a disposed on the upper surface of the wafer 20. The line 30 is disposed on the fluorescent substrate 10 and extends along the sidewall of the wafer 20 and is electrically connected to the electrode 20a. Therefore, at least a portion of the wiring 30 is disposed on the wafer 20. The protective layer 40 is formed on the wafer 20 and has an opening to expose a portion of the wafer 20. The heat dissipation block 60 is formed on the protective layer 40 and filled in the opening of the protective layer 40.
因此，如第2圖所示，本發明實施例之發光二極體封裝結構200可具有約130-200 μm之總厚度T，例如小於約200 μm。這也就是說，本發明所提供之發光二極體封裝結構可具有微米等級的總厚度。本發明之發光二極體封裝結構還具有下列優點，例如在製程中不需打線、不需封裝膠、並且在晶片與基板間無間隙而可增加散熱，因此可克服例如製程繁雜費時、斷線、封裝膠剝離、固晶膠散熱不佳等的缺點。Therefore, as shown in FIG. 2, the LED package structure 200 of the embodiment of the present invention may have a total thickness T of about 130-200 μm, for example, less than about 200 μm. That is to say, the light emitting diode package structure provided by the present invention can have a total thickness of a micron order. The LED package structure of the invention also has the following advantages, such as no need for wire bonding, no encapsulation glue, and no gap between the wafer and the substrate to increase heat dissipation, so that, for example, the process is complicated, time-consuming, and broken. The disadvantages of poor peeling of the encapsulant and poor heat dissipation of the solid crystal adhesive.
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.
10．．．螢光基板10. . . Fluorescent substrate
11．．．支架11. . . support
11a、60．．．散熱塊11a, 60. . . Heat sink
11b．．．導線腳11b. . . Wire foot
11c．．．主體部分11c. . . main part
15．．．出光方向15. . . Light direction
20、21．．．發光二極體晶片20, 21. . . Light-emitting diode chip
20a、21a、21b．．．電極20a, 21a, 21b. . . electrode
30．．．線路30. . . line
31．．．導線31. . . wire
40．．．保護層40. . . The protective layer
41．．．封裝膠41. . . Packaging adhesive
40a．．．開口40a. . . Opening
50．．．黏著層50. . . Adhesive layer
70．．．共晶層70. . . Eutectic layer
200．．．發光二極體封裝結構200. . . Light emitting diode package structure
t、T．．．厚度t, T. . . thickness
第1A~1D圖顯示一習知使用表面黏著技術的封裝製程剖面示意圖。Figures 1A-1D show a schematic cross-sectional view of a conventional packaging process using surface mount technology.
第2圖為一根據本發明實施例之發光二極體封裝結構200的剖面圖。2 is a cross-sectional view of a light emitting diode package structure 200 in accordance with an embodiment of the present invention.
10．．．螢光基板10. . . Fluorescent substrate
15．．．出光方向15. . . Light direction
20．．．發光二極體晶片20. . . Light-emitting diode chip
20a．．．電極20a. . . electrode
30．．．線路30. . . line
40．．．保護層40. . . The protective layer
40a．．．開口40a. . . Opening
50．．．黏著層50. . . Adhesive layer
60．．．散熱塊60. . . Heat sink
70．．．共晶層70. . . Eutectic layer
200．．．發光二極體封裝結構200. . . Light emitting diode package structure
t、T．．．厚度t, T. . . thickness
Claims (12)
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| CN105047795A (en) * | 2015-08-26 | 2015-11-11 | 朱中华 | Preparation methods for fluorescent substrate and light-emitting device |
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| CN1521863A (en) * | 2003-02-10 | 2004-08-18 | 光磊科技股份有限公司 | Light-emitting diode packaging device |
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