201248772 六、發明說明： 【發明所屬之技術領域】 本發明係關於搬運半導體之半導體搬運用治具’尤其 是，與適合外部連結端子之間隔較窄之半導體積體電路之 搬運的半導體搬運用治具相關。 【先前技術】 半導體積體電路（以下，標示成「1C」）更爲朝高集 積化發展，然而，高集積度1C在製品出廠前’通常要實 施機能試驗、燒入試驗等之事前試驗。 此種事前試驗中，一般係在將個別載置於半導體搬運 用治具之複數個1C載置於搬運框之狀態下，同時進行多 數個1C之檢查。 事前試驗中，爲了連結試驗對象之1c及半導體試驗 裝置（以下，標示成「1C測驗機」），必須使與1C測驗 機電氣性連接之插座所含有之複數接觸銷、與1c之外部 連結端子正確的接觸，故必須使1C正確地定位於半導體 搬運用治具》 可適用於1C之事前試驗的半導體搬運用治具’已有 各式各樣的提案（例如，參照專利文獻1及專利文獻2) 〇 亦即，專利文獻1揭示一種：於本體具備至少1個把 持機構（閂件）之半導體搬運用治具。201248772 VI. [Technical Field] The present invention relates to a semiconductor transport jig for transporting semiconductors, in particular, a semiconductor transport process for transporting a semiconductor integrated circuit having a narrower spacing between external connection terminals. Related. [Prior Art] The semiconductor integrated circuit (hereinafter referred to as "1C") is more highly integrated. However, the high accumulation degree 1C is usually subjected to pre-tests such as functional tests and burn-in tests before the products are shipped. In such a prior test, a plurality of 1C inspections are performed while a plurality of 1Cs placed on the semiconductor transport jig are placed on the transport frame. In the pre-test, in order to connect the test object 1c and the semiconductor test device (hereinafter referred to as "1C test machine"), it is necessary to connect the plurality of contact pins included in the socket electrically connected to the 1C tester and the external connection terminal of 1c. Since the correct contact is made, the 1C must be correctly positioned in the jig for semiconductor transportation. The semiconductor handling jig that can be applied to the pre-test of 1C has various proposals (for example, refer to Patent Document 1 and Patent Literature). 2) Patent Document 1 discloses a jig for transporting a semiconductor provided with at least one gripping mechanism (latch member) on the main body.
此外，專利文獻2揭示一種：於本體具有可把持1C 201248772 之上面及下面之把持機構（閂件）的半導體搬運用治具。 上述半導體搬運用治具皆形成：將1C插入半導體搬 運用治具之凹部，使1C之側壁及半導體搬運用治具之凹 部周壁抵接，而將1C定位於半導體搬運用治具，並以閂 件來防止1C之移動的構造。 [專利文獻1]日本特開2008-261861號公報 [專利文獻2]日本特開2009-139370號公報 【發明內容】 然而，與外部之連結端子持續小徑化、窄間距化，尤 其是使用焊錫球作爲外部連結端子之BGA ( Ball Grid Array )型半導體或使用端子區域作爲外部連結端子之 LG A ( Land Grid Array )型半導體，焊錫球之間距間隔從 傳統之1.0〜0.65毫米間距變窄成0.5毫米間距以下。 而且，由於很難以1C側壁作爲基準來執行1C之外部 連結端子對的定位及確保定位精度，因此上述半導體搬運 用治具，很難隨著外部連結端子之窄間距化，而正確地使 外部連結端子及插座之接觸銷正確的接觸。 此外，上述專利文獻所示之傳統半導體搬運用治具， 係使配置於搬運用治具外部之接觸銷從下方接觸外部連結 端子之構造，半導體搬運用治具之供1C安座的部分（指 該治具上承接1C的部份）不得不縮小。 所以，在半導體對治具傾斜裝設的場合中，有時也會 發生半導體從治具脫落並掉落於1C測驗機上而必須中斷 -6- 201248772 試驗的狀況。 本發明是有鑑於上述課題所硏發而成的發明’ 的目的係在提供：即使在適用於具有0.5毫米間距 窄間距的外部連結端子之半導體的場合’也可正確 部連結端子及插座之接觸銷進行接觸的半導體搬運 〇 此外，本發明的目的係在提供：可確實將半導 於治具內的半導體搬運用治具。 〔解決問題之手段〕 本發明之半導體搬運用治具，係具有：可供於 成有外部連結端子之半導體積體電路插入之凹部、 導體積體電路被插入前述凹部時朝前述半導體積體 方突出之閂件、以及配置於前述凹部之底部且在前 連結端子的對向位置穿設有貫通孔之座板，前述貫 向下面的開口部形成錐形，該下面是指前述底板與 導體積體電路接觸之上面的相反面。 本發明之半導體搬運用治具，藉由具有上述構 但可防止半導體積體電路從半導體搬運用治具脫落 正確地將事前試驗用插座之接觸銷導入貫通孔β 本發明之半導體搬運用治具，具有前述底板之 小於：將前述外部連結端子朝從「事前試驗用插座 出而插入前述貫通孔」之接觸銷壓下時，從前述半 體電路之底面至前述事前試驗用插座之上面爲止之 本發明 以下之 地使外 用治具 體把持 底面形 前述半 電路上 述外部 通孔朝 前述半 造，不 ，也可 厚度係 上面突 導體積 距離的 201248772 構造。 本發明之半導體搬運用治具，藉由具有上述構造，實 施事前試驗時，即使半導體積體電路向下推至接觸銷時， 也可防止壓下力所導致的底板破損。 本發明之半導體搬運用治具，具有以下的構造：於底 面形成有BGA型外部連結端子之半導體積體電路用半導 體搬運用治具，前述貫通孔朝向「前述底板與前述半導體 積體電路接觸」的上面，及「前述上面之相反面」也就是 指下面的開口部形成錐形。 本發明之半導體搬運用治具，藉由具有上述構造，可 以正確地將BGA型外部連結端子導入半導體搬運用治具 之貫通孔。 本發明之半導體搬運用治具，係具有從形成於前述底 板之前述上面之錐部到前述上面之垂直長度，小於從前述 BG A型外部連結端子之最大徑部到前述半導體積體電路底 面的距離之構造。 本發明之半導體搬運用治具，藉由具有上述構造，可 以使BGA型外部連結端子正確地定位於半導體搬運用治 具之貫通孔。 本發明之半導體搬運用治具，係具有形成於前述底板 之前述下面到錐部之前述下面的垂直長度，小於將前述 BG A型連結端子朝接觸銷壓下時，前述接觸銷從前述事前 試驗用插座上面起之突出長度的構造。 本發明之半導體搬運用治具，藉由具有上述構造’可 -8- 201248772 以確實地使BG A型連結端子及接觸銷進行接觸。 本發明之半導體搬運用治具，係具有：前述閂件及前 述半導體積體電路上面之間隙，小於從前述BGA型連結 端子到前述半導體積體電路底面的最大高度之構造。 本發明之半導體搬運用治具，藉由具有上述構造，可 以防止半導體積體電路在搬運中從半導體搬運用治具掉落 〔發明的效果〕 依據本發明之半導體搬運用治具，即使適用於具有 0.5毫米間距以下之窄間距之外部連結端子的BGA型半導 體或LGA型半導體時，也可使外部連結端子與事前試驗 用插座之接觸銷正確地接觸。 此外，本發明之半導體搬運用治具，因爲半導體搬運 用治具具備底板，可以確實施防止半導體之脫落。 【實施方式】 第1圖係顯示將本發明之半導體搬運用治具裝設於搬 運框之狀況的立體圖，鋁製之搬運框1具有複數（例如， 8x8個）之裝設部，於各裝設部，螺固著半導體搬運用治 具2。 第2圖係本發明之半導體搬運用治具的上方立體圖， 於半導體搬運用治具2之樹脂製本體21，形成有供1C插 入之凹部22。 -9- 201248772 此外，於凹部22之周壁的至少一部位，形成有當ic 已插入凹部22時朝1C上方突出之閂件23。 該閂件23,藉由將覆蓋本體上面之操作板24壓下而 進入凹部22之周壁內並構成可插入1C之狀態。 亦即，1C插入半導體搬運用治具2時，壓下操作板 24而使閂件23形成進入凹部22之周壁內的狀態後再將 1C插入凹部22，完成插入後，解除操作板24之壓下而使 閂件23朝1C上方突出，而防止搬運中1C從半導體搬運 用治具2脫落》 第3圖係本發明之半導體搬運用治具的下方立體圖， 於配置在凹部22底部之底板25，在1C之各外部接觸端子 的對向位置，穿設有與外部連結端子相同數目的貫通孔26 〇 第4圖係載置BG A型半導體時，半導體搬運用治具 及事前試驗用插座之嵌合前的部分剖面圖（a)及嵌合後 的部分剖面圖（b) »而且，因爲事前試驗用插座可以適 用眾所皆知之物，省略了剖面構造的記載。 半導體搬運用治具2之凹部22，係由從半導體搬運用 治具2上面朝底面傾斜之錐部22a、及連接於錐部22a之 垂直壁部22b所構成。 並且，垂直壁部22b之下端與底板25相連接，且閂 件23配設於錐部22a。 亦即，在壓下操作板24而形成閂件23將被進入凹部 22之周壁內的狀態，並從半導體搬運用治具2上部插入 -10- 201248772 IC5的話，IC5將被錐部22a所導引而被載置於底板25上 面。 此時，配置於IC5底面之焊錫球51，嵌入「穿設於半 導體搬運用治具2之底板25」之貫通孔26的內部，形成 焊錫球51對半導體搬運用治具2的定位》 並且，爲了確實將焊錫球51導引至貫通孔26，最好 於貫通孔26朝底板25上面的開口部配設上錐部26a。 然而，上錐部26a之垂直方向長度Hu，必須小於焊 錫球51之水平方向最大徑部到IC5之底面的距離Ru。亦 即，必須爲Hu<Ru。 這是爲了在IC5之底面接觸半導體搬運用治具2之底 板25時，使焊錫球51之最大徑部藉由上錐部26a確實深 入並到達貫通孔26，來使焊錫球51正確地定位於半導體 搬運用治具2。 IC5被載置於底板25後，解除操作板24之壓下並使 閂件23從IC5上面突出。 此外，爲了確實防止IC5從半導體搬運用治具2脫落 ，IC5上面與閂件23之間的間隙，必須小於焊錫球51到 IC5下面的最大高度》 並且，因爲焊錫球間距爲0.5毫米之1C，焊錫球之最 大高度爲0.27毫米，0.4毫米之1C的最大高度爲0.18毫 米，故間隙以〇. 1毫米程度爲佳。 與半導體搬運用治具2卡合之事前試驗用插座3係略 呈凸形狀，於下擺平面3a垂直配設著定位銷31。而且， -11 - 201248772 於事前試驗用插座3之頂部平面3b，埋設有導電性之接觸 銷32。並且，接觸銷32由內建於事前試驗用插座3之內 部內的彈簧（未圖示）朝上方彈推，在未與焊錫球51接 觸之無負荷狀態下，從頂部平面3b只以特定長度（=L) 突出。 插入有1C 5之半導體搬運用治具2，被搬運到事前試 驗用插座3之上方的話，穿設於半導體搬運用治具2之本 體的定位孔、便與設於事前試驗用插座3之下擺平面3a 的定位銷31嵌合，形成半導體搬運用治具2定位於事前 試驗用插座3。 所以，從事前試驗用插座3之頂部平面3b突出的接 觸銷32，從下方插入穿設於半導體搬運用治具2之底板 2 5的貫通孔2 6。 此外，爲了確實將接觸銷32導引至貫通孔26，最好 於貫通孔26朝向底板25下面之開口部設置下錐部26b。 然而，下錐部26b之垂直方向長度Hb，必須小於接 觸銷32之突出長度L。亦即，必須爲Hb<L » 這是因爲半導體搬運用治具2卡合於事前試驗用插座 3時，爲了使接觸銷32之頂部確實插入穿設於半導體搬運 用治具2之底板25的貫通孔26。 由於IC5之焊錫球51及半導體搬運用治具2，係藉由 穿設於底板25之貫通孔26所定位，因此使IC5之焊錫球 51、與埋設於事前試驗用插座3之接觸銷32正確接觸。 第5圖係載置LG A型半導體時，半導體搬運用治具2 -12- 201248772 與事前試驗用插座3之嵌合前的部分剖面圖（c)及嵌合 後的部分剖面圖（d )。 此外，對與第4圖相同之部分賦予相同參考編號並省 略詳細說明。 壓下操作板24而形成閂件23導入凹部22之周壁內 的狀態，並從半導體搬運用治具2之上部插入1C 5的話， IC5便由錐部2 2a所導引而載置於底板25之上面。 此時，配置於IC5之底面的端子區域52，係位於穿設 在半導體搬運用治具2之底板25的貫通孔26之上，形成 端子區域52相對於半導體搬運用治具2的定位。 IC5被載置於底板25後，解除操作扳24之壓下而使 閂件23從IC5之上面突出。 其後，使半導體搬運用治具2卡合於事前試驗用插座 3的話，接觸銷32便接觸端子區域52。 此外，第5圖中，端子區域52係貼附於IC5之封裝 外側的部份，然而，端子區域5 2埋設於封裝之凹部時， 也可適用本申請專利發明。 在半導體搬運用治具2完成卡合於事前試驗用插座3 之狀態下，半導體搬運用治具2本體21之下面21a形成 與延伸於事前試驗用插座3之下擺平面3a上延伸之固定 具4上面4a接觸的狀態，但在該狀態下，最好是將半導 體搬運用治具2之底板25的厚度定爲：半導體搬運用治 具2之底板25a的下面25a不會與事前試驗用插座3之頂 部平面3 b接觸。 -13- 201248772 這是因爲半導體搬運用治具2之底板25必須極端薄 化成厚度〇.5mm以下，爲了確實使焊錫球51或端子區域 52、與接觸銷32進行接觸而從IC5上面施加壓下力時， 防止底板25破損》 〔產業上的可利用性〕 IC5被載置於底板25後，解除操作板24之壓下而使 閂件23從IC5上面突出。 本發明之半導體搬運用治具，可適用於窄間距之BGR 型1C或LGA型1C之事前試驗，對產業十分有用。 【圖式簡單說明】 第1圖係將本發明之半導體搬運用治具裝設於搬運框 之狀況的立體圖。 第2圖係本發明之半導體搬運用治具的上方立體圖。 第3圖係本發明之半導體搬運用治具的下方立體圖。 第4圖係BGA型半導體用半導體搬運用治具及事前 試驗用插座之嵌合前的部分剖面圖（a)及嵌合後的部分 剖面圖（b )。 第5圖係LGA型半導體用半導體搬運用治具&事前 試驗用插座之嵌合前之部分剖面圖（c)及嵌合後之部分 剖面圖（d )。 【主要元件符號說明】 -14 - 201248772 1 :搬運框 2:半導體搬運用治具 3 :事前試驗用插座 4 · ·固定具 5 : 1C (半導體積體電路） 2 1 :本體 22 :凹部 23 :閂件 2 4 ‘·操作板 2 5 :底板 2 6 :貫通孔 3 1 :定位銷 32 :接觸銷 5 1 :焊錫球（外部連結端子） 52:端子區域（外部連結端子） -15-Further, Patent Document 2 discloses a semiconductor transport jig having a holding mechanism (latch) that can hold the upper surface and the lower surface of 1C 201248772 on the main body. In the above-described semiconductor transport jig, 1C is inserted into the concave portion of the semiconductor transport jig, and the side wall of the 1C and the peripheral wall of the concave portion of the semiconductor transport jig are brought into contact with each other, and 1C is positioned on the semiconductor transport jig and latched. A piece to prevent the movement of 1C. [Patent Document 1] Japanese Laid-Open Patent Publication No. 2008-139370 (Patent Document 2) However, the external connection terminal has a small diameter and a narrow pitch, and in particular, solder is used. The ball is used as a BGA (Ball Grid Array) type semiconductor with an external connection terminal or a LG A (Land Grid Array) type semiconductor using a terminal region as an external connection terminal, and the distance between the solder balls is narrowed from a conventional 1.0 to 0.65 mm pitch to 0.5. Below the millimeter pitch. Further, since it is difficult to perform the positioning of the external connection terminal pair of 1C and the positioning accuracy by using the 1C side wall as a reference, it is difficult for the above-described semiconductor transportation jig to accurately connect the external connection with the narrow pitch of the external connection terminals. The contact pins of the terminal and the socket are in proper contact. In addition, the conventional semiconductor transport jig shown in the above-mentioned patent document has a structure in which a contact pin disposed outside the transport jig is in contact with an external connection terminal from below, and a portion of the semiconductor transport jig that is seated at 1C (refer to the portion) The part of the jig that takes over 1C has to be reduced. Therefore, in the case where the semiconductor is tilted to the fixture, there is a case where the semiconductor is detached from the jig and dropped on the 1C test machine, and the test of -6-201248772 must be interrupted. The present invention has been made in view of the above-mentioned problems. It is intended to provide a contact between a terminal and a socket in a correct portion even when applied to a semiconductor having an external connection terminal having a pitch of 0.5 mm pitch. Further, the object of the present invention is to provide a jig for semiconductor transportation in which a semiconductor can be surely guided in a jig. [Means for Solving the Problem] The jig for transporting a semiconductor according to the present invention includes a concave portion into which a semiconductor integrated circuit having an external connection terminal is inserted, and a guide body circuit inserted into the concave portion toward the semiconductor integrated body a protruding latch member, and a seat plate disposed at a bottom of the recessed portion and having a through hole at a position opposite to the front connecting terminal, wherein the opening portion of the downwardly facing portion is tapered, and the lower surface refers to the bottom plate and the guiding volume The opposite side of the upper surface of the body circuit contact. In the semiconductor transport jig of the present invention, the semiconductor integrated circuit can be prevented from being detached from the semiconductor transport jig, and the contact pin of the pre-test socket can be accurately introduced into the through hole β. The semiconductor transport jig of the present invention When the external connection terminal is pressed against the contact pin that is inserted into the through hole from the "pre-test socket", the bottom plate is pressed from the bottom surface of the half-body circuit to the top of the pre-test socket. In the present invention, the external treatment specifically controls the outer through hole of the bottom half-shaped half-circuit toward the semi-finished structure, and the thickness may be a structure of the 201248772 having a volumetric distance. According to the jig for transporting a semiconductor of the present invention, when the pre-test is carried out, even when the semiconductor integrated circuit is pushed down to the contact pin, the damage of the bottom plate due to the pressing force can be prevented. The jig for transporting a semiconductor of the present invention has a structure in which a semiconductor-transparent jig for a semiconductor integrated circuit in which a BGA-type external connection terminal is formed on a bottom surface, and the through-hole is in contact with the "backplane and the semiconductor integrated circuit" The upper surface and the "opposite surface of the foregoing" mean that the lower opening portion is tapered. According to the above-described structure, the semiconductor transport jig of the present invention can accurately introduce the BGA type external connection terminal into the through hole of the semiconductor transport jig. The jig for transporting a semiconductor according to the present invention has a vertical length from a tapered portion formed on the upper surface of the bottom plate to the upper surface, and is smaller than a maximum diameter portion from the BG A type external connection terminal to a bottom surface of the semiconductor integrated circuit. The construction of the distance. According to the semiconductor transport jig of the present invention, the BGA type external connection terminal can be accurately positioned in the through hole of the semiconductor transporting tool. The jig for transporting a semiconductor according to the present invention has a vertical length formed on the lower surface of the bottom plate to the lower surface of the tapered portion, and is smaller than when the BG A-type connecting terminal is pressed against the contact pin, and the contact pin is subjected to the foregoing test. The construction of the protruding length from the top of the socket. In the jig for transporting a semiconductor of the present invention, the BG A-type connecting terminal and the contact pin are reliably brought into contact by having the above-described structure -8-201248772. The jig for transporting a semiconductor according to the present invention has a structure in which a gap between the latch and the semiconductor integrated circuit is smaller than a maximum height from the BGA-type connection terminal to the bottom surface of the semiconductor integrated circuit. According to the above-described structure, the semiconductor-transporting jig of the present invention can prevent the semiconductor integrated circuit from being dropped from the semiconductor-transporting jig during transportation. [Effects of the Invention] The semiconductor-transporting jig according to the present invention can be applied to In the case of a BGA type semiconductor or an LGA type semiconductor having a narrow pitch external connection terminal of 0.5 mm pitch or less, the external connection terminal can be brought into proper contact with the contact pin of the pre-test socket. Further, in the jig for transporting a semiconductor of the present invention, since the jig for semiconductor transport has a bottom plate, it is possible to surely prevent the semiconductor from coming off. [Embodiment] FIG. 1 is a perspective view showing a state in which the jig for transporting a semiconductor of the present invention is mounted on a transport frame, and the transport frame 1 made of aluminum has a plurality of (for example, 8×8) mounting portions. In the installation part, the jig 2 for semiconductor transportation is screwed. Fig. 2 is a top perspective view of the jig for transporting the semiconductor of the present invention, and the resin body 21 of the jig for transporting the semiconductor 2 is formed with a recess 22 into which the 1C is inserted. -9- 201248772 Further, at least one portion of the peripheral wall of the recess 22 is formed with a latch 23 that protrudes upward from 1C when the ic has been inserted into the recess 22. The latch member 23 is inserted into the peripheral wall of the recess 22 by pressing the operation panel 24 covering the upper surface of the main body to constitute a state in which the plug 1C can be inserted. In other words, when 1C is inserted into the jig 2 for transporting the semiconductor, the operation panel 24 is pressed to form the latch 23 into the peripheral wall of the recess 22, and then 1C is inserted into the recess 22, and after the insertion is completed, the pressure of the operation panel 24 is released. Next, the latch 23 is protruded upward from 1C, and the transporting 1C is prevented from falling off from the semiconductor transport jig 2. FIG. 3 is a bottom perspective view of the semiconductor transport jig of the present invention, and is disposed on the bottom plate 25 disposed at the bottom of the recess 22. In the opposite position of each external contact terminal of 1C, the same number of through holes 26 as the external connection terminals are provided. When the BG A type semiconductor is placed in the fourth figure, the semiconductor transportation jig and the pre-test socket are placed. Partial cross-sectional view (a) before fitting and partial cross-sectional view (b) after fitting » Moreover, since the well-known test socket is applicable to the well-known thing, the description of the cross-sectional structure is abbreviate|omitted. The concave portion 22 of the jig for transporting the semiconductor is composed of a tapered portion 22a which is inclined toward the bottom surface from the upper surface of the semiconductor transport jig 2, and a vertical wall portion 22b which is connected to the tapered portion 22a. Further, the lower end of the vertical wall portion 22b is connected to the bottom plate 25, and the latch 23 is disposed on the tapered portion 22a. In other words, when the operation panel 24 is pressed to form a state in which the latch 23 is inserted into the peripheral wall of the recess 22, and the -10-201248772 IC5 is inserted from the upper portion of the semiconductor transport jig 2, the IC 5 is guided by the tapered portion 22a. It is placed on top of the bottom plate 25. At this time, the solder ball 51 disposed on the bottom surface of the IC 5 is inserted into the through hole 26 of the bottom plate 25 of the semiconductor transport jig 2 to form the position of the solder ball 51 to the semiconductor transport jig 2 In order to surely guide the solder ball 51 to the through hole 26, it is preferable that the upper taper portion 26a is disposed in the opening portion of the through hole 26 toward the upper surface of the bottom plate 25. However, the vertical length Hu of the upper tapered portion 26a must be smaller than the distance Ru from the horizontal maximum diameter portion of the solder ball 51 to the bottom surface of the IC 5. That is, it must be Hu<Ru. This is to ensure that the solder ball 51 is correctly positioned when the bottom surface of the IC 5 is in contact with the bottom plate 25 of the semiconductor transport jig 2 so that the maximum diameter portion of the solder ball 51 is surely deepened by the upper taper portion 26a and reaches the through hole 26. Fixture 2 for semiconductor transportation. After the IC 5 is placed on the bottom plate 25, the pressing of the operating panel 24 is released and the latch member 23 is projected from the upper surface of the IC 5. Further, in order to surely prevent the IC 5 from falling off from the semiconductor transport jig 2, the gap between the upper surface of the IC 5 and the latch 23 must be smaller than the maximum height of the solder balls 51 to the lower surface of the IC 5 and, because the solder ball pitch is 1 mm of 0.5 mm, The maximum height of the solder ball is 0.27 mm, and the maximum height of 1 C of 0.4 mm is 0.18 mm, so the gap is preferably about 1 mm. The test socket 3 before the engagement with the jig for transporting the semiconductor is slightly convex, and the positioning pin 31 is vertically disposed on the hem plane 3a. Further, -11 - 201248772, a conductive contact pin 32 is embedded in the top plane 3b of the pre-test socket 3. Further, the contact pin 32 is pushed upward by a spring (not shown) built in the inside of the pre-test socket 3, and is only a specific length from the top plane 3b in a no-load state in contact with the solder ball 51. (=L) Prominent. When the jig 2 for semiconductor transportation in which the 1C 5 is inserted is transported to the upper side of the test socket 3, the positioning hole formed in the main body of the semiconductor transport jig 2 is placed under the pedestal of the pre-test socket 3. The positioning pin 31 of the flat surface 3a is fitted, and the jig for transporting the semiconductor is formed in the socket 3 for the test. Therefore, the contact pin 32 which protrudes from the top plane 3b of the front test socket 3 is inserted into the through hole 26 which is inserted through the bottom plate 25 of the semiconductor transport jig 2 from below. Further, in order to surely guide the contact pin 32 to the through hole 26, it is preferable that the lower tapered portion 26b is provided in the opening portion of the through hole 26 toward the lower surface of the bottom plate 25. However, the vertical direction length Hb of the lower tapered portion 26b must be smaller than the protruding length L of the contact pin 32. In other words, the Hb<L> is necessary because the semiconductor transport jig 2 is engaged with the pre-test socket 3, and the top of the contact pin 32 is inserted into the bottom plate 25 of the semiconductor transport jig 2. Through hole 26. Since the solder ball 51 of the IC 5 and the jig 2 for semiconductor transportation are positioned by the through holes 26 that are inserted through the bottom plate 25, the solder balls 51 of the IC 5 and the contact pins 32 embedded in the pre-test socket 3 are correct. contact. Fig. 5 is a partial cross-sectional view (c) of the semiconductor transport jig 2-12-201248772 and the pre-test test socket 3 when the LG A-type semiconductor is mounted, and a partial cross-sectional view (d) after the fitting. . In addition, the same reference numerals are given to the same portions as those in Fig. 4 and detailed description will be omitted. When the operation panel 24 is pressed to form the state in which the latch member 23 is introduced into the peripheral wall of the recessed portion 22, and the 1C 5 is inserted from the upper portion of the semiconductor transport jig 2, the IC 5 is guided by the tapered portion 22a and placed on the bottom plate 25. Above. At this time, the terminal region 52 disposed on the bottom surface of the IC 5 is placed on the through hole 26 that is bored through the bottom plate 25 of the semiconductor transport jig 2, and the terminal region 52 is positioned relative to the semiconductor transport jig 2. After the IC 5 is placed on the bottom plate 25, the pressing of the operating lever 24 is released to cause the latch member 23 to protrude from the upper surface of the IC 5. Thereafter, when the jig for transporting the semiconductor carrier 2 is engaged with the pre-test socket 3, the contact pin 32 contacts the terminal region 52. Further, in Fig. 5, the terminal region 52 is attached to the outer portion of the package of the IC 5. However, when the terminal region 52 is embedded in the recess of the package, the present invention can also be applied. In the state in which the jig for the semiconductor transport 2 is engaged with the pre-test test socket 3, the lower surface 21a of the main body 21 of the semiconductor transport jig 2 is formed with a fixture 4 extending over the hem plane 3a of the pre-test socket 3. In the state in which the upper surface 4a is in contact with each other, it is preferable that the thickness of the bottom plate 25 of the semiconductor transport jig 2 is such that the lower surface 25a of the bottom plate 25a of the semiconductor transport jig 2 does not correspond to the pre-test socket 3. The top plane 3 b is in contact. -13- 201248772 This is because the bottom plate 25 of the jig for transporting the semiconductor must be extremely thinned to a thickness of 〇5 mm or less, and the solder ball 51 or the terminal region 52 is surely brought into contact with the contact pin 32 to be pressed from the upper surface of the IC5. When the force is applied, the bottom plate 25 is prevented from being damaged. [Industrial Applicability] After the IC 5 is placed on the bottom plate 25, the pressing of the operating plate 24 is released, and the latch 23 protrudes from the upper surface of the IC 5. The jig for transporting a semiconductor of the present invention can be applied to a pre-test of a narrow-pitch BGR type 1C or LGA type 1C, and is very useful for the industry. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view showing a state in which a jig for transporting a semiconductor of the present invention is mounted on a transport frame. Fig. 2 is a top perspective view of the jig for semiconductor transportation of the present invention. Fig. 3 is a bottom perspective view of the jig for semiconductor transportation of the present invention. Fig. 4 is a partial cross-sectional view (a) before the fitting of the BGA type semiconductor semiconductor transport jig and the pre-test test socket, and a partial cross-sectional view (b) after the fitting. Fig. 5 is a partial cross-sectional view (c) of the LGA-type semiconductor semiconductor-carrying jig and the pre-test socket, and a cross-sectional view (d) after the fitting. [Description of main component symbols] -14 - 201248772 1 : Transport frame 2: Fixture for semiconductor transportation 3: Pre-test socket 4 · Fixing device 5 : 1C (semiconductor integrated circuit) 2 1 : Main body 22 : Concave portion 23 : Latch 2 4 '· Operation panel 2 5 : Base plate 2 6 : Through hole 3 1 : Locating pin 32 : Contact pin 5 1 : Solder ball (external connection terminal) 52: Terminal area (external connection terminal) -15-