201244020 六、發明說明： 【發明所屬之技術領域】 本發明涉及-種半導體封裝，更具體地涉及—種將半導 體晶片附著在薄膜上的C0F (chip_〇n_film，薄膜覆晶） 導體封裝。 【先則技術】 C0F型半導體封裝與TCP⑽咖加触鄉，帶載 相ϊίϊ用的帶互連基底並且可更密集地設計互 ΐϊί °，地’ 型半導體封裝使用形成在帶互連基底 早的ΐΐϊί圖案和輸出端子圖案取代錫珠作為外部連接端 路板或顯it㈣繼翻著到印刷電 80年產ίΛ辨度監視器的TCP技術在20世紀 為了降低工μ *隨後成為市場上最優選的方法。然而， ί 且Λ據半導㈣件的期距來提高產 斷增加。/而封裝技術的市場份額不 :時，驅動器1C的驅動負載； 發熱成為嚴封農技術時’IC(集成電路）晶片的 在安2提出-種方法，將熱_塾附著 晶片18 中」由半導體集成電路實現的 這裏，薄膜U ^ )附著在具有柔性的薄膜11上。 在下絕緣㈣㈣面上。 4 201244020 * 封裝中，由晶片18操作產生的熱量通過成型樹脂層μ、引 線12和下絕緣層10傳遞到熱輻射塾2〇，並且通過熱輻射墊 20輻射到外部。 ‘ 在附著有熱輻射墊20的COF型半導體封裝中，封裝的厚 度由於熱輻射墊20而增加，因此不利於生產較薄的產品。此 外，由於從晶片產生的熱通過彼此具有不同材料的元件也就 是成型樹脂層16、引線12、下絕緣層10和熱輻射墊2〇輻射， 所以熱輻射效果差。此外’通過黏合劑21附著於下絕緣層1〇 的熱輻射墊20可由於諸如集中作用在如部分“A，，的角部上 的摩擦力等外力而容易地與下絕緣層1〇分離。201244020 VI. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor package, and more particularly to a COF (chip-on-film) conductor package in which a semiconductor wafer is attached to a thin film. [First-class technology] C0F-type semiconductor package and TCP (10) coffee and touch, with a built-in phase-to-interconnect substrate and more densely designed mutual ΐϊ °, ground-type semiconductor package used in the formation of interconnected substrates Ϊ́ΐϊί pattern and output terminal pattern replaced tin bead as external connection end plate or display it (four) followed by flipping to printed electricity 80 years of production TCP technology in the 20th century in order to reduce the work μ * subsequently became the most preferred on the market method. However, ί and the increase in the output of the semi-guided (four) pieces increase the output. / The market share of packaging technology is not: when the driving load of the driver 1C; the heat becomes the technology of the 'IC (integrated circuit) chip proposed in the 2nd, the method of heat, 塾 attached to the wafer 18 The semiconductor integrated circuit is realized here, the film U^) is attached to the flexible film 11. On the lower insulation (four) (four) surface. 4 201244020 * In the package, heat generated by the operation of the wafer 18 is transferred to the heat radiation 通过2〇 through the molding resin layer μ, the lead wire 12, and the lower insulating layer 10, and is radiated to the outside through the heat radiation pad 20. ‘In the COF type semiconductor package to which the heat radiation pad 20 is attached, the thickness of the package is increased by the heat radiation pad 20, which is disadvantageous for producing a thin product. Further, since the heat generated from the wafer passes through the elements having different materials from each other, that is, the molding resin layer 16, the lead 12, the lower insulating layer 10, and the heat radiation pad 2, the heat radiation effect is poor. Further, the heat radiating pad 20 attached to the lower insulating layer 1 by the adhesive 21 can be easily separated from the lower insulating layer 1 due to an external force such as a frictional force concentrated on a corner portion such as a portion "A".
L發明内容J 的—個目的是提供—種能夠增強熱輕射性 ίϋΐί Ϊ墊分離問題的C0F型半導體封裝。 根據本&明的一方面，提供一種C0F型 3體絕緣薄膜、形成在絕緣薄膜上;金Ϊ ίΐ上:ϊΐ裝㈣互連基底上的半導體晶片，ΐΐ:屬5 ^2以=電氣連__ ’以及與電路圖i 暴露:射孔’以允許絕緣圈案的-部分 發熱案可連_晶⑽端子+發婦α於其他端子的 ίίΞ:可包括用於給晶片供應驅動電源的供電端子。 連接到晶片的端子中的接地端子 其他電路,Γ目薄膜上延伸，以構造成為與 緣_可形成有熱輻射孔，以允許擴展_的一部八 5 刀 201244020 暴露，絕緣薄膜的底部表面。 成在絕緣0以可熱輕射部形 展圖案傳遞的熱散發該熱輻射部用於將通過擴 別從成，並且細案分 寬的為使得其端部與其其他部分相比具有較 在與擴展圖案的端部相對應的位置上。 量大於其個可連制晶片的端舰 於給晶片供應驅動電源的供電端子。 端子二展圖案巾的至〉、任何—個可連接到晶片端子中的接地 端子可讀*帶任何隆起部的電關*直接接觸。 、番、型半導體封装，由於從半導體晶片產生的執 案消散到基底的後部内，所以絕緣圖案可 墊的作用。此外，絕緣圖案形成在帶互連基底的 内側中’因此林在由諸如摩擦力料力引起分離的風險。 β絕緣圖案可與半導體晶片的底部上的晶片安裝區域重 曼’因此可以獲得減少從半導體晶片產生的電魏的附帶效 果。此外’紫外光可引起半導體晶片的故障，其中絕緣圖案也 可執行防止紫外光引起的問題的功能。 實施方式】 下文將參考附圖詳細描述本發明的C0F型半導體封裝的 201244020 示例性實施例。 [第一實施例] 的頂J體封裝具有在帶互連基底1。〇 >〇〇 金屬圖案120和130、以及保‘屬110上的 絕緣層140。典型地，絕緣^ 120矛口 130的表面 圖案120和13。由具有優土【亞胺製成’金屬 140 基晶片20°通過成型樹脂_附在帶互連 f2。導2°°;氣 ===的 案12〇Ϊ邑案130。這裏爾^ ^端子〔去」山/成在半導體晶片200的底部表面的圓周中 112)通過隆起部122與電路圖㈣〇電氣連= 域（圖3中的限f為安裝半導體晶片測的區 13〇ϊ最。圖才CA )’並且半導體200與絕緣圖案 電路圖緣圖案130極好地與半導體晶片200和 ί5眾ii 2 ί 2緣，並且成型樹脂16〇被注射到其頂部， 日日片200的底部表面黏附於成型樹脂16〇。 導體Κ 底1GQ的俯視圖並且示出了暴露安裝半 &曰^f*CA的狀態。如圖3中所示，絕緣圖案 圖窣片安襄區域CA大致重疊的位置上，並且絕緣 |=30，的多個電路圖案透與絕緣圖案i3Q以預定距 σ 二者之間的絕緣狀態。此外，在封裝好的成 :缝^緣_ 130和電路圖案120通過成型樹脂⑽電氣 絕緣，從而安全地實現絕緣狀態。 电 在上述結構的帶互連基底100和C0F型半導體封裝中， 201244020 ϊίί=ϋ00產生的熱通過其底部的絕緣圖案13〇排放 作:。由ί半導體晶片200和絕緣圖案= 也佈f ’所以從半導體晶片200產生的大部分埶被3 ίίϋίίί案130，並且由於絕緣圖案130由具有優良導 …、性的金屬材料製成而易於執行熱輻射。 此外與上述現有技術不同，由於本發明中數 塾功，，絕緣圖*⑽形成在帶互連基底1〇〇❺内側；'所 以不存在由於諸如摩擦科力*分_風險。料，由 =月〇旨成在絕緣圖案i3G周圍，所以即使將帶i連i yoo相以安裝時’也能安全地轉絕緣圖案⑽鱼 形成=緣_ 13〇周圍的電路贿12G之間的絕H。、 安絕Λ圖ΐ130與半導體晶片咖的底部上的晶片 ⑽的中央區域，從而獲得附帶效Ϊ ^電氣穩定性並域少電磁波引起的干擾。此外， ^ tiii體晶片的故障，其中絕緣圖案i3G也可執行防 止紫外光引起問題的功能。 丁防 輪5示出了能夠使形成有絕緣圖案i3G的封褒的 :、輪射效果最大化賴侧。示出本變化綱圖4和圖 相同的附圖標記指代圖2和圖3中相同的元件。 ㈣，tii化觸半導體封裝中進—步形成有熱輕射孔 ha:輕射孔150穿透絕緣圖案130和絕緣薄膜110中定位 J邑緣圖案130的底部上的部分。由此，絕緣圖案13〇暴1露 膜110的底部表面，從而更有效地消散從半導體 片^0產生的熱。在本變化财，熱輻射孔⑽延伸到 和f緣圖案13G ’但與此不同，熱輻射孔150可^ 僅去除絕緣薄膜110的所述部分的狀態下形成。 [第二實施例] ^ 7^ 了本發，的第二實施例。在本發明中， /、第一貫施例相同的附圖標記指代相同的元件。 201244020 如圖p中所示，電路圖案12〇 一般沿一定方向成線型佈 ^在絕緣薄膜110上，並且特別地，大部分電路圖案12〇以 沿縱向由兩根線形成的形式佈置在絕緣薄膜U0上。電路圖 案120的一部分在絕緣薄膜上延伸，以便構造成為與其 =電^圖案120相比具有寬表面積的擴展圖案125。如圖6 中所示，擴展圖案125朝絕緣薄膜11〇上的中央區域延伸並 且利用絕緣薄臈11〇上未形成有電路圖案12〇的額外空間形 成。 具有與第一實施例相同的概念的絕緣圖案13〇形成在絕 緣溥獏110上未形成有擴展圖案125的區域内。因此，在本 發=中，絕緣圖案130和擴展圖案125是一起形成的。擴展 圖案125通過延伸電路圖案120的所述部分而構成，因此與 圖案120電氣連接。絕緣圖案13〇形成在除形成有擴展 圖案125的區域以外的區域内，因此與電路圖案12〇電氣 緣0 、 另一方面，如圖6中所示，擴展圖案125分別從形成電 "圖案120的兩根線交替地延伸。亦即，第一擴展圖案 從圖6的底線上的電路圖案12〇中的任何一個向上延伸'，其 f側上的第二擴展圖案125從圖6的頂線上的電路圖案12〇 二，，何-個向下延伸，並且與此相似，擴展圖案125從了頁 線和底線上的電路圖案12〇,交替地形成。此外，擴展圖案125 成使得其端部與其其他部分相比具有較寬的寬度的形 =二1此，圖6示出了其端部由四邊形形成。使擴展圖 案125的知部延伸，以在可能的情況下加寬擴展圖案 面，，，展圖案125的形式並不限於四邊形，並且例如可以 由圓盤等形成。 如圖7中所示，熱輻射孔150豎直穿透絕緣薄獏11() 板表面’並且擴展圖案125通過熱輻射孔150暴露於絕緣壤 表面。熱輻射孔150優選形成在與形成有擴ΐ 圖案125的區域相對應的位置上，以使得擴展圖案1 命 於絕緣薄膜110的底部表面。然而，熱輻射孔150不必二^ 201244020 展圖案125相對應地形成，並且可以針The purpose of the invention is to provide a C0F type semiconductor package capable of enhancing the thermal light-sensitive 分离 分离 separation problem. According to an aspect of the present invention, a COF-type 3-body insulating film is formed on an insulating film; a semiconductor wafer on an interconnected substrate is fabricated on a metal substrate, and is: 5^2 to = electrical connection __ 'and exposed with circuit diagram i: perforation to allow the insulation case - part of the heating case can be connected _ crystal (10) terminal + hair α 于 其他 其他 其他 其他 其他 Ξ Ξ Ξ Ξ 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可. The grounding terminal connected to the terminal of the wafer, the other circuit, is extended on the eye-catching film to be formed into a rim with a heat-radiating hole to allow expansion of a portion of the octagonal octagonal octagonal portion of the insulating film. The heat radiated in the pattern of the heat-insulating pattern in the insulation 0 is used to diffuse the heat radiation portion, and the fine film is widened so that the end portion thereof is more than the other portion. The end of the extended pattern corresponds to the position. A terminal that is larger than one of its connectable wafers supplies a power supply terminal that supplies driving power to the wafer. To the second terminal of the pattern wiper, any ground terminal that can be connected to the wafer terminal is readable* with any ridges of the electrical contacts* direct contact. In the case of a semiconductor package, the insulating pattern can act as a pad because the solution generated from the semiconductor wafer is dissipated into the rear portion of the substrate. Further, the insulating pattern is formed in the inner side of the interconnected substrate. Therefore, the forest is at risk of being separated by a force such as friction. The β-insulating pattern can be heavier with the wafer mounting region on the bottom of the semiconductor wafer. Thus, the incidental effect of reducing the electrical power generated from the semiconductor wafer can be obtained. Further, ultraviolet light can cause malfunction of a semiconductor wafer, and the insulating pattern can also perform a function of preventing problems caused by ultraviolet light. Embodiments Hereinafter, an exemplary embodiment of a 20124020 of a CMOS type semiconductor package of the present invention will be described in detail below with reference to the accompanying drawings. The top J body package of the [first embodiment] has the interconnect substrate 1 in the tape. 〇 > 〇〇 metal patterns 120 and 130, and insulating layer 140 on genus 110. Typically, the surface patterns 120 and 13 of the sprinkler 130 are insulated. It is attached to the tape f2 by a molding resin _ which is made of a high-quality [imine made of metal] 140-base wafer. Guide 12°; gas === case 12〇Ϊ邑130. Here, the ^^ terminal [to" mountain/in the circumference of the bottom surface of the semiconductor wafer 200 is 112) passed through the ridge portion 122 and the circuit diagram (4) 〇 electrical connection = domain (the limit f in Fig. 3 is the area 13 where the semiconductor wafer is mounted) 〇ϊ最。 Figure CA)' and the semiconductor 200 and the insulating pattern circuit pattern 130 are excellently bonded to the semiconductor wafer 200 and the ii 2 ί 2 edge, and the molding resin 16 〇 is injected to the top thereof The bottom surface is adhered to the molding resin 16 〇. A top view of the conductor 1GQ and shows the state in which the mounting half & As shown in Fig. 3, the insulating pattern is at a position where the ampule area CA is substantially overlapped, and the plurality of circuit patterns of the insulation |=30 are infiltrated with the insulating pattern i3Q by a predetermined distance σ. Further, the packaged sealing edge _130 and the circuit pattern 120 are electrically insulated by the molding resin (10), thereby safely achieving the insulating state. In the above-described structure of the interconnected substrate 100 and the CMOS type semiconductor package, the heat generated by 201244020 ϊίί=ϋ00 is discharged through the insulating pattern 13〇 at the bottom thereof. Since the semiconductor wafer 200 and the insulating pattern = are also f', most of the defects generated from the semiconductor wafer 200 are 3, and since the insulating pattern 130 is made of a metal material having excellent conductivity, it is easy to perform heat. radiation. Further, unlike the above-described prior art, the insulating pattern *(10) is formed on the inner side of the interconnected substrate 1〇〇❺ due to the numerical work in the present invention; 'There is no such a risk due to friction such as friction. Material, by = 〇 〇 在 在 在 在 在 在 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 Absolute H. The central area of the wafer (10) on the bottom of the semiconductor wafer and the semiconductor wafer is secured, thereby obtaining the effect of the electrical stability and the electromagnetic interference caused by the electromagnetic field. In addition, ^ tiii body wafer failure, in which the insulation pattern i3G can also perform a function of preventing ultraviolet light from causing a problem. The Ding wheel 5 shows that the sealing effect of the insulating pattern i3G can be maximized. 4 and the same reference numerals are used to refer to the same elements in FIGS. 2 and 3. (4) The step of forming the thermal light perforation is carried out in the semiconductor package of the tii. The light perforation 150 penetrates the portion of the insulating pattern 130 and the bottom portion of the insulating film 110 which is positioned on the bottom of the J-edge pattern 130. Thereby, the insulating pattern 13 smashes the bottom surface of the film 110, thereby more effectively dissipating the heat generated from the semiconductor wafer. In the present variation, the heat radiation hole (10) extends to and from the f-edge pattern 13G', but the heat radiation hole 150 can be formed in a state where only the portion of the insulating film 110 is removed. [Second Embodiment] ^ 7^ The second embodiment of the present invention. In the present invention, the same reference numerals are used to refer to the same elements. 201244020 As shown in FIG. p, the circuit pattern 12A is generally linearly arranged on the insulating film 110 in a certain direction, and in particular, most of the circuit patterns 12 are arranged in an insulating film in the form of two lines formed in the longitudinal direction. U0. A portion of the circuit pattern 120 extends over the insulating film to be configured to have an expanded pattern 125 having a wide surface area compared to its pattern 120. As shown in Fig. 6, the expanded pattern 125 extends toward the central portion on the insulating film 11A and is formed by an additional space on the insulating thin film 11 on which the circuit pattern 12A is not formed. The insulating pattern 13A having the same concept as that of the first embodiment is formed in the region of the insulating spacer 110 where the expanded pattern 125 is not formed. Therefore, in the present invention, the insulating pattern 130 and the expanded pattern 125 are formed together. The extended pattern 125 is formed by extending the portion of the circuit pattern 120, and thus is electrically connected to the pattern 120. The insulating pattern 13 is formed in a region other than the region in which the expanded pattern 125 is formed, and thus is electrically connected to the circuit pattern 12, and on the other hand, as shown in FIG. 6, the expanded pattern 125 is formed from the electric pattern, respectively. The two lines of 120 alternately extend. That is, the first expanded pattern extends upward from any one of the circuit patterns 12A on the bottom line of FIG. 6, and the second expanded pattern 125 on the f-side thereof is formed from the circuit pattern 12 on the top line of FIG. There is a downward extension, and similarly, the expansion pattern 125 is alternately formed from the circuit patterns 12A on the page line and the bottom line. Further, the expanded pattern 125 is formed such that its end portion has a wider width than the other portions = 2, and Fig. 6 shows that its end portion is formed by a quadrangle. The knowledge of the expanded pattern 125 is extended to widen the expanded pattern surface where possible, and the form of the spread pattern 125 is not limited to a quadrangle, and may be formed, for example, by a disk or the like. As shown in Fig. 7, the heat radiating hole 150 vertically penetrates the insulating sheet 11() board surface' and the expanded pattern 125 is exposed to the insulating soil surface through the heat radiating hole 150. The heat radiation hole 150 is preferably formed at a position corresponding to a region where the expanded pattern 125 is formed, so that the expanded pattern 1 is on the bottom surface of the insulating film 110. However, the heat radiation holes 150 do not have to be formed correspondingly to the 201244020 pattern 125, and can be needled
陶案I =圖;S =目熱輻射孔150形成在擴展圖請的四邊S 又ΐ可能的情況下優選擴展圖案125 _具有寬區 域的邛为可暴露於絕緣薄膜11〇的底部表面。 絲ίΊ方面，形成在晶片咖中的端子（未示出）包括用 的端子、用於供電的端子、和用於接地的端子等， 子的發熱程度由於這種用途的差異而不相同。例 於其他端言端: 2發种的發熱端子連接到擴展圖案⑵，並且1他端子 ίίί=ί=曰5以外的電路圖案120。為此:優選電 f晶片的規格變化，以使晶片200的 Ζ no j, 靜電5夕i 而Λ’在晶片封裝中，除熱輻射問題之外，The ceramic case I = Fig.; S = the heat radiation hole 150 is formed on the four sides S of the expanded view. Further, the extended pattern 125 is preferably used. The 具有 having a wide area is exposed to the bottom surface of the insulating film 11A. In terms of the wire, the terminals (not shown) formed in the wafer coffee include terminals for use, terminals for supplying power, and terminals for grounding, etc., and the degree of heat generation of the sub-different is different due to the difference in such use. For example, in other end words: the heating terminal of the second type is connected to the extended pattern (2), and the circuit pattern 120 other than the terminal ίίί=ί=曰5. To this end: it is preferable to change the specification of the electric f-chip so that the 200 no j of the wafer 200, and the static electricity, in the chip package, in addition to the heat radiation problem,
產生靜電，以能夠防止晶片的故障:異7㊁S ϊ法200的端子中的接地端子的面;的 方止靜電的方法之一，並且馨於此’在本發明中 吏ίϊ端子接觸擴展圖案125。類似於這種構造，可以 的規格瞭解接地端子的位置來將位於與接 地位置的電路圖案12G構造為擴展圖案125。 、^、=有&種構造的本發明中，電路圖案12G的一部分構 ΪΠ絕上的額外空間佔據寬區域的擴= ^壯ίζ·通過曰曰4 200的端子與擴展圖案125相接觸而 1特別地，擴展圖案125從通過彼此平行的 Λ 力電路圖案120交替地延伸，並且通過橫向延伸 201244020 擴展圖案125的端部而增加由擴展圖案125佔據的整個區 域，從而進一步增強熱輻射效果。此外，在絕緣薄膜110上 形成熱輻射孔150，用於形成有擴展圖案125的區域，因此 傳遞到擴展圖案125的晶片200的熱可被有效地消散到絕緣 薄膜110的底部内。 此外，使晶片200的發熱端子如供電端子與擴展圖案125 相接觸，以進一步增強熱輻射效果，並且使晶片2〇〇的接地 端子與擴展圖案125相接觸，以增強防靜電效果。 圖8示出了第二實施例的變化例。 在本變化例中’除進一步形成在絕緣薄膜的底部表 面上的熱輻射部128之外，其他構造與圖6和圖7的實施例 相同。熱輻射部128連接到通過熱輻射孔15〇暴露於絕緣薄 =110的底部表面的電路圖案12〇 (更精確而言，擴展 ^5) ’並且用於將通過電路圖案⑽傳遞的熱輻射到外部。、 所述，由於通過熱輻射孔ΐ5θ暴露於絕緣薄膜U0 案125，所以連接到熱輻 3 Ρ 2=的電路圖案12〇成為擴展圖案125。 ，樹以由考慮了 熱輻射部 和130以使電路圖案120不會盥絕 案120 時， 了熱i射效果，5 θ ° 此分隔的多個熱輻射部128 3上„。彼 圖案120之駄合㈣紅„各電路圖案⑽以使電路 從而通過擴展圖案125進二步增^ 件例ί諸等裝在需要晶片200的外呷哭 傷内的液晶模組_的機械結= 201244020 裝在機械結構上時，如圖8中所示，执 的表面相接觸’從而通麵 圖9示出了第—貫施例的另—變化例。 —it，，在隆起部m之外與圖6和圖7的實施 詳細描述°在本發明中， 伽直接 _，s M 9mi Μ Π ^ 的糕子直接連接到電路圖案120 電路圖案120和絕緣圖 接到施例中晶片的發熱端子或接地端子連 一眚^存丨Ϊρ 的任何一個的構造可以類似地適用於第 即’在第一實施例中，使晶片咖的發熱端ΐ 夕Ϊ :、曰片130 ’從而增強熱輻射效果。此 ESD^。 連接觸緣®案13G，從而增強防 展_冓成上擴 暴露於絕緣薄膜的底部表面，從射孔 此外^= 地端子與擴展圖案相接觸，得射效果。接 參考優選實施例描述了本發明，但相關領域的技 打人貝應理解，可在其中作出各 過所附_要求雜糾树_細稀離如通 12 201244020 【圖式簡單說明】 面圖圖1是包括熱輕射塾的現有技術⑽型半導體封褒的戴 截面^是轉本發明的第—實關的GQF型半導體封裝的 底的㈣2巾解續型糊封_互連基 圖4是示出第一實施例的變化例的C0F型半導體封裝的 截面圖； 、 圖5是用於圖4中所示的c〇F型半導體封裝的帶互連基 底的俯視圖； 嫌圖6是用於根據本發明第二實施例的c〇F型半導體封裝 的▼互連基底的俯視圖； 圖7是圖6的截面圖； 圖8是示出了第二實施例的變化例的截面圖；以及 圖9是示出了第二實施例的另一變化例的截面圖 【主要元件符號說明】 10 下絕緣層 11 薄膜 12 引線（lead) 14 表面絕緣層 16 成型樹脂層 18 晶片 20 熱輔射墊 21 黏合劑 100 帶互連基底 13 201244020 絕緣薄膜 金屬圖案 隆起部 熱輻射部 擴展圖案 金屬圖案 表面絕緣層 熱輔射孔 成型樹脂 半導體晶片 構造 14Static electricity is generated to be able to prevent the failure of the wafer: one of the methods of stopping the static electricity in the terminal of the terminal of the different method, and is in this case. In the present invention, the terminal contacts the expanded pattern 125. Similar to this configuration, the specification of the ground terminal can be understood to configure the circuit pattern 12G located at the grounding position as the expanded pattern 125. In the present invention, the structure of the circuit pattern 12G occupies a portion of the circuit pattern 12G, and the additional space occupies a wide area. The terminal of the 曰曰4 200 is in contact with the extension pattern 125. In particular, the expanded pattern 125 alternately extends from the force-sensitive circuit pattern 120 which is parallel to each other, and the entire area occupied by the expanded pattern 125 is increased by laterally extending the end portion of the 201244020 extended pattern 125, thereby further enhancing the heat radiation effect. Further, a heat radiating hole 150 is formed on the insulating film 110 for forming a region where the expanded pattern 125 is formed, so that the heat transferred to the wafer 200 of the expanded pattern 125 can be effectively dissipated into the bottom of the insulating film 110. Further, the heat generating terminal of the wafer 200, such as the power supply terminal, is brought into contact with the expanded pattern 125 to further enhance the heat radiation effect, and the ground terminal of the wafer 2 is brought into contact with the expanded pattern 125 to enhance the antistatic effect. Fig. 8 shows a modification of the second embodiment. In the present modification, other configurations are the same as those of the embodiment of Figs. 6 and 7 except for the heat radiation portion 128 which is further formed on the bottom surface of the insulating film. The heat radiation portion 128 is connected to the circuit pattern 12A (more precisely, the extension ^5) that is exposed to the bottom surface of the insulating thin film =1 through the heat radiation hole 15 ' and is used to radiate heat transmitted through the circuit pattern (10) to external. As described above, since the thermal film aperture 5θ is exposed to the insulating film U0 case 125, the circuit pattern 12A connected to the heat radiation 3 Ρ 2 = becomes the expanded pattern 125. When the tree considers the heat radiation portion and 130 so that the circuit pattern 120 does not collapse 120, the thermal radiation effect is separated by 5 θ °, and the plurality of heat radiation portions 128 3 are separated. Coupling (four) red „ each circuit pattern (10) so that the circuit is further expanded by the expansion pattern 125. The mechanical junction of the liquid crystal module that is contained in the outer crumb of the wafer 200 is required. In mechanical construction, as shown in Fig. 8, the surface of the surface is in contact with each other', and Fig. 9 shows another variation of the first embodiment. -it, in addition to the ridges m and the implementation of Figures 6 and 7, in the present invention, the glaze directly, s M 9mi Μ Π ^ of the cake is directly connected to the circuit pattern 120 circuit pattern 120 and insulation The configuration of any one of the heat-generating terminal or the grounding terminal of the wafer in the embodiment can be similarly applied to the first embodiment. In the first embodiment, the heat-generating end of the wafer coffee is: The cymbal 130' enhances the heat radiation effect. This ESD^. Connect the contact edge case 13G to enhance the expansion _ 上 上 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露 暴露The present invention has been described with reference to the preferred embodiments, but it should be understood by those skilled in the related art that various modifications may be made in the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1 is a cross-sectional view of a prior art (10) type semiconductor package including a thermal light ^ 是 是 是 转 转 转 是 是 是 是 是 是 是 是 是 四 四 四 四 四 互连 互连 互连 互连 互连 互连 互连 互连 互连 互连 互连 互连Is a sectional view showing a CMOS type semiconductor package of a variation of the first embodiment; and FIG. 5 is a plan view of the interconnected substrate for the c〇F type semiconductor package shown in FIG. 4; a top view of a ▼ interconnect substrate of a c〇F type semiconductor package according to a second embodiment of the present invention; FIG. 7 is a cross-sectional view of FIG. 6; FIG. 8 is a cross-sectional view showing a variation of the second embodiment; Figure 9 is a cross-sectional view showing another variation of the second embodiment [Major component symbol description] 10 Lower insulating layer 11 Thin film 12 Lead 14 Surface insulating layer 16 Molded resin layer 18 Wafer 20 Thermal auxiliary pad 21 Adhesive 100 with interconnected substrate 13 201244020 Thin film metal pattern portion of the heat radiating bump pattern portion extended surface of the insulating layer patterned metal auxiliary heat perforating shaped resin structure 14 of the semiconductor wafer