KR101166069B1 - Chip-on-film type semiconductor package, and tape circuit board for the same - Google Patents

Chip-on-film type semiconductor package, and tape circuit board for the same Download PDF

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Publication number
KR101166069B1
KR101166069B1 KR1020110008739A KR20110008739A KR101166069B1 KR 101166069 B1 KR101166069 B1 KR 101166069B1 KR 1020110008739 A KR1020110008739 A KR 1020110008739A KR 20110008739 A KR20110008739 A KR 20110008739A KR 101166069 B1 KR101166069 B1 KR 101166069B1
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KR
South Korea
Prior art keywords
pattern layer
semiconductor chip
wiring board
insulating film
isolation pattern
Prior art date
Application number
KR1020110008739A
Other languages
Korean (ko)
Inventor
박상홍
임준성
홍성원
강석훈
최영민
전민호
Original Assignee
주식회사 루셈
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 루셈 filed Critical 주식회사 루셈
Priority to KR1020110008739A priority Critical patent/KR101166069B1/en
Application granted granted Critical
Publication of KR101166069B1 publication Critical patent/KR101166069B1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

According to an embodiment of the present disclosure, a CFO semiconductor package may include: a tape wiring board in which an insulating film, a metal pattern layer formed on the insulating film, and a surface insulating layer protecting the metal pattern layer are sequentially stacked; And a semiconductor chip mounted on the tape wiring board, wherein the metal baton layer comprises: a circuit pattern layer electrically connected to the semiconductor chip; And an isolation pattern layer electrically insulated from the circuit pattern layer, wherein the semiconductor chip is mounted on the isolation pattern layer.

Description

Chip-on-Film Type Semiconductor Package, and Tape Circuit Board for the Same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a chip on film (COF) type semiconductor package having a semiconductor chip attached on a film, and a tape wiring board for the same.

Recently, with the development of the flat panel display industry such as liquid crystal display (LCD) for mobile phones, thin film transistor LCD (TFT-LCD) for computers, and plasma display panels (PDP) for homes, the manufacture of tape packages, which are the driving chip components of flat panel display devices The industry is also developing. These tape packages require thinner line width wiring patterns as the display device becomes thinner.

Such a tape package is a semiconductor package using a tape wiring board, and may be divided into a tape carrier package (TCP) and a chip on film (COF) package. TCP has a structure in which a semiconductor chip is mounted in an inner lead bonding (ILB) method to an inner lead exposed to a window of a tape wiring board. The COF package has a structure in which a semiconductor chip is mounted in a flip chip bonding method on a tape wiring board without a window.

COF packages, on the other hand, allow for the use of thinner tape wiring boards compared to TCP, and the ability to design wiring patterns more densely. In particular, the COF package uses an input / output terminal pattern formed on a tape wiring board instead of a solder ball as an external connection terminal, and is mounted by directly attaching the input / output terminal pattern to a printed circuit board or a display panel.

TCP technology was introduced for mass production of high resolution monitors in the late 1980s, and was the most preferred packaging method in the market afterwards.However, COF packaging technology has been introduced since the late 1990s to reduce process costs and improve yields due to the fine pitch of semiconductor devices. The share of the market is increasing. COF packaging technology has been developed to cope with the trend of light and short and short of communication devices. However, in order to realize a display device having a high resolution, a driving load of a driver-IC increased as the driving frequency of a TV, a monitor, etc. increased to 60 hertz (Hz). Thus, when a COF packaging technology is applied, an integrated circuit (IC) ) The problem of heat generation of chips is serious.

In order to solve the above problem, a method of attaching a heat dissipation pad to a lower surface of a wiring film on which a semiconductor chip is to be mounted has been proposed. For example, as shown in FIG. 1, in a COF type semiconductor package, a chip 18 having a semiconductor integrated circuit implemented on a flexible film 11 is attached by an adhesive (not shown). Here, the film 11 is formed by stacking the lower insulating layer 10, the lead 12, and the surface insulating layer 14. The heat dissipation pad 20 is attached to the lower surface of the lower insulating layer 10 by the adhesive 21. In the COF type semiconductor package having such a structure, heat generated by the operation of the chip 18 is transferred to the heat radiation pad 20 through the underfill layer 16, the lead 12, and the lower insulating layer 10. The heat radiating pad 20 radiates heat to the outside.

In the above-described COF type semiconductor package with a heat dissipation pad, it is intended to solve the heat dissipation problem of the recently emerging package, but the thickness of the package is increased due to the attachment of the heat dissipation pad, which is disadvantageous for thinning. In addition, in order to heat the heat generated from the chip through the heat dissipation pad, the heat dissipation effect is insufficient since the heat is generated through components of different materials, that is, the underfill layer, the lead, the lower insulation layer, and the heat dissipation pad. In addition, the heat dissipation pad attached to the lower insulating layer by an adhesive can be easily separated from the lower insulating layer by external stress such as frictional force intensively applied to corner portions such as the "A" part.

The present invention is to solve the above-described problems of the prior art, and to improve the heat dissipation of the seaf-type semiconductor package and at the same time the heat dissipation member of the structure having excellent reliability of the heat dissipation member is excellent and a tape wiring board for the same It aims to provide.

Furthermore, another object of the present invention is to provide a CFO type semiconductor package capable of blocking interference by electromagnetic waves generated by a semiconductor chip and ultraviolet interference by external light, and a tape wiring board for the same.

According to an embodiment of the present disclosure, a CFO semiconductor package may include: a tape wiring board in which an insulating film, a metal pattern layer formed on the insulating film, and a surface insulating layer protecting the metal pattern layer are sequentially stacked; And a semiconductor chip mounted on a tape wiring board, wherein the metal baton layer comprises: a circuit pattern layer electrically connected to the semiconductor chip; And an isolation pattern layer electrically insulated from the circuit pattern layer, wherein the semiconductor chip is mounted on the isolation pattern layer.

Here, the circuit pattern layer is electrically connected to the electrode pad formed on the semiconductor chip by the electrode bumps. The semiconductor chip is bonded to the upper portion of the isolation pattern layer with a molding resin. In addition, an opening for exposing a part of the isolation pattern layer may be formed in the insulating film, and further, an opening may be formed through the isolation pattern layer and a portion of the insulating film disposed under the insulating pattern layer.

The tape wiring board according to the present invention is a tape wiring board for a semiconductor type semiconductor package in which an insulating film, a metal pattern layer formed on the insulating film, and a surface insulating layer for protecting the metal pattern layer are sequentially stacked. A circuit pattern layer electrically connected to the semiconductor chip to be mounted on the tape wiring board; And an isolation pattern layer electrically insulated from the circuit pattern layer.

Here, the opening may be formed in the insulating film to expose a part of the isolation pattern layer, and further, an opening may be formed through the isolation pattern layer and a portion of the insulating film positioned below the insulating pattern layer.

In the CFO semiconductor package having the above-described structure, the heat generated in the semiconductor chip is discharged to the back surface of the substrate via the isolation pattern layer below it. That is, the isolation pattern layer can function as a heat radiation pad of the semiconductor package. Since the semiconductor chip and the isolation pattern layer are disposed close to each other, heat generated in the semiconductor chip is transferred directly to the isolation pattern layer, and heat dissipation can be effectively performed due to the isolation pattern layer made of a metal having excellent thermal conductivity.

In addition, unlike the prior art described above, since the isolation pattern layer functioning as the heat radiation pad in the present invention is formed inside the tape wiring board, there is no risk of separation due to external stress such as friction. Furthermore, since the molding resin is formed around the isolation pattern layer, even when the flexible tape wiring board is bent and disposed, the insulation state with the circuit pattern layer formed in the periphery can be safely maintained.

Furthermore, the isolation pattern layer may be disposed in the lower portion of the semiconductor chip so as to overlap with the chip mounting region, thereby attracting the electromagnetic waves generated from the semiconductor chip as a center to obtain an additional effect of reducing electrical stability and interference by electromagnetic waves. Can be. Furthermore, a malfunction of the semiconductor chip may be caused by ultraviolet rays (UV) generated from light, and the isolation pattern layer may also serve to block interference caused by the ultraviolet rays.

1 is a cross-sectional view of a conventional Seaf type semiconductor package having a heat dissipation pad.
2 is a cross-sectional view of a CIF semiconductor package according to an exemplary embodiment of the present invention.
FIG. 3 is a top view of the tape wiring board for the CMOS package of the present invention shown in FIG. 2.
4 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
FIG. 5 is a top view of the tape wiring board for the CFC semiconductor package according to the present invention shown in FIG. 4.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the tape wiring board according to the present invention and the Seaf type semiconductor package using the same will be described in detail.

[First Embodiment]

First, the structure of the CFP semiconductor package according to the present invention will be described with reference to FIGS. 2 and 3 as follows.

The semiconductor F semiconductor package according to the present invention has a structure in which the semiconductor chip 200 is mounted on the tape wiring board 100. Here, the tape wiring board 100 includes an insulating film 110 having flexibility, metal pattern layers 120 and 130 formed on the insulating film 110, and a surface insulating layer 140 protecting the metal pattern layers. It consists of. The insulating film 110 is usually made of polyimide, the metal pattern layers 120 and 130 are made of a metal (eg, copper) pattern having excellent electrical conductivity, and the surface insulating layer 140 is made of a resist layer. Can be. In addition, the semiconductor chip 200 having a predetermined integrated circuit is bonded by the molding resin 160 on the tape wiring board 100.

The metal pattern layer included in the tape wiring board 100 may include a circuit pattern layer 120 electrically connected to the semiconductor chip 200, and an isolation pattern layer electrically insulated from the circuit pattern layer 120. 130). Here, an electrode bump 122 is formed at one end of the circuit pattern layer 120, and an electrode pad (not shown) formed around the bottom surface of the semiconductor chip 180 is connected to the circuit pattern layer 120 via the electrode bump 122. ) And a flip chip bonding structure electrically connected thereto.

In addition, the isolation pattern layer 130 defines a region ('CA' in FIG. 3) on which the semiconductor chip 200 is to be mounted, and the semiconductor chip 200 is disposed to overlap the isolation pattern layer 130. Here, the isolation pattern layer 130 is electrically insulated from the semiconductor chip 200 and the circuit pattern layer 120. The molding resin 160 is injected into the upper portion of the isolation pattern layer 130 so that the bottom surface of the semiconductor chip 200 is formed. It is glued here.

3 is a top view of the tape wiring board 100 and shows a state in which a region in which the semiconductor chip 200 is to be mounted is exposed. As shown in FIG. 3, the isolation pattern layer 130 is formed at a position substantially overlapping the chip mounting area CA, and a plurality of circuit pattern layers 120 are separated from the isolation pattern layer 130 by a predetermined distance. It is formed in an insulated state spaced apart. In addition, in the packaged finished product, the insulating pattern layer 130 and the circuit pattern layer 120 may be secured to the electrical insulation state by the molding resin 160.

In the tape wiring board 100 and the CMOS type semiconductor package having the above-described structure, the heat generated in the semiconductor chip 200 is discharged to the rear surface of the substrate via the isolation pattern layer 130 below. That is, the isolation pattern layer 130 may function as a heat radiation pad of the semiconductor package. Since the semiconductor chip 200 and the isolation pattern layer 130 are disposed close to each other, heat generated in the semiconductor chip 200 is transferred directly to the isolation pattern layer 130, and the isolation pattern of a metal material having excellent thermal conductivity is provided. Due to the layer 130, heat dissipation can be easily achieved.

In addition, unlike the prior art described above, since the isolation pattern layer 130 that functions as a heat radiation pad in the present invention is formed inside the tape wiring board 100, there is no risk of separation due to external stress such as friction. Furthermore, since the molding resin 160 is formed around the isolation pattern layer 130, even when the tape wiring board 100 is bent and disposed, the insulation state with the circuit pattern layer 120 formed around the insulation pattern layer 130 can be safely maintained. Can be.

In addition, the isolation pattern layer 130 may be disposed to overlap the chip mounting area CA at the bottom of the semiconductor chip 200. An additional effect of reducing interference due to electromagnetic waves can be obtained. Furthermore, malfunction of the semiconductor chip may be caused by ultraviolet rays (UV) generated from light, and the isolation pattern layer 130 may also serve to block interference by the ultraviolet rays.

[Second Embodiment]

4 and 5 illustrate another embodiment in which the heat dissipation effect of the package according to the formation of the isolation pattern layer 130 can be maximized. In the second embodiment shown in Figs. 4 and 5, the components with the same reference numerals are the same as the components of the first embodiment.

In the semiconductor package shown in the second embodiment, an opening 150 penetrating through the isolation pattern layer 130 and a part of the insulating film 110 positioned below it is further formed. As a result, heat generated in the semiconductor chip 200 may be more effectively discharged. Furthermore, in this embodiment, the opening 150 is extended to not only the insulating film 110 but also to the isolation pattern layer 130. However, unlike the insulating pattern 110, only a part of the insulating film 110 is removed to form the isolation pattern. It may also be formed to expose a portion of layer 130.

Although a preferred embodiment of the present invention has been described so far, those skilled in the art will be able to implement in a modified form without departing from the essential characteristics of the present invention. Therefore, the embodiments of the present invention described herein are to be considered in descriptive sense only and not for purposes of limitation, and the scope of the present invention is shown in the appended claims rather than the foregoing description, and all differences within the equivalent scope of the present invention Should be interpreted as being included in.

100: tape wiring board 110: insulating film
120: circuit pattern layer 130: isolation pattern layer
140: surface insulating layer 150: opening
160: molding resin 200: semiconductor chip

Claims (8)

  1. A tape wiring board on which an insulating film, a metal pattern layer formed on the insulating film, and a surface insulating layer protecting the metal pattern layer are sequentially stacked; And
    A semiconductor package comprising a semiconductor chip mounted on the tape wiring board,
    The metal pattern layer may include a circuit pattern layer electrically connected to the semiconductor chip; And an isolation pattern layer electrically insulated from the circuit pattern layer.
    The semiconductor chip is mounted on an upper portion of the isolation pattern layer, and the opening is formed through the portion of the insulating film positioned on the isolation pattern layer and the lower portion of the semiconductor chip package.
  2. The method of claim 1,
    And the circuit pattern layer is electrically connected to an electrode pad formed on the semiconductor chip by an electrode bump.
  3. The method of claim 1,
    The semiconductor chip is a semiconductor package, characterized in that bonded to the upper portion of the isolation pattern layer with a molding resin.
  4. delete
  5. delete
  6. A tape wiring board for a CMOS type semiconductor package in which an insulating film, a metal pattern layer formed on the insulating film, and a surface insulating layer protecting the metal pattern layer are sequentially stacked.
    A circuit pattern layer in which the metal pattern layer is electrically connected to a semiconductor chip to be mounted on the tape wiring board; And an isolation pattern layer electrically insulated from the circuit pattern layer, wherein an opening is formed through the isolation pattern layer and a portion of the insulating film disposed below the isolation pattern layer.
  7. delete
  8. delete
KR1020110008739A 2011-01-28 2011-01-28 Chip-on-film type semiconductor package, and tape circuit board for the same KR101166069B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110008739A KR101166069B1 (en) 2011-01-28 2011-01-28 Chip-on-film type semiconductor package, and tape circuit board for the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020110008739A KR101166069B1 (en) 2011-01-28 2011-01-28 Chip-on-film type semiconductor package, and tape circuit board for the same
CN2012100175079A CN102623419A (en) 2011-01-28 2012-01-19 Chip-on-film type semiconductor package, and tape circuit board for the same
TW101102522A TW201244020A (en) 2011-01-28 2012-01-20 Chip-on-film type semiconductor package with enhanced performance of heat radiation
JP2012012552A JP2012160728A (en) 2011-01-28 2012-01-25 Cof type semiconductor package having improved heat radiation efficiency

Publications (1)

Publication Number Publication Date
KR101166069B1 true KR101166069B1 (en) 2012-07-19

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KR1020110008739A KR101166069B1 (en) 2011-01-28 2011-01-28 Chip-on-film type semiconductor package, and tape circuit board for the same

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JP (1) JP2012160728A (en)
KR (1) KR101166069B1 (en)
CN (1) CN102623419A (en)
TW (1) TW201244020A (en)

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KR20160007968A (en) * 2014-07-10 2016-01-21 삼성디스플레이 주식회사 Display apparatus and method of manufacturing the same
US10163927B2 (en) 2016-11-04 2018-12-25 SK Hynix Inc. Semiconductor memory device

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JP2004119650A (en) 2002-09-26 2004-04-15 Nec Kansai Ltd Semiconductor device
US20070215991A1 (en) * 2006-03-14 2007-09-20 Chyh-Yih Chang Tape

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US6617521B1 (en) 1998-12-21 2003-09-09 Seiko Epson Corporation Circuit board and display device using the same and electronic equipment
JP2003086629A (en) * 2001-09-13 2003-03-20 Hitachi Ltd Cof-type semiconductor device and manufacturing method thereof
JP2004119650A (en) 2002-09-26 2004-04-15 Nec Kansai Ltd Semiconductor device
US20070215991A1 (en) * 2006-03-14 2007-09-20 Chyh-Yih Chang Tape

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160007968A (en) * 2014-07-10 2016-01-21 삼성디스플레이 주식회사 Display apparatus and method of manufacturing the same
KR101685020B1 (en) 2014-07-10 2016-12-12 삼성디스플레이 주식회사 Display apparatus and method of manufacturing the same
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US10163927B2 (en) 2016-11-04 2018-12-25 SK Hynix Inc. Semiconductor memory device

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Publication number Publication date
TW201244020A (en) 2012-11-01
CN102623419A (en) 2012-08-01
JP2012160728A (en) 2012-08-23

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