JP2003086629A - Cof-type semiconductor device and manufacturing method thereof - Google Patents

Cof-type semiconductor device and manufacturing method thereof

Info

Publication number
JP2003086629A
JP2003086629A JP2001277803A JP2001277803A JP2003086629A JP 2003086629 A JP2003086629 A JP 2003086629A JP 2001277803 A JP2001277803 A JP 2001277803A JP 2001277803 A JP2001277803 A JP 2001277803A JP 2003086629 A JP2003086629 A JP 2003086629A
Authority
JP
Japan
Prior art keywords
semiconductor chip
cof
semiconductor device
hole
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001277803A
Other languages
Japanese (ja)
Inventor
Masahito Futami
Masayoshi Shinoda
Katsuhiro Tabata
Yoshiyuki Tanigawa
Nobuhisa Toma
雅人 二見
克弘 田畑
展久 當麻
政佳 篠田
義之 谷川
Original Assignee
Hitachi Ltd
Hitachi Tokyo Electronics Co Ltd
日立東京エレクトロニクス株式会社
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tokyo Electronics Co Ltd, 日立東京エレクトロニクス株式会社, 株式会社日立製作所 filed Critical Hitachi Ltd
Priority to JP2001277803A priority Critical patent/JP2003086629A/en
Publication of JP2003086629A publication Critical patent/JP2003086629A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

(57) Abstract: In a method of manufacturing a semiconductor device, there is provided a manufacturing method for aligning leads and bumps with high accuracy and high reproducibility, and a semiconductor device manufactured by the manufacturing method. A semiconductor device comprising: a semiconductor chip; and a COF film having leads formed on a main surface of an insulating base film at intervals corresponding to external electrodes (pads) of the semiconductor chip. A through hole is provided between the tips of the inner leads of the leads facing each other on the COF film.

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to inner leads and bumps on external electrodes (hereinafter referred to as pads) of a semiconductor chip. Related to effective technology applied to the bonding of
The present invention relates to a technology effective for an OF type semiconductor device, for example, an LCD driver product. [0002] Conventional chip-on-film (hereinafter, referred to as “chip-on-film”)
As shown in FIG. 7, in a COF tape (film) in a semiconductor device (referred to as a COF) type, leads 102 are formed on a main surface of an insulating base film at intervals corresponding to external electrodes (pads) of a semiconductor chip. ing. Also, CO
A sprocket hole 201 for feeding an F tape (film) is formed. The bonding between the inner leads and the bumps formed on the pads is performed in the following procedure. The COF tape (film) is conveyed to a predetermined position, and then the semiconductor chip is transferred to a bonding head and held by suction. Deviations from the predetermined positions of the COF tape and the semiconductor chip are determined, and the bonding head is transported to a predetermined position below the COF tape based on the deviations. Next, fine adjustment is performed based on an image obtained when the COF tape and the semiconductor chip are overlaid, and the inner leads and the bumps are aligned. [0005] Next, the bumps on the pads of the semiconductor chip and the leads on the COF tape that have been aligned are subjected to collective bonding using the stage of the bonding station and the tool thermal load of the bonding head which are heated to a high temperature. The present inventor has found the following problems as a result of studying the prior art. [0007] At the time of bonding positioning, a recognition pattern serving as a positioning reference on the device side is captured by a chip pattern via a COF tape, so that it is difficult to obtain a stable recognition image and erroneous recognition. Or the recognition system is deteriorated, leading to poor lead position misalignment. For example, in a liquid crystal driving device, the number of bumps is five.
Since the number of the bumps and the inner leads are becoming finer and finer, the width is narrower and closer to each other. Therefore, it is necessary to align the inner leads and the bumps on the semiconductor chip pads with high precision. Therefore, it is necessary to improve the recognition accuracy of the specific pattern. An object of the present invention is to provide a technique capable of positioning a lead and a bump with high precision in a method of manufacturing a semiconductor device. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. The following is a brief description of an outline of typical inventions disclosed in the present application. According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip; and a COF film having leads formed on a main surface of an insulating base film at intervals corresponding to external electrodes (pads) of the semiconductor chip. The COF
A through hole is provided between the tips of inner leads of the leads facing each other on the film. According to the present invention, since a through hole is provided between the tips of the opposed inner leads, a specific pattern on the surface of the semiconductor chip can be directly taken in without using a COF tape. Pads can be positioned with high precision. Further, by providing the through hole between the tips of the inner leads facing each other, it is possible to prevent the bending of the leads during bonding and the contact with the adjacent leads, and an open defect that occurs when the inner leads are not connected to predetermined bumps. And short circuit can be prevented. Further, by filling the underfill from the through hole, the gap between the tape and the semiconductor chip can be evenly and easily filled, so that the coating shape and the coating accuracy can be improved and stabilized. According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the size of the through hole is defined as a whole or a part of a region where the semiconductor chip is mounted. According to a third aspect of the present invention, in the semiconductor device according to the first aspect of the present invention, the positions of the through holes are two places at both ends in a longitudinal direction of a region where the semiconductor chip is mounted. According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the position of the through hole is defined by a central portion of a region where the semiconductor chip is mounted and a longitudinal direction of the region where the semiconductor chip is mounted. At both ends. According to a fifth aspect of the present invention, a semiconductor chip is mounted on a COF film having leads formed on a main surface of an insulating base film at intervals corresponding to external electrodes (pads) of the semiconductor chip. A plurality of the external electrodes are connected to inner leads, and the semiconductor chip and CO are connected.
A method of manufacturing a COF type semiconductor device in which an underfill is filled between F films, comprising: a first step of preparing an insulating base film; and a step of preparing the insulating base film at intervals corresponding to the external electrodes of the semiconductor chip. A second step of forming a lead on the main surface of the film, a third step of providing a through hole between the tips of the inner leads of the lead, and using a predetermined pattern on the semiconductor chip that can be recognized from the through hole, A fourth step of aligning the inner lead and a bump formed on an external electrode (pad) on the semiconductor chip corresponding to the inner lead; and, in the aligned state, the external electrode (pad) and the inner A fifth step of bonding leads to the external electrodes via bumps formed on the external electrodes, and an underlayer between the semiconductor chip and the COF film. Is a manufacturing method of the COF-type semiconductor device characterized by having a sixth step of filling the fill. According to the present invention, since a through hole is provided between the tips of the opposed inner leads, a specific pattern on the surface of the semiconductor chip can be directly taken in without using a COF tape. Pads can be positioned with high precision. Further, by providing the through hole between the tips of the inner leads facing each other, it is possible to prevent the bending of the leads during bonding and the contact with the adjacent leads, and an open defect that occurs when the inner leads are not connected to predetermined bumps. And short circuit can be prevented. Further, by filling the underfill from the through hole, the gap between the tape and the semiconductor chip can be evenly and easily filled, so that the coating shape and the coating accuracy can be improved and stabilized. A sixth invention is directed to the COF according to the fifth invention.
In the method for manufacturing a semiconductor device, the size of the through-hole in the third step may be the whole or a part of a region where a semiconductor chip is mounted. According to a seventh aspect, the COF according to the fifth aspect is provided.
In the method for manufacturing a semiconductor device, the position of the through hole in the third step may be two places at both ends in a longitudinal direction of a region where the semiconductor chip is mounted. An eighth invention is directed to the COF according to the fifth invention.
In the method for manufacturing a semiconductor device, the position of the through hole in the third step may be set at three positions: a central portion of a region where the semiconductor chip is mounted and both ends in a longitudinal direction of the region where the semiconductor chip is mounted. And According to a ninth aspect, in the method of manufacturing a COF semiconductor device according to the fifth to eighth aspects, the underfill in the third step is filled from the through hole. I do. Hereinafter, the present invention will be described in detail along with embodiments (examples) with reference to the drawings. In all the drawings for describing the embodiments (examples), those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted. (Embodiment 1) As shown in FIG. 1, a COF type semiconductor device according to the present embodiment
A bump 103 is formed on a pad (not shown) of FIG. 1, the bump 103 is bonded to a lead 102 formed on a COF tape (film) 101, and an underfill 1 is provided between the semiconductor chip 104 and the COF tape 101.
05 is filled, and a through hole 106 is provided between the opposed inner leads of the COF tape 101. As shown in FIG. 2, a plurality of leads 102 are formed on the COF tape (film) 101. The plurality of leads 102 include a right input-side lead,
A distinction is made between the left output leads, which are formed in opposing positions. A through hole 106 is provided between the inner leads facing each other. The lead is manufactured in the following procedure.
For example, a sprocket hole 201 and a through hole 106 are provided in a base made of a polyimide film by, for example, a punching method or etching. Next, a copper foil serving as a lead is bonded, and a resist film of a lead pattern is formed on the surface of the bonded copper foil. Next, the copper foil is etched using the resist film as a mask. Next, tin, solder,
Plating gold etc. The through-hole 106 is preferably formed between the inner leads facing each other, so that the COF tape remains on the tip of the lead. By doing so, it is possible to prevent the bending of the lead during the bonding and the contact with the adjacent lead, and it is possible to prevent the open defect and the short circuit that occur when the inner lead is not connected to the predetermined bump. The alignment between the lead 102 and the bump 103 on the pad is performed as shown in FIG.
A first camera 301 for reading a deviation of the tape (film) 101 from a predetermined transport position, and a bonding head 3
A second camera 304 that reads a deviation of the semiconductor chip 104 supplied to the semiconductor chip 104 from a predetermined supply position, and a correction amount of the stage operation of the bonding head 305 is determined from the deviation amounts read by the first camera 301 and the second camera 304. The bonding head 30 is calculated based on the correction amount.
And a semiconductor device 1 on the top.
04 having a flat surface for sucking and holding the semiconductor chip 10
And a bonding head 305 having a stage for transporting the bonding head 4 directly below the COF tape 101.
The bonding is performed by using a COF bonding apparatus including a bonding station 303 having a pressing surface facing the flat surface 05. First, when the COF tape (film) 101 is transported to a predetermined position, the first camera 301
A shift amount from a predetermined transport position is obtained. Next, the semiconductor chip 104 is selected, and the selected semiconductor chip 104 is
The second camera 304 transfers the image data to a position 05 and holds it by suction. Next, in the control device 302, the first
A correction amount of the stage operation of the bonding head 305 is calculated based on the shift amount obtained by the camera 301 and the second camera 304, and the bonding head 305 is transported to a predetermined position below the COF tape 101 based on the correction amount. I do. Next, an image obtained when the COF tape 101 and the semiconductor chip 104 are overlapped is recognized by the first camera 301, and fine adjustment is performed. First, the first camera 301 registers a characteristic pattern directly formed on the surface of the semiconductor chip 104 together with its position (coordinates) in advance using the registered pattern (referred to as a specific pattern). . When a specific pattern is recognized,
The coordinates are obtained, and the deviation from the coordinates of the registered specific pattern is obtained. Based on the shift amount, correction in the X direction, the Y direction, and the θ direction is performed via the control device 302.
Reflected in the stage operation of the bonding head 305,
Positioning is performed. Since a specific pattern on the surface of the semiconductor chip 104 can be directly recognized by the first camera 301 from the through-hole 106 without using a COF tape, a stable recognition image can be obtained. Lead position misalignment failure can be prevented. As described above, the alignment between the inner leads formed on the COF tape and the bumps 103 on the semiconductor chip pads is performed indirectly. As the specific pattern, for example, a wiring pattern or a pattern having a characteristic on the surface is used. The specific pattern may be one place or plural places. In addition, the present invention is not limited to the characteristic pattern formed on the surface of the semiconductor chip 104, and a cross or square pattern may be separately provided. Thereafter, the aligned bumps 103 and leads 102 are subjected to collective bonding by the stage of the bonding station 303 and the tool heat load of the bonding head 305 which have been heated to a high temperature. After bonding, the semiconductor chip 104 and C
An underfill is filled between the OF tapes 101. As shown in FIG. 4, it is also possible to arrange a nozzle 401 for filling the underfill above the through hole 106 of the COF tape and discharge the underfill. By doing so, the underfill can be filled first between the semiconductor chip 104 and the COF tape 101, so that the underfill is filled between the semiconductor chip 104 and the COF tape 101 after wrapping around the inner leads. Unfilling and voids can be prevented. Further, since the underfill is filled first between the semiconductor chip 104 and the COF tape 101, the protrusion of the fillet can be reduced. Also,
It is also advantageous if the gap between the semiconductor chip and the COF tape is reduced. Also, the injection time can be reduced. (Embodiment 2) The semiconductor device according to Embodiment 2 has the same configuration as that of FIG. 1 except for the COF tape. As shown in FIG. 5, the COF tape in the semiconductor device according to the second embodiment is different from the first embodiment in that the position of the through hole 106 is set at two positions at both ends in the longitudinal direction of the region where the semiconductor chip 104 is mounted. There are features. When two or more specific patterns are set, it is preferable that the specific patterns are set at locations apart from each other in terms of improving accuracy. By providing the through-hole 106 in the above-described region, a specific pattern can be set at a distant place, so that the lead 102 and the bump 103 can be positioned with high accuracy. (Embodiment 3) A semiconductor device according to Embodiment 3 has the same configuration as that of FIG. 1 except for a COF tape. As shown in FIG. 6, in the COF tape in the semiconductor device of the third embodiment, the positions of the through-holes are aligned with the center of the region where the semiconductor chip is mounted and the longitudinal direction of the region where the semiconductor chip is mounted. It is characterized in that it is provided at three places, that is, at both ends. By providing through holes in two regions including both ends in the longitudinal direction of the semiconductor chip, the same effect as in the second embodiment can be obtained. Further, by providing a through hole in the center region where the semiconductor chip is mounted, when the underfill is filled between the semiconductor chip 104 and the COF tape 101 after bonding, as shown in FIG. By disposing a nozzle 401 for filling the semiconductor chip above the through hole 106 in the central region where the semiconductor chip is mounted and discharging the liquid, the underfill can be evenly filled between the semiconductor chip 104 and the COF tape 101. Therefore, the coating shape and the coating accuracy are stabilized. As described above, the invention made by the present inventor is:
Although the present invention has been described in detail with reference to the examples, it is needless to say that the present invention is not limited to the above-described embodiment, and can be variously changed without departing from the gist of the present invention. The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. In other words, in the COF type semiconductor device, by providing the through hole between the opposed inner leads of the COF film, a specific pattern on the surface of the semiconductor chip can be accurately read directly without using a COF tape. As a result, a stable image can be obtained, and it is possible to prevent lead position misalignment due to erroneous recognition or reduction in recognition accuracy.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a COF semiconductor device according to a first embodiment. FIG. 2 is a plan view of the COF tape on which the leads of the first embodiment are formed. FIG. 3 is a diagram illustrating a schematic configuration of a COF bonding apparatus. FIG. 4 is a diagram for explaining underfill filling in a manufacturing process of the COF semiconductor device of the first embodiment. FIG. 5 is a plan view of a COF tape on which leads of Embodiment 2 are formed. FIG. 6 is a plan view of a COF tape on which leads of Embodiment 3 are formed. FIG. 7 is a plan view of a conventional COF tape on which leads are formed. DESCRIPTION OF SYMBOLS 101 ... COF tape (film) 102 ... Lead 103 ... Bump 104 ... Semiconductor chip 105 ... Underfill 106 ... Through hole 201 ... Sprocket hole 301 ... First camera 302 ... Control device 303 ... Bonding station 304 ... No. 2 camera 305 ... bonding head 401 ... nozzle

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Masato Futami             3-3, Fujibashi, Ome City, Tokyo 2 Hitachi East             Kyoto Electronics Co., Ltd. (72) Inventor Katsuhiro Tabata             5-20-1, Josuihoncho, Kodaira-shi, Tokyo             Hitachi, Ltd. Semiconductor Group (72) Inventor Nobuhisa Taima             5-20-1, Josuihoncho, Kodaira-shi, Tokyo             Hitachi, Ltd. Semiconductor Group (72) Inventor Masayoshi Shinoda             5-20-1, Josuihoncho, Kodaira-shi, Tokyo             Hitachi, Ltd. Semiconductor Group F term (reference) 5F044 KK03 LL00 NN09 RR18 RR19

Claims (1)

1. A semiconductor chip, and a COF film having leads formed on a main surface of an insulating base film at intervals corresponding to external electrodes (pads) of the semiconductor chip. A semiconductor device, wherein a through-hole is provided between the tips of inner leads of the leads facing each other on the COF film. 2. The semiconductor device according to claim 1, wherein:
The semiconductor device according to claim 1, wherein the size of the through hole is the whole or a part of a region where the semiconductor chip is mounted. 3. The semiconductor device according to claim 1, wherein:
2. The semiconductor device according to claim 1, wherein the positions of the through holes are two at both ends in a longitudinal direction of a region where the semiconductor chip is mounted. 4. The semiconductor device according to claim 1, wherein:
The semiconductor device is characterized in that the positions of the through holes are three, that is, a central portion of a region where the semiconductor chip is mounted and both ends in a longitudinal direction of the region where the semiconductor chip is mounted. 5. A semiconductor chip is mounted on a COF film having leads formed on a main surface of an insulating base film at intervals corresponding to external electrodes (pads) of the semiconductor chip, and a plurality of external components on the semiconductor chip are provided. A method for manufacturing a COF-type semiconductor device, comprising connecting an electrode and an inner lead and filling an underfill between the semiconductor chip and the COF film, wherein a first insulating base film is prepared.
A step of forming leads on the main surface of the insulating base film at intervals corresponding to the external electrodes of the semiconductor chip; and a third step of providing a through hole between the tips of inner leads of the leads. And positioning the inner leads and bumps formed on external electrodes (pads) on the semiconductor chip corresponding to the inner leads by using a predetermined pattern on the semiconductor chip that can be recognized from the through hole. Fourth step, a fifth step of bonding the external electrode (pad) and the inner lead via the bump formed on the external electrode in the aligned state, and a step of bonding the semiconductor chip and the COF film. And a sixth step of filling an underfill therebetween. 6. The method of manufacturing a COF semiconductor device according to claim 5, wherein the size of the through hole in the third step is the whole or a part of a region where a semiconductor chip is mounted. A method for manufacturing a COF semiconductor device, comprising: 7. The method for manufacturing a COF semiconductor device according to claim 5, wherein the position of the through hole in the third step is two at two longitudinal ends of a region where the semiconductor chip is mounted. A method for manufacturing a COF semiconductor device, comprising: 8. The method of manufacturing a COF semiconductor device according to claim 5, wherein the position of the through hole in the third step is such that the position of the center of the region where the semiconductor chip is mounted and the position of the semiconductor chip are mounted. A COF type semiconductor device comprising three regions, that is, a longitudinal region and two longitudinal ends. 9. The method of manufacturing a COF semiconductor device according to claim 5, wherein said underfill in said sixth step is filled from said through hole. .
JP2001277803A 2001-09-13 2001-09-13 Cof-type semiconductor device and manufacturing method thereof Pending JP2003086629A (en)

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Application Number Priority Date Filing Date Title
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100610144B1 (en) 2004-11-03 2006-08-09 삼성전자주식회사 manufacturing method of chip-on-board package having flip chip assembly structure
KR100726996B1 (en) 2005-11-07 2007-06-14 엘지전자 주식회사 Integrated circuit package
US7981779B2 (en) 2003-10-09 2011-07-19 Panasonic Corporation Method for making junction and processed material formed using the same
KR101166069B1 (en) * 2011-01-28 2012-07-19 주식회사 루셈 Chip-on-film type semiconductor package, and tape circuit board for the same
KR20150128212A (en) * 2014-05-09 2015-11-18 주식회사 동부하이텍 Method of packaging semiconductor devices and apparatus for performing the same
WO2019127786A1 (en) * 2017-12-29 2019-07-04 武汉华星光电半导体显示技术有限公司 Flexible display panel and chip on film structure thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7981779B2 (en) 2003-10-09 2011-07-19 Panasonic Corporation Method for making junction and processed material formed using the same
KR100610144B1 (en) 2004-11-03 2006-08-09 삼성전자주식회사 manufacturing method of chip-on-board package having flip chip assembly structure
KR100726996B1 (en) 2005-11-07 2007-06-14 엘지전자 주식회사 Integrated circuit package
KR101166069B1 (en) * 2011-01-28 2012-07-19 주식회사 루셈 Chip-on-film type semiconductor package, and tape circuit board for the same
KR20150128212A (en) * 2014-05-09 2015-11-18 주식회사 동부하이텍 Method of packaging semiconductor devices and apparatus for performing the same
KR101666711B1 (en) 2014-05-09 2016-10-14 주식회사 동부하이텍 Method of packaging semiconductor devices and apparatus for performing the same
WO2019127786A1 (en) * 2017-12-29 2019-07-04 武汉华星光电半导体显示技术有限公司 Flexible display panel and chip on film structure thereof

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