201241948 六、發明說明： 【發明所屬之技術領域】 【_】 本發明係關於一種半導體測試裝置，詳而言之，係關於高 邏輯訊號產生之改善》 % 【先前技術】 【0002】 導體測試裝置之一種中，為了將自内建於半導體測試裝置 ，成唬產生部所輸出的相對地較低頻率邏輯訊號更為高頻率之 以3本產生輸出’如圖5所示，將對於安裝有圖形訊號 早兀的半導體測試裝置係為可裝卸之複數之喊卡，以與各 设置，該圖形訊號產生單元’將自内建於半導 、>j 5式裝置之訊號魅部所輸出的複數彡統其邏輯喊相加 出。 【0003】 半導Ξ、^二ϊ1，產生部1與第2訊號產生部2，為分別設於 【0004】 輸出將Λ等自第1訊號產生部1與第2訊號產生部2 亦即將具有ig:列：^加1將此等邏輯訊號si與S2之頻率， 號S3輸統鮮其2倍頻率的高速邏輯訊 D。 《邮喊產輯元之㈣B(lateh)4其資料端子 【0005】 自設置於半導體測試裝置的虹㈣咖^組。叩，鎖相迴 4 201241948 於—輸之時脈CU被閃鎖。另，pLL5，亦 分別將時^‘ 2由稷數之訊號卡組成之群組設置複數系統， 生單元的Γ· 文。之訊號卡之各個構成圖形訊號產 【0006】 6被，繼取之開關 單元之Η閼7、士认、+象（DUT) ’並介由構成圖形訊號產生 7__&彻職㈣麵fll f產生 形訊此—校正路徑係供修正自各圖 ^斤用，選伽電器8以^一二=之時序誤 輸出至DUT的僅k擇將閃鎖裔4之輪出訊號s4 動而驅動。 4虎產生早70之系統的方式，與開關6、7連 【0008】 閂鎖器?s8被輸入至設於半導體測試裝置之 出【的時脈CU之時序^¥。體測試裝置之基準時序產生部10所輸 門鎖器9之輪φ如Λ 、 之訊號判定部。。〜s，被輪出至未圖示的半導體測試裝置 【0010】 圖6為’顯示選握έ。 ^關被連接為3階段的樹狀厂之一例的構成說明圖，複數切換 訊號時序圖。圖7中，⑷顯示第1 訊號S2，（Ο I員示加；=j 2顯示第2訊號產生部2之輸出 敲部1、2内部各自訊號s3。此—時間點中，訊號 目之h序块差重疊而直接顯現於加算器3之輸 5 201241948 出訊號 s3〇(d)瑟 顯示經重定時的閃鎖器4之^寺=，5輸入之時脈CXWe) 【0012】 勒出5il3虎s4。 圖5之構成中，—iin. τ- 一時序精度造ΐ巨大頻率變高，則前一㈣之狀態對:欠 產生之以：並前-資料之狀態’故斷 [0013] 舌除之 與二相依性時序誤差’設置_器4 【0014】 的方ΪΞΪ述自【自5 訊號產生單元係以與連接針_ 接針之訊號間產生時間差（時滞）。 果^ 遺 3 '' 9 诗导-^ 士 ，設有由選擇繼 藉此-校2'= ΐίΐ時序產生部10組成的共通之校正路徑: 出路經所具備的未圖;; 滯）調整為0。 狀深寻將如此而測疋出之時間差（時 [習知技術文獻] [專利文獻] [0016] 術（it獻1，揭示關於輸出訊號（圖形訊號）之時滞調整的技 [0017] 專利文獻1日本特開2008 —145266號公報 【發明内容】 [本發明所欲解決的問題] 6 201241948 【0018】 之時脈⑴ 【0019】 干雞以進仃阿速切換之：DUT測定。 cu t㈣輪出之時脈 tsr性時序誤差料‘無法部卜2具有 滯之^無傳輸通路之傳輪損耗變大，故有時 【0021】 心 如圖8所示’因傳輪“之損 【0022】 (b)顯示輸入(至)第之第1接腳ΗΝ1的波形， 顯，第！接腳職其校正路波形，⑷ 示由閃鎖器4重定時之第2接腳酸2^=輸出^形’⑷顯 恥其校正路徑之_器9的_第 【嶋f正路徑之咖，出的波形。…2接腳 201241948 此外，此等訊號通常有雜訊重疊，故通過既定之邏輯訊號時， 產生，輯成為不定之不定區間。此一不定區間中，無法正確地與 f準時序比較’變得無法測定時間差（時滯）Tskw。圖8之例中。 顯不，重定時之第1接腳ΡΙΝΙ的波形與第2接腳ΡΓΝ2的波形間 不定區間變得較初期時滯Tskw的寬度更大，無法正確地檢測原 本之初期時滯Tskw的狀況。 【0025】 為解決此等課題，本發明之目的在於，提供一種能夠以低成 生輸出較半導體測試裝置之系統頻率更為高頻率的邏輯訊 即時地更邊緣與頻率，獲得高精度的時序精度之半導 體須!J§式裝置。 [解決問題之技術手段] 【0026】 為達成此等課題，本發明的請求項丨所請之發明為， 半導剩試裝置，設置有複數之®形賴產生單元以及 圖形訊號產生單7"，由將自内建於半導體測 器、將此斤出^的^士系士統其邏輯訊肋^ 抵以Uhl "*。。輸出依照重定時時脈而導入的閂鎖器、以及 此—閃鎖輸出的開關所構成，·該校正路徑，修正自 滞、;複婁之圖形峨產生單元介由闕而輸出之輸出訊號間的時 5亥半導體測試裝置之特徵為： ^而驅7，擇—地選擇既定之產生早兀之開關連 置，所請之發料，如項1所記載之半導體測試裝 為可生單元’各自安胸彻測試裝置 8 201241948 【0028】 置，所清之發明為，如請求項1所記載之半導體測試裝 【〇〇3'數之圖㊉喊產生單元，各自組裝於半導制試裝置。 請求項4所請之發明為， 數之圖ΪΪίΐΪ試裝置，具有複數之圖形訊號產生單元，該複 i部^出Si早凡’由將自内建於半導體測試裝置之訊號產 之輸出^ 統其祕訊號相加的加算11、將此一加算器 閃鎖輸導人的_、、以及選擇性地輸出此— 而產Ϊ特徵為’該重定命寺脈係藉由相加至少2系統之邏輯訊號 【0030】 請求項5所請之發明為， 之校ΐϊί導體戦^，設置有修正複數之®職制的時滞 遠動雜正雜含有邏朗，無各_訊號之選擇 連動而驅動’擇—地選擇既定之輸出訊號。 [本發明之效果] 【0031】 夕’⑨夠以低成本產生高速的邏輯訊號，亦可岸用於既在 之半導體測試裝置。 力J愿用於既存 【0032】 重疋日$時脈，係藉由相加至少2李铋之漏蘇走 可即時地變更邊緣間隔與頻率。系、、，先之_«而產生，故 【0033】 亞，由於校正路徑巾不具損耗大之獅繼妓等的時序 心化要因，故可施行南精度的校正，獲得高精度的時序精^。、序 201241948 【實施方式】 [實施本發明之最佳形態] 【0035】 明的為顯示本發 與圖5之相異點在於；使用由輪出邏^訊同第一3符^產圖生1 ===㈡=產生部12、== 5之PLL5 ;以及使用邏ϋ 14斤構成的重定時時脈產生部取代圖 【0036】 使用物間14取代圖5之選擇繼電器8。 工3二= 生部12及加算器 號卡組叙馳設數之訊 13之輸出訊號sl3，侃*〜=寻重物時脈產生部的加算器 _器4其時^分別被輸出至設於複數之訊 關7 _ 4之輸出訊號S4，各自介由開 【0038】 -校正路徑係縣^^擇繼電11 8隱輯紐正路徑，此 複數輸出訊號s、/pa1 1 σ號產生單元介由閂鎖器4輸出的 將閃鎖器4之輪出!夺所用，邏輯閘W以擇-地僅選擇 與開關6、7連動而tj；輸出至贿的訊號卡之系統的方式， 【0039】 軔 邏輯閘14之於山 所輪出的==^^=_89，並以自時脈產 閃在負哭9 半導體測部與圖5同樣地，被輸出至未圖示的 10 201241948 【0041】 訊』時序圖。圖2中，⑴顯示第丄 訊號s2，（e)顯H^ Sl，=)顯示第2訊號產生部2之輸出 生部11之輪出訊號二之:出，虎33，，顯示第3訊號產 Sl2，⑴顯示加‘ 13 以訊號產生部12之輪出訊號 鎖器4之輪出訊H輪出訊相3，⑷顯示被重定時的閃 【0042】 出訊ί 11之輪出訊號SU與第4訊號產生部12之幹 山口 ，為早純之觸 1 U之輸 依性時序誤差。此—α/:二1(^。波^的重^故不存在資料相 號仍亦成為不具資=^力:^^力^輸出之重定時時脈訊 =r誤差之重定時二^②。，以此—不具資料 關於資料相依性時序誤差 3為’於觸發點τρ使邏輯：=詳細地 Ϊ 之時序以細與案例2進行比ί Ϊ:。:： 【_Γ 想波形，下段㈨顯示實際波形例 例! S 想===，之時間較案 =移至Ηι蜂且遷移至辦驗 [0045] 實際波形中，具有過衝、下衝、 為如圖所示之波形。案例f之實 升，及下降之遷移時間，成 移至Lo位準並於£ 後，間、’、、’理想波形自位準遷 [0046] 袖疋後間始自L〇位準往K位準遷移。 一方面，案例2之實際波形為，自Hi位進'黑秒 下衝的減_㈣，_奴仏位 201241948 移，成為自較案例1更低位準之L〇位準往 結果，如同圖示，與案例丨比較，則至 1位準的遷移。此一 生時間差。此一時間差，成為資料相 s値丁}1為止之時間產 【_7】 為科相依性時序誤差Ter而呈I見。 一與其相對，前一資料之時間通常為—定 一疋的位準之上升，此等資料相依性時 、月况，成為常時自 亦即，圖2的⑷及㈦所示 的魅差如憂得不再產生。 況，資料相依性時序誤差Ter不再產(〇1〇1)之情 路徑，校正時滯等之時序誤差。 、、乂重疋時後，介由校正 【0048】 ' 圖1所示之本發明的校正路徑中， 以邏輯閘14施行各訊號的切換。藉此^知之選擇繼電器8， 與問鎖器9相連接，故與習知之選擇間Μ之輸出鄰近地 部分變少，如圖4之時序圖所示， ^ 8相異而損耗訊號的 響地精度良好地校正時序嗜差。 又/皮形的趨緩或雜訊的影 【0049】 °、 圖4中’（a)顯示由閂鎖器4 ，輸入至们接腳_其‘;^ 3閃鎖器4重定時之第2 _ _ 輸出的^⑷顯 2接腳PIN2其校正路經之閃錯哭 0波形’（〇顯不輸入至第 Ρί^ί】校正路徑之問鎖器9輸出的波形形’⑴顯示自第2接腳 2 PIN2 朗鎖器9構叙奴路 形在通過由邏輯閉Μ 的，響，被改善至實際應用輸，路之訊號損耗而趨緩 期時滯Tskw之校正。 …优文私度’而以高精度施行初 [0051J 人 —般而言，邏輯閘使用之城選擇，使用同—晶片之閑極而 12 201241948 訊號選擇者較能降低訊號間的時滯。 曰 數，一般為4至8CH。§CH以上的訊择1片之閘極的輪入通道 晶片的邏輯閘，其他晶片彼此之時滯此^ 4滯調整，經由各別之 【0052】 二旰恶化。 然而，一般而言，半導體測試裝 入元件，為自1對起多至4對之輸入，广對象係高速串列輸 在實質上不形成問題。 右至〉、具有8CH的時滯， 【0053】 伴隨近年的串列介面之高逮化 急速增加。然則，例如LCD驅動的1C測試 的S〇C測試機進行測定，必須有LCD雜動^專具用有;高速了〇 驅動測試機之10頻率無法追隨急遽的輸^但LCD 試困難的狀況。 頻率之向逮化，形成測 【0054】 有飽=:進展而出貨量亦 ===大，亦有無二^率 【0056】 冗护:投高==機犧獲得可 6 實麵巾，雖係對將複數之卿訊號產生單元，久 說Ϊ衣但本為爾之複數之訊號卡的例子進^ 【0058】 月不限疋於此，亦可組裝於半導體測試裝置。 13 201241948 此外，上述實施例中，雖對介由诖接 裝置之第i訊號產生部！與第2訊號產生部十2於^導^試 輸入至構成圖形訊號產生單元的加算器3之3、^=與必 不限於連接針，亦可介由例如連接哭輸入。1 2 3子進仃况明，但並 【0059】 〇〇 【0060] 子進行酬，但_ 3纽減相加的例 【圖式簡單說明】 【0034】 圖1顯示本發明之_ 降Η細圖4:=。。 之波费 H 兄明圖1的動作之時序圖。 14 1 6 2:為體!m裝置之-例的方塊圖。 ® 7(a)〜(e)說明圖 5 8 ° 的動作之波形圖。 【主要元件符號說明】 【0061】 1第1訊號產生部 2 第2訊號產生部 3 、13加算器 4'9閂鎖器 6'7開關 201241948 ίο 時脈產生部 11第3訊號產生部 12 第4訊號產生部 14 邏輯閘201241948 VI. Description of the invention: [Technical field to which the invention pertains] [_] The present invention relates to a semiconductor test device, in particular, to an improvement of high logic signal generation. [Prior Art] [0002] Conductor test device In one type, in order to self-contain the semiconductor test device, the relatively low frequency logic signal outputted by the enthalpy generating unit generates a higher output with a higher frequency of three copies as shown in FIG. The signal testing device of the early signal is a detachable card, and with each setting, the graphic signal generating unit will generate a plurality of signals from the signal enchant built in the semi-conductive, >j 5 type device. Si's logic shouted out. [0003] The semi-conductor ^, the ϊ2ϊ, the generating unit 1 and the second signal generating unit 2 are respectively provided in [0004], and the output signal is generated from the first signal generating unit 1 and the second signal generating unit 2, respectively. Ig: column: ^ plus 1 the frequency of these logic signals si and S2, the number S3 is the same as the high-speed logic D of 2 times the frequency. "Pushing the production of the series (4) B (lateh) 4 its data terminal [0005] from the semiconductor test device of the rainbow (four) coffee group. Hey, phase lock back 4 201241948 The clock of CU is flashed. In addition, pLL5 also sets the complex system for the group consisting of the number of signal cards of the number 2, and the data of the unit. Each of the signal cards constitutes a graphic signal product [0006] 6 is, followed by the switch unit Η阏 7, 士 recognize, + image (DUT) ' and generated by the formation of the graphic signal 7__ & (4) face fll f generated This is the correction path that is used for correction from each picture. The selection of the galvanic device 8 is output to the DUT with the timing error of ^2===================================================================== 4 The method of generating the system of the early 70 is connected with the switches 6, 7 [0008] The latch s8 is input to the timing of the clock CU provided in the semiconductor test device. The reference timing generating unit 10 of the body test device receives the signal φ of the wheel φ of the door lock 9 as a signal determining unit. . ~s, is taken out to a semiconductor test device not shown [0010] Fig. 6 is a display display grip. ^A description of the configuration of an example of a tree plant connected to a three-stage, and a complex switching timing diagram. In Fig. 7, (4) shows the first signal S2, (Ο I member shows the addition; = j 2 shows the respective signal s3 inside the output knocking parts 1 and 2 of the second signal generating unit 2. This time point, the signal head h The sequence block overlaps and appears directly in the input of the adder 3 201241948 The signal number s3〇(d) shows the re-timed flash locker 4^^, 5 input clock CXWe) [0012] Pull out 5il3 Tiger s4. In the composition of Fig. 5, -iin. τ- a time-frequency precision ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态 状态The two-dependent timing error 'Setting_4' is described in [From the 5 signal generation unit to generate a time difference (time lag) between the signals connected to the pin _ pin. Fruit ^ 3 3'' 9 Poetry Guide - ^, with a common correction path consisting of the selection - the 2' = ΐίΐ timing generation unit 10: the unsuccessful path of the exit path; 0. The time difference between the time and the depth is as follows (patent literature) [patent literature] [0016] technology (it 1 reveals the technique of time-delay adjustment of the output signal (graphic signal) [0017] [Document 1] JP-A-2008-145266 SUMMARY OF INVENTION [Problems to be Solved by the Invention] 6 201241948 [0018] Clock (1) [0019] Dry chicken is switched by A-speed: DUT measurement. cu t (4) The round-trip clock tsr-type timing error material 'can't be part 2' has a hysteresis ^ no transmission path, the transmission loss becomes larger, so sometimes [0021] the heart as shown in Figure 8 'transmission wheel' damage [0022 】 (b) Display the waveform of the first (first) pin 1 of the input (to), and the waveform of the correction path of the first pin; (4) the second pin of the re-timing of the flash lock 4; ^形 '(4) is stunned by its correction path _ _ 9 嶋 [ 嶋 f positive path of the coffee, the waveform of the output. ... 2 pin 201241948 In addition, these signals usually have noise overlap, so through the established logic signal When it is generated, the series becomes an indefinite interval. In this indefinite interval, it cannot be correctly compared with the f-time sequence. It is impossible to measure the time difference (time lag) Tskw. In the example of Fig. 8, the interval between the waveform of the first pin and the waveform of the second pin 2 of the retiming is smaller than the width of the initial time lag Tskw. Larger, it is impossible to correctly detect the condition of the original initial time lag Tskw. [0025] In order to solve these problems, an object of the present invention is to provide a frequency that can be output at a lower frequency than a system frequency of a semiconductor test device. The logic is instantaneously more edge-to-frequency, and a semiconductor with high precision timing accuracy is required. J §-type device. [Technical means for solving the problem] [0026] In order to achieve such a problem, the request of the present invention is requested. The invention is a semi-conducting residual test device, which is provided with a plurality of TM-shaped generating units and a graphic signal generating unit 7", which is to be self-built in the semiconductor measuring device, and the singularity of the singer is unified. The rib ^ is connected to Uhl "*. The output is formed by the latch that is introduced according to the retiming clock, and the switch that outputs the flash lock, the correction path, the correction of the self-lag, and the retracement pattern generation Unit The characteristic of the 5 hai semiconductor test device between the output signals outputted by 阙 is: ^ and drive 7, select the switch to establish the switch that is set up early, and the requested material, as described in item 1. The semiconductor test device is a regenerative unit's respective chest test device 8 201241948 [0028] The invention is as shown in claim 1, the semiconductor test device according to claim 1 They are each assembled in a semi-conducting test device. The invention requested in claim 4 is a digital image display device having a plurality of graphic signal generating units, and the complex i-components are pre-existing in the semiconductor. The output of the test device's signal output ^ is added by the addition of its secret signal number 11. This adder adds the _, and selectively outputs the _, and selectively outputs the —, and the calving feature is 'the re-determination of the temple By adding at least 2 systems of logic signals [0030] The invention requested in item 5 is the ΐϊ ΐϊ 戦 conductor 戦 ^, and the time-delay of the calibrated complex number is set to contain the logic, no The selection of each _ signal is linked to drive the selection Select the intended output signal. [Effects of the Invention] [0031] It is sufficient to generate a high-speed logic signal at a low cost, and it is also applicable to a semiconductor test device. Force J is willing to be used for the existing [0032] The day-to-day clock is repeated, and the edge interval and frequency can be changed instantaneously by adding at least 2 铋 漏. The system, and the first _« are produced, so [0033] ya, because the correction path towel does not have the loss of the big lion, such as the timing of the heart, so you can perform the correction of the South precision, to obtain high-precision timing precision ^ . [Embodiment] [Best Mode for Carrying Out the Invention] [0035] It is obvious that the difference between the present invention and FIG. 5 is that the use of the round-off logic is the same as the first one. 1 === (2) = PLL 5 of the generating section 12, == 5; and a retiming clock generating section constituted by a logic of 14 kg instead of the drawing [0036] The selection relay 8 of Fig. 5 is replaced with the inter-substance 14. Work 3 2 = Health Department 12 and Adder No. Card Group Sets the number of signals 13 output signal sl3, 侃 * ~ = homing object clock generation part of the adder _ 4 when the ^ is separately output to the set In the complex signal 7 _ 4 output signal S4, each through the opening [0038] - correction path system ^ ^ select relay 11 8 hidden New Zealand path, the complex output signal s, / pa1 1 σ number generated The unit outputs the flash locker 4 through the latch 4, and the logic gate selects only the linkage with the switches 6, 7 and tj; the way of outputting the signal to the bribe signal card, [0039] 轫 轫 14 之 于 于 山 山 山 山 山 山 山 山 山 山 山 山 山 山 山 山 山 山 山 山 山 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体[0041] News timing diagram. In Fig. 2, (1) shows the third signal s2, (e) shows H^ Sl, =) shows the output signal of the output of the second signal generating unit 2: two, the tiger 33, the third signal is displayed. Production Sl2, (1) display plus '13 to the signal generation unit 12 of the round signal lock 4 wheel out of the H round of the signal phase 3, (4) display retimed flash [0042] message ί 11 wheel out signal SU And the dry mountain pass of the fourth signal generating unit 12 is the timing error of the input of the early pure touch 1 U. This - α / : 2 1 (^. Wave ^ heavy ^ so there is no data phase number is still not qualified = ^ force: ^ ^ force ^ output of the re-timed pulse = r error of the timing of two ^ 2 In this way, there is no data on the data dependency timing error 3 as 'the trigger point τρ makes the logic:= detailed time 以 the timing is fine compared with case 2 Ϊ 。:.:: [_Γ wants the waveform, the lower part (nine) shows Example of actual waveform! S want ===, the time is better than the case = move to Ηι蜂 and migrate to the test [0045] In the actual waveform, there is overshoot, undershoot, and the waveform as shown in the figure. Real-time, and the migration time of the decline, after moving to the Lo level and after £, the inter-, ',, and 'an ideal waveform self-alignment [0046] from the back of the armband to the K-position quasi-migration On the one hand, the actual waveform of Case 2 is that the decrease from the Hi bit into the 'black second undershoot _ (four), the _ slave position 201241948 shifts, becomes the result of the L position from the lower case of the case 1 as the figure Show, compared with the case ,, then to the one-level migration. This life time difference. This time difference, become the data phase 値 値 } 1 1 1 1 1 1 1 1 1 1 1 _ _ The timing error is shown by I. In contrast, the time of the previous data is usually the rise of the level of the first one. When the data is dependent, the monthly condition becomes constant, ie, (4) of Figure 2 (7) The charm difference shown in the picture is no longer generated. In other cases, the data dependency timing error Ter no longer produces (〇1〇1) the path of the emotion, corrects the timing error such as time lag, etc. In the calibration path of the present invention shown in FIG. 1, the switching of each signal is performed by the logic gate 14. The selection of the relay 8 is connected to the locker 9, so that it is a conventional choice. The output of the inter-turn is less in the vicinity, as shown in the timing diagram of Figure 4, the difference between the sounds of the 8 and the loss signals is accurate and the timing is poor. 0049] °, in Figure 4 '(a) is displayed by the latch 4, input to the pin _ its '; ^ 3 flash lock 4 retimed 2 _ _ output ^ (4) display 2 pin PIN2 its Correcting the path of the flashing crying 0 waveform '(〇显不输入到第Ρ^^^) Correction path of the waveform of the output locker 9 output '(1) display The second pin 2 PIN2 locker 9 is in the form of a circuit that is closed by the logic, and is improved to the actual application, the signal loss of the road and the delay of the delay time Tskw. Degrees and the implementation of high precision [0051J people - in general, the choice of logic gates used, the use of the same - wafer idler 12 201241948 signal selector can reduce the time lag between the signals. 4 to 8CH. §CH above the gate of the gate of the transistor, the logic gate of the turn-in channel chip, the other chips are delayed by the delay of each other, and the two [0052] are worsened. However, in general, the semiconductor test loading component is input from up to four pairs from a pair, and the high-speed serial transmission of the wide object system does not substantially pose a problem. Right to 〉, with a time lag of 8CH, [0053] With the recent high-speed serialization of the serial interface, it has increased rapidly. However, for example, the LCD driver's 1C test S〇C tester must be used for LCD spurs. The high-speed 〇 drive tester's 10 frequency cannot follow the irritable input, but the LCD test is difficult. The frequency of the capture, the formation of the test [0054] full =: progress and the shipment is also === large, there are no two ^ rate [0056] redundancy: cast high == machine sacrifice can be 6 real face towel, Although it is for the plural signal generation unit, the example of the signal card that has been said for a long time but is a plural is entered into the [0058] month, and may be assembled in the semiconductor test device. 13 201241948 In addition, in the above embodiment, the i-th signal generating unit via the splicing device is provided! The second signal generating unit 12 is input to the adder 3 constituting the graphic signal generating unit, and the ^= is not limited to the connecting pin, and may be input via, for example, a connection. 1 2 3 sub-introduction, but [0059] 〇〇 [0060] sub-remuneration, but _ 3 new de-addition example [schematic description] [0034] Figure 1 shows the _ Η Detail 4:=. . The wave diagram of the action of H brother Ming Figure 1. 14 1 6 2: block diagram of the -m device - example. ® 7(a) to (e) illustrate the waveform diagram of Figure 8 8 ° action. [Description of main component symbols] [0061] 1 first signal generating unit 2 second signal generating unit 3, 13 adder 4'9 latch 6'7 switch 201241948 ίο clock generating unit 11 third signal generating unit 12 4 signal generation unit 14 logic gate