TW201240033A - Method for mold array process to encapsulate substrate sides - Google Patents

Method for mold array process to encapsulate substrate sides Download PDF

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Publication number
TW201240033A
TW201240033A TW100108994A TW100108994A TW201240033A TW 201240033 A TW201240033 A TW 201240033A TW 100108994 A TW100108994 A TW 100108994A TW 100108994 A TW100108994 A TW 100108994A TW 201240033 A TW201240033 A TW 201240033A
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Taiwan
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substrate
units
substrate units
wafers
strip
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TW100108994A
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Chinese (zh)
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TWI455261B (en
Inventor
Kuo-Yuan Lee
Yung-Hsiang Chen
Wen-Chun Chiu
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Walton Advanced Eng Inc
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Publication of TWI455261B publication Critical patent/TWI455261B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

Disclosed is a method for mold array process to encapsulate substrate sides. A plurality of substrate units in a substrate strip are arranged in an array. There is a cutting line defined between the substrate units and on the periphery of the array. A pre-cutting slot is formed along the cutting line with a width greater than the corresponding cutting line. An encapsulant is formed on the substrate strip to continuously cover the substrate units and the cutting lines and further to fill in the pre-cutting slot so that the sides of the substrate units are encapsulated. After the singulation step to form individual semiconductor packages, the cut sides of the substrate units are still encapsulated by the encapsulant. There can be solved the exposed issue of plating circuits in the substrate units to promote the moisture resistance of the semiconductor package.

Description

201240033 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置之封裝製造技術，特別係 有關於一種包覆基板側邊之模封陣列處理方法。 【先前技術】 傳統在半導體封裝技術中基於成本考量與量產需求 普遍採用模封陣列處理（Mold Array Process，Map)製 程。以一基板條（substrate strip)作為多個晶片之載體， 基板條包含有複數個排列成一矩陣之基板單元，在經過 設置晶片、電性連接等半導體封裝作業後’一形成面積 大於矩陣之模封膠體係連續覆蓋基板單元及基板單元之 間的切割道，再沿著切割道進行單體化切割，便可製得 複數個半導體封裝構造。 第1圖為一種利用模封陣列處理製得之習知窗口球 格陣列型態之半導體封裝構造，第2圖為模封陣列處理 中所使用之基板條。如第丨圖所示，習知半導體封裝構 造100係主要包含一基板單元113、一晶片12〇、一封膠 體130。該晶片120係設置於該基板單元113之上表面 in。如為窗口球格陣列型態時，該基板單元113更具有 -貫穿上表面U1與下表面112之中央槽孔ιΐ7，並且 位於該晶片120之主動面121之複數個電極122係對準 於該中央槽孔117 β。該晶片12〇係常見地藉由複數個 打線形成之銲，線150通過該中央槽?L "7電性連接該些 電極122至該基板單元113。而該封膠體i3Q係形成於 201240033 該基板單元113之該上表面1U上與該中央槽孔ιΐ7 内’以密封該晶片120與該些銲線150，並且該基板單 元113之該下表面112係可設有複數個銲球16〇，以作 為該半導體封裝構造1 〇〇對外電性連接之端子。然而依 目前習知模封陣列處理技術，該封膠體130係無法覆蓋 至該基板單元113之側邊116,不可避免地造成該基板 單凡113内部的核心層與金屬線路外露，使得水氣容易 入侵到封裝内部，導致產品可靠度不佳。 如第2圖所示’上述的基板單元丨13在習知模封陣列 處理過程中係為多個一體形成並呈矩陣排列在一習知基 板條110内。在相鄰基板單元113之間與周邊係定義有 複數個縱橫交錯的切割道114。配合參閱第i圖，在黏 晶與電性連接之後，上述的封膠體130為模封形成並連 續地覆蓋在該些基板單元113與該些切割道114上。而 在每一基板單元113之間的切割道114在製程後段必須 被移除，以達到單體化分離，故基板條丨〗〇之切割道i工4 部位與在該些切割道U4上的封膠體不會存在於最終的 封裝產品内。當依據該些切割道114切離該基板單元113 時，會同時切穿該封膠體130與該基板條11〇，使得該 基板單元113具有切齊於該封膠體13〇被切侧面之顯露 側邊116,即該基板單元113之侧邊116無法被該封膠 體130保護。因此，在單體化分離之後，該基板單元ιι3 之侧邊11 6的電鍍線路與核心層會呈現外露狀態，導致 耐濕性較差，且易受到外界異物之干擾。此外，在單體[ 4 201240033 化分離過程中切宅丨工目# ° 具各易拉扯或是破壞到位於該基板 單元113的周邊線路 ^^ 而造成後續的不良影響。 【發明内容】 有赛於此，本發明少+ φ。h 之主要目的係在於提供一種包覆基 板侧邊之模封陣列處理方法，利用基板條具有特定預切 槽孔之型態’解決f知模封陣列處理方法中基板側邊外 露的門題彳避免在單體化分離過程—切割到基板單元 内部之線路’並防止基板單元之電鍵線路外露，進而提 升半導體封裝構造的耐濕性。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種包覆基板侧邊之模封陣列 處理方法，包含：提供一基板條，係具有複數個排列成 一 N乘以Μ矩陣之基板單元，每一基板單元的尺寸係對 應於一半導體封裝構造，在相鄰基板單元之間與該矩陣 之周邊係各定義有一切割道’並且在相鄰基板單元之間 與該矩陣之周邊係形成有一寬度大於對應切割道之預切 槽孔’使該些基板單元之側邊呈内凹地顯露於該些預切 槽孔内。設置複數個晶片至該些基板單元上。電性連接 該些晶片至對應之該些基板單元。模封形成一封膠體於 該基板條上’以連續地覆蓋在該矩陣内之該些基板單元 以及該些切割道，使該封膠體填入至該些預切槽孔内， 以更覆蓋該些基板單元之侧邊。以切割方式移除在該些 切割道處之該封膠體，以單體化分離該些基板單元為個 別的半導體封裝構造，並且在切割後該些基板單元之側丨 201240033 邊係仍被該封膠體所包覆。 本發明的目的及組玉廿 叹解決其技術問題還可採用以 措施進一步實現。 在前述的模封+ 歹J處理方法中，該基板條在每—基 單元内可另形成有一中 中央槽孔，在設置該些晶片之步驟 中，該些晶片之生命 動面係貼附至該基板條，並且該些晶 片之複數個電極係齄霞 货、顯露在該中央槽孔内。 在前述的模封陳功丨_ 玎早列處理方法中，所述的電性連接該些 晶片與該些基板單元之牛 疋之步驟係可包含以打線方式形成複 數個鲜線，該此链始总丄 二鲜線係經由該些中央槽孔連接該些晶片 與該些基板單元。 在前述的模封陣列處理方法中，所述的電性連接該些 晶片與該些基板單元之步驟係可包含以該基板條之複數 個内引線通過該些中央槽孔接合至該些晶片之複數個電 極0 在前述的模封陣列處理方法中，在所述的模封形成步 驟之前，可另包含之步驟為：貼附一保護膠帶於該基板 條之下表面。 在前述的模封陣列處理方法中，該基板條在該些基板 單凡的角隅係可形成有一十字連接條，以對角線方式連 接該些基板單元，並使該些預切槽孔不相互連通。 在前述的模封陣列處理方法中，在所述的模封形成步 驟之後與在所述的單體化分離步驟之前，可另包含之步 驟為：形成複數個銲球於該些基板單元之下表面。 201240033 i 在前述的模封陣列處理方法中，該封膠體所切割移除 - 之間隙寬度係可相同於該些切割道之寬度。 由以上技術方案可以看出，本發明之包覆基板側邊之 模封陣列處理方法’具有以下優點與功效： 一、可藉由在相鄰基板單元之間與矩陣之周邊形成寬度 大於對應切割道之預切槽孔作為其中之一技術手 段’由於封膠體係填入預切槽孔内，而更覆蓋基板 單元之側邊，並且在切割後基板單元之側邊仍被封 膠體所包覆《因此，在單體化分離步驟時，只會切 穿封裝材料，不會切到基板結構，解決習知模封陣 列處理方法中基板側邊外露的問題，可避免基板單 元周邊之金屬線路與核心層外露，進而使封裝產品 達到抗氧化、抗濕氣及對抗其它環境侵害的作用， 並提升半導體封裝產品的耐用度。 了藉由MAP製程中封膠體填入寬度大於對應切割道 之預切槽孔作為本發明之其中一技術手段，在模封 陣列處理之單體化分離步驟中不會切到基板結構， 避免單體化分離步驟的厚切割應力作用於基板而造 成内部線路變形或位移。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 201240033 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種包覆基板側邊之 模封陣列處理方法舉例說明於第3圖繪示其所製成的半 導體封裝構造之截面示意圖、第4A1 4F圖之各步驟中 元件截面示意圖以及第5圖繪示其基板條之局部上視 圖。詳細說明如下。 首先，請參閱第4A與5圖所示，提供一基板條21〇, 係具有複數個基板單元212,其係在製程中為該基板條 210内部之一體連接部分並在製程後為保留於半導體封 裝構造内的基板部位，用以承載與電性連接晶片。其中 該些基板單元212係排列成一 N乘以M之矩陣2ιι。如 第5圖所示，N為2,M為3,由多個基板單元構成μ 矩陣型態，僅是為了便於理解而減少1^與]^的數目。在 一實際產品中，Ν可為5，而μ可為8，以構成5χ8矩 陣型態，其中^^與Μ值的選擇係可適當的調整，以符合 不同種類之自動組裝設備的要求◊詳細而言，通常該基 板條210係為一印刷電路板並設有單面或雙面電性導通 之金屬線路。該基板條210亦可為一軟性電路薄膜或陶 瓷電路板。該基板條210的核心層材料係可選用高分子 樹脂材料，例如：FR-4環氧樹脂（FR_4 ep〇xy)。或者， 為了適合特殊應用需求，亦可選用其它高性能的樹脂材丨 201240033 •料例如.聚亞醯胺（PI)樹脂、三氮雜苯雙馬來醯亞胺（ΒΤ) • 樹月曰此外，當適用於窗口球栅陣列封裝類型，該基板 條210在每一基板單元212内可另形成有一中央槽孔 ，、係對準在該些基板單元212之中央部位，並且該 些中央槽孔215係由該基板條21〇之上表面216貫穿至 下表面217，用以作為打線連接之通道，以適用於窗口 型球格陣列封裝。此外，在相鄰基板單元212之間與該 矩陣211之周邊係各定義有一切割道如第3與$ 圖所示，該矩陣211之每一基板單元212的尺寸係具體 界疋為對應於一半導體封裝構造2〇〇，即第4Α圖與第$ 圖之基板單元212在兩平行切割道213之間之一寬度係 相同於第3圖半導體封裝構造2〇〇之同一截面方向之寬 度。並且，在相鄰基板單元212之間與該矩陣211之周 邊係形成有一寬度大於對應切割道2丨3之預切槽孔 214,使該些基板單元212之側邊212Α呈内凹地顯露於 該些預切槽孔214内《也就是說’在一完整且未切割的 基板條210中，該些預切槽孔214之兩側係作為相鄰的 基板單元212的侧邊212Α。在一較佳型態中，該些預切 槽孔214之寬度係為該些切割道213之寬度的i 2至2 倍’可與該些中央槽孔215在同一成孔步驟中形成。較 佳地’該基板條210在該些基板單元212的角隅係可形 成有一十字連接條218’以對角線方式連接該些基板單 元212，並使該些預切槽孔214不相互連通。所稱之「對 角線方式連接」係指每一十字連接條2 1 8之十字端部連F ^ 9 201240033 接於該些基板單元212之角隅並對準該些基板單元212 之對角線，使得該些十字連接條21 8能夠以最小連接面 積的方式連接相鄰的基板單元》 接著，請參閱第4B圖所示，設置複數個晶片22〇至 該些基板單元2 12上，例如可以利用既有的黏晶操作達 成。詳細而言，該些晶片220係可為形成有積體電路 (integrated circuit，1C)之半導體元件，例如：記憶體晶 片、邏輯晶片及特殊應用晶片等等’可由一晶圓分割而 成。該些晶片220之主動面221係可具有複數個電極 222，作為該些晶片220傳輸内部訊號至外界的端點。通 常該些電極222係為鋁或銅材質之銲墊，或可為突出於 該些主動面221之導電凸塊。該些電極222係可設置於 該些晶片22〇之該些主動面之單一側邊、兩對應侧 邊、四周側邊或是中央位置。通常該些晶片22〇係設置 於對應基板單元212内的中央位置。在本實施例中，每 基板單元上212皆設有一晶片220，但不受限定地， 亦可應用至多晶片堆疊之封裝，在每一基板單元2 12上 可疊複數個晶片。在本實施例中，在設置該些晶片2 2 〇 之步驟中，該些晶>} 220之主動面221係貼附至該基板 條210，並且該些晶片220之該些電極222係顯露在該 中央槽孔215内。在一較佳型態中，每—晶片22〇與對 應基板單元2 12之間係可設有一黏晶枯料2 2 3，用以 接合該些晶片220與該些基板單元212。一般而言，該 黏阳材料223係可預先塗佈於該基板條21〇之上表面【 10 201240033 216’或者是預先形成於該些晶片220之主動面221，但 不覆蓋位於該主動面221中央之該些電極222。該黏晶 材料223係可為一雙面Ρϊ膠帶、液態環氧膠、預型片、 Β階黏膠（B-stage adhesive)或是晶片貼附物質（Die Attach Material，DAM)，以黏接該些晶片220至該些基 板單元212上。 請參閱第4C圖所示’電性連接該些晶片220至對應 之該些基板單元212。在本實施例中，所述的電性連接 該些晶片220與該些基板單元212之步驟係可包含以打 線方式形成複數個銲線240，該些銲線240係經由該些 中央槽孔215連接該些晶片220與該些基板單元212内 部線路之接指。其中’由於該些銲線240之一部分係可 隱藏於該些中央槽孔215之内，使得該些銲線24〇之打 線線弧突出於該基板條210之下表面217的高度降低， 進而減少了整體封裝厚度。該些銲線24〇係可利用打線 製程所形成之金屬細線，其材質可為金、或是採用類似 的南導電性的金屬材料（例如銅或銘），可利用該此鲜線 240係作為該些晶片220至該些基板單元212之間的訊 號傳遞與接地/電源的連接。然不受限地，該些晶片22〇 除了可以打線電性連接之外，亦可以覆晶接合（fUp Ah bonding)、引腳接合（leadbond)或是其它已知電性連接方 式完成該些晶片220與該些基板單元212之電性互連。 之後，請參閱第4D圖所示，模封形成一封膠體23〇 於該基板條210上，以連續地覆蓋在該矩陣2ΐι内之該丨 201240033 些基板單元212以及該些切割道213，使該封膠體23 0 填入至該些預切槽孔214内，以更覆蓋該些基板單元212 之側邊212A。請配合參酌第5圖所示，位於該基板條 2 10内的斜線部位即為模封區域，相當或大於該矩陣 2 11，在模封過程中呈現流動態之封膠體230會主動地填 滿於該些預切槽孔214内，直到完全包覆該些基板單元 2 1 2之侧邊2 1 2A。此外，該封膠體23〇係可更填入至該 些中央槽孔215内’而經由該些中央槽孔215突出於該 基板條210之下表面217且包覆該些銲線240，進而保 護該些銲線240不會受到外界的干擾與損害。但不受限 定地’該些晶片220亦可為裸晶型態而顯露出該些晶片 220之背面以利散熱。具體而言，該封膠體23〇係可為 一環氧模封化合物（epoxy molding c〇mp〇und，EMC)，通 常具有絕緣性與熱固性。該封膠體23〇係能以轉移成型 (transfer molding)或稱壓模的技術加以形成或者該封 膠體230亦可使用其他已知的模封製程形成，例如壓縮 模封、使用一模具之印刷或喷塗等等。 請參閱第4E圖所示，在所述的模封形成步驟之後 在所述的單體化分離步驟之前，可另形成複數個鲜 250於該些基板單元212之下表面2丨7,以作為半導體封 裝構k對外電性連接之通道。在一較佳實施例中，該些 銲球250之材質係可為錫膏或其它適當的無鉛材料。該 些銲球250係可呈柵狀陣列排列，使相同單位面積之基 板單元2U可以容納更多輸人/輸出連接端⑽ 12 201240033201240033 VI. Description of the Invention: [Technical Field] The present invention relates to a package manufacturing technique for a semiconductor device, and more particularly to a method of processing a package array on the side of a coated substrate. [Prior Art] Traditionally, based on cost considerations and mass production requirements in semiconductor packaging technology, the Mold Array Process (Map) process is commonly used. A substrate strip is used as a carrier for a plurality of wafers, and the substrate strip comprises a plurality of substrate units arranged in a matrix, and after forming a semiconductor package operation such as a wafer or an electrical connection, a molding layer having a larger area than a matrix is formed. The glue system continuously covers the scribe line between the substrate unit and the substrate unit, and then singulates along the scribe line to obtain a plurality of semiconductor package structures. Fig. 1 is a conventional semiconductor package structure of a conventional window grid array obtained by a mask array process, and Fig. 2 is a substrate strip used in a mold array process. As shown in the figure, the conventional semiconductor package structure 100 mainly includes a substrate unit 113, a wafer 12, and a gel 130. The wafer 120 is disposed on the upper surface of the substrate unit 113. The substrate unit 113 further has a central slot ι 7 extending through the upper surface U1 and the lower surface 112, and a plurality of electrodes 122 located on the active surface 121 of the wafer 120 are aligned with the window array pattern. Central slot 117 β. The wafer 12 is commonly formed by a plurality of wires, and the wire 150 electrically connects the electrodes 122 to the substrate unit 113 through the central slot L " The encapsulant i3Q is formed on the upper surface 1U of the substrate unit 113 and the central slot ΐ7 in 201240033 to seal the wafer 120 and the bonding wires 150, and the lower surface 112 of the substrate unit 113 is A plurality of solder balls 16 可 may be provided to serve as terminals for externally electrically connecting the semiconductor package structure 1 . However, according to the conventional masking array processing technology, the encapsulant 130 cannot cover the side 116 of the substrate unit 113, which inevitably causes the core layer and the metal line inside the substrate to be exposed, so that moisture is easily invaded. Inside the package, resulting in poor product reliability. As shown in Fig. 2, the substrate unit 13 described above is integrally formed in a conventional matrix array process and arranged in a matrix in a conventional substrate strip 110. A plurality of criss-crossing dicing streets 114 are defined between adjacent substrate units 113 and the peripheral system. Referring to FIG. i, after the adhesion and electrical connection, the above-mentioned encapsulant 130 is formed by molding and continuously covers the substrate unit 113 and the dicing streets 114. The scribe line 114 between each substrate unit 113 must be removed in the latter part of the process to achieve singulation separation, so that the slabs of the slabs and the slabs on the scribe lines U4 The sealant will not be present in the final packaged product. When the substrate unit 113 is cut away according to the dicing lines 114, the sealing body 130 and the substrate strip 11 切 are cut through at the same time, so that the substrate unit 113 has the exposed side of the sealed side of the sealing body 13 The side 116, that is, the side 116 of the substrate unit 113 cannot be protected by the encapsulant 130. Therefore, after the singulation separation, the plating line and the core layer of the side edge 116 of the substrate unit ι are exposed to an exposed state, resulting in poor moisture resistance and being easily interfered by external foreign matter. In addition, in the monomer [4 201240033 separation process, the cut housework #° has easy to pull or break to the peripheral circuit ^^ located in the substrate unit 113, causing subsequent adverse effects. SUMMARY OF THE INVENTION In this case, the present invention is less + φ. The main purpose of h is to provide a method for processing a package array on the side of a coated substrate, which utilizes a pattern of a specific pre-cut slot of the substrate strip to solve the problem of the exposed side of the substrate in the method of processing the array. Avoiding the singulation process—cutting the line to the inside of the substrate unit' and preventing the key line of the substrate unit from being exposed, thereby improving the moisture resistance of the semiconductor package structure. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a method for processing a patterned array on a side of a coated substrate, comprising: providing a substrate strip having a plurality of substrate units arranged in an N by a matrix, each substrate unit having a size corresponding to a semiconductor package Constructing a scribe line between each adjacent substrate unit and the periphery of the matrix and forming a pre-cut slot having a width greater than the corresponding scribe line between adjacent substrate units and the periphery of the matrix The side edges of the substrate units are concavely exposed in the pre-cut slots. A plurality of wafers are disposed on the substrate units. The wafers are electrically connected to the corresponding substrate units. Forming a gel on the substrate strip to continuously cover the substrate units in the matrix and the dicing lines, so that the encapsulant is filled into the pre-cut slots to cover the The sides of these substrate units. Removing the encapsulant at the dicing lines in a dicing manner to singulate the substrate units into individual semiconductor package structures, and after the dicing, the sides of the substrate units are still sealed by the 201240033 side Coated with a gel. The object and group of the present invention solve the technical problems and can be further implemented by measures. In the foregoing method of processing the mold + 歹J, the substrate strip may be further formed with a central central slot in each of the base units. In the step of disposing the wafers, the living surface of the wafers is attached to The substrate strips, and the plurality of electrodes of the plurality of wafers are exposed in the central slot. In the foregoing method of modulating the gong 玎 玎 玎 , , , , , , , 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤 步骤The second fresh line connects the wafers and the substrate units via the central slots. In the foregoing method of processing a package array, the step of electrically connecting the wafers and the substrate units may include bonding a plurality of inner leads of the substrate strip to the wafers through the central slots. The plurality of electrodes 0. In the foregoing method of processing the mold array, before the step of forming the mold, the method further comprises the step of: attaching a protective tape to the lower surface of the substrate strip. In the foregoing method for processing a sealed array, the substrate strip may be formed with a cross connecting strip on the substrate, and the base unit may be connected diagonally, and the pre-cut slots are not Connected to each other. In the foregoing method of processing a sealed array, after the step of forming the mold and before the step of separating the singulation, the method further comprises the steps of: forming a plurality of solder balls under the substrate unit surface. 201240033 i In the foregoing method of processing a sealed array, the gap width of the encapsulant is removed - the gap width may be the same as the width of the dicing streets. It can be seen from the above technical solution that the method for processing the encapsulated array on the side of the coated substrate of the present invention has the following advantages and effects: 1. The width can be formed by the width between the adjacent substrate units and the periphery of the matrix. The pre-cut slot of the track is one of the technical means' because the sealing system fills the pre-cut slot and covers the side of the substrate unit, and the side of the substrate unit is still covered by the sealant after cutting. Therefore, in the singulation separation step, only the encapsulation material is cut through, and the substrate structure is not cut, and the problem of the exposed side of the substrate in the conventional mold-sealing array processing method is solved, and the metal line and the core layer around the substrate unit can be avoided. Exposed, which in turn makes the packaged product resistant to oxidation, moisture and other environmental insults, and enhances the durability of semiconductor package products. As a technical means of the present invention, the pre-cut slot having a width larger than the corresponding scribe line is filled in the MAP process, and the substrate structure is not cut in the singulation separation step of the mold array processing, avoiding the single The thick cutting stress of the bulk separation step acts on the substrate to cause internal line deformation or displacement. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. Only the components and combinations related to this case are displayed. The components shown in the figure are not drawn in proportion to the number, shape and size of the actual 201240033 implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to a first embodiment of the present invention, a method for processing a package array on the side of a coated substrate is illustrated in FIG. 3, which is a schematic cross-sectional view of a semiconductor package structure and a step of the fourth embodiment. A cross-sectional view of the component and a fifth diagram depict a partial top view of the substrate strip. The details are as follows. First, as shown in FIGS. 4A and 5, a substrate strip 21 is provided, which has a plurality of substrate units 212 which are connected to the inside of the substrate strip 210 during the process and remain in the semiconductor after the process. A substrate portion within the package structure for carrying and electrically connecting the wafer. The substrate units 212 are arranged in a matrix of N times M matrix 2 ιι. As shown in Fig. 5, N is 2 and M is 3, and the μ matrix type is constituted by a plurality of substrate units, and the number of 1^ and ^^ is reduced only for the sake of easy understanding. In an actual product, Ν can be 5, and μ can be 8 to form a 5 χ 8 matrix type, wherein the selection of ^ and Μ values can be appropriately adjusted to meet the requirements of different types of automatic assembly equipment. In general, the substrate strip 210 is a printed circuit board and is provided with a single-sided or double-sided electrically conductive metal line. The substrate strip 210 can also be a flexible circuit film or a ceramic circuit board. The core layer material of the substrate strip 210 may be a polymer resin material such as FR-4 epoxy resin (FR_4 ep〇xy). Alternatively, in order to meet the needs of special applications, other high-performance resin materials can be used. 201240033 • Materials such as poly-liminamide (PI) resin, triaza-benza-bis-imine (imine) • The substrate strip 210 may be further formed with a central slot in each of the substrate units 212, and is aligned with a central portion of the substrate units 212, and the central slots are applicable to the window ball grid array package type. The 215 is penetrated from the upper surface 216 of the substrate strip 21 to the lower surface 217 for use as a channel for wire bonding to be suitable for a window type ball grid array package. In addition, a scribe line is defined between the adjacent substrate units 212 and the periphery of the matrix 211, as shown in the third and third figures. The size of each of the substrate units 212 of the matrix 211 is specific to one. The semiconductor package structure 2, that is, the substrate unit 212 of the fourth and third figures has a width between the two parallel dicing streets 213 which is the same as the width of the semiconductor package structure 2 of the third embodiment. And a pre-cut slot 214 having a width larger than the corresponding scribe line 2丨3 is formed between the adjacent substrate units 212 and the periphery of the matrix 211, so that the side edges 212 of the substrate units 212 are concavely exposed. Within the pre-cut slots 214, that is, in a complete and uncut substrate strip 210, the sides of the pre-cut slots 214 act as side edges 212 of adjacent substrate units 212. In a preferred embodiment, the pre-cut slots 214 have a width i 2 to 2 times the width of the scribe lines 213 and may be formed in the same hole forming step as the central slots 215. Preferably, the substrate strip 210 may be formed with a cross connecting strip 218 ′ in a corner of the substrate unit 212 to diagonally connect the substrate units 212 , and the pre-cut slots 214 are not connected to each other. . The term "diagonal connection" means that the cross end of each of the cross-connecting strips 2 1 8 is connected to the corners of the substrate units 212 and aligned with the opposite corners of the substrate units 212. The wires are such that the cross-connecting strips 21 8 can connect adjacent substrate units with a minimum connection area. Next, as shown in FIG. 4B, a plurality of wafers 22 are disposed on the substrate units 2 12, for example It can be achieved by using the existing die bonding operation. In detail, the wafers 220 may be semiconductor elements formed with integrated circuits (1C), such as memory chips, logic chips, and special application wafers, etc., which may be divided by a wafer. The active surface 221 of the wafers 220 can have a plurality of electrodes 222 as the end points of the wafers 220 for transmitting internal signals to the outside world. Usually, the electrodes 222 are solder pads made of aluminum or copper, or may be conductive bumps protruding from the active faces 221 . The electrodes 222 can be disposed on a single side, two corresponding sides, a peripheral side or a central position of the active surfaces of the wafers 22 . Typically, the wafers 22 are disposed at a central location within the corresponding substrate unit 212. In this embodiment, a wafer 220 is disposed on each of the substrate units 212, but is not limited thereto, and may be applied to a package of a multi-wafer stack, and a plurality of wafers may be stacked on each of the substrate units 2 12 . In this embodiment, in the step of disposing the wafers 2 2 , the active surfaces 221 of the crystals are attached to the substrate strip 210 , and the electrodes 222 of the wafers 220 are exposed. In the central slot 215. In a preferred embodiment, a die bond 2 2 3 may be disposed between each wafer 22 and the corresponding substrate unit 2 12 for bonding the wafers 220 and the substrate units 212. In general, the viscous material 223 can be pre-applied to the upper surface of the substrate strip 21 [ 10 201240033 216 ′ or the active surface 221 formed on the wafer 220 in advance, but not covered by the active surface 221 . The electrodes 222 in the center. The adhesive material 223 can be a double-sided adhesive tape, a liquid epoxy adhesive, a pre-formed sheet, a B-stage adhesive or a Die Attach Material (DAM) for bonding. The wafers 220 are on the substrate units 212. Referring to FIG. 4C, the wafers 220 are electrically connected to the corresponding substrate units 212. In this embodiment, the step of electrically connecting the wafers 220 and the substrate units 212 may include forming a plurality of bonding wires 240 by wire bonding, and the bonding wires 240 are through the central slots 215. The wafers 220 are connected to the internal lines of the substrate units 212. Wherein, because a portion of the bonding wires 240 can be hidden in the central slots 215, the arcing of the bonding wires 24 protrudes from the lower surface 217 of the substrate strip 210, thereby reducing The overall package thickness. The wire bonding wires 24 can be formed by using a metal wire formed by a wire bonding process, and the material thereof can be gold or a similar south conductive metal material (for example, copper or inscription), and the fresh wire 240 can be used as the wire. The signal transfer between the wafers 220 and the substrate units 212 is connected to a ground/power source. However, the wafers 22 can be electrically connected by fray bonding, lead bonding, or other known electrical connections to complete the wafers. 220 is electrically interconnected with the substrate units 212. After that, as shown in FIG. 4D, a mold is formed on the substrate strip 210 to continuously cover the substrate unit 212 and the cutting channels 213 in the matrix 2? The encapsulant 230 is filled into the pre-cut slots 214 to cover the side edges 212A of the substrate units 212. Please refer to FIG. 5, the oblique line portion located in the substrate strip 2 10 is a molding area, which is equivalent to or larger than the matrix 2 11, and the encapsulant 230 exhibiting flow dynamics during the molding process is actively filled. In the pre-cut slots 214, until the side edges 2 1 2A of the substrate units 2 1 2 are completely covered. In addition, the encapsulant 23 can be further filled into the central slots 215, and protrudes from the lower surface 217 of the substrate strip 210 via the central slots 215 and covers the bonding wires 240 to protect the bonding wires 240. The bonding wires 240 are not subject to external interference and damage. However, the wafers 220 may also be in a bare crystalline form to expose the backside of the wafers 220 for heat dissipation. Specifically, the encapsulant 23 can be an epoxy molding compound (EMC), which is generally insulative and thermosetting. The encapsulant 23 can be formed by transfer molding or compression molding or the encapsulant 230 can be formed using other known molding processes, such as compression molding, printing using a mold, or Spray and so on. Referring to FIG. 4E, after the singulation forming step, a plurality of fresh 250 may be further formed on the lower surface 2丨7 of the substrate unit 212 as The semiconductor package structure is a channel for external electrical connection. In a preferred embodiment, the solder balls 250 are made of solder paste or other suitable lead-free material. The solder balls 250 can be arranged in a grid array so that the base unit 2U of the same unit area can accommodate more input/output connections (10) 12 201240033

Connection)以符合高度集積化（Integrati〇n)之半導體晶 片所需。然而不受限定地’在不同的實施例中，該些銲 球250亦可替換為錫膏、接觸墊或接觸針。 請參閱第4F圖所示’以切割方式移除在該些切割道 213處之該封膠體23〇,以單體化分離該些基板單元212 為個別的半導體封裝構造200，由於該些預切槽孔214 之寬度係大於該些切割道213，故可避免在單體化分離 過程中直接切割到該些基板單元2 1 2，並且在切割後該 些基板單元212之側邊21 2A係仍被該封膠體230所包 覆。在已完成封裝之該些基板單元212由該基板條210 單體化分離之後，即可得到個別的半導體封裝構造 200(如第3圖所示）。請配合參酌第4e與4F圖所示，該 封膠體230所切割移除之間隙寬度s係可相同於該些切 割道2 1 3之寬度W ’所以在該封膠體2 3 0切割之後，仍 可使該封膝體230包覆於該些基板單元212之側邊 212A。在模封陣列處理之單體化分離步驟中不會切到基 板結構’避免單體化分離步驟的厚切割應力作用於該基 板條210而造成内部線路變形或位移。 在本發明中’可藉由在相鄰之該些基板單元212之間 與該矩陣211之周邊形成寬度大於對應該些切割道213 之預切槽孔214作為其中之一技術手段，由於該封膠體 230係填入該些預切槽孔214内，而更覆蓋該些基板單 元2 1 2之側邊2 1 2 A，並且該些預切槽孔2 1 4之寬度係大 於該些切割道2 1 3之寬度，故當切割刀具依據該些切割[ 13 201240033 道213切穿該封膠體2 _ u 時，可避免切割刀具直接切割 到該些基板單元212内邱夕始杜 °卩之線路。此外，由於在切割後 ^基板單元212之側邊2以仍被該封膠體23〇所包 ，故解決習知模封陣列處理製程中基板側邊外露的問 題’能防止該些基板單元212内部的電链線路與核心層 外露，進而提升半導體封裝構造的耐渴性。 依據本發明之第二具體實施例，另一種包覆基板側邊 之模封陣列處理方法舉例說明於第6A至圖各步驟中 元件之截面示意圖，用以說明本發明可適用於不同封裝 類型’其中主要元件與第一實施例相同者以相同符號標 示並不再詳予贅述。 睛參閱第6Α圖所示，提供一基板條21〇，係具有複 數個排列成一 Ν乘以Μ矩陣211之基板單元212。在本 實施例中，除了内部線路結構，該基板條2丨〇係可另具 有複數個内引線319，並顯露於該些基板單元212之中 央槽孔215内。該些内引線319係可為該基板條210内 部金屬線路層之延伸部份或由外附加的懸空内引線 (lead)，通常係為表面有電鍍層之銅線，可利用蝕刻銅箔 等的金屬箔或導電箔再經電鍍而形成，故具有可撓曲 性。在未電性連接之前，該些内引線319係可通過上述 之該些中央槽孔215而為騰空。 請參閱第6B圖所示，設置複數個晶片220至該些基 板單元212上’並使該些晶片220之主動面221朝向該 基板條210之上表面216 ’其中該些晶片220之複數個【 14 201240033 電極222係對準於對應之基板單元212之中央槽孔215。 請參閱第6C圖所示，藉由該基板條21〇之該些内引 線319通過該些中央槽孔215接合至該些晶片22〇之該 些電極222’所以不會有打線線弧突出於該基板條210 之下表面217’更加降低了整體的封裝厚度。可利用内 引腳壓合治具（ILB bonding head)打斷該些内引線319的 預斷點並使該些内引線319壓合接觸至該些晶片220之 該些電極222 ’而與該些晶片22〇達到訊號溝通之電性 連接。 請參閱第6D圖所示，較佳地可貼附一保護膠帶36〇 於該基板條210之下表面217，並緊密地封住該些中央 槽孔2 1 5與該些預切槽孔2 1 4之下方開口，以避免在後 續模封形成步驟中發生封膠體由該些中央槽孔215與該 些預切槽孔2 1 4溢流至基板條下表面之情況。 請參閱第6E圖所示，模封形成一封膠體230於該基 板條210上，以密封該些晶片220。該封膠體230係填 入至該些中央槽孔215與該些預切槽孔214内，並包覆 該些基板單元212之側邊212A。在模封形成步驟之後， 如第6F圖所示，由該基板條210之下表面217移除該保 護膠帶360。 請參閱第6G圖所示’形成複數個銲球25〇於該些基 板單元212之下表面217。之後’如第6H圖所示’單體 化分離該基板條210之該些基板單元212，進而形成為 個別的半導體封裝構造300。 [ 15 201240033 依據本發明之第三具體實施例’另一種包覆基板側邊 之模封陣列處理方法舉例說明於第7A至7G圖各步驟中 之元件截面示意圖，用以說明預切槽孔非必要形成於基 板條提供步驟’其中主要元件與第一實施例相同者以相 同符號標示並不再詳予贅述。 請參閱第7A圖所示，提供一基板條210，係具有複 數個排列成一 N乘以Μ矩陣211之基板單元212。請參 閱第7Β圖所示，設置複數個晶片22〇至該些基板單元 212’並使該些晶片220電性連接至該些基板單元212。 請參閱第7C圖所示，可貼附一切割膠帶470於該基板 條210之下表面217，用以承載該基板條21〇，並作為後 續切割承載之用。 請參閱第7D圖所示，形成該些預切槽孔214於該基 板條21 0。在本實施例中，可藉由切割刀具沿著該些切 割道213切割形成該些預切槽孔214於該些基板單元 212之周邊，並且由於該基板條210之下表面217設置 有該切割膠帶470，在形成該些預切槽孔214而切穿該 基板條2 1 0之後，仍可保持該些基板單元2 1 2在該切割 膠帶470上的固定位置而不散離，故使得該些預切槽孔 2 1 4係可相互連通。 請參閱7Ε圖所示，模封形成一封膠體230於該基板 條210上，以連續地覆蓋在該矩陣211内之該些基板單 元212與在該些基板單元212之間之該些預切槽孔 2 1 4，以密封該些晶片220。在模封形成步驟中，該封膠【 16 201240033 - 體230係填入至該些預切槽孔214内，以更覆蓋該些基 板單元212之側邊212A。 請參閱第7F圖所示，以切割方式移除在該些切割道 213處之該封膠體23〇，以單體化分離該些基板單元212 為個別的半導體封裝構造4〇〇，並且在切割後該些基板 單元212之側邊212A係仍被該封膠體23〇所包覆。在 單體化分離過程中，所使用之刀具並不會切穿該切割膠 帶470 ’以確保該切割膠帶47〇在切割後能發揮承栽該 些基板單元212之作用。之後，如第7f與7G圖所示， 移除該切割膠帶470之後，即可得到個別的半導體封裝 構造400。由於每一半導體封裝構造4〇〇皆個別獨立地 黏貼於該切割膠帶47〇上，故可輕易地由該切割膠帶47〇 上剝離該半導體封裝構造400。 X上所述’僅疋本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上，然而並非用以限定本發明，任何熟悉本項技 術者，在不脫離本發明之技術範圍内，所作的任何簡單 修改、#效性變化與修飾，均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第1圖種以習知模封陣列處理製造之半導體封裝構 造之截面示意圖。 第2圖：一種基板條之局部俯視示意圖。 第3圖：依據本發明之第一具體實施例的一種包覆基抝 17 201240033 御/it之模封陣列處理方法所製成之半導體封裝 構造之截面示意圖。 第4A至4F圖：依據本發明之第一具體實施例的包覆基 板側邊之模封陣列處理方法各步驟中之元件截 面示意圖。 第5圖.依據本發明之第__具體實施例的包覆基板側邊 之模封陣列處理方法繪示其基板條之局部上視 圖0 第6A至6H圖：依據本發明之第二具體實施例的另一種 包覆基板側邊之模封陣列處理方法各步驟中之 元件截面示意圖。 第7A至7G圖：依據本發明之第三具體實施例的另一種 包覆基板側邊之模封陣列處理方法各步驟中之 元件戴面示意圖。 【主要元件符號說明】 S封膠體切割移除之間隙寬度 W 切割道之寬度 100半導體封裝構造 110基板條 111 113基板單元 ι14 11 6側邊 117 120晶片 121 130封膠體 ι5〇 200半導體封裝構造 上表面 切割道 112 下表面 中央槽孔 主動面 122 電極 銲線 160 銲球 18 201240033 210 基板條 211 矩陣 212 基板單元 212A 側邊 213 切割道 214 預切槽孔 215 中央槽孔 216 上表面 217 下表面 218 十字連接條 220 晶片 221 主動面 222 電極 223 黏晶材料 230 封膠體 240 銲線 250 鲜球 300 半導體封裝構造 3 19 内引線 360 保護膠帶 400 半導體封裝構造 470 切割膠帶 19Connection) is required for semiconductor wafers that are highly integrated (Integrati). However, without limitation, in various embodiments, the solder balls 250 may be replaced with solder pastes, contact pads or contact pins. Referring to FIG. 4F, the encapsulant 23 在 at the dicing streets 213 is removed in a dicing manner to singulate the substrate units 212 into individual semiconductor package structures 200, due to the pre-cuts. The width of the slot 214 is larger than the scribe lines 213, so that the substrate unit 2 1 2 can be directly cut during the singulation separation process, and the side edges of the substrate units 212 are still 21 2A after cutting. It is covered by the sealant 230. After the substrate units 212 that have been packaged are singulated and separated by the substrate strips 210, individual semiconductor package structures 200 (as shown in Fig. 3) are obtained. Please refer to the 4th and 4F drawings, the gap width s of the sealing body 230 can be the same as the width W of the scribe lines 2 1 3, so after the sealing body 2 3 0 is cut, The sealing body 230 can be wrapped around the side edges 212A of the substrate units 212. The substrate structure is not cut in the singulation separation step of the mold array processing. The thick cutting stress that avoids the singulation separation step acts on the substrate strip 210 to cause internal line deformation or displacement. In the present invention, by forming a pre-cut slot 214 having a width larger than the corresponding scribe lines 213 between the adjacent substrate units 212 and the periphery of the matrix 211, as a technical means, The colloid 230 is filled into the pre-cut slots 214 to cover the side edges 2 1 2 A of the substrate units 2 1 2, and the widths of the pre-cut slots 2 1 4 are larger than the scribe lines. 2 1 3 width, so when the cutting tool cuts the sealing body 2 _ u according to the cutting [ 13 201240033 213, the cutting tool can be prevented from directly cutting into the substrate unit 212 . In addition, since the side 2 of the substrate unit 212 is still covered by the encapsulant 23〇 after the dicing, the problem of the exposed side of the substrate in the conventional stencil array processing process can be solved, and the internal electricity of the substrate unit 212 can be prevented. The chain line and the core layer are exposed, thereby improving the thirst resistance of the semiconductor package structure. According to a second embodiment of the present invention, another method of processing a package array on the side of a coated substrate exemplifies a cross-sectional view of the components in the steps of FIGS. 6A to illustrate that the present invention is applicable to different package types. The same components as those in the first embodiment are denoted by the same reference numerals and will not be described in detail. Referring to Figure 6, a substrate strip 21 is provided having a plurality of substrate units 212 arranged in a matrix multiplied by a germanium matrix 211. In this embodiment, in addition to the internal circuit structure, the substrate strip 2 can have a plurality of inner leads 319 and are exposed in the central slot 215 of the substrate unit 212. The inner leads 319 may be extensions of the inner metal circuit layer of the substrate strip 210 or external lead wires, which are usually copper wires with a plating layer on the surface, and may be etched with copper foil or the like. The metal foil or the conductive foil is formed by electroplating, so that it has flexibility. The inner leads 319 can be emptied through the central slots 215 described above prior to the electrical connection. Referring to FIG. 6B, a plurality of wafers 220 are disposed on the substrate units 212 and the active surfaces 221 of the wafers 220 are directed toward the upper surface 216 of the substrate strip 210. 14 201240033 The electrode 222 is aligned with the central slot 215 of the corresponding substrate unit 212. Referring to FIG. 6C, the inner leads 319 of the substrate strip 21 are bonded to the electrodes 222' of the wafers 22 through the central slots 215 so that no arcing of the wires is protruded. The lower surface 217' of the substrate strip 210 further reduces the overall package thickness. The pre-break points of the inner leads 319 can be broken by the ILB bonding head and the inner leads 319 can be pressed into contact with the electrodes 222 ′ of the wafers 220 and the wafers 22〇 The electrical connection to signal communication. Referring to FIG. 6D, a protective tape 36 is preferably attached to the lower surface 217 of the substrate strip 210, and the central slots 2 1 5 and the pre-cut slots 2 are tightly sealed. The opening below the lower portion of the substrate strip is prevented from overflowing from the central slots 215 and the pre-cut slots 2 14 to the lower surface of the substrate strip in the subsequent mold forming step. Referring to Figure 6E, a mold is formed on the substrate strip 210 to seal the wafers 220. The encapsulant 230 is filled into the central slots 215 and the pre-cut slots 214 and covers the side edges 212A of the substrate units 212. After the mold forming step, as shown in Fig. 6F, the protective tape 360 is removed from the lower surface 217 of the substrate strip 210. Referring to Fig. 6G, a plurality of solder balls 25 are formed to be formed on the lower surface 217 of the substrate unit 212. Thereafter, the substrate units 212 of the substrate strip 210 are singulated and separated as shown in Fig. 6H, and further formed into individual semiconductor package structures 300. [15 201240033 According to a third embodiment of the present invention, another method of processing a package array on the side of a coated substrate is illustrated in a cross-sectional view of the elements in the steps of FIGS. 7A to 7G for explaining the pre-cut slot. It is necessary to form the substrate strip providing step 'where the main elements are the same as those of the first embodiment, and the same reference numerals are used for the details. Referring to Figure 7A, a substrate strip 210 is provided having a plurality of substrate units 212 arranged in an N by Μ matrix 211. Referring to FIG. 7 , a plurality of wafers 22 are disposed to the substrate units 212 ′ and the wafers 220 are electrically connected to the substrate units 212 . Referring to Figure 7C, a dicing tape 470 can be attached to the lower surface 217 of the substrate strip 210 for carrying the substrate strip 21 〇 and used as a subsequent dicing load. Referring to Figure 7D, the pre-cut slots 214 are formed in the substrate strip 210. In the embodiment, the pre-cut slots 214 are cut along the scribe lines 213 by the cutting tool to the periphery of the substrate units 212, and the lower surface 217 of the substrate strip 210 is provided with the cut. The tape 470 can maintain the fixed position of the substrate unit 2 1 2 on the dicing tape 470 without being scattered after forming the pre-cut slots 214 and cutting through the substrate strip 210. The pre-cut slots 2 1 4 are interconnected. Referring to FIG. 7 , the mold is formed on the substrate strip 210 to continuously cover the substrate units 212 in the matrix 211 and the pre-cuts between the substrate units 212 . Slots 2 1 4 to seal the wafers 220. In the mold forming step, the sealant [16 201240033 - body 230 is filled into the pre-cut slots 214 to more cover the side edges 212A of the substrate units 212. Referring to FIG. 7F, the encapsulant 23〇 at the dicing streets 213 is removed in a diced manner to singulate the substrate units 212 into individual semiconductor package structures, and are cut. The side edges 212A of the substrate units 212 are still covered by the encapsulant 23〇. During the singulation process, the tool used does not cut through the dicing tape 470' to ensure that the dicing tape 47 is capable of functioning to support the substrate units 212 after cutting. Thereafter, as shown in Figures 7f and 7G, after the dicing tape 470 is removed, an individual semiconductor package structure 400 is obtained. Since each of the semiconductor package structures 4A is individually and independently adhered to the dicing tape 47, the semiconductor package structure 400 can be easily peeled off from the dicing tape 47. The above description of the preferred embodiments of the present invention is not intended to limit the scope of the present invention, and the present invention has been disclosed in the preferred embodiments. Any simple modifications, changes, and modifications made by the skilled person within the technical scope of the present invention are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a semiconductor package structure manufactured by a conventional mold-sealed array process. Figure 2: A partial top view of a substrate strip. Fig. 3 is a cross-sectional view showing a semiconductor package structure produced by a method of processing a packaged substrate according to a first embodiment of the present invention. 4A to 4F are schematic cross-sectional views showing the components in the respective steps of the method of processing the package substrate on the side of the cladding substrate according to the first embodiment of the present invention. 5 is a partial top view of a substrate strip according to a method of processing a package substrate on a side of a coated substrate according to a first embodiment of the present invention. FIGS. 6A to 6H are diagrams showing a second embodiment according to the present invention. Another cross-sectional view of an element in each step of the method for processing a package array covering the sides of the substrate. 7A to 7G are views showing a component wearing surface in each step of a method of processing a package array on the side of a coated substrate according to a third embodiment of the present invention. [Main component symbol description] S sealant cutting removal gap width W scribe line width 100 semiconductor package structure 110 substrate strip 111 113 substrate unit ι14 11 6 side 117 120 wafer 121 130 sealant ι5 〇 200 semiconductor package structure Surface cutting channel 112 lower surface central slot active surface 122 electrode bonding wire 160 solder ball 18 201240033 210 substrate strip 211 matrix 212 substrate unit 212A side 213 cutting channel 214 pre-cut slot 215 central slot 216 upper surface 217 lower surface 218 Cross connecting strip 220 wafer 221 active surface 222 electrode 223 die bonding material 230 sealing body 240 bonding wire 250 fresh ball 300 semiconductor package structure 3 19 inner lead 360 protective tape 400 semiconductor package structure 470 cutting tape 19

Claims (1)

201240033 七、申請專利範圍： 1、 一種包覆基板側邊之模封陣列處理方法，包含： 提供一基板條’係具有複數個排列成一 N乘以]VI矩 陣之基板單元，每一基板單元的尺寸係對應於一 半導體封裝構造，在相鄰基板單元之間與該矩陣 之周邊係各定義有一切割道，並且在相鄰基板單 元之間與該矩陣之周邊係形成有一寬度大於對應 切割道之預切槽孔’使該些基板單元之側邊呈内 凹地顯露於該些預切槽孔内； 設置複數個晶片至該些基板單元上； 電性連接該些晶片至對應之該些基板單元； 模封形成一封膠體於該基板條上，以連續地覆蓋在 該矩陣内之該些基板单元以及該些切割道，使該 封膠體填入至該些預切槽孔内，以更覆蓋該也基 板單元之側邊；以及 以切割方式移除在該些切割道處之該封膠體，以單 體化分離該些基板單元為個別的半導體封裂構 造，並且在切割後該些基板單元之側邊係仍被該 封膠體所包覆。 2、 根據申請專利範圍第1項之包覆基板側邊之模封陣 列處理方法，其中該基板條在每一基板單元内另形 成有一中央槽孔，在設置該些晶片之步驟中，該些 晶片之主動面係貼附至該基板條，並且該些晶片之 複數個電極係顯露在該中央槽孔内。 20 201240033 3根據申請專利範圍第2項之包覆基板側邊之模封陣 列處理方法，其中所述的電性連接該些晶片與該些 基板單元之步驟係包含以打線方式形成複數個銲 線’該些銲線係經由該些中央槽孔連接該些晶片與 該些基板單元。 4、 根據申請專利範圍第2項之包覆基板側邊之模封陣 列處理方法，其中所述的電性連接該些晶片與該些 基板單元之步驟係包含以該基板條之複數個内引線 通過該些中央槽孔接合至該些晶片之複數個電極。 5、 根據申請專利範圍第4項之包覆基板側邊之模封陣 列處理方法，在所述的模封形成步驟之前，另包含 之步驟為：貼附一保護膠帶於該基板條之下表面。 6、 根據申請專利範圍第i項之包覆基板側邊之模封陣 列處理方法，其中該基板條在該些基板單元的角隅 係形成有一十字連接條，以對角線方式連接該些基 板單元’並使該些預切槽孔不相互連通。 7、 根據申請專利範圍第i項之包覆基板側邊之模封陣 列處理在所述的模封形纟步驟之後與在所述 的單體化分離步驟之前’另包含之步驟為：形成複 數個銲球於該些基板單元之下表面。 8、 根據申請專利範圍第1項之包覆基板側邊之模封陣 列處理方法，其中該封膠體所切割移除之間隙寬度 係相同於該些切割道之寬度。 义 種包覆基板側邊之模封陣列處理方法，句冬· 21 201240033 模封形成一封膠體於一基板條上，以連續地覆蓋在 一矩陣内之複數個基板單元以及在該些基板單元 之間之複數個切割道’其中在相鄰基板單元之間 與該矩陣之周邊係形成有一寬度大於對應切割道 之預切槽孔’使該些基板單元之側邊呈内凹地顯 露於該些預切槽孔内，在所述的模封形成步驟 中，該封膠體係更填入至該些預切槽孔内，以更 覆蓋該些基板單元之側邊；以及 以切割方式移除在該些切割道處之該封膠體，以單 體化分離該些基板單元為個別的半導體封裝構 造’並且在切割後該些基板單元之側邊係仍被該 封膠體所包覆。 10、根據申請專利範圍第9項之包覆基板側邊之模封 陣列處理方法’在所述的模封形成步驟之前，另包 含之步驟為： δ又置複數個晶片至該些基板單元，並使該些晶片電 性連接至該些基板單元；以及 在設置晶片與電性連接步驟之後，形成該些預切槽 孔於該基板條。 1卜根據申請專利範圍第9項之包覆基板側邊之模封陣 列處理方法，在形成該些預切槽孔之前，另包含之 步驟為：貼附一切割膠帶於該基板條之下表面。 12、根據申請專利範圍第u項之包覆基板側邊之模封 陣歹j處理方法，其中該些預切槽孔係相互連通。r 22201240033 VII. Patent application scope: 1. A method for processing a package array on a side of a coated substrate, comprising: providing a substrate strip having a plurality of substrate units arranged in an N multiplied by a VI matrix, each substrate unit The dimension corresponds to a semiconductor package structure, a scribe line is defined between adjacent substrate units and the periphery of the matrix, and a width between the adjacent substrate units and the periphery of the matrix is formed to be larger than the corresponding scribe line. Pre-cutting the slot to make the sides of the substrate unit concavely exposed in the pre-cut slots; and providing a plurality of wafers to the substrate units; electrically connecting the wafers to the corresponding substrate units Forming a gel on the substrate strip to continuously cover the substrate units in the matrix and the dicing lines, so that the encapsulant is filled into the pre-cut slots to cover more The side of the substrate unit; and the encapsulant at the dicing streets are removed by dicing to separate the substrate units into individual semiconductor sealing structures And after dicing the substrate unit side of the plurality of lines are still coated with the encapsulant. 2. The method of processing a package array on the side of a coated substrate according to claim 1, wherein the substrate strip is further formed with a central slot in each of the substrate units, and in the step of disposing the wafers, The active surface of the wafer is attached to the substrate strip, and a plurality of electrode systems of the wafers are exposed in the central slot. The method for processing a packaged array on the side of a coated substrate according to claim 2, wherein the step of electrically connecting the wafers and the substrate units comprises forming a plurality of bonding wires by wire bonding The soldering wires connect the wafers and the substrate units via the central slots. 4. The method of processing a package array according to the second aspect of the patent application scope, wherein the step of electrically connecting the wafers and the substrate units comprises a plurality of inner leads of the substrate strip A plurality of electrodes are bonded to the plurality of electrodes through the central slots. 5. The method according to claim 4, wherein before the step of forming the mold, the method further comprises: attaching a protective tape to the lower surface of the substrate strip. . 6. The method of processing a package array according to the aspect of the invention, wherein the substrate strip forms a cross connecting strip at a corner of the substrate unit to diagonally connect the substrates The unit 'and the pre-cut slots are not in communication with each other. 7. The mold array array according to the side of the coated substrate according to item i of the patent application scope, after the step of forming the mold and before the step of separating the singulation, the steps further included: forming a plurality Solder balls are on the lower surface of the substrate units. 8. The method of processing a sealed array on the side of a coated substrate according to the first aspect of the patent application, wherein the gap width of the sealant is removed by the same width as the width of the cut streets. A method for processing a patterned array on the side of a coated substrate, Sentence 21 201240033, forming a gel on a substrate strip to continuously cover a plurality of substrate units in a matrix and on the substrate units a plurality of dicing streets between the adjacent substrate units and the periphery of the matrix forming a pre-cut slot having a width greater than the corresponding scribe line, such that the sides of the substrate units are concavely exposed to the sides In the pre-cut slot, in the molding forming step, the encapsulation system is further filled into the pre-cut slots to cover the sides of the substrate units; and removed in a cutting manner The encapsulant at the dicing streets separates the substrate units into individual semiconductor package structures by singulation and the side edges of the substrate units are still covered by the encapsulant after dicing. 10. The method for processing a packaged array on the side of a coated substrate according to claim 9 of the patent application scope, before the step of forming the mold, further comprising the steps of: δ placing a plurality of wafers to the substrate units, And electrically connecting the wafers to the substrate units; and forming the pre-cut slots in the substrate strip after the step of disposing the wafer and the electrical connection. According to the method for processing a package array on the side of a coated substrate according to claim 9 of the patent application, before the forming the pre-cut slots, the method further comprises: attaching a dicing tape to the lower surface of the substrate strip . 12. The method of processing a mask of a side of a coated substrate according to the scope of claim U, wherein the pre-cut slots are in communication with each other. r 22
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US7390688B2 (en) * 2005-02-21 2008-06-24 Casio Computer Co.,Ltd. Semiconductor device and manufacturing method thereof
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