TW201133757A - Semiconductor device having a conductive structure and method of forming the same - Google Patents

Abstract

A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern.

Description

.X 201133757 VI. INSTRUCTIONS: [RELATED APPLICATIONS] This application claims Korean Patent Application No. 2009-0046383 filed on May 27, 2009, and Korean Patent Application No. The priority of the present application is incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention An exemplary embodiment of the present invention relates to a semiconductor component having a conductive structure, and more particularly to a semiconductor component having a conductive structure in contact with a data storage component. [Prior Art] Data can be stored in a resistive memory device or read from a resistive memory device by applying heat to a predetermined position of a resistive memory device. To generate localized heating at predetermined locations on the resistive memory device, the resistive memory component can include a conductive structure that acts as a heating electrode. Therefore, there is a need for a conductive structure that provides high heating efficiency for resistive memory elements. SUMMARY OF THE INVENTION According to an exemplary embodiment of the present invention, a semiconductor device includes: an interlayer insulating layer 'disposed on a substrate, the interlayer insulating layer including an opening, the opening exposing the substrate; a barrier layer pattern, Arranging in the opening; and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending from the opening and a non-oxidizing portion located in the opening, wherein the conductive pattern The width depends on the thickness of the barrier pattern 4 201133757 layer. The width of the conductive pattern may be less than the width of the opening. The oxidized portion extending out of the opening may be thicker than the oxidized portion disposed in the opening. The width of the oxidized portion may be substantially the same as the width of the non-oxidized portion. The width of the oxidized portion may be greater than the width of the non-oxidized portion. The semiconductor device may further include a filling pattern disposed in the opening such that the conductive pattern is disposed between the barrier layer pattern and the filling pattern. The conductive pattern may have a cylindrical tube shape. The conductive pattern may comprise tungsten. The barrier layer pattern may include at least one of titanium or titanium nitride. The barrier layer pattern may include at least one of a nitride or an oxynitride. The oxidized portion of the conductive pattern may contact a phase change material film in a phase change random access memory (PRAM). The barrier layer pattern may be in contact with the barrier layer pattern P-N diode. The oxidized portion of the conductive pattern may contact a free layer pattern in a magnetic random access memory (MRAM). The barrier layer pattern can electrically contact the MOS transistor disposed under the barrier. θ ^ The size of the cross-sectional area of the oxidized portion in plan view may be smaller than the cross-sectional area of the opening of the 201133757 opening at the plane. The size of the cross-sectional area of the portion in the plan view may depend on the size of the cross-section of the layer. According to an exemplary embodiment of the present invention, forming a semiconductor device includes: forming an interlayer insulating layer on the substrate; forming an opening in the third insulating layer to expose the substrate; forming a barrier layer Figure = the opening; forming a guide on the barrier in the opening, and growing the conductive pattern by oxidizing the conductive pattern to partially extend one of the conductive patterns The opening. Growing the conductive pattern may include from about 4 Å <>> to about 6 Å. The RTA process is performed in an oxygen atmosphere for about -minute to about 1 minute in an oxygen atmosphere. Growing the conductive pattern can include performing a plasma treatment in an oxygen atmosphere by applying about 2 watts to a ratio of about 10,000 minutes to about growth. The conductive pattern can include isotropic or anisotropic Perform growth. The providing method may further include surrounding the oxidized portion of the conductive pattern, the method further comprising forming a fill pattern in the opening to dispose a second conductive pattern between the fill pattern and the barrier A layer pattern according to an exemplary embodiment of the present invention, a semiconductor element earth-filled board having an insulating layer disposed on the substrate, a metal layer disposed on the substrate, and a metal oxide pattern, Disposed on the metal® case and the opening, the cross-sectional area of the gold secret pattern of the towel is smaller than the cross-sectional area of the metal pattern. The metal pattern may comprise a crane. A portion of the metal pattern contacting the metal oxide pattern may be recessed' and the recess receives a protrusion of the metal oxide pattern. A gap wall may be disposed between the metal oxide pattern and the insulating layer. The metal pattern can be disposed on the p_N junction. The metal pattern can be electrically connected to the DOO 03 crystal. The metal oxide pattern can contact the MRAM2 free layer pattern. The metal oxide pattern can contact the phase change material film of the pRAM. A top portion of the phase change material film and the insulating layer may be disposed with a gap having a width wider than a bottom portion of the phase change material film phase change material according to an exemplary embodiment of the present invention For example, a method of forming a semiconductor device 2 includes: forming a metal pattern on a substrate; forming an insulating layer on the second pattern to form an opening through the insulating layer, the opening exposing a portion of the metal pattern And oxidizing the exposed portion of the metal pattern to form a metal oxide pattern in the opening. The metal oxide pattern may be in contact with the "sixth percent free layer. The metal oxide pattern may be electrically contacted with the MRAM & s s. The metal oxide pattern may contact the phase change film of the pRAM. 7 201133757 The metal pattern may contact the PN diode of the PRAM. The width of the metal oxide pattern may be smaller than the width of the metal pattern. [Embodiment] Hereinafter, the present invention will be more fully described with reference to the accompanying drawings. The present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. It is understood that when a component or layer is When a layer is "on (〇n)", "connected to" or "coupled to" another member or layer, the member or layer may be directly located on another member or layer, connected to Or coupled to another component or layer, or an intermediate component or layer. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a conductive structure not according to an exemplary embodiment of the present invention. 2 is a perspective view of a conductive structure in accordance with an exemplary embodiment of the present invention. Referring to Figures 1 and 2, an insulating interlayer 52 is disposed on the substrate 50. The insulating interlayer 52 includes an opening 54 that exposes a portion of the substrate 50. For example, opening 54 may expose a conductive area of the substrate. In an exemplary embodiment, a conductive pattern can be disposed on the substrate 50 such that the opening 54 can expose a conductive pattern on the substrate 5. In an exemplary embodiment, the opening 54 can have the shape of a contact hole. However, the structure of the opening 54 may vary depending on the configuration of the conductive structure. That is, the opening 54 can have various shapes, so the structure of the opening 54 is not limited to that shown in Fig. 1. For example, the opening 54 can have a treneh structure. 8 201133757. A barrier metal layer pattern S6a is formed on the bottom and sidewalls of the opening 54. The barrier metal layer pattern 56a may have a meandering structure. The barrier metal layer pattern 56a may include at least one of a metal or a nitride. For example, the barrier metal layer pattern 56a may include at least one of tantalum (Ti) or titanium nitride (τίΝχ). The barrier metal layer pattern 56a may have a single layer structure or a mUltilayer structure. For example, the barrier metal layer pattern 56a may include a titanium film and a titanium nitride film. The barrier metal layer pattern 56a prevents metal atoms and/or metal ions in the metal pattern 58b from diffusing toward the insulating interlayer 52. The barrier metal layer pattern finely increases the lying area of the conductive structure so that the conductive structure has a reduced contact resistance. Field Film In an exemplary embodiment, the barrier metal layer pattern 56a may include a material that is oxidized or hardly oxidized. The metal pattern 58b is disposed on the barrier metal|pattern 56a. Metal pattern 58b can comprise, for example, tungsten (w). The metal pattern 5 may not completely fill the opening 54. The barrier metal layer pattern 56a and the metal pattern 58b can be used as a conductive pattern electrically connected to the conductive region of the substrate 50. The metal oxide pattern 60 is formed on the metal pattern 58b. The metal oxide pattern can comprise, for example, an oxidized crane (WOx). In the exemplary embodiment, the metal oxide pattern 60 can be obtained by oxidizing the surface of the metal pattern 58b. The metal oxide pattern 60 may protrude upward from the insulating interlayer 52. In an exemplary embodiment, the protrusion (t) of the metal oxide pattern 60 may have a thickness (t) that is substantially greater than a portion of the fill opening 54 of the metal oxide pattern 6''. Further, the metal oxide pattern 60 has a width 201133757, (W) which may be substantially the same as the metal pattern 58b. In an exemplary embodiment, the metal oxide pattern 60 has a resistance that is substantially higher than the resistance of the metal pattern 58b. The thickness (t) of the metal oxide pattern 60 can be adjusted by controlling the conditions of the oxidation process for forming the metal oxide pattern 60 by oxidizing the metal pattern 58b. Thereby, the resistance of the metal oxide pattern 60 can also be adjusted. The width (w) of the metal oxide pattern 60 can be substantially less than the critical dimension (CD) of the photolithography process. In an exemplary embodiment, the width (w) of the metal oxide pattern 60 may decrease as the thickness (t) of the barrier metal layer pattern 56b increases. For example, the width (w) of the metal oxide pattern 6 可 can be less than about 50 nm. When the metal oxide pattern 60 has a high electrical resistance, the metal oxide pattern 60 can be used as a heating electrode because a Joule heating effect can be generated in the metal oxide pattern 6〇 by applying f to the metal oxide pattern 60. (j〇ule heating effect) ° In an exemplary embodiment, the metal oxide pattern 60 can be used as a contact plug. 'This contact plug has a high resistance and a width substantially smaller than the critical dimension of the lithography process. . An exemplary implementation, when the metal oxide _(9) has a line shape, the metal oxide pattern 6 〇 can be used as a wiring, and the width of the wiring is smaller than the critical dimension of the lithography process. . 3 to 5 are cross-sectional views showing a method of forming a conductive, σ-structure according to an exemplary embodiment of the present invention. 201133757 Referring to Fig. 3', the insulating loss layer 52 is formed on the substrate 5A. The substrate % includes a semiconductor substrate, a substrate having a semiconductor layer, or at least a metal oxide substrate. The insulating interlayer 52 may be formed of an oxide such as oxidized rock.

A partial residue is applied to the insulating layer 52 to form an opening M 5 over 4 = base = 〇Γ portion. The opening 54 can be formed by a lithography process, a rim edge interlayer 52. The exposed portion of the substrate 5 can include a conductive region. In an exemplary embodiment, the opening 54 may have the shape of a contact hole. When the opening 54 is formed by the lithography process, the opening % may have a width substantially the same as or greater than the critical dimension of the lithography process (CD^. Z metal layer 56 axis (four) σ 54 bottom material And the insulating interlayer 52. The barrier metal layer 56 can be along the opening 54 and the insulating interlayer a = genus 1 56 to prevent the atoms and/or domain ions contained in the metal layer 58 from facing the interlayer 5 The early metal layer 56 may comprise titanium or titanium telluride alone or in a mixed 2= structure or a multi-layer structure. The opening 54 may not be completely filled in. The barrier metal layer 56 is shaped as a barrier metal layer. When formed on the sidewall of the opening 54, the opening degree 'reduction amount is adjusted as the thickness I of the metal transition layer 56 is reduced. The thickness of the barrier metal layer 56 is controlled to be adjusted: 'The metal layer 58 can be formed on the turn The metal layer 56 is filled with openings 201133757 54. The metal layer 58 may comprise, for example, a crane. In an exemplary embodiment, the width of the opening 54 is varied by adjusting the thickness of the barrier metal layer 56, the metal layer The thickness or width of the 58 may vary depending on the thickness of the barrier metal layer 56. Referring to Figure 4', the metal layer 58 and the barrier metal layer 56 are partially removed until the insulating interlayer 52 is exposed. For example, the metal may be locally removed by, for example, a chemical mechanical polishing 'CMP process. The layer 58 and the barrier metal layer 56. Therefore, the barrier metal layer pattern 56a and the preliminary metal pattern 58a are formed in the opening 54. In the CMP process according to an exemplary embodiment, the insulating interlayer 52 can be performed. Grinding, so that the initial metal pattern 58a and the barrier metal layer pattern 56a may protrude upward from the insulating interlayer 52. For example, the protrusions of the initial metal pattern 58a and the barrier metal layer pattern 56a may have a twist In this case, the initial metal pattern having the protrusions and the barrier metal layer pattern 56a can be obtained by a single CMP process without additional etching or planarizing processes.

In the exemplary embodiment, the initial metal pattern % having the protrusions and the barrier metal layer pattern 56a may be formed by one or more (10) processes having different (four) conditions. For example, the first CM can be ground at the first and second metallurgical layers 58 and the metallization layer, and then the inner edge interlayer 52 can be ground under the second process conditions in the second process. As such, the initial metal pattern and the metal layer pattern 56a may have portions protruding from the insulating interlayer 52. Referring to Fig. 5, the initial metal pattern 2 is subjected to an operation in an oxygen atmosphere to form a metal pattern Na and a metal halide pattern 6? on the metal pattern 56a. Although the initial metal pattern 58a is heat-treated in an oxygen atmosphere, the surface of the initial metal pattern 58a reacts with oxygen and thereby thermally expands the surface of the initial metal pattern 58a along the sidewall of the opening 54. As a result, the metal oxide pattern 6 is formed on the initial metal pattern 58a while the initial metal pattern 58a is changed to the metal pattern 58b. In an exemplary embodiment, the metal oxide pattern 60 may have a shape that varies according to the structure of the initial metal pattern 58 & When the top surface of the initial metal pattern 58a is formed higher than the top surface of the insulating interlayer 52, the metal oxide pattern 6〇 may grow non-isotropically from the upper surface of the initial metal pattern 58a. Therefore, the width of the metal oxide pattern can be substantially similar to the width of the initial metal pattern 58a. However, when the top surface of the initial metal pattern 58a is substantially lower than the insulating interlayer & surface, the metal oxide pattern can be grown equitably from the top surface of the initial metal pattern tear. In an exemplary embodiment, the metal oxide pattern 60 may be wider than the initial metal pattern 58a. As shown in Fig. 4, the initial metal pattern has a top surface slightly higher than the top surface of the insulating interlayer 52 to allow the metal oxide pattern 6 to grow non-isotropically from the top surface of the initial metal pattern. That is, the metal oxide pattern 60 may be formed vertically from the initial metal pattern 58a, and the metal oxide pattern 60 may have a width substantially similar to the width of the initial metal pattern tear. Thus, the width of the metal oxide pattern 60 can be substantially less than the width of 54. Meanwhile, when the width of the metal oxide pattern 60 is reduced, the metal oxide pattern 60 may have a reduced surface roughness. For example, when the metal oxide pattern 60 has a width of about 50 nanometers, the metal oxide pattern 60 may have a reduced surface roughness ranging from a few tenths of an angstrom (A) to about 1 angstrom. As a result, electrical failure due to the surface roughness of the metal oxide pattern 60 can be prevented. In an exemplary embodiment, when the opening 54 is formed by the lithography process, the metal oxide pattern 60 may have a width of less than about 50 nm by adjusting the thickness of the barrier metal layer pattern 56a. In an exemplary embodiment, the metal oxide pattern 60 may be formed on the upper portion of the opening 54 while reacting oxygen with the upper surface of the initial metal pattern 58a. Therefore, the metal oxide pattern 6〇 can protrude from the opening 54. At the same time as the formation of the metal oxide pattern 60, the initial metal pattern 58a becomes the metal pattern 58b. The metal pattern 58b has a height lower than that of the initial metal pattern 58a. As the thickness (t) of the metal oxide pattern 60 increases, the height (h) of the initial metal pattern 58a can be reduced to the height (h,). In an exemplary embodiment, the metal oxide pattern 60 has a resistance that is substantially greater than the resistance of the metal pattern 58b. In an exemplary embodiment, the metal pattern 58b can be obtained by heat-treating the initial metal pattern 58a. The heat treatment process can be performed in the vicinity of the initial metal pattern 58a. The heat treatment process may include at least one of a plasma treatment or a rapid thermal annealing (RTA) process. For example, the metal oxide pattern 60 can be formed by performing a plasma treatment or an RTA process. Alternatively, the plasma processing and the RTA process may be sequentially performed to form the metal pattern 58b. Each of the gold pattern 58b and the metal oxide pattern 6 can be divided into a thickness (h) and a thickness (1) by controlling the height (7) and thickness (1) of the heat treatment process. Further, the widths of the metal pattern 58b and the metal oxide pattern 60 can be adjusted by controlling the thickness of the barrier metal layer 56. Thereby, the resistance of the metal pattern tearing and the metal oxide 60 can be controlled. "In an exemplary embodiment, the metal pattern 5 can be formed by the RTA process and the metal oxide pattern can be performed. The RTA process can be performed in an oxygen atmosphere at a temperature of about 4 Torr to about _c. From about one minute to about one minute. Alternatively, the metal pattern 58b^ metal oxide pattern 60 can be obtained by electrical processing. In the exemplary embodiment, by applying about 2 watts to about 100 The power of the watts is performed while the plasma treatment is performed in the Wei gas atmosphere for about 10 minutes. In the exemplary embodiment, the process gas containing oxygen (02) gas or ozone (〇3) gas may be used to oxidize the initial metal pattern. 58a. For example, the initial metal pattern 58a can be oxidized by supplying oxygen gas at a flow rate of about 500 sccm. However, the initial metal pattern 58a can be oxidized by various gases and process conditions, and is not limited to the upper Wei body. And/or process conditions. In an exemplary embodiment, the barrier metal layer pattern 56a may not be oxidized when the initial metal pattern 58a is oxidized. Although the barrier metal layer pattern 5 is slightly oxidized, the barrier metal layer Oxidation of pattern 56a The thickness of the portion may be substantially smaller than the thickness of the metal oxide pattern 6 。. For example 15

201133757 _ L ‘ When the barrier metal layer pattern 56a contains at least one of titanium or titanium nitride, the barrier metal layer pattern 56a may not be substantially oxidized. After the metal oxide pattern 60 is formed, a surface treatment process can be performed. The surface treatment process can include a rapid thermal nitration (rTN) process in which the surface of the metal oxide pattern 60 is subjected to a nitrogen atmosphere. Further, a reduction process can be performed on the surface of the metal oxide pattern 60 to reduce the amount of metal oxide in the metal oxide pattern. The electrical resistance of the metal oxide pattern 60 can be varied by the surface treatment process and/or the reduction process to further control the electrical resistance of the conductive structure. According to an exemplary embodiment, the metal oxide pattern 6〇 can be obtained without depositing a metal oxide or etching the deposited metal oxide. The metal oxide pattern 60 can have a width that is substantially less than the critical dimension of the lithography process. The metal pattern 58b serving as a contact plug and the barrier metal layer pattern 56a may be disposed under the metal oxide pattern 60. Accordingly, the resistance of the contact plug can be substantially less than the resistance of the metal oxide pattern 60, and the contact plug can have a width substantially greater than the width of the metal oxide pattern 60. Since the resistances of the metal oxide pattern 60 and the metal pattern 58b can be adjusted by controlling the thickness and width of the metal oxide pattern 60 and the metal pattern 58b, the conductive structure can determine the resistance. Figure 6 is a cross-sectional view showing a magnetic memory device in accordance with an exemplary embodiment of the present invention. The magnetic memory component shown in Figure 6 can comprise a conductive structure in accordance with an exemplary embodiment of the present invention. For example, the magnetic component can include a conductive structure having substantially the same set of 201133757 states as the conductive structure described with reference to FIG. Referring to Fig. 6', a metal oxide semiconductor (MOS) transistor is provided on the semiconductor substrate 400. The MOS transistor can select at least one unit cell of the magnetic memory element. The MOS transistor may include a gate insulating layer 402, a gate electrode 404, and an impurity region 406. The gate electrode 4〇4 can be used as a word line of the magnetic C memory element. In an exemplary embodiment, gate electrode 404 can extend in a first direction. Current can be supplied to the magnetic tunnel junction (MTJ) structure in the spin transfer torque magnetic memory element simultaneously with respect to the magnetic memory element. Therefore, the MOS transistor can operate as an open member in the magnetic memory element. A first insulating layer 408 is formed on the semiconductor substrate 400 to cover the MOS transistor. The first insulating interlayer 408 can comprise an oxide, such as hafnium oxide. A contact plug 410 is formed through the first insulating interlayer 408. The contact plug 41 electrically contacts the impurity region 406. A conductive pattern 412 is disposed on the contact plug 410. The conductive pattern 412 may extend in the first direction. The conductive pattern 412 may have a shape of a line. Conductive line 412 can comprise a metal, such as tungsten. A second insulating interlayer 414 is formed over the first insulating interlayer 408 to cover the conductive pattern 412. The second insulating interlayer 414 can comprise an oxide, such as oxidized oxide. An opening 415 is formed through the second insulating interlayer 414. The opening 415 partially exposes the conductive pattern 412. The opening 415 may have a shape of a contact hole. In an exemplary embodiment, a plurality of openings may be periodically provided in the cell region 17 201133757 * l of the magnetic memory device. In an exemplary embodiment, an opening may form a first barrier metal layer pattern 416 on the bottom and sidewalls of the opening 415 corresponding to a unit cell e of the magnetic memory element. A metal pattern 418 is disposed on the first barrier metal layer pattern 416. The metal pattern 418 can comprise tungsten. The metal pattern 418 can partially fill the opening 415. The metal oxide pattern 42 is placed on the metal pattern 418. The metal oxide pattern 420 may protrude from the opening 415. The metal oxide pattern 42 can be obtained by oxidizing the metal pattern 418. When the metal pattern 418 contains a crane, the metal oxide pattern 420 may contain ruthenium oxide. In an exemplary embodiment, the metal pattern 418 has a width that is substantially the same as the width of the metal oxide pattern 42A. For example, the first barrier metal layer pattern 416, the metal pattern 418, and the metal oxide pattern 420 may correspond to the barrier metal layer pattern 56a, the metal pattern 58b, and the metal oxide pattern 60 described with reference to FIG. In the conductive structure, the metal pattern 418 and the first barrier metal layer pattern 416 serve as electrode contacts under the magnetic memory element. A metal oxide pattern 420 having a high electrical resistance can be used as a heating electrode to heat a free layer pattern in the magnetic tooth interface structure of the magnetic memory element. A third insulating interlayer 422 is formed over the second insulating interlayer 414. The third insulating interlayer 422 fills the gap between the adjacent metal oxide patterns 42. The third insulating interlayer 422 may comprise a material having a dense structure and good step coverage. For example, the third insulating interlayer 422 can include yttrium oxide of 201133757_A. obtained by, for example, a HDP-CVD process or an ALD process. Thereby, the third insulating interlayer 422 can be conformally formed along the outline of the metal oxide pattern 420. In an exemplary embodiment, the upper surfaces of the third insulating interlayer 422 and the metallization pattern 420 may be located on substantially the same plane. The upper surface of the first barrier metal layer pattern 416 is covered with a third insulating interlayer 422, so that the first barrier metal layer pattern 416 may not be exposed. The magnetic tunneling junction structure is disposed on the third insulating interlayer 422. The magnetic tunnel junction structure can have a sandwich-shaped multilayer structure. This ensures that electrons are tunneled between the two ferromagnetic layers when applying a signal to the magnetic tunnel junction structure. Very thin oxide layer. The magnetic tunnel junction structure includes a free layer pattern 426, a tunnel oxide layer pattern 428, and pinned layer patterns 430a, 430b, 430c, and 432. The pinned pattern 430a, 430b, 430c, and 432 may include a spin having a magnetization direction that is substantially the same as a magnetization direction of the magnetic polarization fixed in the ferromagnetic layer. In the magnetic tunnel junction structure, at least a portion of the bottom of the free layer pattern 426 may contact the upper surface of the metal oxide pattern 420. In accordance with an exemplary embodiment of the present invention, the magnetic tunnel junction structure may include a free layer pattern 426, a tunnel oxide layer pattern 428, and fixed layer patterns 430a, 430b, 430c, and 432. In an exemplary embodiment, the free layer pattern 426 can comprise a metal compound, such as cobalt-iron-boron (Co-Fe-B). A second barrier metal layer pattern 424 is formed between the third insulating interlayer 422 and the free layer pattern 426. The second barrier metal layer pattern 424 prevents abnormal growth of the metal contained in the layer pattern 426 from 201133757. The second barrier metal layer pattern 424 may include at least one of a metal or a metal compound. The second barrier metal layer pattern 424 may comprise, for example, a group, a titanium, a nitride group, or a gasification. The tunnel oxide layer pattern 428 may comprise a metal oxide such as an oxidized lock (Mg〇x). The pinned layer patterns 43A, 430b, 430c, and 432 may have a stacked structure including first pinned layer patterns 43a, 43b, and 430c and a second pinned layer pattern 432. The first pinned layer patterns 43A, 430b, and 430c may directly contact the tunnel oxide layer pattern 428. In an exemplary embodiment, the first pinned layer patterns 43A, 43B, and 430c are divided into a lower ferromagnetic layer pattern 43a, an anti-ferromagnetic coupling spacer 430b, and Ferromagnetic layer pattern 430c. The first pinned layer patterns 430a, 430b, and 430c may have a synthetic antiferromagnetic layer structure. The lower ferromagnetic layer pattern 430a may include cobalt-iron-boron (Co-Fe-B), and the upper ferromagnetic layer pattern 430c may include cobalt-iron (Co-Fe). The antiferromagnetic coupling spacer layer 430a may comprise, for example, germanium (RU). The second pinned layer pattern 432 may include platinum-manganese (Pt_Mn). In the magnetic wear-fed surface structure, the bottom of the free layer pattern 426 is disposed on the metal oxide pattern 420. The metal oxide pattern 420 can be further used as a heating layer pattern for heating the free layer pattern 426. The metal oxide pattern 420 has a width substantially less than the width ′ of the opening 415 formed through the first insulating interlayer 408 such that the metal oxide pattern 420 can have a high electrical resistance to more efficiently heat the free layer pattern 426. When the magnetic tunnel junction structure is disposed on a layer having a poor coarseness (e.g., a layer having a rough surface), Neel coupling 20 201133757, the phenomenon may cause deterioration of characteristics of the magnetic tunnel junction structure. However, the magnetic memory element according to an exemplary embodiment of the present invention is disposed on the metal oxide pattern 420 having excellent roughness, so that the magnetic memory element can ensure good operational characteristics. When the free layer pattern 426 has a high temperature, the free layer pattern 426 may have a reduced coercive force when storing data in the magnetic memory element. When the free layer pattern 426 has a high temperature, the spin can be made by reducing the write current or the critical current of the spin transfer torque magnetic random access memory (SIT-MRAM). Transfer torque magnetic random access memory has reduced power consumption. In an exemplary embodiment, a hard mask pattern (har (j mask pattern) may be disposed on the magnetic tunnel junction structure. A fourth insulating interlayer 434 is disposed on the third insulating interlayer 422 to fill adjacent magnetic properties. A gap between the tunnel junction structures is disposed. A fifth insulating interlayer 436 is disposed on the fourth insulating interlayer 434. The fourth insulating interlayer 434 and the fifth insulating interlayer 436 may include, for example, an oxide. Upper electrode 438. Upper electrode 438 can pass through fifth insulating interlayer 436 and can contact the uppermost fixed layer pattern of the magnetic tunneling junction structure. Upper electrode 438 can comprise a material having a small electrical resistance, such as a crane. A bit line 440 is formed over 436. The bit line 44A is electrically connectable to the upper electrode 438. The bit line 440 can extend in a second direction that is substantially perpendicular to the first direction in which the word line extends. The process of storing data in a magnetic 21 201133757 memory device in accordance with an exemplary embodiment will be explained. See Figure 6 'Applying a word line signal to the gate electrode 4〇4 of the transistor while applying bit line writes Signal Bit line 440. The word line scent may correspond to a voltage pulse signal having a word line voltage substantially greater than a threshold voltage of the transistor in a predetermined period °. Therefore, ^ is applied to the word line When the voltage is applied to the transistor, the transistor electrically connected to the word line is turned on. The bit line signal can be a current pulse signal, and when the word line signal is applied to the transistor, the current pulse signal applies current to the bit line. 44. As a result, the write current can flow through the magnetic tunnel junction structure and the serially-connected (serial) electrical connection to the transistor of the magnetic tunnel junction structure. The write current can include the first write current and a second write current. The first write current may flow from the free layer pattern 426 toward the second pinned layer pattern 432. The second write current may flow from the second pinned layer pattern 432 toward the free layer pattern 426. In an embodiment, the first write current may flow in the magnetic tunnel junction structure along the positive axis, and the second write current may flow in the negative direction along the x-axis. That is, at the first write current Flowing in the magnetic tunnel junction structure At the same time, electrons can move in the negative direction of the γ-axis. While the second write current flows in the magnetic tunnel junction structure, electrons can flow in the positive direction of the γ-axis. When the first write current flows through the magnetic wear In the tunnel junction structure, electrons may be injected into the free layer pattern 426. The electrons may include upper and lower electrons. When most of the magnetic polarizations fixed in the second fixed layer pattern 432 have an upper germanium state' Only the spin-on electrons injected into the free layer pattern 426 can flow through the tunnel oxide layer pattern 428, and then can reach the second pinned layer 22 201133757^ pattern 432. The spin-electron can be accumulated in the free layer pattern 426. In the free layer pattern 426, the number of spintronics and spindown electrons injected into the free layer pattern 426 can be proportional to the density of the first write current. When the density of the first write current increases, the free layer pattern 426 may have a plurality of main magnetic polarizations that are anti-parallel to the first cause caused by the accumulation of spintronics in the free layer pattern 426. The magnetic polarization of a solid layer pattern 426 is not dependent on the initial polarization of the free layer pattern 426. Therefore, when the density of the first write current is greater than the first critical current density, the magnetic tunnel junction structure can be switched to have the maximum resistance. When a first write to the magnetic tunnel junction structure is provided, the metal germanide pattern 420 can heat the free layer pattern 426 to reduce the coercivity formed on the free layer pattern 426 and reduce the first critical current density. Therefore, the magnetic memory element can have a minimized power consumption while reducing the first write current. When the second write current flows through the magnetic tunnel junction structure, the spin of most of the electrons passing through the second pinned pattern 432 may exhibit a magnetization of the fixed magnetic polarization with the second pinned pattern 432. The direction of magnetization is substantially the same. For example, when a plurality of main magnetic polarizations in the second pinned layer pattern 432 have an up-rotation state, most electrons passing through the second pinned layer pattern 432 may have an upper state. For example, most electrons have a spin that is substantially the same as the direction of the ferromagnetic layer pattern 43a in the synthetie antiferromagnetic structure. The number of spintronics above the germanium electrons that can pass through the oxide layer pattern 428 and reach the free pattern 426 to ij to the free layer pattern 426 can be proportional to the density of the second write current. The free layer pattern 426 may have a plurality of magnetic polarizations when the density of the second write current increases, the plurality of magnetic polarizations being substantially parallel to the magnetic polarization of the fixed magnetization polarization of the second pinned layer pattern 426 It does not depend on the initial polarization of the free layer pattern 426. This is caused by the spin-on electrons injected into the free layer pattern 426. Therefore, when the density of the second write current is greater than the second critical current density, the magnetic tunnel junction structure can be switched to have a low resistance. When a second write to the magnetic tunneling junction structure is provided, the metal oxide pattern 420 can heat the free layer pattern 426 to reduce the coercive force formed on the free layer pattern 426 and reduce the second critical current density. Thus, a magnetic memory element can have a minimized power consumption while reducing a second write current. 7 through 1B are plan views showing a method of fabricating a magnetic memory device in accordance with an exemplary embodiment of the present invention. Referring to Fig. 7, a MOS transistor is formed on a semiconductor substrate 400 for selecting a desired unit cell of a magnetic memory element. In the process of forming the MOS transistor, the gate insulating layer 402 and the gate electrode layer are formed on the semiconductor substrate 4A. Next, the gate electrode layer is etched to form a gate electrode 404 on the gate insulating layer 402. An impurity region 4?6 is formed at a portion of the semiconductor substrate 400 adjacent to the gate electrode 4?1. The gate electrode 404 can be used as a word line of a magnetic g-resonance element. The gate electrode 404 may have a line shape extending in the first direction. A first insulating interlayer 4?8 is formed on the semiconductor substrate 400 to cover the MOS transistor. A contact plug 41 is formed through the first insulating interlayer 4〇8. The contact plug 410 contacts the impurity region 406. At the contact plug 41〇 and the first 24

A conductive pattern 412 is formed on the insulating interlayer 408 of 201133757. The conductive pattern 412 can be electrically connected to the impurity region 406 via the contact plug 410. Each of the contact plug 410 and the conductive structure may comprise a metal having a low electrical resistance. During formation of the contact plug 410 and the conductive pattern 412, the first insulating interlayer 408 may be locally etched to form a contact hole through the first insulating interlayer 408. The contact holes can be formed, for example, by a lithography process. A conductive layer may be formed on the first insulating interlayer 408 to fill the contact holes. This conductive layer can be patterned' to form contact plugs 410 and conductive patterns 412. In an exemplary embodiment, the contact plug 410 may be formed in a contact hole. A conductive pattern 412 can be formed on the contact plug 410 and the first insulating interlayer 408 by forming an additional conductive layer on the contact plug 410 and the first insulating interlayer 408. This additional conductive layer can then be patterned. In an exemplary embodiment, the contact plug 410 and the conductive pattern 412 can be formed by a damascene process. Referring to Figure 8, a second insulating interlayer 414 is formed over the first insulating interlayer 408 to cover the conductive pattern 412. The second insulating interlayer 414 is partially etched to form an opening 415 that at least partially exposes the conductive pattern 412. Opening 415 can be obtained by, for example, a lithography process. The opening 415 can have the shape of a contact hole. The opening 415 is filled by a substantially private/conducting structure similar to that described with reference to Figs. 3 through 5. This conductive structure can protrude from the opening 415. The conductive structure includes a first barrier metal layer pattern, a metal pattern 418, and a metal oxide pattern 420. A first barrier metal layer pattern 416 is formed on the bottom and sidewalls of the opening 415, and the metal pattern is sin. 25 201133757

a L is formed on the first barrier metal layer pattern 416. The metal pattern 418 partially fills the opening 415. The metal oxide pattern 420 protrudes from the opening 415. The metal pattern 418 and the metal oxide pattern 420 may include tungsten and tungsten oxide, respectively. In an exemplary embodiment, the first barrier metal layer pattern 416 and the metal pattern 418 can be used as the lower electrode of the magnetic memory element, and the metal oxide pattern 420 can be used as the heating electrode of the magnetic memory element. Referring to Figure 9, a third insulating interlayer 422 overlying the metal oxide pattern 420 is formed over the second insulating interlayer 414. Next, the third insulating interlayer 422 is partially removed until the metal oxide pattern 42 is exposed. The third insulating interlayer 422 can be partially removed by a CMP process. The third insulating interlayer 422 can be formed using a material having a dense structure and excellent step coverage. For example, the third insulating interlayer 422 can be formed using yttrium oxide by, for example, a HDP-CVD process or an Ald process. Thereby, the third insulating interlayer 422 can be uniformly formed along the contour of the conductive structure. When the third insulating interlayer 422 has a dense structure, after performing the CMp process: after partially removing the third insulating interlayer 422, the third insulating film The layer-like and metal oxide pattern 420 can have a uniform surface without a coarse face. Referring to Fig. 10', a plurality of layers of a magnetic tunneling junction structure are sequentially formed in the third insulating interlayer 422 and the metal oxide pattern 42. In an exemplary embodiment, the second barrier metal layer, the layer, the tunneling oxide layer, the first pinned layer, and the second pinned layer of the magnetic tunnel junction structure may be sequentially formed. The first solid layer may include a lower ferromagnetic layer, an antiferromagnetic coupling spacer layer, and an upper ferromagnetic layer. The second barrier metal layer prevents abnormal growth of the metal contained in the free layer. The second barrier layer may be formed using an amorphous metal. For example, 26 201133757, == barrier layer may comprise group, chin, nitride or titanium nitride. The free layer L = ia iron through oxide layer may comprise magnesium oxide. As for the first lower ferromagnetic layer, the upper ferromagnetic layer and the antiferromagnetic light-separating spacer, cobalt-iron-boron, cobalt-iron and antimony may be additionally contained. The second pinned layer may be sequentially patterned by a plurality of layers of a platinum-doped magnetic permeation surface structure to form a second barrier metal layer pattern 424, a free layer pattern 426' tunneling oxide layer pattern 428, The first pinned layer patterns 43A, 43% and 43〇c, and the second pinned layer pattern 432. That is, the magnetic tunnel junction structure includes a second barrier metal layer pattern, 424, a free layer pattern 426, a pass oxide layer pattern 428, a first solid layer pattern 430a, 430b, and 430c, and a second fixed layer pattern. 432. The magnetic tunneling junction structure can contact the metal oxide pattern 42A. The magnetic tunneling junction structure may have an island shape. In an exemplary embodiment, a hard mask pattern can be formed on the magnetic tunnel junction structure. The hard mask pattern can be used as an etch mask for forming a magnetic tunnel junction structure. Referring to Figure 6, a fourth insulating interlayer 434' is formed over the third insulating interlayer 422 to cover the magnetically compliant interface structure. The fourth insulating interlayer 434 can sufficiently fill the gap between adjacent magnetic tunnel junction structures. A fifth insulating interlayer 436 is formed over the fourth insulating interlayer 434. A second contact hole is formed through the fifth insulating layer 436 by locally etching the fifth insulating interlayer 436. The second opening partially exposes the magnetic tunneling plane structure. That is, the second pinned layer pattern 432 is exposed through the second opening. A conductive material is formed on the fifth insulating interlayer 436 to fill the second opening and then partially remove the conductive material until the fifth insulating central layer 436 is exposed. Thereby, the upper electrode electrode is formed in the second opening. The conductive material may comprise tungsten and the upper electrode 438 may be formed by a CMP process. A conductive layer is formed on the fifth insulating interlayer 436 and the upper electrode 438. The conductive layer is patterned ' to form a bit line. The bit line paste can be obtained by a lithography process. - As described above, the conductive structure can have a metal oxide pattern 42A containing oxygen and tungsten by a simplified process. The metal oxide pattern 42A may have a resistance and a small width so that the metal oxide pattern 42 can be used as a heating electrode of the magnetic memory element. When the magnetic (4) element contains the metal oxide pattern 42 形成 formed by the oxidized crane, the magnetic memory element can ensure a low coercive force. FIG. 11A is a cross-sectional view of a phase change counter element according to an exemplary embodiment of the present invention. The phase change element shown in FIG. 1 u may include a conductive structure. The structure of the conductive structure is substantially the same as the reference. The construction of the electrically conductive structure illustrated in Figure i. Referring to Figure 11, a substrate 49A comprising an isolation region and an active region is prepared. An impurity region 49 is formed in the active region of the substrate 490. Impurity zone milk (9) can be packaged = impurity 'for example (P) or stone (As). A trench for the isolation member is provided in the isolation region of the substrate, and an isolation layer pattern 492 is formed in the trench. A first insulating interlayer 494 is formed on the substrate 490. A first opening 496 is formed through the first insulating interlayer 494 to expose the impurity region 49. In the first opening 496, the p_N junction type diode 5〇〇(}ρ·Ν diode 5〇〇28 201133757 ^ 1 can be substantially filled with the opening 4%. The p_N diode can be electrically impurity. The region 490a. In an exemplary embodiment, the PN diode 500 includes a first polycrystalline layer pattern 5GGa and a second polycrystalline 7 layer pattern. The first-polycrystalline layer pattern 5〇〇a can be doped. There is a type 1 impurity, and a P-type impurity may be doped in the second polycrystalline layer pattern 500b. A metal halide pattern may be disposed on the PN diode 500 to reduce the P_N diode 5〇〇. a second insulating interlayer 504 is formed on the first insulating interlayer 494 and the PN diode 500. The second insulating interlayer 5〇4 may have a second opening 5〇5, and the second opening 505 is partially The P_N diode 5〇〇 is exposed. The second opening 5〇5 may have the shape of a contact hole. The conductive structure is located in the second opening 505. The conductive structure may have a level substantially the same as described with reference to FIG. The structure of the contact structure. The conductive structure includes a barrier metal layer pattern 506, a metal pattern 5〇8, and a metal oxide pattern 510. The pattern 508 and the metal oxide pattern 51 can respectively comprise, for example, tungsten and tungsten oxide. In the phase change memory device, the conductive structure can be used as a lower electrode of the memory cell. The metal oxide pattern of the conductive structure can be heated. The phase change material layer pattern 514 is because the metal oxide pattern 510 formed of tungsten oxide can have a high electrical resistance. For example, the metal oxide pattern 510 has a resistance souther than the metal pattern 508. For example, a metal oxide pattern 510 has a resistance to the combination of the metal pattern 508 and the barrier metal layer pattern 506. A third insulating interlayer 5 丨 2 is formed on the second insulating interlayer 504. The metal oxide pattern 510 of the conductive structure is available from the second The insulating layer 504 protrudes, and 29 201133757, can be buried in the third insulating interlayer 512 t. Therefore, the third insulating interlayer 512 can fill the gap between the adjacent metal oxide patterns 51. In an exemplary embodiment, The three insulating interlayer 512 may comprise a material having a dense structure and good step coverage so that the third insulating loss layer 512 can be conformally formed along the outline of the metal oxide pattern 510. The insulating metal layer 51 is sufficiently insulated on the second insulating interlayer 504. For example, the third insulating interlayer 512 may comprise a high density plasma-chemical vapor deposition (high-density plasma-chemical vapor deposition). The ruthenium oxide obtained by the HDP-CVD process or the ruthenium oxide formed by an atomic layer deposition (ALD) process. The third insulating interlayer 512 has a height substantially the same as the metal oxide pattern 510. The degree of direction. In an exemplary embodiment, the third insulating interlayer 512 and the upper surface of the metal oxide pattern 510 may be on substantially the same plane. The phase change structure 514 is disposed on the metal oxide pattern 51A of the conductive structure. When the metal oxide pattern 510 has a width substantially less than the critical dimension of the lithography process, the contact area between the phase change structure 514 and the conductive structure can be reduced. Thus, a phase transition reaction can easily occur in the phase change structure 514 by the Joule heating mechanism. In an exemplary embodiment, phase change structure 514 can comprise a chalcogenide compound whose crystal structure reversibly changes between an amorphous state and a crystalline state. When the chalcogen compound has a crystal structure, the chalcogenide compound can have high optical reflectance and low electrical resistance. When the chalcogenide has an amorphous structure, the chalcogenide can have low optical reflectivity and high electrical resistance. The phase change structure 514 can be formed using a chalcogenide compound containing an alloy of germanium (Ge>(Sb)-tellurium (Te). The upper electrode 516 is disposed on the phase change material layer pattern 514. The upper electrode 516 can include a metal nitride, For example, titanium nitride is formed on the third insulating interlayer 512 to cover the upper electrode 516. That is, the upper electrode 516 and the phase change structure 514 can be buried in the fourth insulating interlayer 518. A contact hole is provided in the interlayer 518. The contact hole may partially expose the upper electrode 516. The upper contact 522 is formed in the contact hole such that the upper contact 522 may contact the upper electrode 516. The upper contact 522 may comprise a metal such as tungsten In the phase change memory device according to an exemplary embodiment, the conductive structure may include a metal oxide pattern in contact with the phase change structure. Since the metal oxide pattern formed by the tungsten oxide may have high resistance and small width, the phase The variable structure can have an improved Joule heating effect, and the phase change memory element can ensure a reduction in reset current. In an exemplary embodiment, the phase change memory element can have a different setting And the reset state, because the phase change structure may have a reduced resistance distribution of the set state and the reset state. FIG. 4 is a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention. Referring to Fig. 12, an impurity region is formed in a predetermined portion of the substrate 490 by replacing impurities in a predetermined portion of the substrate 490. The impurity regions can be formed by an ion implantation process. 31 201133757 " The substrate 49 is partially etched to form an additional channel for the barrier amine on the substrate 490. The trench may extend in the first direction. The substrate 490 is separated from the layer to fill the trench, and then the isolation layer is partially removed. The spacer layer pattern 492 is formed in the trenches. The spacer layer pattern milk 2 may comprise, for example, an oxide - a first insulating interlayer 494 is formed on the substrate 49,0 having the spacer layer pattern 492. The first insulating interlayer 494 may comprise oxidation The first insulating interlayer 494 is etched to form a first opening 496, and the first opening 496 partially exposes the impurity region 49A. The first insulating interlayer 494 is formed for filling. An opening 49 The layer of ruthenium 6 is partially removed until the first insulating interlayer 494 is exposed. Thereby, a ruthenium layer pattern is formed on the impurity region 490a in the first opening 496. The upper layer of the ruthenium layer pattern may be doped a p-type impurity, and an N-type impurity is implanted in a lower portion of the germanium layer pattern. Thereby, a PN diode 500 is formed on the impurity region 490a in the first opening 496. The PN diode 500 includes the first layer The pattern 500a and the second layer pattern 5〇〇b. The first layer layer pattern 500a and the second layer layer pattern 500b may respectively include [s] type impurities and p type impurities. In an exemplary embodiment, a metallite pattern may be additionally formed on the p_N diode 500. A second insulating interlayer 504 is formed on the P-N diode 500 and the first insulating interlayer 494. The second insulating interlayer 504 can comprise an oxide, such as hafnium oxide. The second insulating interlayer 504 is partially etched to thereby form a second opening 505 that exposes a portion of the P-N diode 500. A conductive structure is formed on the P-N diode 500. The conductive structure can be formed by substantially the same process as described in FIG. Conductive ί = Γ 5. 5 and protrudes from the second opening 505. On the metal = barrier layer pattern 5G5, the pattern 508 on the 505 is located in the barrier metal layer pattern _ _ genre is partially filled with the second opening σ 5 〇 5. Gold may contain oxidized 5G5. Metal oxide pattern 510 metal oxide pattern 5 second opening 505 protrudes ° w tea has a width substantially smaller than the second opening „ again, because the metal oxide pattern 512 is by the barrier metal p bow Γ5 is sandwiched between the second opening 505 and the metal oxide pattern 512 to be formed in the second opening 505. ★ The first, and the 'edge edge clips covering the metal oxide pattern 510 are formed on the second insulating interlayer 504. Layer 512. The third insulating interlayer 512 may comprise a material having a dense structure and excellent step coverage. For example, the third insulating layer 512 may comprise an oxidized oxide obtained by an HDp_CVD process or an AL]D process. The third insulating interlayer 512 is partially removed until the metal oxide pattern 510 is exposed. The third insulating interlayer 512 can be partially removed by a CMp process and/or an etch-back process. A phase change material layer is formed on the third insulating interlayer 512. The phase change material layer may comprise a chalcogenide such as 锗_锑_碲. The upper electrode layer is formed on the phase change material layer. The upper electrode layer may comprise a metal nitride, Such as titanium nitride. Will be powered The layer and the phase change material layer are patterned, 33 201133757 ^ WW Λ ^ ΛΛ to form the upper electrode 516 and the phase change structure 514. The upper electrode 516 and the phase change structure 514 can be formed by a lithography process. A fourth insulating interlayer 518 is formed thereon to cover the upper electrode 516 and the phase change structure 514. The fourth insulating interlayer 518 is locally etched to form a contact hole 520'. The contact hole 520 at least partially exposes the upper electrode 516. Depositing a conductive material to fill The contact hole 520 is filled, and the upper electrode contact 522 is formed on the upper electrode 516. The upper electrode contact 522 may comprise a metal such as tungsten, aluminum, titanium, a button, copper or platinum. According to an exemplary embodiment, it may be simplified The metal oxide pattern 51A having a high resistance and a small width formed by an oxide is obtained by the process. The metal oxide pattern 510 can be sufficiently used as an electrode for heating the phase change structure 514. When the phase change memory element contains a metal When the oxide pattern is 51 ,, the phase change memory element can have a reduced reset current and a reduced resistance distribution, so that the data can be easily stored in the phase change memory element and can be easily self-phased. Memory element readout. Figure 13 is a cross-sectional view of a phase change memory device in accordance with an exemplary embodiment of the present invention. The phase change memory device of Figure 13 includes a conductive structure, the conductive structure being substantially The conductive structure is the same as described with reference to Figure i. In addition to the phase change structure, the phase change memory component of Figure 13 can have a configuration substantially identical to that of the phase change memory component described with reference to Figure 11. Referring to Figure 13, A first insulating interlayer 494, a p_n one body 500, and a second insulating interlayer 504 are provided on the substrate 490. A second opening 505 is formed through the second insulating interlayer 504, and the second opening 505 exposes the p_N diode 500. 34 201133757^ The conductive structure is disposed in the second opening 5G5. The conductive structure includes a barrier metal layer pattern 5% substantially the same as that described with reference to Fig. 11, a metal pattern 508, and a metal oxide pattern 51A. A third insulating interlayer 512 is disposed on the second insulating layer 504. A third insulating interlayer 512 covers the conductive structure. The third insulating layer may comprise a material having a dense structure and good step coverage. For example, the third insulating interlayer 512 may comprise an oxidized oxide obtained by a HDp_CVD process or an ald process. The third insulating interlayer 512. has an upper surface that is substantially higher than an upper surface of the metal oxide pattern 510. The teeth pass through the second insulating interlayer 512 to form a third opening 515, and the third opening 515 exposes the metal oxide pattern 51A. The third opening 515 has a width substantially the same as the width of the metal oxide pattern 51. A phase change structure 51 is formed on the metal oxide pattern 510 to fill the third opening 515. The phase change structure 5Ma protrudes from the third opening 515. In an exemplary embodiment, the phase change structure 514a may have a lower width in the third opening 515 and an upper width above the third opening 515. The width of the lower portion of the phase change structure 514a may be substantially smaller than the width of the upper portion 1 due to the phase change junction & 514a contacting the metal oxide pattern 51, and a portion of the phase change structure 514a heated by the metal oxide pattern may be limited to the third portion. In the opening 515. An upper electrode 516 is disposed on the phase change structure 514a. A fourth insulating interlayer 518 for covering the upper electrode 516 and the phase change structure 514a is formed on the third insulating interlayer 512. Upper electrode contact 522 is formed through fourth insulating interlayer 518. The upper electrode contact 522 is electrically connected to the upper electrode 516. 14 is a cross-sectional view showing a method of making a phase change memory device in accordance with an exemplary embodiment of the present invention. Referring to Fig. 12, an isolation layer pattern 492, a first insulating interlayer 494, and a P-N diode 500 are formed on the substrate 490. A second insulating interlayer 5〇4 is formed on the first insulating interlayer 494 and the P-N diode 500. The second opening 505 is formed by locally etching the second insulating interlayer 504' through the second insulating interlayer 504. The second opening 505 exposes at least a portion of the p·Ν diode 5〇〇. An initial conductive structure is formed on the Ρ-Ν-pole body 500 by a process substantially the same as that described with reference to Figs. This initial conductive structure can fill the second opening 505 and can protrude from the second opening 5?5. The initial conductive structure includes a barrier metal layer 506, a metal pattern 508, and an initial metal oxide pattern. The metal pattern 508 and the initial metal oxide pattern can be made of tungsten and tungsten oxide, respectively. A resistive early metal layer pattern 506 is formed on the bottom and sidewalls of the second opening 505. A metal pattern 5?8 is formed on the barrier metal layer pattern 5?6 to partially fill the second opening 5?5. The initial metal oxide pattern may protrude above the second opening 505. The initial metal oxide pattern may have a height substantially greater than the height of the subsequently formed metal oxide pattern 51a. For example, the height of the initial metal pattern may be substantially the same as the sum of the height of the metal oxide pattern 51a and the height of the lower portion of the phase change structure 514a. Here, the lower portion of the phase change structure 514a may have a smaller width than the upper portion of the phase change two structure 514a. A third insulating interlayer 512 is formed over the second insulating interlayer 504 to cover the initial conductive structure. The third insulating interlayer 512 can be formed using a material having a dense structure and excellent step coverage. The third insulating interlayer 36 201133757, 512 is partially removed until the initial metal oxide pattern is exposed. The third insulating interlayer 512 can be partially removed by a CMP process and/or an etch back process. Referring to Fig. 14, the initial metal oxide pattern is partially removed to form a metal oxide pattern 510a on the metal pattern 508. Here, the metal oxide pattern 510a may protrude above the third insulating interlayer 512 to not expose the barrier metal layer pattern 506 after forming the metal oxide pattern 510a. When the metal oxide pattern 51〇a is formed on the metal pattern 508, a third opening 515 is formed on the metal oxide pattern 510a. That is, the removed portion of the initial metal pattern may correspond to the third opening 515. Therefore, the third opening 515 is located in the third insulating interlayer 512. Third, the opening 515 exposes the metal oxide pattern 510a. The third opening 515 has a width substantially the same as the width of the metal oxide pattern 510a. Referring to Figure 13, a phase change material layer is formed over the third insulating interlayer 512 to completely fill the third opening 515. The phase change material layer may comprise a chalcogenide compound such as an alloy of ruthenium-iridium-ruthenium. The upper electrode layer is formed on the phase change material layer. The upper electrode layer can be formed using a metal nitride such as nitride. The upper electrode layer and the phase change material layer are patterned to sequentially form the phase change structure 514a and the upper electrode 516 on the metal oxide pattern 510a. In an exemplary embodiment, the phase change structure 514a can have a third opening si5: = a lower portion of the metal oxide pattern 510a. The phase change structure 51 is known to have an upper portion that protrudes above the third opening 515. The lower portion of the phase change structure 5Ma may have a width smaller than the width of the upper portion of the phase change structure 514a. A fourth insulating interlayer 518 covering the upper electrode 516 is formed on the third insulating interlayer 512. Forming an upper electrode contact through the fourth insulating interlayer 518. 37 201133757 The upper electrode contact 522 contacts the upper electrode 516. Figure 15 is a cross-sectional view of a phase change recession element in accordance with an exemplary embodiment of the present invention. The phase change memory element shown in Figure 15 includes a conductive, '. The structure of the conductive structure is substantially the same as that of the conductive structure described with reference to FIG. 1. In addition to the phase change structure, the phase change memory device of FIG. 15 may have substantially the same phase change memory as described with reference to FIG. Configuration of components. Referring to Figure 15, the conductive structure is located in a second opening 505 formed through the second insulating interlayer 504. The conductive structure includes a barrier metal layer pattern 506, a metal pattern 508, and a metal oxide pattern 51〇a. The third insulating interlayer 512a is located on the second insulating interlayer 504. A third opening 513 is formed through the second insulating interlayer 512a. The third opening 513 exposes at least the metal oxide pattern 510a at least partially. The third opening 513 has a width substantially the same as the width of the metal oxide pattern 510a. The phase change structure 514a is disposed on the metal oxide pattern 510a in the third opening 513. The phase change structure 514a is located in the third opening 515 and does not protrude above the third opening 513. That is, the phase change structure 514a has a width substantially the same as the depth of the third opening 513. The upper electrode 516 is disposed on the phase change structure 514a and the third insulating layer 512a. A fourth insulating interlayer 518 covering the upper electrode 516 and the glazing structure 514a is formed on the third insulating interlayer 512a. The upper electrode contact 522 is formed through the fourth insulating interlayer $丄8. The upper electrode contact 522 can be electrically connected to the upper electrode 516. The phase change memory element shown in Fig. 15 can be manufactured by the following process. The resulting structure has the same structure as that of Figure 14 by reference.

The configuration shown in Fig. 14 obtained by the process described in 201133757.A. Referring to Fig. 15', a phase change material layer is formed on the third insulating interlayer 512a, and ^ is completely filled in the third opening 513. The phase change material is locally removed until the third insulating layer 513a is violent. Thereby, the formation of the phase π 514a phase change structure 514a in the third opening 513 can be formed by, for example, a CMP process. An upper electrode layer is formed on the phase change structure 514a and the third insulating interlayer 512a. The upper electrode layer is then patterned to form an upper electrode 516 on the phase change structure 514a. A fourth insulating interlayer 518 is formed over the second insulating interlayer 512a to cover the upper electrode 516 and the phase change material structure 514a. The fourth insulating interlayer 518 is opened; the upper electrode contact 522 is electrically connected to the upper electrode 516. Figure 16 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. Referring to Figure 16, an insulating interlayer 52 is provided on the substrate 50. The insulating interlayer 52 includes an opening 54 that exposes a portion of the substrate 5〇. 9 Place a spacer on the side wall of the opening 54. The spacers 62 may comprise, for example, tantalum nitride nitride or a oxidized oxide such as nitrogen oxide. The presence of 62 prevents metal atoms and/or metal ions contained in the metal pattern from diffusing into the human insulating layer 52. The barrier metal layer may not be provided on the sidewalls of the opening 54 in the exemplary embodiment. In an exemplary embodiment, a barrier metal layer may be disposed on the spacers 62 and the substrate 5A in the opening 54. A metal pattern 59a is disposed in the opening 54. The metal pattern 59a can partially fill the opening 54. The metal opening σ 59a may include a crane. The metal oxide pattern 39 201133757 has a width which can be substantially = the pattern is torn and oxidized to form a metal oxide, pattern 60. The metal oxide pattern 6() can protrude above the opening %. Production Ϊ = In the exemplary embodiment, the metal oxide pattern 6G has a width of 彡f. The metal oxide pattern can be controlled by the thickness of the opening. A cross-sectional view of a method of forming a conductive structure in accordance with an exemplary embodiment of the present invention is provided. Second, 17' forms an insulating loss layer having an opening 54 on the substrate 5A. Port 54 exposes a predetermined portion of substrate 50, such as a conductive region. The bottom of the π 54 , the side wall of the opening 54 and the insulating interlayer are formed into a layer. The spacer formation layer may comprise, for example, a vapor or nitrogen oxide. 2 For example, the spacer formation layer may comprise nitride or arsenic. ^, the spacer forms a layer ' to form a gap j 62 on the sidewall of the opening 54. Although the spacer 62 is formed, the width of the opening 54 can be reduced by a factor of twice the thickness of the spacer 62. A metal layer 59 is formed on the spacer 62, the substrate 5G, and the insulating layer 52 to completely fill the opening 54. Metal layer 59 can comprise, for example, tungsten. m Referring to Figures 16 and Π, the metal layer 59 is partially removed until the insulating loss layer 52 is exposed to form an initial metal pattern in the opening 54. = Metal pattern can be formed by CMP process. In an exemplary embodiment, ° 201133757

The upper metal si case has an upper surface that is substantially higher than the insulating interlayer force and the upper surface of the spacer 62. For example, the initial metal pattern may protrude above the insulating interlayer 52 by a thickness of about 10 angstroms. Namely, the upper surface of the primary metal pattern may slightly protrude from the upper surface of the insulating inflammatory layer 52 / heat-treat the initial metal pattern in an atmosphere containing oxygen to obtain a metal oxide pattern 6 〇. Here, the metal layer 59 becomes the metal pattern 59a while the initial metal pattern is being developed. The initial metal pattern can be subjected to a process substantially the same as that described with reference to Figure 5. M The conductive structure shown in Fig. 16 can be formed on the substrate 50 by the above process. In an exemplary embodiment, the conductive structure shown in Figure 16 can be used in the magnetic memory component of Figure 6, the phase change memory component of Figure u, or the phase change memory component of the figure. Figure 18 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. Figure 19 is a perspective view of a conductive structure in accordance with an exemplary embodiment of the present invention, and 2G is a plan view showing a conductive structure in accordance with an exemplary embodiment of the present invention. An insulating interlayer 66 is disposed on the substrate 64 with reference to Figs. 18 to 20'. The interlayer 66 includes an opening 68 that exposes the contact area on the substrate. Another option is that the 'opening 68' directly exposes the substrate from it. In an exemplary solid towel, the opening alpha 68 can have a variety of miscellaneous shapes, such as contact hole shapes or trench shapes. The barrier metal layer pattern 7 is located on the bottom and sidewalls of the opening 68, for example. The barrier metal layer pattern 7Ga can be conformally formed along the outline of the opening 68. Resistance 201133757 3=?^ may include, for example, titanium, titanium nitride, and material nitrided surfaces. This special material can be used alone or in the form of a mixture.岚 障 = barrier metal layer pattern can prevent the track included in the metal pattern 72b "child and / or metal ion diffusion. The barrier metal layer pattern can be applied to the large conductive structure of the joint area" and thus can reduce the j pattern 72b configuration On the barrier metal layer pattern I in the opening 68. The metal pattern 72b may have a cylindrical shape and belong to the genus, 7: the upper portion may have a ring shape. In an exemplary embodiment, it has a cylindrical tube shape. The metal pattern resembles the upper surface 72b. The enamel layer is on the upper surface of the layer 1. Therefore, the metal pattern 72b can be located inside the open anvil. The metal oxide pattern 76 is formed on the smear pattern 72b. The metal oxide pattern 76 can be contacted on the outer side of the lower portion. The barrier metallurgy pattern (4) is upward from the upper surface of the metal pattern 72b = oxygen, and the material pattern 76 protrudes from the insulating interlayer % 可' may include, for example, _. Jin Weihua _ 76 is greater than the metal pattern 7 and has an electric 1 The resistance can be in the exemplary embodiment, the metal oxide pattern is %-shaped, and the ring shape is in the shape of the portion. The metal oxide pattern 76 has a width = 2 = the width of the metal pattern 72b. Metal servant - generated. When the metal oxide pattern = 47; the ringable ring pattern gold oxide pattern 76 has an area that can be substantially smaller than the circular or multi-layer 42 201133757 xi area of the prismatic column structure. 76 has a width smaller than the width of the opening 68. A buried layer pattern 74a is disposed on the metal pattern 72b to completely fill the opening 68. Therefore, the upper surface of the buried layer pattern 74a and the upper surface of the insulating interlayer 66 may be located. Substantially in the same plane, the inner side of the lower portion of the metal oxide pattern 76 may contact the buried layer pattern 74a. In an exemplary embodiment, the buried layer pattern 74a may comprise a material that is substantially slowly oxidized or hardly oxidized. The buried layer pattern 74a may include at least one of titanium, titanium nitride, a button, or a nitride button. These materials may be used alone or in a mixture thereof. Alternatively, the buried layer pattern 74a may include insulation. A material such as an oxide, a nitride or a gas oxide. In an exemplary embodiment 10, the barrier metal layer pattern 7a, the metal pattern 72b, and the i-in layer pattern 74a may be used together as an electrical connection to the conductive The conductive pattern of the region. The metal oxide pattern 76 can be used as a heating electrode because the metal oxide pattern 76 can have high electrical resistance and small area. Figures 21 and 22 illustrate an exemplary embodiment in accordance with the present invention. A cross-sectional view of a method of forming a conductive structure. Referring to Figure 2, an insulating interlayer 66 is formed on a substrate 64 having conductive regions formed thereon. An insulating interlayer 66 is partially engraved to form an open anvil, and the opening 68 partially exposes the substrate. Conductive area on 64. The opening anvil is formed by a lithography process. A barrier metal layer 70 is formed on the insulating interlayer 66, on the bottom of the opening 68, and on the sidewall of the opening. The barrier metal layer 7 can be along the opening 68 and 43 201133757t ^ x^/xl The edge of the edge layer 66 is formed uniformly. When the barrier metal layer 70 is formed on the opening 68, the opening 68 may have a reduced width which is twice the thickness of the barrier metal layer 70. Therefore, the width of the opening 68 can be adjusted by controlling the thickness of the barrier metal layer 70. Thus, the width of the metal pattern 72a and the metal oxide pattern % can be controlled by adjusting the width of the opening 68. A metal layer 72 is formed on the barrier metal layer 70. Metal layer 72 can comprise, for example, a crane. The metal layer 72 can be conformally formed along the contour of the barrier metal layer. The metal layer 72 has a thickness that substantially corresponds to the width of the upper portion of the metal pattern 72a. Therefore, the width of the upper portion of the metal pattern 72a can be adjusted by controlling the thickness of the metal layer 72. A buried layer 74 is formed on the metal layer 72 to completely fill the opening 68. Layer 74 can be formed from a material that oxidizes very slowly or hardly. In an exemplary embodiment, buried layer 74 may comprise a material that is substantially the same as the material of the barrier metal layer. In an exemplary implementation, η λ _ 4 1 少 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / And barriers. Layer 70 is exposed until an insulating interlayer 66 is exposed. The buried layer 74, the metal layer 72, and the barrier gold may be partially removed by the CMp process and the etching process. Thus, the barrier metal layer pattern 7Qa, the preliminary metal pattern 72a, and the buried portion are formed in the opening 68. The layer pattern 74a is incorporated. Each of the barrier metal layer patterns 7a and the initial metal patterns 72a may have a cylindrical shape. The buried layer pattern 74 on the initial pattern 72a fills the opening 68. 201133757 Λ. * Hunting CMP process and partially removing buried layer 74, metal layer 72 two resistance? During the metal layer 70, the insulating interlayer % can be locally ground by a polishing rate substantially greater than the rate of the metal layer 72. Therefore, the initial gold layer pattern 72a, the barrier metal layer pattern 7Ga, and the buried layer pattern 74a are largely above the insulating interlayer 66. For example, the initial metal layer pattern =, the metal layer pattern, the surface above the 7Qa and the buried layer pattern % can be self-exposed, and the upper surface of the edge interlayer 66 slightly protrudes by about 10 angstroms. In Fig. 18, metal oxide is formed on the barrier metal layer pattern 7a in the initial metal layer pattern in the atmosphere containing oxygen, and the case 76 and the metal_72a are formed. The metal oxide pattern % and the metal pattern can be obtained by the same process as that described in the reference 5, and the metal pattern is 72a, which is _古~35^. The metal pattern Hr is at the height of the initial metal layer pattern 72a. Is a pattern 72b. Therefore, the metal pattern is ok, and the layer 66 has a __ shape. Metal Oxidation = Figure ~ has a cylindrical shape extending from the metal pattern 72b. This 'genus' ^ = top material has a lion, and can be insulated / insulating ns on an exemplary embodiment 10, the metal oxide pattern layer pattern can be controlled by the degree of oxidation according to an exemplary implementation For example, it is possible to obtain a face-to-face contact such as a case under the pattern of an oxidized crane product and/or a crane layer having a column shape in the case of not being embossed. It can be used in the oxidation crane. The resistance can be substantially smaller than the resistance of the tungsten oxide pattern. Due to the tungsten pattern and oxygen 45 201133757. Each of the crane patterns can have an easily adjustable thickness and width, so that the conductive structure comprising the tungsten pattern and the tungsten oxide pattern ensures the desired electrical resistance of the various semiconductor memory elements. Figure 23 is a cross-sectional view showing a magnetic memory element in accordance with an exemplary embodiment of the present invention. The magnetic memory device shown in Fig. 23 includes a conductive structure. The structure of this conductive structure is substantially the same as that of the conductive structure described with reference to Fig. 18. In an exemplary embodiment, the magnetic memory component of Figure 23 can have substantially the same configuration as the conductive structure described with reference to Figure 6, except for the conductive structure. Referring to Fig. 23, an m〇S transistor is provided on a semiconductor substrate 400, and a first insulating interlayer 408 covering the MOS transistor is formed on the semiconductor substrate 400 to cover the MOS transistor. A contact plug 410 is formed through the first insulating interlayer 4〇8. The contact plug 410 electrically contacts the impurity region 406 of the MOS transistor. A conductive pattern 412 is disposed on the contact plug 410. A second insulating interlayer 414, overlying the conductive pattern 412, is formed over the first insulating interlayer 408. The opening 415 is formed through the second insulating interlayer 414, and the opening 415 partially exposes the conductive pattern 412. The opening 415 may have the shape of a contact hole. The conductive structure is disposed in the opening 415. The electrically conductive structure can have substantially the same configuration as the electrically conductive structure described with reference to FIG. The conductive structure includes a first barrier metal layer pattern 610 formed on the bottom and sidewalls of the opening 415, a metal pattern 612 on the first barrier metal layer pattern 61, and a buried layer pattern 614 disposed on the metal pattern 612. And a metal oxide pattern 616 extending from the metal pattern 612. 46 1 1201133757 Metal pattern 612 and metal oxide pattern 616 can be coated with tungsten and tungsten oxide, respectively. Metal pattern 612 can have a cylindrical shape, and =3, for example, 614 can fill opening 415. Metal oxide pattern 616 can be overlying layer 415. The metal oxide pattern 616 can be formed by oxidizing the metal. Therefore, when the metal pattern 612 includes tungsten, the "612 oxide pattern 616 includes tungsten oxide. ', 'the metal is mainly at 1; the structure 丨 丨 1 1 1 layer layer 610 and the buried layer pattern 614 can be used together The magnetic memory element is a lower electrode contact. The metal oxide pattern 616 having a relatively high resistance can be used as a heating electrode for heating the free layer pattern in the magnetic tunneling structure of the magnetic memory element. 618 is disposed on the second insulating interlayer 414. The =, the edge interlayer 618 can fill the gap between the adjacent metal oxide patterns 616. The insulating interlayer 618 can comprise a material having a dense structure and good step coverage, for example by The ruthenium oxide obtained by the HDP-CVD process or the ALD process. The upper surface of the third insulating interlayer 618 and the metal oxide pattern 616 may be disposed on substantially the same plane. The upper surface of the first barrier metal layer pattern 010 is covered with a third insulation. The interlayer 618 is such that the first barrier metal layer pattern 61 is not exposed. The magnetic tunnel junction structure is located on the third insulating interlayer 618. The magnetic tunnel junction structure may have the same as that described with reference to FIG. The magnetic tunneling junction structure has substantially the same structure. The free layer pattern 426 of the magnetic tunneling junction structure is disposed on the metal oxide pattern 616. When the metal oxide pattern 616 has a dome-shaped structure, the free layer pattern The contact area between 426 and metal oxide pattern 616 can be reduced. The entanglement efficiency L of the sample 426 can have a surface on the upper surface of the oxide pattern (4). The oxide pattern (4) has a process in which the process is substantially the same as the smooth process, and the magnetic 434, the fifth insulating interlayer (10), the fourth insulating interlayer layer 436, the upper electrode 438, and the bit line. A cross-sectional view of the external image 2 ===^ method according to an exemplary embodiment of the present invention. The conductive structure may be provided with a magnetic di-state 7 as described with reference to FIG. Therefore, except for the process for forming the conductive junction to fabricate the magnetic memory n of FIG. a, the process of which is substantially the same as that described with reference to FIG. 7 is performed in the semiconductor: 412 into the first insulation. 24408, contact plug _ and conductive Referring to Fig. 24', a second insulating interlayer 414 covering the conductive pattern 412 is formed over the first insulating loss layer 408. The second insulating interlayer 4 is partially engraved to form an opening 415 that at least partially exposes the conductive pattern 412. The conductive structure is formed to be substantially filled with the opening α 415 by substantially the same as those described with reference to FIGS. 21 and 22. The conductive structure may protrude above the opening 415. The conductive structure includes a barrier metal layer pattern having a cylindrical shape _, A metal pattern 418 having a cylindrical shape, a ruthenium layer pattern (4) filled with an opening, and a metal oxide 48 201133757 pattern 016 extending upward from the metal pattern (10). The metal pattern 612 and the metal oxide pattern 616 may be separated into, for example, a crane and an oxidized crane. Referring to Figure 25, a third insulating interlayer 618 overlying the metal oxide pattern 616 is formed over the second insulating interlayer 414. The third insulating interlayer 6丨8 may comprise a material having a dense structure and stepped over, and having good cover properties. For example, the second insulating interlayer 618 can comprise germanium oxide by HDP_CVD process or ald^j. The third insulating interlayer 618 is partially removed until the metal oxide pattern 616 is exposed. The third insulating loss layer can be locally removed by the CMP process. 61 = Here, the transfer gold pattern (10) is exposed by the interlayer 61 曰 8 . Since the third insulating interlayer 6丨8 has a dense structure, the third insulating layer (10) and the metal oxide pattern 616 may have a uniform surface without coarse after performing the c Μρ process to partially remove the third insulating interlayer 618. Chain surface. As shown in FIG. 23, a magnetic tunnel junction structure is formed on the third insulating interlayer 618 and the metal oxide pattern 616. A fourth insulating interlayer 434, a fifth insulating interlayer 436, an upper electrode 438, and a bit line 44A covering the magnetic-penetrating surface structure are formed on the third insulating interlayer 618. The description for forming the fourth insulating interlayer 434, the fifth insulating interlayer 436, the upper electrode 438, and the bit line 440 can be substantially the same as described with reference to FIG. Figure 26 is a cross-sectional view of a phase change memory element in accordance with an exemplary embodiment of the present invention. The phase change memory element of Figure 1 may comprise a conductive structure, the structure of which is substantially the same as the conductive structure described with reference to Figure 1 or Figure 22. In an exemplary embodiment, the phase change memory component of Figures 3 49 201133757 may have substantially the same configuration as the phase change memory component described with reference to Figure U, in addition to the conductive structure.

Referring to Fig. 26', a first insulating interlayer 494, a P-N diode 500, and a second insulating interlayer 504 are disposed on the substrate 490. The first insulating interlayer 494 includes a first opening 'P-N diode 500 in the first opening. Forming a second opening through the second insulating interlayer 504 505 The αρ_Ν diode 500 may be partially exposed through the second opening 505. A barrier metal layer pattern 65A, a metal pattern 652, a buried layer pattern 654, and a metal oxide pattern 656 are disposed in the second opening 505. Metal pattern 652 and metal oxide pattern 656 may comprise, for example, tungsten and tungsten oxide, respectively. The barrier metal layer pattern 650, the metal pattern 652, the buried layer pattern 654, and the metal oxide pattern 656 may have the first barrier metal layer pattern 70a, the metal pattern 72b, and the buried layer pattern 74a as described with reference to FIG. The metal oxide pattern 67 has substantially the same structure. Metal oxide pattern 656 can be added to phase change structure 514. > ^ A third insulating interlayer 66 is formed on the second insulating interlayer 504. The jth and the edge interlayer 660 may fill the gap between the adjacent metal oxide patterns 656. The phase change structure Μ4 is disposed on the metal oxide pattern 656 and the third annihilation 2 060. Phase change structure 514 contacts metal oxide pattern 656. When the oxide pattern 656 has a ring shape, the contact area between the metal oxide pattern 65 and the target structure 5 can be reduced. Therefore, the phase transition can easily occur in the phase change structure 5 i 4 by the focal mechanism. An upper electrode 516, a fourth insulating delamination Μ, and an upper electrode contact 522 are provided on the phase change structure 514. 50 201133757 According to an exemplary embodiment, the phase change memory element can ensure improved Joule heating efficiency and reduced reset current. The resistance distribution of the set state and the reset state of the phase change memory element can be reduced so that the set state and the reset state can be significantly different when the phase change memory element is operated. In the process of manufacturing the phase change memory device shown in FIG. 26, the first insulating interlayer 494, the PN diode 500, and the second insulating are obtained on the substrate 490 by a process substantially the same as that described with reference to FIG. The interlayer 504 and the second opening 505. Then, a conductive structure for filling the second opening 505 and protruding over the second opening 505 can be formed by a process substantially the same as that described with reference to Figs. 21 and 22. A third insulating interlayer 660 covering the metal oxide pattern 656 of the conductive structure is formed on the second insulating interlayer 504, and then the third insulating interlayer 660' is partially removed by a CMP process to thereby expose the metal oxide pattern 656. . A phase change structure 514, an upper electrode 516, a fourth insulating interlayer 518, and an upper electrode contact 522 are formed on the metal oxide pattern 656 and the third insulating interlayer 660 by a process substantially the same as that described with reference to FIG. Figure 27 is a cross-sectional view showing a conductive crusted structure in accordance with an exemplary embodiment of the present invention. An insulating interlayer 66 is provided on the substrate 64 as seen in FIG. The insulating loss layer 66 includes an opening 68' opening 68 that exposes the conductive regions on the substrate 64. A spacer 80 comprising an insulating material is located on the sidewall of the opening 68. For example, the spacer 80 may comprise tantalum nitride or hafnium oxynitride. In an example two embodiment, the barrier metal layer may not be formed on the sidewalls of the opening 68. In a 51 20113373⁄4 embodiment, a barrier metal layer may be disposed on the spacers 8 and the substrate 64 in the opening 68. A metal pattern 82 including a crane and having a cylindrical shape is disposed in the opening 68. Metal pattern 82 can be formed along the contours of opening 68 and substrate 64. A buried layer pattern 84 is disposed on the metal pattern 82. The buried layer pattern 84 fills the opening 68. A metal oxide pattern 86 containing tungsten oxide is disposed on the metal pattern 82. The metal oxide pattern 86 extends from the metal pattern 82. The metal pattern 82, the buried layer pattern 84, and the metal oxide pattern 86 may have substantially the same structure as the metal pattern 72a, the buried layer pattern 74a, and the metal oxide pattern 7.6 described with reference to Fig. 18. In a method of forming the conductive structure of FIG. 27, an insulating interlayer 66 is formed on the substrate 64. The insulating interlayer 66 is partially etched to form an opening 68 that exposes a portion of the substrate 64. The opening 68 can be formed by a lithography process. A spacer 80 is disposed on the side wall of the opening 68. A metal layer containing a crane is formed on the spacer 80, the substrate 64, and the insulating interlayer 66. This metal layer can be conformally formed along the contour of the opening 68. The metal layer and spacers 80 are partially removed by the CPM process until the insulating interlayer 66 is exposed. Thereby, an initial metal pattern is formed in the opening 68. The initial metal pattern is heat treated in an atmosphere containing oxygen, whereby a metal pattern 82 and a metal oxide pattern 86 containing tungsten oxide are formed in the opening 68. As a result, a conductive structure having substantially the same configuration as that of the conductive structure described with reference to Fig. 27 was formed. In an exemplary embodiment, the conductive structure shown in FIG. 27 can be used in the magnetic memory component of FIG. 6, the phase change memory component of FIG. 11, or the phase 52 201133757 variable memory component of FIG. Figure 28 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. Referring to Fig. 28, a first insulating layer 494 and a P-N one body 5 are disposed on the substrate 490. The first insulating interlayer 494 and the p_N diode 5' can be substantially identical to those described with reference to FIG. A metal pattern 53〇a containing tungsten is disposed in the first insulating interlayer 494. The metal pattern 530a is in electrical contact with the p_N diode 5〇〇. A second insulating interlayer covering the metal pattern 53A is formed on the first insulating interlayer 494. A metal oxide pattern 536 containing yttrium oxide is disposed on the metal pattern 530a. The metal oxide pattern 536 may extend from the metal pattern 53A and may have a cylindrical shape. An insulating layer pattern 534 is formed on the inner sidewall of the metal pattern 530a. The insulating layer pattern 534 may comprise an oxide such as oxidized ground. Alternatively, S3 Ϊ/534 may have a multilayer structure. The multilayer structure includes a ruthenium film and an oxidized dicing film. The phase change junction is arranged on the 241 and the second insulating interlayer 5〇5. =it =14 The contact metal oxide pattern is light. Upper electrode 516 and upper electrode contact 522 are disposed on phase change structure 514. Figure 29 is a cross-sectional view showing a method of manufacturing a phase 3 memory element according to an exemplary embodiment of the invention. Referring to Fig. 29', a spacer layer pattern and a P-N diode 500 are formed on the slab 4 by substantially the same manufacturing method as that described in Fig. 12 with a plate 490 At.曰 (2) Case 492, the first insulation interlayer 494 53 201133757.  An initial metal pattern 530' containing a crane is formed on the body 500, and a second insulating clip > f 504 covering the initial metal pattern 53A is formed on the fourth battery. The second insulating interlayer 5〇4 is partially engraved to form a first opening 505'. The second opening σ 505 exposes a portion of the initial metal pattern 53〇. A first insulating layer is formed on the bottom and sidewalls of the opening 505. The first insulating layer may comprise, for example, an oxide, a nitride or an oxynitride. For example, the first insulating layer may include oxygen cutting, nitrogen cutting or oxynitridation, and the first insulating layer is partially etched by an anisotropic etching process to form an internal gap on the sidewall of the second opening 505. wall. A second insulating layer is formed in the opening 505 of the gap wall. The first oxide, nitride or oxynitride. The in-situ and etched-first insulating layer may comprise a material that is materially and selectively selective with respect to the first insulating layer. For example, in the case of nitriding, the second insulating layer may comprise bismuth fossils. Hao insulation in addition to the second insulation layer 'until the inner gap wall is exposed and the second removal = two can be formed by the CMP process and / or the return of the shoulder shape == 3 =: 7 in the second,: Jing Cheng = If the process or non-equal 1 is used, the insulating layer pattern _ may include oxygen oxide in the broad formation of the second insulating/third opening 532. In the exemplary embodiment, the insulating layer pattern 534 is seen. The thickness varies. 54 201133757 Referring to FIG. 28, by inverting the initial pattern 530 exposed by the third opening 532, & + @一„, the genus of the genus genus includes a tungsten oxide oxide pattern 536. Metal oxidation The object pattern 536 can be filled with the first. Three ΐ I f2 ° simultaneously from the formation of the metal oxide pattern * 536 from: : The metal pattern 530 forms a metal pattern 53 〇 a. That is, the initial metal pattern 53 is partially consumed by oxidation so that the initial metal pattern 53 becomes the metal pattern 53A. The metal pattern 530a and the metal oxide pattern 536 are partially removed until the second insulating layer 5 〇 4 is exposed. The metal pattern 53A and the metal oxide pattern 536 can be partially removed by, for example, a CMP process. ▲ A phase change structure 514 is formed on the metal oxide pattern 536 and the second insulating interlayer 5?4. The upper electrode 516 and the upper electrode contact 522 are sequentially formed on the phase change structure 514. Figure 30 is a cross-sectional view showing a method of fabricating a conductive structure in accordance with an exemplary embodiment of the present invention. Referring to Fig. 30, an isolation layer pattern 492, a first insulating interlayer 494, and a P-N diode 500 are formed on the substrate 490 by substantially the same process as described with reference to FIG. The initial metal pattern 530, the second insulating interlayer 504, and the second opening 5〇5 are formed by a process substantially the same as that described with reference to Fig. 29, wherein the initial metal pattern 530 contains tungsten. The initial metal pattern 53A contacts the p_N diode 500' and the second insulating interlayer 504 covers the initial metal pattern 53A. The second opening 505 partially exposes the upper surface of the initial metal pattern 53. A first insulating layer is formed on the bottom and sidewalls of the opening 505. A second insulating layer is formed on the first 201133757 insulating layer to completely fill the second opening 505. In an exemplary embodiment, the second insulating layer may comprise a material having side selectivity with respect to the first insulating material. The first insulating layer and the second insulating layer are partially removed until the second insulating layer 504 is exposed. The partial lateral side-insulating layer and the second insulating layer are then patterned into an insulating layer pattern 534 having a second opening 532. The insulating layer pattern can be formed by a non-specific etching process. The insulating layer pattern 534 may have a cylindrical shape. Since the first insulating layer is partially retained in the second opening 5〇5, the insulation 544 includes yttrium oxide and tantalum nitride. That is, the insulating layer pattern edge 4 includes a remaining portion of the first insulating layer and the second insulating layer. The metal pattern 53A, the metal oxide pattern 536 containing tungsten oxide, the phase change structure 514, and the upper electrode 5 are sequentially formed on the insulating layer pattern 534 by a process substantially the same as that described with reference to FIG. 6 and upper electrode contact 522. Figure 31 is a cross-sectional view showing a phase change memory element according to an exemplary embodiment of the present invention. In addition to the phase change structure, the phase change memory device of Figure 31 can have substantially the same configuration as the phase change memory device described with reference to Figure 28. Referring to Fig. 31, the phase change structure 514a of the phase change memory element has a lower portion extending from the upper portion of the metal oxide pattern 536a containing tungsten oxide. Therefore, the phase change structure 514a may have a cylindrical shape. Phase change structure 514a protrudes into second insulating interlayer 504. A method of fabricating the phase change memory component of Figure 31 can be substantially identical to that described with reference to Figure 29. 56 201133757r In a method of fabricating the phase change memory device of FIG. 31, the initial metal pattern exposed by the third opening 532 and containing tungsten is oxidized to form a metal oxide pattern 536a and metal containing the oxide crane Pattern 530 Here, the metal oxide pattern 536a partially fills the second opening 'Μ' metal oxide pattern 536a and the metal pattern 530a is not partially removed. A phase change structure 514a' is formed on the metal oxide pattern 536a and the second insulating interlayer 5?4 to completely fill the third opening 532 because the third opening 532 is partially filled with the metal oxide pattern 536a. In the exemplary embodiment, the conductive node used as the heating electrode shown in Fig. 28 is used in the magnetic memory element of Fig. 6. That is, the conductive structure in contact with the magnetic tunneling interface structure in Fig. 6 can be replaced with the conductive structure shown in Fig. 28. / Figure 32 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. Referring to Figures 32 and 33, a metal pattern 92a containing tungsten is disposed on the substrate 90. The metal pattern 92a has an upper portion including a groove formed thereon. That is, by controlling the processing conditions of the subsequent heat treatment process, the center of the upper portion of the initial metal pattern 92 can be oxidized faster than the edge of the upper portion of the initial metal pattern 92. The groove of the metal pattern 92a may have a circular shape such as a circular arc shape. Thereby, the edge of the upper portion of the metal pattern 92 & can be substantially higher than the center of the upper portion of the metal pattern. An insulating interlayer 94 covering the metal pattern 92a is formed on the substrate 90. An opening 96 is provided through the insulating interlayer 94. The opening 96 exposes an upper portion of the metal pattern 92a having a groove. 57 201133757 A metal oxide pattern containing oxidized crane is placed on the genus pattern 92a. The metal oxide pattern 98 can fill the opening %. The metal oxide pattern 98 can be produced by the metal pattern 92a. For example, a metal oxide pattern can be obtained by oxidizing the metal pattern 92a. Figure 33 is a cross-sectional view of a method of fabricating a conductive structure that is not an exemplary implementation of the present invention. > Referring to Fig. 33, a metal layer containing tungsten is formed on the substrate 90, and then the metal layer is patterned' to form an initial metal pattern % on the substrate 9G. An insulating interlayer 94 is formed on the substrate 90 to cover the initial metal pattern %. The insulating interlayer 94 is partially etched to form the opening 96, and the opening % is at least partially reduced. The opening σ % can be formed by a micro-pass. Referring to Figures 32 and 33, the initial metal pattern 92 exposed by the opening 96 is heat-treated in an atmosphere containing oxygen to form a metal oxide pattern 98 and a metal pattern 92a on the substrate 9A. For example, the metal pattern 98 and the metal pattern 92a include tungsten oxide and tungsten, respectively. In the heat treatment for forming the metal oxide pattern 98 and the metal pattern 92a, the initial metal pattern 92 may be reacted with oxygen to expand upward in the opening 96. Thereby, the metal oxide pattern 98 filling the opening 96 can be formed on the metal pattern 92a. At the same time, the upper portion of the initial metal pattern % may be oxidized so that the initial metal pattern 92 can become the metal pattern 92a. The process of the heat treatment process can be used to make the center of the upper portion of the initial metal pattern 92 more than the initial metal pattern 92. The upper edge oxidizes faster. Therefore, the metal pattern 92a may have an upper portion including a circular groove, 58 201133757 and the metal oxide pattern 98 may have a protrusion corresponding to the groove of the metal pattern 92a. In an exemplary embodiment, the metal oxide pattern 98 and the insulating interlayer 94 may be planarized by a planarization process. For example, the metal oxide pattern 98 and the insulating interlayer 94 can be subjected to a CMP process. Figure 34 is a cross-sectional view showing a magnetic memory element in accordance with an exemplary embodiment of the present invention. The magnetic memory device of Fig. 34 includes a conductive pattern and a lower electrode contact. The conductive pattern and the lower electrode contact have substantially the same configuration as the conductive pattern and the lower electrode contact of the magnetic memory element described with reference to Fig. 29. The magnetic memory device of Figure 34 can have substantially the same configuration as the magnetic memory device described with reference to Figure 6, except for the conductive pattern and the lower electrode contacts. Referring to Fig. 34', a conductive structure is disposed on the first insulating interlayer 408 and the contact plug 410. The conductive structure may have a configuration substantially the same as that of the conductive structure described with reference to FIG. The conductive structure has a metal pattern 450 comprising tungsten and a metal oxide pattern 454 comprising tungsten oxide. The metal pattern 450 contacts the contact plug 410. The metal pattern 450 has an upper portion including a circular groove. The edge of the upper portion of the metal pattern 450 may be substantially higher than the center of the upper portion of the metal pattern 450. A second insulating interlayer 452 covering the metal pattern 450 is disposed on the first insulating interlayer 408. An opening 453 is provided through the second insulating interlayer 452. The opening 453 exposes at least a portion of the upper portion of the metal pattern 45 having a circular groove. A metal oxide pattern containing an oxidized crane is disposed on the metal pattern 450. 59 201133757 Fills the opening 453. The metal oxide pattern #4 can be produced by patterning the metal pattern 450. Metal oxide pattern 454 450 is oxidized from metal 454. The metal oxide pattern 454 玎田仏, the sexual memory is a hybrid addition and subtraction pole, and (4) the heating magnetic π field interface structure. The metal oxide pattern 454 can be used as a mosquito element electrode contact. The magnetic A read 'body element of Fig. 34' except the conductive pattern and the lower electrode ▲ has a group substantially 5 with the miscellaneous element described in the reference 6, 4', except for forming a conductive pattern and powering off The magnetic memory element of the process diagram 34 can be manufactured by a process substantially the same as that described with reference to FIGS. 7 to W. The conductive pattern and the lower electrode contacts can be formed by a process substantially parallel to the side of the reference 32. Figure 35 is a cross-sectional view of a magnetic memory element in accordance with an exemplary embodiment of the present invention. The magnetic Z memory element of Fig. 35 may have substantially the same configuration as the magnetic memory element described with reference to Fig. 6, except for the conductive pattern and the lower electrode contact. The magnetic memory device of FIG. 35 includes a conductive pattern and a lower electrode having substantially the same configuration as the conductive pattern and the lower electrode contact of the conductive structure described with reference to FIG. 28 except for the spacer on the sidewall of the metal oxide pattern. Contact. Referring to Figure 35, a spacer 455 is provided on the sidewall of the opening 453 formed through the second insulating interlayer 452. The spacer 455 can reduce the width of the opening 453, and thus the metal oxide pattern 456 comprising tungsten oxide can have a reduced amount of upper portion width than the conductive structure described with reference to FIG. The process of manufacturing the magnetic memory device of FIG. 35 can be substantially the same as the manufacturing process of the magnetic memory device described with reference to FIG. In the exemplary embodiment, after the opening 453 is formed through the second insulating interlayer 452, a spacer 455 is formed on the sidewall of the opening 453. The spacer 455 may, for example, comprise an oxide, a nitride, an oxynitride. For example, the spacer portion may comprise hafnium oxide, tantalum nitride or hafnium oxynitride. Figure 36 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. Referring to Fig. 36, a first insulating interlayer 494 and a P N one body 5G0 are provided on the substrate 490. The metal pattern containing the crane is placed on the first insulating layer 494. The metal pattern 5〇2a contacts the p_N diode $(8). The metal pattern 502a may have an upper portion including a circular groove. In an exemplary embodiment, a circular groove can be formed during a subsequent oxidation process. A second, 邑, 彖 层 layer 550 covering the metal pattern 5〇2a is disposed on the first insulating interlayer 494. An opening is formed through the second insulating interlayer 55. The opening 553 exposes the metal pattern 502a at least partially. At the side wall 552 of the opening 553. The spacer 552 can comprise an insulating material. When the gap wall 55 = is in the opening 553, the opening 553 may have a reduced width. In the opening 553 of the upper gap 552, the metal oxide pattern 554 of the crane is oxidized in the metal pattern 502a. Metal oxides can be generated from the metal map by local oxidation of the metal i:tr:;5r. On top of the r, the metal oxide pattern 5 Μ can be partially sweat 553. Metal oxide pattern 554 can be used as a lower electrode contact in phase change memory element 61 201133757. In the metal oxide pattern S54 "π m ^ structure fills the opening 553 and protrudes = configures the phase change structure 556. The phase change junction may have an opening 553 located in the opening 553. The phase change structure 556 is upper. The phase change junction The width of the upper portion above the opening 553. The width of the crucible can be substantially smaller than the upper electrode provided thereon, and the second insulating layer is provided, the Vli疋 will V ^ the invention The conductive junction 实施q of the embodiment. In addition to the metal oxide containing the oxidized crane, the H structure of the partially identical conductive structure may have the process of the conductive structure of the H37 of 29, which may be substantially In the same embodiment as the prime phase of the reference figure, the first insulating layer 1Q is provided on the substrate 8 by controlling the initial metal diagram and the phase change pattern according to the exemplary embodiment of the present invention. Ρ_Ν = the diode body U and the first insulating layer are disposed on the conductive pattern 12a of the group 1. The conductive pattern 12a may be a metal. For example, the conductive pattern 12a may be covered with a tungsten _ edge clip to cover the pattern The second insulating layer pattern Μ. Through the second insulating interlayer, the figure 14 Forming a first opening 62 201133757 16. The opening 16 at least partially exposes the conductive pattern 12 & the second insulating interlayer pattern 14 may comprise an oxide or a nitride. For example, the second insulating interlayer pattern 14 may comprise hafnium oxide or nitrogen In an exemplary embodiment, the conductive pattern 12a has an upper portion, and the upper portion is formed with a groove formed thereon. The edge of the upper portion of the conductive pattern 12a is applied to the center of the upper portion of the electric pattern 12a. In an exemplary embodiment, by controlling the process conditions of the heat treatment process, the center of the crucible above the initial metal pattern can be oxidized faster than the edge of the upper portion of the initial metal pattern. The lower electrode contact is disposed in the first opening 16. Point 18. The power-off may include a metal oxide generated by the conductive pattern 12a. The lower electrode contact 18 may fill the first opening 16. In an exemplary embodiment, the conductive pattern 12a may be oxidized to obtain the lower portion. The electrode contact 18. For example, the metal oxide generated by the conductive pattern 12a may grow upward in the first opening 16, thereby forming the lower electrode contact 18 in the first opening 16. The conductive pattern 12a It may have a circular recess' and the lower electrode contact. The dot 18 has a circular protrusion which is opposed to the circular groove of the conductive pattern 12a. When the lower electrode contact 18 includes a circular projection and the conductive pattern 12a has a circular recess, the upper surface of the lower electrode contact 18 may be spaced further apart from the upper surface of the guide 12a. Therefore, the heat generated between the phase change structure coffee and the lower electrode contact 18 can be further restrained by reducing the loss of heat. That is, the phase change structure 22 & can have Joule heating efficiency. In an exemplary embodiment, the conductive pattern 12a may comprise a crane, and thus the lower electrode contact 18 may comprise tungsten oxide. 63 201133757 A spacer 20 is disposed on a side wall of the first opening 16. The spacer 2 is connected to the electrode contact 18. The width of the first opening 16 may be reduced by the formation of the spacer 2〇. Therefore, the contact area between the lower electrode contact 18 and the phase change structure 22a can also be reduced. The spacer 20 may comprise a nitride such as tantalum nitride or a nitrogen oxide such as nitrogen oxide. The phase change structure 22a is disposed on the lower electrode contact 18 to completely fill the first opening 16. In an exemplary embodiment, the amount of contact between the lower electrode contact 18 and the phase change structure 22a is reduced by the contact area of the spacer 20 disposed on the lower electrode contact 18. The phase change structure 22a may comprise a chalcogenide whose structure varies between a crystalline state and an amorphous state. When the chalcogenide is in a crystalline state, the chalcogenide has a relatively high reflectance and a relatively low electrical resistance. When the chalcogenide is amorphous, the chalcogenide has low reflectance and high electrical resistance. In an exemplary embodiment, the chalcogenide compound may comprise an alloy of bismuth-tellurium-tellurium. The phase change structure 22a filling the first opening 16 may protrude above the second insulating interlayer pattern 14. In the exemplary embodiment, the upper portion of the phase change structure 22a may have a width greater than the width of the lower portion thereof. The upper electrode 24 is disposed on the f-phase change structure 22a. The upper electrode 24 may comprise an example of titanium. The ± electrode 24 may have the same width as the σ ρ above the phase change structure 22a. A third insulating interlayer pattern is disposed on the 26H insulating interlayer pattern 14 ... H edge material ^ ^ upper electrode 24 and extinguishing structure 22; the edge sandwich pattern 26 forms a second opening 28. The second opening exposes the upper electrode 24 at least marginally. 64 201133757! -----r-l The upper electrode contact 30 is disposed in the second opening 28. The upper electrode contact 30 may comprise a metal such as tungsten. According to an exemplary embodiment, the phase change memory element may have an electrode contact comprising a metal oxide, the metal oxide being produced from a conductive pattern comprising a metal. In an exemplary embodiment, the lower electrode contact may have a large electrical resistance. Since the phase change memory element includes the lower electrode contact formed by the metal oxide, the phase change memory element ensures that the reset current is reduced by increasing the Joule heating efficiency. Since the phase change structure has a small resistance distribution between the set state and the reset state, the phase change memory element can have significantly different set states and reset states. In an exemplary embodiment, since the lower electrode contact is disposed under the phase change structure in the opening π, the opening configured with the phase change structure may have a reduced aspect ratio. Therefore, voids or slits may not be generated in the phase change structure to prevent operation failure of the phase change memory element. 39 to 44 are diagrams showing a method (4) of manufacturing a phase memory element according to the present invention. Referring to Fig. 39, a first insulating layer 1 and a dummy '8a region 8a are formed on the substrate 8 on the substrate 8. The first insulating interlayer 10 can cover the isolation layer pattern and the impurities. The formation of the oxide such as gasification fossils through the first insulating interlayer 1 _ body 11 can electrically contact the impurity region 8a. In K J' pole body 11. An initial conductive pattern i, a torsion body 11, and a first insulating P-N diode 11 are formed on the p-N bipolar interlayer 10. Initial Conductive Pattern 12 Knife Start Conductive Pattern 12 Contact In an exemplary embodiment, the initial ft metal is introduced. The I electrical pattern 12 can comprise a material having a low 65 201133757 lpif resistance, the oxide of the material being electrically conductive and the oxide of the material expanding upward as the material is oxidized. For example, the initial conductive pattern 12 can comprise a metal such as tungsten. A second insulating interlayer is formed on the first insulating interlayer 10 to cover the initial conductive pattern 12. The second insulating interlayer may comprise an oxide such as yttria, such as a nitride of nitride. The second insulating interlayer is partially etched to form a first opening 16, and the first opening 16 partially exposes the initial conductive pattern 12. The first opening 12 may have the shape of a contact hole. To form the first opening 16, a second insulating interlayer pattern 14 having a first opening 16 is provided on the first insulating interlayer. Referring to Fig. 40, a portion of the initial conductive pattern 12 exposed through the first opening 16 is heat-treated in an oxygen atmosphere to form a lower electrode contact 18 on the initial conductive pattern 12. For example, oxygen can be reacted with the initial conductive pattern 12, and the reactive portion of the initial conductive pattern 12 can be thermally expanded toward the first opening 16, thereby forming the lower electrode contact 18. The lower electrode contact occupies the first opening 16 in a partial manner. In an exemplary embodiment, the lower electrode contact 8 may include a metal oxide produced by the metal contained in the initial conductive pattern 12. The electrical resistance of the electrode contact 18 underlying the metal oxide can be substantially greater than the initial conductive pattern 12. 'σ while heat-treating the initial conductive pattern 12 in an oxygen atmosphere' additionally reacts the exposed portion of the initial conductive pattern 12 with oxygen so that the lower electrode contact 18 can extend laterally along the upper portion of the initial conductive pattern 12. Thereby, the initial conductive pattern 12 is changed to the conductive pattern 66 201133757 12a on which the groove is formed. In an exemplary embodiment, the groove may have a sloped side wall. The lower electrode contact 18 may have a laterally enlarged lower portion which is located in the recess of the conductive pattern 12a. For example, the lower electrode 18 may have an arrow shape that is truncated. As described above, according to the heat treatment process, the conductive pattern 12a has a groove and the lower electrode contact 18 has an enlarged lower portion. Therefore, the contact area between the conductive pattern and the lower electrode 18 can be increased. In an exemplary embodiment, the heat treatment process may include a plasma treatment or an RTA process. For example, the conductive pattern 12a and the lower electrode 18 can be formed by a power treatment or an RTA process. Alternatively, the conductive patterns 12& and the lower electrode 18 can be obtained by sequentially performing an electroforming process and an RTA process. According to an exemplary embodiment, the thickness of the lower electrode contact 18 can be varied by controlling the conditions of the heat treatment process. For example, the lower electrode 18 may have a thickness of from about angstrom to about fine, as measured from the upper surface of the conductive pattern Ua. In an exemplary embodiment, the conductive pattern 12a may include tungsten. In a first embodiment, the lower electrode contact 18 can comprise ruthenium oxide. It can be oxidized in oxygen cranes, and cerium oxide can be rapidly expanded. Oxidized cranes can be larger than. Resistance, and can also be resistant to _ in the wet process. In order to ensure that the conductive pattern i2a and/or the lower electrode H have a long-lasting resistance, the conductive pattern 12a and the lower electrode contact 18 may respectively contain !| and an oxidized crane. 2 in the atmosphere. Implement the shooting. The heat treatment residue may be subjected to an RTA process at a temperature of about 〇〇C to about 6 〇〇C to about one minute 67 201133757 Γ minutes. Alternatively, the heat treatment process can be carried out by applying a power of from about 20 watts to about watts in the oxygen-containing gas to about 1 minute to about 1 minute. (4) Light-bearing children implement T--- The electrode contacts are below the middle of 16 without any layer deposition and singularity. Thereby, the lower electrode 18 can be obtained by a simplified process. f The formation of the spacer layer on the puncture 18 is due to the thickness of the wide wall forming layer of the =r surface-opening 16 so that the first partial _axis layer, called the first σ丨, is not (10) bribe And get. width. The width can be substantially the same as the material formed between the layers 11a2. The electrode contacts 18 and the spacers 20 form a phase change 2: an opening 16. The phase change material layer 22 can be formed using a chalcogenide compound, for example, using an alloy of 锗_锑_碲. Due to the presence of the spacers 20, the contact area between the lower electrode contacts 18 and the phase change material layer 22 is reduced. Thus, portions of the phase change material layer 22 in which the phase transition occurs due to the Joule heating effect can have a reduced area, thereby reducing the reset current in the phase change memory element. Since the lower electrode contact 18 is provided in the first opening 16, the first opening 16 in which the phase change material layer 22 is disposed may have a reduced aspect ratio. Therefore, the phase change material layer 22 can be easily formed in the first opening 16 by light 68 201133757 without creating voids or slits in the phase change material layer 22. Referring to Fig. 43', an upper electrode layer is formed on the phase change material layer 22. The upper electrode layer may comprise a metal nitride. For example, the upper electrode layer may comprise nitride. The upper electrode layer and the phase change material layer 22 are patterned to form a phase change structure 22a and an upper electrode 24. The phase change structure 22a is formed on the lower electrode contact 18 and the first insulating interlayer 14 and the upper electrode is disposed on the phase change structure 22a. Here, phase change, ,,. The lower portion of the structure 22a is located in the first opening 16, and the upper portion of the phase change structure protrudes from the second insulating interlayer pattern 14. A third insulating interlayer is formed on the second insulating interlayer 14, >, and the phase change structure 22 & The third insulating clip is locally etched; the first: the second opening 28 of the upper electrode 24 is exposed. By this, case 26. The second door 9 is a third insulating interlayer pattern having the second opening 28. The IS D 28 may have a shape such as a contact hole. Forming a power-on 忑: Γ is configured with a conductive material such that, in the second opening 28, the upper electrode contacts, and the upper electrode contact 3 〇 may comprise metal. For example, under the oxide ^ can contain cranes. In this way, a phase change memory element having a gold-containing picture 45 H-contact 18 is obtained. The recall of the body element according to the present invention - the implementation of the phase change of the phase change, Figure 45 of the figure. Except that no spacer is provided on the sidewall of the first opening. The memory element H memory element can have the same configuration as described in reference 38 with reference to Figure 45. A lower electrode contact 18 is provided in the first opening 16 through the second insulating interlayer pattern 14 on the substrate 8. The lower electrode contact 18 partially fills the first opening 16 and contains a metal oxide. A phase change structure Ua is disposed on the lower electrode contact 18. The phase change structure 22a 3 = t ^ the first opening 16 ° The phase change structure 22a has an upper surface which is opposite to the upper surface of the second insulating interlayer pattern 14. The upper electrode 24 is located on the phase change structure 22a. 26, the first insulating interlayer _ 14 is disposed on the fourth insulating interlayer pattern 26 to cover the upper opening 24 and the phase change structure 22a by the third insulating interlayer pattern opening 28 through the third insulating interlayer pattern 26 to form a second opening 28. The second opening e ^ partially exposes the upper electrode 24. The upper electrode contact 30 is disposed in the second J σ 28 . The phase change 5 self-remembering element has no gap wall on the side wall of the phase change structure 22a, so the connection between the phase change structure melon and the lower electrode contact 18 is the same as the first The width of the opening 16. Thus, Figure 45 can be made by a simplified process while ensuring the desired characteristics of the page. Eight & Figure 46 is an exemplary implementation in accordance with the present invention. A cross-sectional view of a method of phase-change memory elements of the example. The phase change of the phase change memory of Figure 45 is made, and the method of the component can be the same as that described in Figure 4G. The process provides a resulting structure having substantially the same configuration as that of the reference frame 4. Referring to Figure 46, a phase 22 is formed on the second insulating interlayer bet M to fill the first opening 16 in which the lower electrode contact 18 is formed. The Width 20 Π 33757 does not form a spacer on the sidewall of the first opening 16. Next, the phase change memory element of the circle 45 can be obtained by a process substantially the same as that described with reference to FIGS. 43 and 44. 47 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. The phase change memory element may have a configuration in which the unit cells are configured in an array structure. Referring to Figure 47', a first insulating interlayer pattern 102 is disposed on a substrate 1A defining an isolation region 10, such as an active region. An insulating interlayer pattern 1〇2 forms a first opening 1〇4. The first opening 104 may be disposed at a portion of the substrate 10 that is formed with a unit cell of a phase change δ-resonance element. The first opening 1〇4 may be repeated. Each of the first openings 104 may have a shape of a contact hole. The first opening 104 exposes a predetermined portion of the substrate 1〇〇. The first opening 104 is respectively disposed with a Ρ-Ν diode 1 〇 6. In an exemplary embodiment, a vertical Ρ_Ν diode 106 is disposed in the first opening 104. Each vertical type 1>_>; [dipoles 1 〇 6 may include, for example, polysilicon. 1 > _: The diode 10 ό can partially fill the first opening 1 〇 4. For example, the ρ_ Ν diode 106 can fill the lower portion of the first opening 1 〇 4. The metal 矽 is disposed on the Ρ-Ν diode 1 〇 6 The pattern 1〇8. The metal halide pattern 108 reduces the Ρ-Ν diode 106 and the conductive pattern 11 Contact resistance between a. Each metal halide pattern 108 may comprise, for example, sillimanite, titanium hydride, nickel hydride or tungsten ruthenium. The conductive pattern 110a is disposed on the metal hydride pattern 1 〇 8. Each conductive pattern 110a may include The metal of the small resistance. Here, the upper surface of the conductive pattern may be substantially lower than the upper end of the first opening 106. Conductive 71 201133757 mf V/A JKAJ^ The pattern ll〇a may be above the ancient a 110a, * There is a portion including a circular groove. That is, the conductive pattern may be higher than the center of the upper portion of the conductive pattern 11a in an example. In the package example, each of the conductive patterns 11a may include tungsten. The insulating loss-loss pattern is removed from the conductive pattern UGa to provide a second, for example, oxidized. The first insulating interlayer pattern I12 may include an oxide, 114. The second opening forms a second opening through the second insulating interlayer pattern 112. The first sweating port 114 partially exposes the conductive pattern UOa. Each of the ^ - network ports ΐΐ 4 · όΓ 曰 中, the second Η /, has the shape of the contact hole. The width of an exemplary embodiment can be substantially smaller than the conductive pattern in the conductive pattern 116 D 114 to apply the lower electrode contact ® ^ . The electrode contact U6 may comprise a gold generated by the conductive pattern 110a. The lower electrode contact 116 may partially fill the second opening. The cow, mouth, and lower electrode contacts 116 may fill the lower portion of the second opening 114. 116 H is oxidized by the conductive pattern to form a lower electrode contact Chu - „, in other words, the metal oxide generated by the conductive pattern U()a can grow upward in the current 〇 114 to be in the second opening D An electrode contact 116 including a round object is formed in 114. The conductive pattern should be formed with a groove, and the lower electrode contact 116 may have a circular protrusion which is a circular groove corresponding to the conductive pattern 110a. In an exemplary embodiment, each of the conductive patterns 11a may include tungsten, and thus each of the lower electrode contacts u includes tungsten oxide. A spacer 118 is disposed on a sidewall of the second opening 114. The spacer 118 contacts the lower electrode contact 116. The width of the second opening 114 may be due to the spacer wall 118 72 201133757 WWW Λ.  ^ Λ ί is reduced by the formation. Each spacer 118 can comprise a nitride or an oxynitride. For example, each of the spacers 118 may comprise tantalum nitride or hafnium oxynitride. A phase change structure 12A is disposed on the lower electrode contact 116 to completely fill the second opening 114. Phase change structure 120 can comprise a chalcogenide. The upper surface of the phase change structure 120 filling the second opening 114 and the upper surface of the second insulating interlayer pattern 112 may be disposed on substantially the same plane. Therefore, the phase change structure 120 may not protrude above the second insulating interlayer pattern 112. Upper electrodes 122 are disposed on the respective phase change structures 120. Each of the upper electrodes 122 may comprise a metal nitride such as titanium nitride. The upper electrode 122 has a width that is substantially greater than the width of the phase change structure 12A. A third insulating interlayer pattern 124 is disposed on the second insulating layer pattern 112. The second insulating interlayer pattern 124 covers the upper electrode 122 and the phase change structure 120. A third opening is formed through the second insulating interlayer pattern 124. The third opening 126 partially exposes the upper electrode 122. Upper electrode contacts 128 are disposed in each of the third openings 126. Each of the upper electrode contacts 3A may comprise a metal, such as a crane. 48 through 51 are cross-sectional views showing a method of fabricating a phase change element in accordance with an exemplary embodiment of the present invention. The phase change memory element shown in Fig. 47 can have a configuration in which a first opening and a second opening are provided in a portion of the substrate on which the cell of the phase change memory element is formed. Referring to Fig. 48', a trench isolation process is performed around the substrate i00 to define the dirty and active regions of the isolation region of the substrate. Forming a 73 201133757f oxide layer on the substrate with the quarantine area and the active area. The oxide layer is partially engraved to form a first opening 1〇4 while the oxide layer is changed to the first insulating interlayer pattern 1〇2. The first opening 1〇4 may be formed at a portion of the substrate 100 where the unit cell is formed. A p·Ν diode 106 is formed in the first opening 104 of the first insulating interlayer pattern 102. Each of the Ρ-Ν diodes 1 〇 6 may comprise polycrystalline germanium and may have a vertical type. ~ During the formation of the erbium-tellurium diode 106, a polysilicon layer can be formed on the first opening 1 〇 4 and then the polysilicon layer can be locally etched. The polysilicon layer may be doped with impurities in-situ or out_situ. Thereby, the P-N diode 1〇6 is formed in the first opening 104. In an exemplary embodiment, when a P-type impurity can be implanted in the upper portion of the polysilicon layer of the first opening 104, an N-type impurity can be doped in the lower portion of the polysilicon layer of the first opening 1〇4. * A metal lithium pattern is formed on the body 106. The metal halide pattern 1〇8 can be formed by forming a metal layer on the P-N one body 106 and heat-treating the metal layer and the p_N diode 106. Thereby, the metal halide pattern 108 can be obtained according to the reaction between the metal in the metal layer and the germanium in the P_N diode 1?6. Each of the metal telluride patterns 1〇8 may include Shi Xihua, 5; Xixihua; 5 Xihua, Shi Xihua and the like.

An initial conductive pattern 丨1〇 is formed on the metal lithium pattern 108. The initial conductive pattern 110 may fill the first opening 1〇4. Each of the initial conductive patterns HQ can be formed by metal opening. For example, each of the initial conductive patterns 11 can be formed using a crane. In the process of forming the initial conductive pattern 110, a metal layer may be formed on the metal germanide 74 201133757 1 i pattern 108 and the first insulating interlayer pattern 102 to fill the first opening 104 and then locally moved by the CMP process. Except this metal layer until the first insulating interlayer pattern 1〇2 is exposed. Thereby, the initial conductive pattern 丨1〇 can be formed on the metal lithium pattern 1〇8. Referring to Fig. 49, a second insulating interlayer containing an oxide is formed on the first insulating interlayer pattern 1〇2 to cover the initial conductive pattern 110. The second insulating layer can be formed using yttrium oxide. The second insulating interlayer is locally etched to form a second opening 114 that partially exposes the initial conductive pattern 110 while the second insulating interlayer is changed to the second insulating interlayer pattern 112. The second opening 114 can be formed by a lithography process. In an exemplary embodiment, the second opening 114 has a width that is substantially smaller than the width of the initial conductive pattern 11G. Thereby, the second opening 114 can partially expose the initial conductive pattern u〇. Dew "see the heat treatment of the second opening σ 114 in the atmosphere containing the reduction, and the heat conduction pattern 11G is heat-treated to form the lower electrode contact 116 on the initial conductive pattern no. The lower electrode ιΐ6 can be locally Filling the first opening 114. During the electrode contact 116, the initial conductive pattern can be reacted with oxygen, whereby the metal emulsion can be grown upward in the second opening ι4. Therefore, the initial conductive _ u oxygen can be touched Point, here, the material initial conductive pattern m = electrical pattern 110a. The lower electrode contact 116 has a pattern, the electric (four) is initially large; the electrode contact 116 contains tungsten oxide. 75 201133757 JUWJ ipif in the initial conductive pattern lio After the heat treatment, the conductive pattern 110a may have an upper portion including a circular groove, and the lower electrode contact ι 16 may have a circular groove including a lower portion of the protrusion corresponding to the conductive pattern 11a. The conductive pattern 110a and the lower portion The electrode contact 116 can be obtained by a process substantially the same as or substantially similar to that described with reference to Figure 36. Referring to Figure 51', a spacer 118 is formed on the sidewall of the second opening 114. A phase change material layer is formed over 116 to completely fill the second opening 114. The phase change material layer can be formed using a chalcogenide compound (e.g., an alloy of 蹄_录_蹄). Partially remove the phase change material layer until exposed The second insulating interlayer pattern 112' is formed to form a phase change structure 12 in the second opening 114. The upper surface of the phase change structure 120 and the upper surface of the second insulating interlayer pattern 112 may be located on substantially the same plane. An upper electrode layer is formed on the phase change structure 12A and the second insulating interlayer pattern 112. The upper electrode layer is patterned to form the upper electrode 122 on the phase change structure 120. The second insulating interlayer pattern 112 is formed on the second insulating interlayer pattern 112. Three insulating interlayers are provided to cover the upper electrode 122. The third insulating interlayer is locally etched to form a third opening 126'. The third opening 126 partially exposes the upper electrode 122. Thereby the third insulating interlayer is changed to have a third opening 126. a third insulating interlayer pattern 124. Each of the second openings 126 may have a shape such as a contact hole. A conductive material is deposited in the third opening 126 to form an upper electrode contact on the upper electrode 122 in the third opening 128. Each of the upper electrode contacts may be formed of a metal. For example, each of the upper electrode contacts 128 may be formed using a crane 76 201133757. Figure 52 is a diagram showing a phase change memory element according to a second embodiment of the present invention. The phase change memory element of FIG. 52 may have a phase change memory element as described with reference to FIG. 47, except for the vertical stack structure including the lower electrode contact and the dotted structure of the phase change structure and the first insulating interlayer pattern. A configuration that is substantially the same or substantially similar. Referring to Figure 52, a vertical stack structure including a lower electrode contact U6 and a phase change structure 12A may have a rectangular upper surface and may be repeatedly arranged in a dashed line on the substrate 1〇〇 (dashed) shape. Therefore, a relatively large area of the substrate 1 提供 can be used to provide a large number of vertical stacked structures. The first insulating interlayer pattern 162 may surround the lower electrode contact ι16 and the phase change structure 120. The first insulating interlayer pattern 162 may comprise a nitride such as nitrogen hydride. In an exemplary embodiment, as shown in Fig. 52, no spacers may be provided on the sidewalls of the lower electrode contact 116j and the second opening 16, and the upper (6) may have a sufficiently small width. In a further exemplary embodiment, a spacer may be additionally disposed on the lower electrode 116. ί υ υ 图 图 图 图 图 图 图 图 图 图 图 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The "non-phase-change memory element" of the "52" system is shown in Fig. 53, and the same or substantially similar structure can be selected on the substrate 100 by the process of the plan. Scale structure. The top layer of the nucleus is formed on the initial conductive pattern 11 () and the insulating interlayer pattern 102. 201133757 xyil The first first insulating layer may be formed using a nitride such as nitride. The first insulating layer is partially engraved to form a first trench 15 , and the first drain 150 exposes the initial conductive pattern 11 . Each of the first trenches 15 can form a first insulating layer pattern 152 having the first trench 150 on the first insulating wire® 1G2 in the girth direction H. A second insulating layer is formed on the initial conductive pattern u〇 in the first trench 150. The second insulating layer may be formed using a material having a relatively high selectivity with respect to the first insulating layer pattern 152. For example, the second insulating layer can be formed using an oxide such as yttrium oxide. The second insulating layer is partially removed until the first insulating layer pattern is exposed. 52 The first insulating layer can be partially removed by a process and/or a last-pass process. Therefore, a second insulating layer 154 is formed between the first insulating layer and 152. Each of the second insulating layer patterns 154 may extend in a second direction substantially perpendicular to the first direction. A mask pattern is formed on the first insulating layer pattern 152 and the second insulating layer pattern 154. The mask pattern may extend in a second direction that is substantially perpendicular to the first direction. Each mask pattern may have a shape. Thereafter, the mask pattern can be regularly repeated on the first insulating layer pattern 152 and the second insulating layer pattern I%. The first insulating layer pattern 152 and the second insulating layer pattern ι54 are partially etched by using the mask pattern as an etch mask until the first insulating layer pattern 102 is exposed by locally etching the first insulating layer pattern ι52 And the second insulating layer pattern 154 forms a first trench 156 on the first insulating interlayer pattern 102. Here, the initial conductive pattern 11〇 is not exposed. Each of the first and second solar layers 152 and the second insulating layer pattern 154 may have a circular or polygonal column shape. Referring to Fig. 55', a third insulating layer is formed on the first insulating layer pattern 152 and the second insulating layer pattern 154. The third insulating layer may be formed using a nitride such as nitride nitride. The third insulating layer is partially removed until the first insulating layer pattern 152 and the second insulating layer pattern 154 are exposed to form a third insulating layer pattern 158 in the third trench 156. After forming the second insulating layer pattern 158, the first insulating layer pattern 152 and the third insulating layer pattern 158 including substantially the same material may surround the second insulating layer pattern 154'. The second insulating layer pattern 154 includes a different insulating layer than the first insulating layer. The material of the pattern 152 and the third insulating layer pattern 158. Referring to FIG. 56, the second insulating layer pattern 154 is selectively removed from the first insulating interlayer pattern 1 〇 2 to form a second opening 160 between the first insulating layer pattern 152 and the third, rim layer pattern 158. . The second opening ι6 〇 partially exposes the initial conductive pattern 110. As a result, the second insulating interlayer pattern 162 is provided on the first insulating interlayer pattern °1〇2. The second insulating interlayer pattern /62 includes a first insulating layer pattern 152, a third insulating layer pattern 158, and a second opening = 160. Each of the second openings 160 may have the shape of a contact hole. Further, the port 160 can extend in the first direction and the second direction at the same time. One open 1 system two diagrams; engraved plasma pair adjacent 54 to prevent damage in the dry handle engraving process 158: tea: a rim pattern of insulation layer pattern 15 4 . 1^ From the side of the wire, the second is the second. 79 201133757 X "In the exemplary embodiment, the second opening (10) has a width which is substantially smaller than the width of the conventional contact hole formed by the lithography process. The first & port 160 may be arranged in a dashed line on a plane. Referring to Fig. 57, the initial conductive pattern 110 is locally oxidized by an oxidation process so that the metal oxide generated by the initial conductive pattern 11G is grown upward in the second opening 160. Thereby, the lower electrode contact 116 is formed at the second opening. In the oxidation process, the initial conductive pattern 11 turns into the conductive pattern 110a. The electrical pattern 11A has an upper portion including the circular groove and the electrode 116 may have a lower portion including the protrusion, which corresponds to the conductive pattern 〇 a groove. The conductive pattern 11A and the lower electrode contact layer 6 can be obtained by substantially the same or substantially similar to those described with reference to Fig. 4A. Referring to Fig. 58, a phase change material layer is formed on the lower electrode contact 116 to fill the second opening 160, and then the phase change material layer is partially removed until the second insulating interlayer pattern 162 is exposed. Thereby, a phase change structure 12A filling the second opening 160 is formed on the lower electrode contact 116. In an exemplary embodiment, the second opening 16'' may have a relatively small width so that no spacers may be formed on the sidewalls of the second opening 160. However, a spacer may be additionally provided on the side wall of the second opening 160 to extend the width of the second opening 16''. # Referring to FIG. 53, an upper electrode 122 is formed on the phase change structure 120. A third insulating refreshing pattern 124 having a third opening is formed on the second insulating interlayer pattern 162 to cover the upper electrode 122. Next, an upper electrode contact port 28 is formed on the upper electrode 122 in the third opening. Thereby, a phase change memory component having a high integrated body 201133757 -----Γ can be produced. Phase Change of Exemplary Embodiment FIG. 59 is a cross-sectional view showing a memory element in accordance with the present invention. Referring to FIG. 59, a first insulating layer 192 and a pole body 194 are provided on the substrate 190. A second insulating interlayer pattern 202 is formed on the first insulating loss layer 192. The second insulating inflammatory layer pattern includes a first opening H 204 to expose the P_N diode 194. The second insulating interlayer pattern may comprise a nitride such as a nitrogen cut or an oxide such as an oxygen cut. The first lower electrode contact 2〇6& is disposed on the P-N one body 194 to partially fill the first opening. The first-lower electrode contact vein may contain metal. The second lower electrode contact 208a is located on the first lower electrode contact 2〇6a to completely fill the mG4. The second lower electrode contact class a may include a metal oxide produced by the metal in the first-lower electrode contact 206a. In an exemplary implementation, the first-lower electrode contact a and the second lower electrode contact 208a may comprise tungsten and tungsten oxide, respectively. A phase change structure 210 is formed on the first lower electrode contact 208a and the second insulating interlayer pattern 2'2. The upper electrode 212 is disposed on the phase change structure 2〇2. The upper electrode 212 can comprise, for example, a metal nitride. A third insulating layer pattern 214' is disposed on the first insulating interlayer pattern 202. The second insulating interlayer pattern 214 covers the upper electrode 212. A second opening σ is provided through the third insulating interlayer pattern 214. The second opening at least partially exposes the upper electrode 212. An upper electrode contact 216 is disposed on the upper electrode 212 in the second opening. According to an exemplary embodiment, the phase change memory element may have an improved operation because the second lower electrode contacting the phase change structure is difficult to have a large resistance. Insertion ί 6 2 7 62 is a cross-sectional view showing a method of manufacturing a phase change (four) element according to an exemplary embodiment of the present invention. The PN H60' forms a first insulating interlayer 192 and Γρ- on the substrate 190; 192^190^ The second type of sound is formed on the first insulating interlayer 192 to remove the second insulating interlayer. In this way, in the first - absolutely. Dimensional ^ contains the second insulating layer pattern 2第2 of the first-opening. The first opening 204 exposes the ρ_Ν diode μ. The first tungsten 204 is formed on the common ΓΝ ΓΝ diode 194 and the second insulating interlayer pattern 2G2 to fill the first opening 204. The first metal layer can be utilized at the first opening by removing the first metal layer. The initial lower electrode contact 206 has an upper end of the lower electrode first opening 204. Alternatively, the initial 3 surface and the upper end of the first opening 204 may be located in a real-iiH oxygen atmosphere to the initial lower electrode contact-lower to form an initial stage on the first lower electrode contact 2〇6a. - Electrode contact 2G8, while making the initial lower electrode Na 2 () 6 become = : ΓΓ Initially the second lower electrode contact contains the metal oxide produced by the metal in the initial electrical contact. In the second embodiment, since the initial lower electrode contact is oxygenated as the initial second lower electrode contact, the first-lower electrode contact 2〇6a 82 201133757 VVW Λ has the upper surface substantially The upper end is lower than the upper end of the first opening 2〇4. Since the oxidation process is performed around the initial lower electrode contact 206, the initial second lower electrode contact 208 may protrude above the first opening 2〇8. That is, the initial lower electrode contact 206 has an upper surface substantially the same as or substantially lower than the upper end of the second opening 204, so that the metal oxide can be grown isotropically from the initial lower electrode contact 2〇6. The initial second lower electrode contact 2A8 protrudes from the first opening 204. Referring to FIG. 62, the initial second lower electrode contact 2〇8 is partially removed until the first insulating interlayer pattern 202' is discharged to form a second underfill first opening 204 on the first lower electrode contact 206a. Electrode contact 2〇8a. Referring to Fig. 59, a phase change material layer and an upper electrode layer are formed on the second insulating interlayer pattern 2'' to cover the second lower electrode contact 208a. The phase change material layer and the upper electrode layer are patterned to form a phase change structure 21 and an upper electrode 212 on the second lower electrode contact 2'8' and the second insulating interlayer pattern 202. A third insulating interlayer pattern 214' having a second opening is formed on the second insulating interlayer pattern 202 to cover the upper electrode 212. The second opening locally violently exits the upper electrode 212. An upper electrode contact 216 is formed on the upper electrode 212 to fill the second opening. Figure 63 is a diagram showing a broadband communication system including a mobile telecommunications telephone network capable of broadband communication, in accordance with an exemplary embodiment of the present invention. Referring to Figure 63, the broadband communication system 250 includes a sensor module 252, a global positioning system (GPS) 254, and an active telecommunications telephone 256. The broadband communication system 250 can communicate with the data server 258 83 201133757 juuoiinf and the network base 260. Since the mobile telecommunications telephone 250 can receive/transmit large amounts of data from/to the data server 258 and the network base station 26, the mobile telecommunications telephone 256 may require fast communication speed and high data reliability. According to an exemplary embodiment, mobile telecommunications phone 256 may include at least one of a resistive memory device. The resistive memory element can include the above described magnetic memory element and/or phase change memory element. These resistive memory elements can be employed in the mobile telecommunications phone 256 because the resistive memory elements in accordance with the exemplary embodiments ensure low drive current, fast response speed, and high data reliability. The resistive memory element according to an exemplary embodiment can be used for various electrical devices and electronic devices; for example, the secret communication line (5) service ai serial bus, USB) memory, Mp3 player, digital camera or memory card in. Evaluation of the Resistance of the Contact Structure Due to the high resistance of the lower electrode contact, the electric (4) component according to an exemplary embodiment of the present invention can have a high Joule heating rate. Sample to compare its lower electrode contacts with sample 1 to sample 8 Figure 64 is based on the sample! Cross section of the contact structure to the sample 8 Referring to Fig. 64', an insulating interlayer pattern 302 having an opening is formed on the substrate 300. A contact plug is formed in the opening. The contact plug has a pattern of a sunburst 84 201133757 and a tungsten oxide pattern 3〇8 formed on the tungsten pattern 3〇4. The tungsten oxide pattern 308 is obtained by processing the tungsten pattern 3〇4 in an RTA process. The contact plugs 308 of Samples 1 through 8 have different diameters. Table 1 shows the diameter of the contact plugs 3〇8 according to Samples 1 through 8. The contact plugs 3A8 of the samples 1 to 8 have substantially the same configuration as the above-described conductive structure of the resistive memory element. Control Sample 11 to Control Sample 18 Figure 65 is a cross-sectional view showing the contact structure from the control sample 11 to the control sample 18. Referring to Fig. 65, an insulating interlayer pattern 302 having an opening is formed on the substrate 300. A contact plug is formed in the opening. The contact plug 308 has a town pattern 304 and a tantalum nitride pattern 31〇 formed on the crane figure #3〇4. The contact plugs 312 of the sample 11 to the control sample 18 have different diameters. Table 1 below shows the diameter of the contact plug 312 from the control sample u to the control sample 18. β Control Sample 21 to Control Sample 28 FIG. 66 is a cross-sectional view showing the configuration from the control sample 21 to the control sample 28. As shown in Fig. 66, an insulating stalk having an opening is formed on the substrate 3, and a contact plug 314 including a crane is formed in the drawing. The contact woven 314 of Comparative Example 2 to Comparative Example 28 has a different diameter. Table ι shows the contact plug 31 diameter from the control sample 2丨 to the control sample 28. Star Table 1 85 201133757 JVIUJ ipif Diameter 130 nm sample 1 Control sample 11 140 nm sample 2 Control sample 12 Control sample 2? 150 nm sample 3 Control sample 13 Control 160 nm 170 nm sample 4 Control sample 14 Control sample 24 Sample 5 Control sample 15 Control 180 nm - ... J90 nm _ sample 6 Control sample 16 Control sample 7 Control sample 17 Control sample 200 nm sample 8 Control sample 18 Control sample - Figure 67 shows the sample and A graph of the resistance of the contact structure of the control sample. In Fig. 67, 'line 320 represents the resistance of the contact structure according to sample 丨 to sample 8' line 322 represents the resistance of the contact structure according to the control sample U to the control sample ,, and line 324 represents the control sample 21 to the control sample 28 Contact the resistance of the structure. As shown in FIG. 67, in measuring the electric shout with the phase-diameter contact structure according to the sample and the control sample, the resistance according to the sample 丨 to the sample 8 is greater than the control sample 11 to the control sample 19 and ί Γ The resistance of the contact structure to the control sample 28. For example

The contact structure of f 1 having a diameter of 13 G nm has a resistance of about W and a large t, and according to the control sample 11 and the control; the contact structure of (10) nanometers has a resistance of 1310 ohms, respectively. As described above, the contact structure of the resistive memory device of the present invention 86 201133757 w W Λ ^λΙ. The tungsten pattern and the tungsten oxide pattern are included, so that the contact structure can have an improved resistance. These resistive memory elements ensure enhanced characteristics due to the contact structure that increases the Joule heating efficiency of the resistive memory elements. Evaluation of Electrical Characteristics of Resistive Memory Element Sample 9 A phase change memory element was fabricated by the process described with reference to Figs. 45 and 46. The phase change memory component of sample 9 has the same vertical configuration as that described with reference to FIG. According to the conductive pattern of the phase change memory element of sample 9, 成 is used. The lower electrode contact is formed on the conductive pattern in the first opening by heat-treating the conductive pattern by the RTA process. The lower electrode contact contains tungsten oxide. _Titanium nitride forms the upper electrode and uses the 嫣 to form the upper electrode contact. Comparative Example 9 To compare the characteristics of the phase change memory element according to the sample 9, another phase change memory element was fabricated. 68 is a cross-sectional view showing a phase change memory element according to a control sample 9. Referring to FIG. 68, the phase change memory element of Comparative Example 9 includes a conductive pattern 12a, a phase change structure 52a, an upper electrode 24, and an upper electrode contact 3A. . This phase change includes a first edge interlayer pattern s 14 and a second insulating layer pattern 26. In the phase change memory element of Comparative Example 9, the phase change structure 52a was disposed on the conductive pattern 12a without the lower electrode contact. Therefore, the conductive pattern is used as the lower electrode. The phase change memory element of Comparative Example 9 includes a spacer 50a, and the interlayer 坌5〇a is disposed on the sidewall of the opening 87 201133757 JUUJipif formed with the phase change structure 52a. According to the sample 9 and the control sample 9, a plurality of phase change memory elements were fabricated. The resistance of these phase change memory elements in the set state and the reset state is measured' and the current of these phase change memory elements in the reset state is also measured. Table 2 below shows the set resistance, reset resistance, and reset current for these phase change memory components. Table 2 Set Resistance (Rset) Reset Resistor C Preset) Reset Current (Ireset) Sample 9 1.63 kohms to 53.8 kohms 2.14 million ohms to 6.35 million ohms 180 (enemy ~ 72 microamps control sample 9 17 thousand Ohm ~ 151 kohms 1.13 million ohms ~ 2.27 million ohms 166 microamperes ~ 188 microamps As shown in Table 2, the phase change memory component of sample 9 has a set resistance lower than that of the phase change memory according to Comparative Example 9. The set resistance of the component, and the phase change memory component of sample 9 has a lower resistance distribution than the phase change memory component according to the control sample 9. The reset resistor of the phase change memory component of sample 9 It is larger than the reset resistance of the phase change memory element according to Comparative Example 9. In the phase change memory element according to Comparative Example 9, the phase change structure has a considerable depth in the open σ, so in the phase change structure Frequent occurrence of voids or slits, which in turn causes operational failure of the phase change memory element and degrades the electrical characteristics of the phase change memory element. The phase change memory element according to the present invention can have a low resistance distribution, 88 201133757, and also has a large resistance difference between the set state and the reset state to easily identify the stored data. Therefore, the phase change memory element of the present invention can ensure the desired operational characteristics. The resistive memory element including the conductive structure can be easily fabricated by a simplified process, and the conductive structure can ensure excellent heating efficiency. Therefore, the resistive memory of the element of the present invention can be used as a high product. The present invention has been described with reference to the drawings, but it should be understood that the present invention should not be limited to the embodiments and those skilled in the art. Various other modifications and changes can be made without departing from the scope and spirit of the invention, and all such modifications and variations are intended to be included within the scope of the invention as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Exemplary embodiments of the present invention can be understood in more detail by reading the above description with reference to the accompanying drawings in which: FIG. Fig. 2 is a perspective view showing the conductive structure of Fig. 1. Fig. 3 to Fig. 5 are sectional views showing the formation of the conductive structure shown in Fig. 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 to FIG. 10 are cross-sectional views showing a method of manufacturing the magnetic memory element shown in FIG. 6. 89 20113373⁄4 11 is a cross-sectional view showing a phase change memory device according to an exemplary embodiment of the present invention. Fig. 12 is a cross-sectional view showing a method of manufacturing the phase change memory device shown in Fig. 11. Fig. 13 is a A cross-sectional view of a phase change memory element in accordance with an exemplary embodiment of the present invention. Figure 14 is a cross-sectional view showing a method of fabricating the phase change memory element of Figure 13; Figure 15 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. Figure 16 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. Figure 17 is a cross-sectional view showing a method of forming the conductive structure shown in Figure 16. Figure 18 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. Figure 19 is a perspective view showing the conductive structure of Figure 18. Figure 20 is a plan view showing the conductive structure of Figure 18. 21 and 22 are cross-sectional views showing a method of forming the conductive structure shown in Fig. 18. Figure 23 is a cross-sectional view showing a magnetic memory element in accordance with an exemplary embodiment of the present invention. 24 and 25 are cross-sectional views showing a method of manufacturing the magnetic memory device shown in Fig. 23. 201133757 Figure 26 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. Figure 27 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. Figure 28 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. Figure 29 is a cross-sectional view showing a method of forming the conductive structure shown in Figure 28. Figure 30 is a cross-sectional view showing a method of fabricating the conductive structure of Figure 28, in accordance with an exemplary embodiment of the present invention. Figure 31 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. Figure 32 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. Figure 33 is a cross-sectional view showing a method of manufacturing the conductive structure shown in Figure 32. Figure 34 is a cross-sectional view showing a magnetic memory element in accordance with an exemplary embodiment of the present invention. Figure 35 is a cross-sectional view showing a magnetic memory element in accordance with an exemplary embodiment of the present invention. Figure 36 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. Figure 37 is a cross-sectional view showing a conductive structure in accordance with an exemplary embodiment of the present invention. 91 201133757 FIG. 38 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. 39 to 44 are cross-sectional views showing a method of manufacturing the phase change memory element shown in Fig. 38. Figure 45 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. Figure 46 is a cross-sectional view showing a method of manufacturing the phase change memory element shown in Figure 45. Figure 47 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. 48 to 51 are cross-sectional views showing a method of manufacturing the phase change memory element shown in Fig. 47. Figure 52 is a perspective view of a phase change memory element in accordance with an exemplary embodiment of the present invention. 53 through 58 are cross-sectional views showing a method of fabricating the phase change memory device of Fig. 52. Figure 59 is a cross-sectional view showing a phase change memory element in accordance with an exemplary embodiment of the present invention. 60 to 62 are cross-sectional views showing a method of manufacturing the phase change memory element shown in Fig. 59. Figure 63 is a diagram showing a communication system including a mobile phone network capable of broadband communication, in accordance with an exemplary embodiment of the present invention. Figure 64 is a cross-sectional view of a cross-section of the contact structure of Sample 1 through Sample 8 92 201133757. Figure 65 is a cross-sectional view showing the contact structure according to the control sample 11 to the control sample 18. Figure 66 is a cross-sectional view showing the contact structure according to the control sample 21 to the control sample 28. Fig. 67 is a graph showing the electric resistance of the contact structure according to the sample and the control sample. Figure 6 is a cross-sectional view showing a phase change memory element according to the control sample 9. [Main component symbol description] 8: Substrate 10: First insulating interlayer 11: PN diode 12a: Conductive pattern 14: Second insulating interlayer pattern 16: First opening 18: Lower electrode contact 20: Clearance wall 22: Phase Variable material layer 22a: phase change structure 24: upper electrode 26: third insulating interlayer pattern 28: second opening 30: upper electrode contact 93 201133757f \»\j^ i 50 : substrate 50a: spacer 52: insulating interlayer 54 Opening 56 barrier metal layer 56a: barrier metal layer pattern 58 metal layer 58a: initial metal pattern 58b: metal pattern 59 metal layer 59a: metal pattern 60 metal oxide pattern 62 spacer 64 substrate 66 insulating interlayer 68 opening 70 barrier Metal layer 70a: barrier metal layer pattern 72: metal layer 72a: metal pattern 72b: metal pattern 74: buried layer 74a: buried layer pattern 76: metal oxide pattern 94 201133757τ ----- 80 : spacer 82 : Metal pattern 84 : Buried layer pattern 86 : Metal oxide pattern 90 : Substrate 92 : Metal pattern 92a : Metal pattern 94 : Insulation layer 96 : Opening 98 : Metal oxide pattern 98a: metal oxide pattern 100: substrate 100a: isolation region 102: first insulating interlayer pattern 104: first opening 106: PN diode 108: metal germanide pattern 110: initial conductive pattern 110a: conductive pattern 112: second Insulating interlayer pattern 114: second opening 116: lower electrode contact 118: spacer 120: phase change structure 95 201133757 122: upper electrode 124: third insulating interlayer pattern 126: third opening 128: upper electrode contact 150: a trench 152: a first insulating layer pattern 154: a second insulating layer pattern 156: a third trench 158: a third insulating layer pattern 160: a second opening 162: a first insulating interlayer pattern 190: a substrate 192: a first insulating interlayer 194 : PN diode 202: second insulating interlayer pattern 2〇4: first opening 206: lower electrode contact 206a: first lower electrode contact 208: second lower electrode contact 208a: second lower electrode contact 210 : Phase change structure 212 : Upper electrode 214 : Third insulating interlayer pattern 216 : Upper electrode contact 96 201133757 250 : Broadband communication system 252 : Sensor module 254 : Global positioning system 256 : Mobile telecommunications telephone 258 : Data servo 260: network base station 300: substrate 302: insulating interlayer pattern 304: tungsten pattern 308 · tungsten oxide pattern 310: tungsten nitride pattern 312: contact plug 314: contact plug 400: semiconductor substrate 402: gate insulation Layer 404: gate electrode 406: impurity region 408: first insulating interlayer 410: contact plug 412: conductive pattern 414: second insulating interlayer 415: opening 416: first barrier metal layer pattern 418: metal pattern 97 20113375^

JL 420: metal oxide pattern 422: third insulating interlayer 424: second barrier metal layer pattern 426: free layer pattern 428: tunnel oxide layer pattern 430a: fixed layer pattern 430b: fixed layer pattern 430c: fixed layer pattern 432: fixed layer pattern 434: fourth insulating interlayer 436: fifth insulating interlayer 438: upper electrode 440: bit line 450: metal pattern 452: second insulating interlayer 453: opening 454: metal oxide pattern 455: spacer 456 Metal oxide pattern 490 · Substrate 490a: impurity region 492: isolation layer pattern 494: first insulating interlayer 496: first opening 98 201133757 500 : P-Ν diode 500a: first polysilicon layer pattern 500b: Second polysilicon layer pattern 502a: metal pattern 504: second insulating interlayer 505: second opening 506: barrier metal layer pattern 508: metal pattern 510: metal oxide pattern 510a: metal oxide pattern 512: third insulation Interlayer 512a: third insulating interlayer 513: third opening 514: phase change material layer pattern / phase change structure 514a: phase change structure 515: third opening 516: upper electrode 518: fourth insulating interlayer 518a: second insulating interlayer 520 : contact hole 5 22: upper contact 530: metal pattern 530a: metal pattern 532: third opening 99 201133757 534: insulating layer pattern 536: metal oxide pattern 550: second insulating interlayer 552: spacer 553: opening 554: metal oxide pattern 556: phase change structure 610: first barrier metal layer pattern 612: metal pattern 614: buried layer pattern 616: metal oxide pattern 618: third insulating interlayer 650: barrier metal layer pattern 652: metal pattern 654: buried Incoming pattern 656: metal oxide pattern 660: third insulating interlayer 100

Claims (1)

201133757 VII. Patent application scope: 1. A semiconductor component comprising: an interlayer insulating layer disposed on a substrate, wherein the interlayer insulating layer comprises an opening, the opening exposing a conductive portion on the substrate; a pattern 'disposed in the opening; and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending from the opening and a non-oxygen located in the opening, wherein the conductive pattern The width of the barrier layer pattern is determined by the thickness of the barrier layer pattern. The semiconductor device of claim 1, wherein the width of the conductive pattern is smaller than the width of the opening. 3. The semiconductor component according to claim 1, wherein the opening is extended. The oxidized portion is thicker than the oxide disposed in the opening. 4. The width of the oxidized portion of the semi-object described in the above-mentioned application (4) is substantially the same as the width of the non-oxidized portion. , thousands of places 5 · such as the scope of patent application! In the semiconductor device of the above aspect, the width of the oxidized portion is larger than the width of the non-oxidized portion. , The semiconductor device of claim 1, wherein the conductive pattern comprises tungsten. 9. The semi-conducting barrier layer pattern of claim 4, wherein the semi-conducting barrier layer pattern comprises titanium or a vaporized titanium, wherein at least one of the semiconductor elements, wherein the resistor is The barrier layer pattern includes at least one of a nitride or an oxynitride. The semiconductor device according to claim 1, wherein the oxidized portion of the conductive pattern contacts a phase change random access memory (PRAM) a phase change material film. 12. The semiconductor device of claim 4, wherein the barrier layer pattern contacts a Ρ_Ν diode disposed under the barrier layer pattern. 13. The semiconductor device of claim 2, wherein the oxidized portion of the conductive pattern contacts a free layer pattern in a magnetic random access memory (MRAM). The semiconductor device according to claim 13, wherein the barrier layer pattern electrically contacts a metal oxide semiconductor (MOS) transistor disposed under the barrier layer pattern. 15. The semiconductor device according to claim 1, wherein a size of a cross-sectional area of the oxidized portion in a plan view is smaller than a size of a cross-sectional area of the opening in the plan view. 16. The semiconductor device according to claim 15, wherein said size of said cross-sectional area of said oxidized portion in said plan view depends on said cross-sectional area of said barrier layer pattern size. 102 201133757 π· A method for forming an element to form an interlayer insulating layer on a substrate; the method of staking includes: forming a substrate with an opening insulating film, the opening exposing a pattern of forming a barrier layer to the opening And forming a conductive pattern on the barrier layer pattern in the opening; growing the conductive pattern by using the conductive pattern to extend the opening of the conductive pattern to the opening. The forming of the semiconductor device described in the above-mentioned patent scope of the invention is carried out in a conductive element comprising performing a rapid thermal annealing (RTA) process in an atmosphere of about 4 〇 ° ° C to about 10 minutes to about 10 minutes. . Forming a semiconductor device according to Item 17, wherein the growth of the conductive pattern comprises performing a slurry in an oxygen atmosphere by applying a power of about 20 watts to about watts. 10 minutes.疋J刀理王, 20. If you are a method of forming a semiconductor device as described in Item (4), the + growth is performed isotropically or non-isotropically. 21. The forming of the semiconductor device of claim 17, further comprising providing a nitrogen atmosphere around the oxidized portion of the conductive pattern. 22. The method of forming a semiconductor device as described in claim 17 further includes a face opening (4) forming a fill pattern such that the conductive pattern 103 201133757 is disposed in the fill pattern and the barrier. Between the layer patterns, a semiconductor device includes: a substrate, an insulating layer having an opening, disposed on the substrate; a metal pattern disposed on the substrate; and a metal oxide pattern disposed on the metal pattern The semiconductor element of the metal oxide pattern according to claim 23, wherein the metal pattern comprises tungsten, and the metal oxide pattern has a cross-sectional area. The semiconductor device of claim 23, wherein a portion of the metal pattern contacting the metal oxide pattern is recessed, and the recess receives a protrusion of the metal oxide pattern 26. The semiconductor device of claim 23, wherein the metal oxide pattern is interposed between the metal oxide pattern and the insulating layer 27. The semiconductor device of claim 23, wherein the metal pattern is disposed on a p_N junction, wherein the semiconductor component of claim 23, wherein The metal pattern is electrically connected to the M〇s transistor. The semiconductor element according to claim 23, wherein the metal oxide pattern contacts the free layer of the MRAM. 30. Patent application The semiconductor device according to Item 23, wherein the metal oxide pattern contacts the phase change material film of the pRAM. ', 104 201133757 The width of the bottom portion of the phase change material two guiding material. The knives have a width wider than the phase change 33. A method of forming a semiconductor element to form a metal pattern on a substrate includes: forming an insulating layer on the metal pattern; forming an opening through the insulating layer, a portion of the pattern; and a smashing out of the gold to oxidize the pattern of the smear of the metal pattern in the opening 4 in the opening to form a metal oxidation method as described in item 33 In the method of the semiconductor device, the metal oxide pattern contacts the free layer. The semiconductor device of claim 34, wherein the metal pattern electrically contacts the M0 body of the MRAM. 36. The method of forming a semiconductor device according to the invention of claim 33, wherein the metal oxide pattern contacts a phase change film of a PRAM. 37. A method of forming a semiconductor device according to the item The metal pattern is in contact with the PRAM 2P_N diode. The method of forming a semiconductor device according to claim 33, wherein a width of the metal oxide pattern is smaller than a width of the metal pattern. 105 201133757 39. A semiconductor device, comprising: a first insulating layer disposed on a substrate, a second insulating layer disposed on the first insulating layer, the second insulating layer comprising an opening; a third insulating layer, Arranging on the second insulating layer; a fourth insulating layer disposed on the third insulating layer; a memory storage element disposed on the fourth insulating layer; and a conductive pattern for heating the memory a storage element, the conductive pattern comprising a metal pattern and a metal oxide pattern, wherein the metal pattern is disposed in the opening of the second insulating layer The metal oxide pattern is disposed in the third insulating layer, and the width of the conductive pattern is smaller than the width of the opening. 40. The semiconductor device according to claim 5, wherein a cell 3 transistor in the first insulating layer and a free layer pattern of the MRAM disposed in the fourth insulating layer. 41. The semiconductor device scoop according to claim 39 is disposed in the first a p_N diode in the insulating layer and a phase change film disposed in the fourth insulating layer. 42. The semiconductor device according to item 5% of the patent application, the top surface of the basin === pattern is The top surface of the third insulating layer includes a semiconductor element, a pattern, and a metal 106 between the pattern and the third insulating layer. 20113375^ 44. The semiconductor device of claim 41, wherein a top surface of the metal barrier pattern is disposed on a same plane as a top surface of the second insulating layer. 45. The semiconductor device according to claim 39, Wherein the top surface of the third insulating layer is configured Higher than the top surface of the metal pattern 46. The semiconductor element of the application of paragraph 43 patentable scope, wherein a top surface of the metal pattern arranged below the top surface of the metallic barrier patterns. 107