TW200840033A - Nonvolatile phase change memory cell having a reduced contact area and method of making - Google Patents

Nonvolatile phase change memory cell having a reduced contact area and method of making Download PDF

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Publication number
TW200840033A
TW200840033A TW096143406A TW96143406A TW200840033A TW 200840033 A TW200840033 A TW 200840033A TW 096143406 A TW096143406 A TW 096143406A TW 96143406 A TW96143406 A TW 96143406A TW 200840033 A TW200840033 A TW 200840033A
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TW
Taiwan
Prior art keywords
dielectric
layer
phase change
pillar
telluride
Prior art date
Application number
TW096143406A
Other languages
Chinese (zh)
Inventor
Usha Raghuram
S Brad Herner
Original Assignee
Sandisk 3D Llc
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Filing date
Publication date
Priority claimed from US11/560,791 external-priority patent/US7728318B2/en
Priority claimed from US11/560,792 external-priority patent/US8163593B2/en
Application filed by Sandisk 3D Llc filed Critical Sandisk 3D Llc
Publication of TW200840033A publication Critical patent/TW200840033A/en

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B63/00Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B63/00Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/061Shaping switching materials
    • H10N70/066Shaping switching materials by filling of openings, e.g. damascene method
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/061Shaping switching materials
    • H10N70/068Shaping switching materials by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • H10N70/231Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/821Device geometry
    • H10N70/826Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/882Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828Tellurides, e.g. GeSbTe
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch in forming a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a space on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.

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200840033 九、發明說明: 顏關申請索 本申請案主張2006年11月16曰所提申之美國專利申 4案序號1 1/560,791,名為、、具有縮減的接觸面積之非揮 發性相變記憶體單元,,,以及2006年U月16曰所提申 之美國專利申請案序f虎1 1/560,792,名為、'具有縮減的接 觸面積之非揮發性相變記憶體單元之製造方法〃之利益, 在此將兩者全體納入參考之。 【發明所屬之技術領域】 本發明關於一種包含一例如由一硫屬化合物所構成之 . 構件的相變構件之非揮發性記憶體單元。 【先前技術】 需要熱來轉換一相變構件之相位,且提供至該相變構 件之熱可藉由減少在該相變構件及熱源間之接觸面積而被 聚集。然而,縮減接觸面積至低於微影成像限制可能有困 因此’需要一種形成一〗 村丨& J於以楗影成像方式所形成之 取小特徵尺寸的接觸面積之方法。 【發明内容】 ’且本節中不應 。大體上,本發 在一相變構件及 ’及利用這類方 本發明係由下列申請專利範圍所定義 有任何事物被視為限制這些申請專利範圍 明係指向一種於一非揮發性記憶體單元中 一熱源之間形成一縮減的接觸面 法所形成之結構。 法 200840033 在一觀點中,一種非揮發性記憶體單元包括:一包括 一導電或半導體材料之柱狀物,該柱狀物具有一柱狀側 壁;一位在該柱狀物上方之介電質間隙壁,該介電質間隙 壁具有一外侧壁及一内側壁,其中,該外側壁係對準著該 柱狀側壁且該内側壁定義一縮減的凹部體積;一相變材 料’其中’一部分相變材料係位在該縮減的凹部體積内; 以及一環繞該柱狀物及該介電質間隙壁之介電質填充材 料’其中’該介電質間隙壁係由一不同於該介電質填充材 料之第二介電質材料所形成。 在一觀點中’一單片式(m〇n〇lithic)三維記憶體陣列包 括 a)弟 δ己丨思體層,該第一記憶體層包括··丨)複數個 柱狀物’母一個柱狀物包括一導電或半導體材料並具有一 柱狀側壁;ii)複數個介電質間隙壁,每一個介電質間隙壁 位在省些柱狀物的其中一者的上方,每一個介電質間隙壁 具有一外側壁及一内側壁,其中,每一個間隙壁之外側壁 係對準著該些柱狀物的其中一者之柱狀側壁且每一個内側 壁定義一縮減的凹部體積;iii}複數個相變構件,其中,該 些相變構件中每一個的某部分係位在該縮減的凹部體積 内 ^及iv) 環繞该些柱狀物及該些介電質間隙壁之介電 夤填充材料,其中,該些介電質間隙壁係由一不同於該介 電質填充材料之第二介電質材料所形成;b)在該第一記憶 體層上方單片地形成一第二記憶體層。 在一觀點中,一種記憶體層包括··複數個柱狀物,每 一個柱狀物包括一導電或半導體材料並具有一柱狀側壁; 6 200840033 ,每-個介電質間隙壁位在該些柱狀 ’每-個彳電質@隙壁具有—外側壁 每-個間隙壁之外側壁係對準著該些 柱狀側壁且每—個内側壁定義一縮減 相艾構件’其巾,該些相變構件中每 該縮減的凹部體積内;以及環繞該些 間隙壁之介電質填充材料,其中,該 一不同於該介電質填充材料之第二介 複數個介電質間隙壁 物的其中一者的上方 及一内侧壁,其中, 柱狀物的其中一者之 的凹部體積;複數個 一個的某部分係位在 柱狀物及該些介電質 些介電質間隙壁係由 電質材料所形成。 在一觀點中’ 一種形成一可七7? i备λα、上、若a • 但D取j切換的半導體構件之方法 包括:形成包括一導電或半導體姑+ ^X亍♦篮材枓、第一介電質填充材 料及一凹部體積之一柱狀物,i 八甲,该弟一介電質填充材 料環繞該柱狀物並具有一填充 昇兄貝表面,其中,該柱狀物 具有-柱狀頂部表m餘㈣部表面相對於該填 充頂部表面係凹陷的,且其中,凹部體積具有側壁並佔 據該填充頂部表面及該城頂部表面間的m·在該填充 頂部表面、言亥些凹部體積側壁及該柱狀頂部表面上形成一 保形介電質材料層;以異向蝕刻將部分的保形介電質層自 該填充頂部表面及該柱狀頂部表面巾移除,其巾,一由該 $貝材料所形成之間隙壁保留在該些凹部體積側壁 $,以定義一在該間隙壁内之縮減的凹部體積,·沉積一相 又材料Z、中,一部分相變材料係位在該縮減的凹部體積 内。 在觀點中,一種形成一單片式三維記憶體陣列之方 7 200840033 法包括:a)以下列方法在一基板上方形成一第一記憶體層, 該方法包括:i)形成複數個柱狀物,每一個柱狀物包括一 導電或半導體材料、一第一介電質填充材料及複數個凹部 體積,其中,該第一介電質填充材料環繞每一個柱狀物並 具有一填充頂部表面,其中,每一個柱狀物具有一柱狀頂 部表面,其中,每一個柱狀頂部表面相對於該填充頂部表 面係凹的,且其中,每一個凹部體積具有側壁並佔據該 填充頂部表面及該些柱狀頂部表面的其中之一柱狀頂部表 面之門的工間,u)在該填充頂部表面、該些凹部體積側壁 及,亥些柱狀頂部表面上形成一保形介電質材料層;出)以異 向钱刻將部分的保形介電質層自該填充頂部表面及該些柱 j ;! P表面中私除’其中’由該保形介電質材料所形成之 複數個間隙壁保留在該些凹部體積側壁上,以定義一在每 一個間隙壁内之縮減的凹部體積;叫沉積一相變材料,盆 中,一部分相變材料係位在每一個縮減的 ^ 在該第-記憶體層上方單片地形成一第二記憶體層、。 灶八ST所述之硯點及實施例中的每一個可被單獨或互相 結合地加以運用。 在將/考.亥些附圖說明該些較佳觀點及實。 【實施方式】 ' 儘管所有材料都可# 了靶改變相位,但本討論中之術語、、相 又":被使用以說明相當容易地由一稃定相仂眢.另 一穩定相位之材料。兮, 私疋相位變成另 結晶態(反之亦然也:广非結晶態變成- 也可以疋例如由一較無次序變成較 8 200840033 有次序的結晶態之中問开> _ 硫屬化合物 T间形^:化,且反之亦然 係眾》所熟知之相變材料。 在一非揮發性記憶體單 般早70中使用例如硫屬化合物係為 口的’其中’一南電阻曰 非…日日恶代表一記憶體狀態, 而一低電阻之結晶能抑本g j 1 心代表另一記憶體狀態,其中,每一種 記憶體狀態對應至1或〇的 ^ ^ ^ ^ 乂的值。右取得中間穩態,則超過 二種記憶體狀態可存在於各加口口 - ·认 ^ Μ母一個早兀;為了簡單起見,本 討論中的範例只會描述二種記憶體狀態。 一相變材料係藉由加埶至高、、西 、 …、1间/皿及/或自南溫中快速地冷 卻下來而自一狀態轉變成另— 七1❻ 、 付夂驭乃狀悲。為了協助此轉變,不 同方式已被使用以將熱集中於接觸到該相變材料之一相告 小的面積中。本揭示藉由形成一較特徵尺寸小的接觸二 來提供有關聚集熱能於包括一相變構件(一種包括一相變材 料之構件)之非揮發性記憶體單元中之問題_種簡單且易於 製造的解決方案’該特徵尺寸係為可由微影成像技術可靠 地形成且不需精確對準之最小尺寸。 一實施例將簡要地被描述。 圖la顯丨以任何傳統方法形成之軌狀底部m⑼。 底邛&體200較佳地係由例如氮化鈦黏附層i 〇4及鎢層i Μ 之金屬或金屬材料所形成。其上與底部導體2〇〇對準者係 柱狀物300。柱狀物300包含阻障物層ιι〇,其阻止鎢層1〇6 及上方半導體材料之間的反應。底部區域丨12係例如以一 =型掺#物進行重度摻雜之矽的非結晶性記憶體材料,而 區域1 1 4係純矽或輕度摻雜的矽。介電質填充材料1⑽係 200840033 環繞柱狀物300,且在以例如化學機械平坦化製程或化學 機械研磨製程之平坦化動作所形成之平坦表面處,介電質 填充材料108所環繞之柱狀物3〇〇的頂部表面被曝露出 來。 轉向圖lb,一選擇性乾式蝕刻使相對於介電質填充材 料108之柱狀物300具有凹部。柱狀物3〇〇具有一相對於 介電質填充頂部表面u 3係為凹陷之柱狀頂部表面1 P, 其形成佔據著柱狀頂部表面丨17及填充頂部表面丨13之間 的空間的凹部體積丨丨5。 較佳地,此時離子植入被執行以形成頂部重度摻雜p 型區域116。底部重度摻雜n型區域112、中間本徵區域ιΐ4 及頂部重度摻雜p型區域116形成一垂直定向之p-i-n二 極體。若為所要的話,此二極體極性可被逆轉,將該p型 區域置於該底部並將該n型區域置於該頂部。 轉向圖1 c,一形成矽化物的金屬層丨2〇被沉積在介電 貝填充頂部表面113、柱狀頂部表面117及該凹部體積11 5 之側壁上。一第一回火使金屬120與該矽的重度摻雜區域 1 1 ό反應’以在該柱狀物300頂部處形成一金屬石夕化物層。 形成矽化物的金屬120可為例如鈷或鈦,以形成圖所 不之矽化鈷或矽化鈦層1 2 1。一選擇性濕式蝕刻係剥去未 反應的鈷或鈦,只在該柱狀物300頂部處留下矽化物12丄。 較佳地’完成該矽化物反應之後接著執行一第二回火。如 將會看見的,矽化物121充當該矽的頂部重度摻雜區域n6 及一稍後要被沉積之相變材料之間的阻障物使用。石夕化物 10 200840033 取後’在圖lg中,—相變材料122層被沉積,以埴充 縮減的凹部體積119。相變材料122較佳地係__硫屬化合 制在本|&例中化學機械研磨終止層(例如,由氮化欽 j成)124被沉積,接著化學機械研磨終止層124及硫屬化 °物122被圖案化、姓刻,並以更多介電質填充物 '会轰夕 〇 产 义 y 、’坦化製程以露出化學機械研磨終止層124頂部 後,在本實施例中,頂部導體4〇〇被形成於硫屬化合物122 之上。頂部導豸400可以相同方式及與底部導體相同 之材料來形成。例如阻障物124之額外阻障物層可被納入。 立圖所不,頂部導體400較佳地以垂直於底部導體2〇〇(以 形式,.肩不延伸出該頁之外之執狀頂部導體4〇〇)之方向 ⑵也用於改變該二極體特徵,即如後所述。請注意的是, 〆夕化物121的頂部表面現在係為該柱狀頂部表面1 17。 μ接者,在圖U中’―保形介電質薄層130被沉積在介 充頂部表面113、該凹部體積⑴之侧壁及柱狀頂 表面117上。如圖lf所示,—異向钮刻被執行;該異向 钱刻大部分係—垂直钮刻,小量或沒有橫向姓刻’藉此移 除水平表面(介電f填充頂部表面113及柱狀頂部表面117) 中之保形"电質層13〇,但留下該凹部體積之垂直(或 、乎垂直)側壁上之保形介電質層⑽’以形成間隙壁132。 以剖面方式顯示間隙壁132;其造形類似一具有一外側壁 及一内側壁之中空圓柱。該間隙f 132之外側壁係與該柱 狀物3GG之侧壁對準。該間隙壁132,特別是它的内側壁, 係界定-小於® le之原凹部體積之縮減的凹部體積119。 11 200840033 延伸。 將看見的是,間隙壁132的存在係縮減硫屬化合物i 22 及下方柱狀物3 00之間的接觸面積。需用熱來將硫屬化合 物轉換在其非結晶及結晶相之間。由在頂部導體4 〇 〇及底 部導體200之間施加一電壓而於本記憶體單元中產生熱。 電流流經该柱狀物3 00之二極體而供熱。介於硫屬化合物 122及該柱狀物300之電晶體間之縮減的接觸面積及由間 隙壁132所界定之縮減的凹部體積内所限制之縮減的硫屬 化合物122體積將電流及所產生的熱聚集,有助於相轉換。 若该柱狀物3 00的寬度係該特徵尺寸,則將會看見該間隙 壁1 32所界定之縮減的凹部體積之寬度係小於該特徵尺 寸。 如所述,形成該二極體之矽實際上係沉積成非結晶的。 接著,回火會結晶化該二極體,其在完成的元件中會是多 晶的。 概言之,在本範例中,該柱狀物、凹部體積及介電質 填充材料係藉由沉積該半導體材料;蝕刻該半導體材料以 形成該柱狀物;將該介電質填充材料沉積覆蓋並環繞該柱 狀物;平坦化製程以露出一部分柱狀物;選擇性蝕刻該柱 狀物以形成該凹部體積;及摻雜一部分柱狀物以形成一垂 直定向的二極體所形成。該二極體及該相變材料被_接於 該底部導體及該頂部導體之間。 、 圖ig所示之記憶體單元可以許多方式來改變。例如, 矽化物層121可被略去,或被形成於間隙壁132的形成之 12 200840033 後’而非之前。在其它實施例中,該柱狀物3 00可以不包 括一二極體,且實際上可以不由半導體材料所形成。該方 法可被使用以形成一縮減的接觸面積至任何下方導體。在 替代性實施例中,該柱狀物可由一些合適的導電材料所形 成,例如,一金屬或包含金屬矽化物之導電性金屬化合物。 如Herner於2004年9月29日所提申之美國專利申請 案號1 0/954,5 1 0,、、包括相鄰於石夕化物所結晶之半導體接 面二極體之記憶體單元,中所述,其後稱之為,51〇申請案; 以及Herner等人於2005年6月8日所提申之美國專利申 睛案號11 /14 8,5 3 0,、、藉由增加多晶半導體材料中之次序 來操作非揮發性記憶體單元,,中所述,其後稱之為,53〇申 請案,兩者皆由本案受讓人所擁有且在此將其全體一併整 合參考之,多晶矽或多晶矽二極體之特徵係受到它如何被 形成所影響。 較佳地,以一非結晶態方式沉積矽(或另一合適的半導 , 體材料),接著以一熱回火來使之結晶化。如該,510申請 案及該’530申請案中所述,已發現到的是,若該矽只與例 如氮化鈦或二氧化矽之具有大量晶格錯配之材料接觸而被 結晶化,所產生之多晶矽會具有許多缺陷,且形成時會有 相當低的電阻率。當該矽承受一高電壓或電流(藉由例如一 咼電壓被施加跨接於該二極體)時,該多晶矽的電阻率會戲 劇性地被降低。如同由受讓人所擁有且在此將其全體一併 整合參考之由Kumar等人於2006年7月28日所提申之美 國專利申請案號1 1/496,986,、、使用包括具有可調整電阻 13 200840033 之可切換的半導體記憶體構件之記憶體單元之方法〃中所 述,電阻率之變化是可逆且可重複的。 人將會回想到該記憶體單元之資料狀態是想要以該硫屬 化口物之電阻率狀態來加以儲存。較佳的是,若這類單元 也包3 —半導體二極體,則該二極體之半導體材料並不會 改變電阻率。 θ 如该’510及’530申請案中所述,已發現到的是,當一 / 例如矽之非結晶半導體材料與例如一合適矽化物之具有緊 么曰日格匹配之材料以一適當方位接觸而被結晶化時,該矽 物於忒石夕結晶化時提供一結晶化模板。所產生之石夕於形 成寸係低缺卩曰、咼品質及低電阻率。此種低缺陷石夕於承受 回電壓或電流時不會明顯地改變電阻率。由接觸一合適矽 化物所結晶化之矽所形成之二極體有利於被使用於像是圖 g中匕3 半^r體二極體及一硫屬化合物的單元之記憶體 單元中在一私式化電壓被施加跨接於該單元時,幾乎所 、有電流流動變化都是導因於該硫屬化合物之電阻率變化, 其簡化單元操作並降低程式化電壓。該單元可被覆寫,以 夕次轉換非結晶態及結晶態間之硫屬化合物,而不會實質 改變該二極體的性質。矽化鈦及矽化鈷於提供一結晶化模 板以形成高品質秒的方面係為具優勢的矽化物。在一些實 施例中,該二極體可由矽_鍺所形成。本例中,例如矽化鈦 -鍺化物或矽化鈷-鍺化物之矽化物或矽化物_鍺化物可提供 該結晶化模板。 大體上’在較佳實施例中,該二極體係由以非結晶態 14 200840033 沉積並與緊密晶格匹配之一矽化物或矽化物-鍺化物接觸以 形成結晶化之矽或矽-鍺所形成。圖1 g中較佳地係為矽化 鈷或矽化鈦之矽化物層121於所提供的範例中充當這個角 色。 該間隙壁縮減該硫屬化合物及該柱狀頂部表面間之接 觸見度及面積之分數值係由該柱狀物之寬度及將形成該間 隙壁之介電質保形層之沉積厚度之間的關係所決定。 f 大體上,該微影成像及蝕刻的製程傾向於圓滑化圖案 化特徵的角落。在小特徵尺寸下,由一光罩之方形或近乎 方形特徵中所形成之圖案化柱狀物會傾向於具有一大體上 士圓柱之外形。於是,為了要相當接近該外形,圖k的 範例中之柱狀頂部表面可視為圓形。 如圖2a所示’例如’對於一具有9〇奈米寬度之柱狀 ::二〇:言,若該保形層約沉積3〇奈米厚,則該縮減的 材料in 3〇奈米寬度。所示柱狀物被介電質填充 之面":心。沒有間隙壁132之下,該柱狀頂部表面 貝、,’、”、、 6350平方奈米。納入間隙壁132之 卞 ==曝露面積約只“❹平方奈米。該接_ 已被、、倍減至大約原面積的11〇/〇。 在另範例中’在圖2b中,假今兮知处仏 奈米官声口斗 假叹该柱狀物約具有5〇〇 、、又,且该保形層厚度約為200奈米。节 面積約具有1〇〇太乎办许%七 、 Μ鈿減的接觸 了頁部表面之面積2見度°〉又有間隙壁132之下,該柱狀 之面積約為196000平方牟半·細 之下,該接鎚而接从 十万不未,納入間隙壁132 接觸面積約只有7850平方奈米。該接觸面積已 15 200840033 被縮減至大^1店工 八约原面積的4%。 厚,心的是;若該保形層相對於該凹部寬度係太 …層可能如圖2。般地夾掉,而益法產生—欲埴 充相變材料之$階_ ^ , 叩…、次座玍奴填 特徵尺寸而;亥接觸面積可被縮減之百分比是隨著 =/。如範例,對於-約具…米寬度之柱 狀物而Β,该保形層較佳地係介於約2 s $ μt 較佳地約為10奈米… 5至約20奈米之間, /、、’邊下介於約4〇至約5奈米寬之間 一 接觸面積,較佳地約為25奈米寬。對於一約 具有25 #米寬度之柱狀物而言,該保形層較佳地係介於 約2.5至約10奈米之間,較佳地約為$奈米,並留下介於 約20至約5太丰宮+ M > 、 ^ 不木冤之間之一縮減的接觸面積,較佳地約 為15奈米寬。許多其它範例可被想像;大體上,該接觸 面積寬度較佳地係至少5奈米寬,更佳地,至少Π)奈米 寬。 i疋在具有杈大特徵尺寸之實施例中,在該縮減的 凹。P體矛貝内之一極體上方包含一介電質破裂抗熔絲可能是 較k的轉向圖3,介電質破裂抗溶絲丨23可於間隙壁13 2 形成後被形成。介電質破裂抗熔絲123較佳地係藉由將矽 化物層121曝露至一含氧及/或氮的大氣中之高溫下進行熱 成長而長成之一氧化物、氮化物或氮氧化物層。當一大電 壓被施加而跨接於介電質破裂抗熔絲丨23時,它遭遇介電 貝朋/貝,且透過該抗溶絲123形成一或多個導電破裂區域 以聚集電流。基於類似目的使用一介電質破裂抗熔絲係述 於Scheuerlein等人於2005年i月19日所提申之美國專利 16 200840033 申請案號1 1/040,255,、一種包括串接之—介電質層及一 相變材料之非揮發性記憶體單元〃,其係由本案受^人所 擁有且在此將其全體一併整合參考之。 一詳細範例會被提供以描述根據一較佳實施例所形成 之一單片式三維記憶體陣列之製造。基於完整性起見;^特 定的製程條件、尺寸、方法及材料會被提供。然而,要了 解的是,這類細節不是要限制用’許多這些細節都可被修 r 改刪去或增添,而該些結果仍落入本發明範圍内。 範例 制將詳述在一基板上方所形成之一單記憶體層(level)之 製造。額外的記憶體層可被堆疊,每一個係於下方記憶體 層上單片地形成。 轉向圖4a,該記憶體之形成開始於一基板1〇〇。此基 板1〇〇可為習知技術中所知之任何半導體基板,例如單晶 石夕、像是石夕-鍺或矽_鍺_碳之IV-IV化合物、Ιπ_ν化合物、 Η-VII化合物、覆蓋在這類基板上之磊晶層、或任何其它 半&體材料。該基板可包含製造於其中之積體電路。 一絕緣層102可被形成於該基板100上。該絕緣層1〇2 為氧化石夕、鼠化石夕、高介電薄膜、石夕-碳_氧_氫薄膜、或 任何其它合適的絕緣材料。 第—導體200被形成於該基板及絕緣體之上。一黏附 了被夾於絕緣層1 0 2及導電層10 6之間以協助導電 層106黏附至絕緣層102。黏附層104可由例如氮化鈦之 任何合適材料所形成。 17 200840033 下層要破沉積者係導電層106。導電;g ιη6 1勺衽 習知技術中所知的、.. 蜍包層106可包括 可以是鎢。 彳合適之導電材料;例如,導電層106 何合導體200之全部各層已被沉積,會使用任 實質平行且“:刻製程來圖案化及蝕刻該些層,以形成 所示延伸出:二平面之執狀導體200,如圖…剖面 —實施財,光阻被㈣,以微影 成傢技術圖幸务> ^ ^ , 術移除該光阻。,該些層’接著使用標準製程技 ::來’介電質填充材料1〇8被沉積在導體軌道2〇〇 材料^b介電f填充㈣⑽可為任何已知電性絕緣 材料,例如,介雷暂吉 積_方、土 材肖108可以是以高密度電漿沉 、 法所沉積之二氧化矽。在導體執道2〇〇頂上之 =0=斤1質/真充材料108被移除以露出由介電質填充材 /、 刀隔之導體執道200之頂部,留下一實質平坦的 表面。所產生之結構係示於圖4a中。此種移除介電質之過 以形成該平坦表面可用習知技術中例如化學機械研 碧衣程或回蝕製程之所知的任何製程來執行。 下來轉向圖4b,垂直柱狀物會被形成於已完成 ^月豆執逼200上方。為了節省空間,基板1〇〇未被顯示於 圖4b +,會假定它有存在。較佳地,在該些導體軌道之 平坦化製程之後,一阻障物層11〇被沉積以充當該第_層。 任何合適導電材料都可被使用於該阻障物層;例如,氮化 鈦可被使用。該氮化㈣11〇的厚度較佳地係自約^至 18 200840033 約200埃。 接下來,欲被圖案化成柱狀物之半導體材料被沉積。 例如矽、鍺或矽-鍺之任何合適半導體材料可被使用。為了 簡單起見,下列說明大體上會將該半導體材料視為矽,但 應了解的是,並沒有要將其它半導體或半導體合金排除在 外0 f ί 重度摻雜區域112較佳地係在該矽沉積期間,藉由提 供例如磷之η型摻雜物原子之施體氣體流動來進行原位置 摻雜。該底部重度摻雜區域112之厚度可介於約1〇〇至約 10 00埃之間,較佳地,約為2〇〇埃。 區域114係純矽,沒有添加摻雜物之下來沉積。此區 域可以習知技術中所知之任何沉積方法來形成之。在一實 施例中,矽被沉積,並沒有蓄意摻雜,但仍具有呈現輕度 η型之缺陷。在沉積期間,磷可輕易地擴散並探索該表面; 因此,來自區域112之磷會擴散至區域U4巾達某種程度。 此時區域112及114之結合厚度較佳地係介於約15〇〇至 約5000埃之間,較佳地約為4000埃。 、_沉積的半導體區域⑴卩114連同下方阻障物層ιι〇 被圖案化及钱刻以形成柱狀&綱。柱狀物_應具有與 下方導體200大約相同的間距及寬度,以使柱狀物则被 形成於-導體·的頂部上。可容許些許的未對準。 可使用任何合適的先置 九罩及蝕刻衣知來形成柱狀物 300。例如,光阻可被沉 、, 、使用知半微衫成像技術圖案 ,钮刻’接著移除該光阻。替代性地,例如二氧 19 200840033 匕立夕之另材料之硬式光罩可被形成於該半導體層堆疊的 =^上’具有底部抗反射塗佈層(BARC)於頂上,接著被圖 及蝕刻頦似地,介電質抗反射塗佈層(DARC)可被使 用充當一硬式光罩。 曰该些微影成像技術被描述於2003年12月5日由Chen 所,申之美國專利中請案號1g/72m36,、、使用替代性相 位移之具有内部無印視窗之光罩特徵夕中;或於2004年4 月^日由Chen所提申之美國專利申請案號1〇/815,312,'、具 有無絡無印相位移視窗之光罩特Π,兩者由本案受讓 =所擁有亚在此將其整合參考之,該些微影成像技術有利 、使用於執仃用以形成一記憶體陣列之任何微影成像。 狀物3 00之寬度可如所要地介於例如約25奈米至約 5〇0不米之間’例如,約為45、90或130奈米。 、貝真充材料1 〇 8被沉積而覆蓋於半導體柱狀物3⑽ 丁 /、’以填充其間的空隙。接下來,柱狀物300的 帝所"包貝材料係透過平坦化製程來移除,曝露出以介 二貝,填充材料1〇8分開之柱狀物3〇〇的頂部,並留下一實 ,: 表面。;丨電質過度填充之移除及平坦化可以習知技 術中例如化學機械研磨製程或回钱製程之所知的任何製程 執行上述結構係示於圖4 b中。 向圖4C,在平坦化製程後,一選擇性蝕刻被執行以 、目對於該介電質填充頂部表面之柱狀物300凹陷,而形 成凹部1 1。 賵知115。凹部體積115之深度係介於約1〇〇至約 1 0 0 0埃之門 、曰,較乜地約為500埃深。同時在該平坦化製程 20 200840033 期間損失一些柱狀物高度,因此之後的回蝕製程,該柱狀 物300之高度係介於約1000至約44〇〇埃之間,較佳地約 為3000埃。 接著,離子植入被執行以例如硼之p型摻雜物重度摻 雜該柱狀物之頂部區域116。底部重度摻雜n型區域112、 中間純矽區域114及頂部重度摻雜區域U6係形成一垂直 定向的p-i-n二極體。所產生的結構係示於圖4c中。 接著,一約20至約1〇〇埃之鈷(未顯示)薄層被沉積。 可藉由例如濺鍍法之任何傳統方法來沉積該鈷層。形成金 屬矽化物之其它金屬,包含鉻、鎳、鉑、鈮、鈀、钽或鈦 可被使用以取代鈷。為了簡單起見,本說明書將詳述鈷之 使用,但應了解的是,上述其它金屬中的任一者都可適當 地取代之。 遥擇性地,一約200埃之覆蓋層,較佳地為鈦或氮化 鈦,被沉積於該鈷層(未顯示)上。該鈦或氮化鈦覆蓋層有 助於接下來鈷層至矽化鈷之轉化。 轉向圖4d,以一合適溫度執行回火動作,以使該鈷層 與該些露出的二極體的多晶矽反應,而只在接觸到該些二 極體頂部的矽的地方形成一矽化鈷阻障物層121 ;在該鈷 層接觸到介電質填充材料108的地方並不會形成矽化物。 例如’可於一快速熱回火系統中以攝氏約4〇〇至約7〇〇度 的溫度執行該回火動作約20至約100秒,較佳地係在攝 氏約500度溫度下執行回火動作約30秒。該覆蓋層(若存 在的話)及該鈷層未起反應的部分可藉由一選擇性濕式蝕刻 21 200840033 來移除。在該選擇性濕式#刻之後,較佳地,—第二回火 動作被執行’以轉㈣化_ 121成為—最後更穩定的狀 態。石夕化姑層⑵會充當一阻障物層,以阻止重度摻雜石夕 區域116及-欲沉積之硫屬化合物之間的接觸。矽化鈷係 -種提供本阻障物層的有利選擇。相較於具有類似導電率 ^其它材料,砍化敍具有較低的熱傳導性,因而會提供較 多的熱給該硫屬化合物層,以協助它的相轉換。如稍早所 (區域112、114及116之石夕係非結晶沉積並於後來的 回火中被結晶化。因為此結晶化會於該矽與矽化物層ΐ2ι 進行接觸時發生,故該結晶化二極體會在—程式化電壓被 施加之前如同前述所形成方式般地由高品質、低缺陷、低 電阻率的矽所形成。 立一保形介電質材料130的薄層被沉積在介電質填充頂 部表面113、該凹部體積之側壁及柱狀物2〇〇頂部表面上。、 介電質材料uo係一具有與介電質填充材料1〇8不同且與 之具有良好蝕刻選擇性的良好步階覆蓋之介電材料。一具 了良好步階覆盍之材料會在水平及垂直兩表面上以近乎相 同的厚度進仃沉積。若介電質填充材 >料108係二氧化矽, 則氮化矽疋一種提供保形介電質材料130的有利選擇。在 替代性實施例中,該介電質填充材料及該保形介電質材 2可以疋相同的,例如,二氧化矽可被使用做為保形介電 材料130。如稍早所述,在柱狀物3〇〇之寬度及保形介 電質厚 1 q A ^ m ^ 9 尽度之間的關係決定在該硫屬化合物及該柱 狀頂部表面間的接觸面積有多少被縮減掉。較佳地,該縮 22 200840033 減的凹部體積之寬度至少要5奈米,較佳地係ι〇奈米。 例如,若柱狀物300之寬度係約9〇奈米,保形介電質層13〇 之厚度較佳地係介於約10奈米至約42奈米之間,更佳地 係介於約20奈米至約40奈米之間,例如,約%奈米。 轉向圖4e,對保形介電質層13〇執行一異向蝕刻,其 係將例如該柱狀頂部表面及該填充頂部表面之水平表面的 保形介電質層130移除,但留下例如該些凹部體積之垂直 表面上的保形介電質層13〇。傳統間隙壁蝕刻條件可被使 用’其典型地使用例如CF4/CHf3之碳氟基化學品。在該異 向蝕刻後,保留圖4d所示的由保形介電質層13〇所形成 之間隙壁132以界定縮減的凹部體積119。若保形介電質 才料13 〇及介電質填充材料10 8兩者係二氧化矽,一旦偵 、J到下方矽化鈷層i 2丨顯露出來就馬上停止該異向蝕刻。 、=欲納入—選擇性介電質破裂抗熔絲(未顯示)時,應 ;此^形成之。該介電質破裂抗熔絲可被熱成長於矽化物 層 1 2 1 μ > ^ ^ 上。在一貫施例中,充當一介電質破裂抗熔絲之二 氧化矽係藉由將矽化鈷層121曝露至一快速熱回火系統中 、5氣中較佳地在攝氏約570度至約800度溫度下持$ 約 20 $的 <a 、、貝 、、、' 秒時間而長成。在替代性實施例中,本抗溶 、糸可被’儿積而得。然而,縮減的凹部體積1 19會進一步被 本n糸層之厚度減少,因☆匕,若是有需要’應據此調整 間隙壁Π2之厚度。 β正 妾著如圖4f所示,一相變材料層122,較佳地為一 ^屬化合物材料,被形成於縮減的凹部體積119内。在填 23 200840033 充縮減的凹部體積119後,額外的相變材料122厚度應被 沉積以使相變材料層的總厚度的範圍從約2〇〇至約又 埃。該相變材料122可以是任何硫屬化合物材料,例如, 任何合適的鍺(Ge)、銻(sb)及碲(Te)化合物;這類化合物係 稱之為一 GST材料。該相變層122可藉由任何傳統方法來 形成。最常使用的硫屬化合物材料的其中之一·200840033 IX. Inventor's Note: Yan Guan's application for a patent application claims the US Patent Application No. 1 1/560,791, which is filed on November 16, 2006, and has a non-volatile phase change with reduced contact area. The memory unit, and, in U.S. Patent Application Serial No. 1/560,792, entitled "The Manufacturing Method of Non-volatile Phase Change Memory Cell with Reduced Contact Area" The interests of 〃 are hereby incorporated by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a non-volatile memory unit comprising a phase change member of a member, such as a chalcogenide compound. [Prior Art] Heat is required to convert the phase of a phase change member, and the heat supplied to the phase change member can be aggregated by reducing the contact area between the phase change member and the heat source. However, reducing the contact area to below the lithographic imaging limit may be difficult. Therefore, there is a need for a method of forming a contact area of a small feature size formed by a photographic image. [Draft] ‘and should not be in this section. In general, the present invention is directed to a phase change member and 'and the use of such a method. The present invention is defined by the following claims. Anything is considered to limit the scope of the patent application to a non-volatile memory unit. A structure formed by a reduced contact surface method is formed between the first heat sources. Method 200840033 In one aspect, a non-volatile memory cell includes: a pillar comprising a conductive or semiconducting material, the pillar having a columnar sidewall; and a dielectric over the pillar a spacer, the dielectric spacer having an outer sidewall and an inner sidewall, wherein the outer sidewall is aligned with the cylindrical sidewall and the inner sidewall defines a reduced recess volume; a phase change material 'partial' portion a phase change material is located within the reduced recess volume; and a dielectric fill material surrounding the pillar and the dielectric spacer 'where the dielectric spacer is different from the dielectric Formed by a second dielectric material of the filler material. In one aspect, a 'm〇n〇lithic three-dimensional memory array includes a) a δ 丨 丨 丨 body layer, the first memory layer including 丨 丨) a plurality of pillars 'mother one column The material comprises a conductive or semiconductive material and has a columnar sidewall; ii) a plurality of dielectric spacers, each dielectric spacer being located above one of the pillars, each dielectric The spacer has an outer side wall and an inner side wall, wherein each outer side wall of the spacer is aligned with the cylindrical side wall of one of the pillars and each inner side wall defines a reduced recess volume; a plurality of phase change members, wherein a portion of each of the phase change members is within the reduced recess volume and iv) a dielectric surrounding the pillars and the dielectric spacers a germanium filling material, wherein the dielectric spacers are formed by a second dielectric material different from the dielectric filling material; b) forming a second monolithically over the first memory layer Memory layer. In one aspect, a memory layer includes a plurality of pillars, each pillar comprising a conductive or semiconducting material and having a columnar sidewall; 6 200840033, each dielectric spacer is located therein Columnar 'each 彳 质 @ 隙 具有 — 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外Each of the phase change members has a reduced volume of the recess; and a dielectric filler surrounding the spacers, wherein the second plurality of dielectric spacers different from the dielectric filler Above and one of the inner side walls, wherein the volume of the recess of one of the pillars; a portion of the plurality of portions is in the pillar and the dielectric dielectric spacer system Formed by an electro-chemical material. In one aspect, a method of forming a semiconductor component that can be switched into a λα, an upper λα, a s, or a sj, includes: forming a conductive or semiconductor package: a dielectric filler material and a pillar of a recess volume, i octa, the dielectric filler material surrounding the pillar and having a filled swell surface, wherein the pillar has - a columnar top surface m (four) portion surface is recessed relative to the filling top surface, and wherein the recess volume has a sidewall and occupies between the filling top surface and the top surface of the city. Forming a conformal dielectric material layer on the sidewall of the recess volume and the top surface of the pillar; removing a portion of the conformal dielectric layer from the top surface of the fill and the top surface of the pillar by anisotropic etching a spacer formed by the $B material remains on the recessed volume sidewalls $ to define a reduced recess volume within the spacer, and a phase and material Z, medium, and a portion of the phase change material Positioned in the reduced recess volume Inside. In one aspect, a method of forming a monolithic three-dimensional memory array 7 200840033 includes: a) forming a first memory layer over a substrate in the following manner, the method comprising: i) forming a plurality of pillars, Each of the pillars includes a conductive or semiconductive material, a first dielectric fill material, and a plurality of recessed volumes, wherein the first dielectric fill material surrounds each of the pillars and has a filled top surface, wherein Each of the pillars has a cylindrical top surface, wherein each of the cylindrical top surfaces is concave relative to the filled top surface, and wherein each of the recessed volumes has sidewalls and occupies the filled top surface and the pillars Forming a gate of one of the cylindrical top surfaces of the top surface, u) forming a conformal dielectric material layer on the filled top surface, the recessed volume sidewalls, and the columnar top surface; Placing a portion of the conformal dielectric layer from the top surface of the fill and the surface of the pillars; the surface of the pillars; the surface of the pillars; The spacers remain on the sidewalls of the recessed volumes to define a reduced recess volume within each of the spacers; a phase change material is deposited, and a portion of the phase change material is in each of the reduced A second memory layer is formed monolithically above the first memory layer. Each of the points and embodiments described in the stove eight ST can be utilized individually or in combination with each other. These preferred views are set forth in the accompanying drawings. [Embodiment] 'Although all materials can change the phase of the target, the terms, phases, and "in this discussion" are used to illustrate that it is quite easy to determine the phase. Another material that stabilizes the phase. .兮, the phase of the private sputum becomes another crystalline state (or vice versa also: the broad non-crystalline state becomes - can also be changed from a less order to a more than 8 200840033 orderly crystalline state) _ chalcogenide compound T The phase change ^:, and vice versa is known as the phase change material. In a non-volatile memory, as early as 70, for example, a chalcogen compound is used as the mouth of the 'in which the south resistance is not... Daytime evil represents a memory state, and a low resistance crystal can suppress the gj1 heart to represent another memory state, where each memory state corresponds to the value of ^^^^ 1 of 1 or 。. To obtain the intermediate steady state, more than two kinds of memory states can exist in each mouth--------------------------------- For the sake of simplicity, the examples in this discussion will only describe the two memory states. The variable material is transformed from one state to another by twisting it to high, west, ..., 1 / dish and / or rapidly cooling from the south temperature - ❻ 夂驭 、 。 。 。 。 。 。 。 。 。 。 。 。 Transformation, different ways have been used to focus heat on exposure to the phase One of the variable materials is in a small area. The present disclosure provides a non-volatile memory for collecting heat energy including a phase change member (a member including a phase change material) by forming a contact 2 having a smaller feature size. Problems in body units - a simple and easy to manufacture solution 'This feature size is the smallest size that can be reliably formed by lithographic imaging techniques without the need for precise alignment. An embodiment will be briefly described. The rail-shaped bottom m(9) formed by any conventional method. The bottom 邛 & body 200 is preferably formed of a metal or metal material such as a titanium nitride adhesion layer i 〇 4 and a tungsten layer i 。. 2 Aligner is a pillar 300. The pillar 300 includes a barrier layer ιι which prevents the reaction between the tungsten layer 1 〇 6 and the upper semiconductor material. The bottom region 丨 12 is, for example, a type The material is heavily doped with a non-crystalline memory material, while the region 1 14 is pure germanium or lightly doped germanium. The dielectric filler material 1 (10) is 200840033 surrounding the pillar 300, and Such as chemical mechanical planarization process or At the flat surface formed by the planarization action of the mechanical polishing process, the top surface of the pillar 3 surrounded by the dielectric filling material 108 is exposed. Turning to FIG. 1b, a selective dry etching makes the relative etching The pillar 300 of the electrical fill material 108 has a recess. The pillar 3 has a cylindrical top surface 1 P that is recessed relative to the dielectric filled top surface u 3 , which forms a cylindrical top surface丨17 and a recess volume 丨丨5 filling the space between the top surface 丨13. Preferably, ion implantation is performed at this time to form a top heavily doped p-type region 116. The bottom heavily doped n-type region 112, The intermediate intrinsic region ι4 and the top heavily doped p-type region 116 form a vertically oriented pin diode. If desired, the polarity of the diode can be reversed, the p-type region is placed at the bottom and the n-type region is placed at the top. Turning to Fig. 1c, a germanium-forming metal layer 丨2 is deposited on the dielectric filled top surface 113, the cylindrical top surface 117, and the sidewalls of the recess volume 115. A first tempering causes the metal 120 to react with the heavily doped region 1 1 ’ of the crucible to form a metallurgical layer at the top of the pillar 300. The telluride-forming metal 120 can be, for example, cobalt or titanium to form a cobalt or titanium telluride layer 1 21 which is not shown. A selective wet etching strips unreacted cobalt or titanium leaving only the telluride 12 顶部 at the top of the pillar 300. Preferably, a second tempering is followed by completion of the telluride reaction. As will be seen, the telluride 121 acts as a barrier between the top heavily doped region n6 of the crucible and a phase change material to be deposited later. Shi Xi Chemical 10 200840033 After taking in Figure lg, a layer of phase change material 122 is deposited to fill the reduced recess volume 119. The phase change material 122 is preferably deposited in a chemical mechanical polishing termination layer (eg, by nitriding) 124 in the present embodiment, followed by a chemical mechanical polishing termination layer 124 and a chalcogenide. The material 122 is patterned, surnamed, and after more dielectric filler 'will 〇 y, 'tank process to expose the top of the chemical mechanical polishing stop layer 124, in this embodiment, The top conductor 4 is formed on the chalcogen compound 122. The top guide 400 can be formed in the same manner and with the same material as the bottom conductor. For example, an additional barrier layer of the barrier 124 can be incorporated. In the vertical view, the top conductor 400 is preferably used to change the direction perpendicular to the bottom conductor 2 (in the form, the shoulder does not extend beyond the top conductor 4 该 outside the page) (2) Polar body characteristics, as will be described later. Please note that the top surface of the enamel 121 is now the columnar top surface 117. In the U, a conformal dielectric thin layer 130 is deposited on the top surface 113, the sidewalls of the recess volume (1), and the columnar top surface 117. As shown in Figure lf, the anisotropic button is executed; the opposite direction is mostly - vertical button engraving, small or no lateral surrogate 'by removing the horizontal surface (dielectric f fills the top surface 113 and The conformal "electroless layer 13' in the cylindrical top surface 117) leaves the conformal dielectric layer (10)' on the vertical (or vertical) sidewalls of the recess volume to form the spacers 132. The spacer 132 is shown in cross section; it is shaped like a hollow cylinder having an outer side wall and an inner side wall. The outer side of the gap f 132 is aligned with the side wall of the pillar 3GG. The spacer 132, and particularly its inner side wall, defines a reduced recess volume 119 that is less than the original recess volume of the ® le. 11 200840033 Extension. It will be seen that the presence of the spacers 132 reduces the contact area between the chalcogenide compound i 22 and the underlying pillars 300. Heat is required to convert the chalcogenide between its amorphous and crystalline phases. Heat is generated in the memory cell by applying a voltage between the top conductor 4 〇 and the bottom conductor 200. A current flows through the diode of the column 300 to supply heat. The reduced contact area between the chalcogenide compound 122 and the transistor of the pillar 300 and the reduced volume of the chalcogenide 122 limited by the reduced recess volume defined by the spacer 132 will result in current flow and Thermal aggregation helps in phase conversion. If the width of the column 300 is the feature size, it will be seen that the width of the reduced recess volume defined by the spacer wall 322 is less than the feature size. As described, the ruthenium forming the diode is actually deposited as amorphous. The tempering then crystallizes the diode, which will be polycrystalline in the finished component. In summary, in the present example, the pillar, the recess volume, and the dielectric filling material are formed by depositing the semiconductor material; etching the semiconductor material to form the pillar; depositing the dielectric filler material And surrounding the pillar; planarizing the process to expose a portion of the pillar; selectively etching the pillar to form the recess volume; and doping a portion of the pillar to form a vertically oriented diode. The diode and the phase change material are connected between the bottom conductor and the top conductor. The memory unit shown in Figure ig can be changed in many ways. For example, the telluride layer 121 may be omitted or formed after the formation of the spacer 132 12 200840033 rather than before. In other embodiments, the pillars 300 may not include a diode and may not actually be formed of a semiconductor material. This method can be used to form a reduced contact area to any of the underlying conductors. In an alternative embodiment, the pillars may be formed from some suitable electrically conductive material, such as a metal or a conductive metal compound comprising a metal halide. U.S. Patent Application Serial No. 10/954,510, issued Sep. 29, 2004, which is incorporated herein by reference. In the above, it is referred to as the 51〇 application; and the US patent application number 11/14 8,5 3 0, as proposed by Herner et al. on June 8, 2005, by The order of the polycrystalline semiconductor materials to operate the non-volatile memory cells, as described therein, is hereinafter referred to as the 53 〇 application, both of which are owned by the assignee of the present application and are hereby incorporated herein in their entirety. For integration, the characteristics of polycrystalline germanium or polycrystalline germanium diodes are affected by how it is formed. Preferably, the crucible (or another suitable semiconducting material) is deposited in an amorphous state and then crystallized by a thermal tempering. As described in the 510 application and the '530 application, it has been found that if the crucible is crystallized only by contact with a material having a large number of lattice mismatches such as titanium nitride or ceria, The resulting polysilicon will have many defects and will have a relatively low resistivity when formed. When the crucible is subjected to a high voltage or current (by, for example, a voltage applied across the diode), the resistivity of the polysilicon is dramatically reduced. U.S. Patent Application Serial No. 1 1/496,986, filed on Jul. 28, 2006, to which the assignee is assigned to the assignee. The method of the memory cell of the switchable semiconductor memory component of the resistor 13 200840033, the change in resistivity is reversible and repeatable. One will recall that the data state of the memory cell is intended to be stored in the resistivity state of the chalcogenide. Preferably, if such a unit also includes a semiconductor diode, the semiconductor material of the diode does not change the resistivity. θ As described in the '510 and '530 applications, it has been found that when a/for example a non-crystalline semiconductor material of tantalum is in a suitable orientation with, for example, a suitable telluride material having a tighter match. Upon crystallization by contact, the ruthenium provides a crystallization template upon crystallization of the ruthenium. The resulting stone is formed in a low-profile, low-quality, low-resistance. Such a low-defect stone does not significantly change the resistivity when subjected to a return voltage or current. The dipole formed by the crystallization of a suitable bismuth compound is advantageously used in a memory unit such as a unit of a 半3 ^r body diode and a chalcogen compound in FIG. When a voltage is applied across the cell, almost any change in current flow is due to a change in resistivity of the chalcogenide compound, which simplifies cell operation and reduces the stylized voltage. The unit can be overwritten to convert the non-crystalline and crystalline chalcogen compounds in the evening without substantially altering the properties of the dipole. Titanium telluride and cobalt telluride are advantageous tellurides in terms of providing a crystallization template to form high quality seconds. In some embodiments, the diode can be formed from 矽_锗. In this case, a crystallization template can be provided, for example, a telluride or telluride- telluride or telluride-telluride telluride or telluride- telluride. In general, 'in a preferred embodiment, the dipole system is formed by a non-crystalline state 14 200840033 deposited and in contact with a compact lattice matching one of the telluride or telluride-telluride to form a crystallized crucible or crucible form. The telluride layer 121, preferably in the form of cobalt telluride or titanium telluride, in Fig. 1 g serves as this role in the example provided. The gap between the chalcogenide compound and the columnar top surface is determined by the difference between the width of the pillar and the deposited thickness of the dielectric conformal layer that will form the spacer. The relationship is determined. f In general, the lithography imaging and etching process tends to round the corners of the patterned features. At small feature sizes, the patterned pillars formed by the square or nearly square features of a reticle will tend to have a generally cylindrical outer shape. Thus, in order to be fairly close to the profile, the cylindrical top surface of the example of Figure k can be considered circular. As shown in Fig. 2a, for example, for a column having a width of 9 〇 nanometer:: 〇: If the conformal layer is deposited by about 3 nanometers thick, the reduced material is in the width of 3 nanometers. . The surface of the column shown is filled with dielectric ": heart. There is no gap wall 132 below, the columnar top surface is shell, ', ', and 6,350 square nanometers. 纳入 is included in the spacer 132 == the exposed area is only about "square nanometer." This connection has been reduced to approximately 11 〇/〇 of the original area. In another example, in Fig. 2b, it is known that the column is about 5 、, and the thickness of the conformal layer is about 200 nm. The area of the joint has about 1%, and the area of the surface of the page is 2%. Under the gap 132, the area of the column is about 196,000 square feet. Under the fineness, the hammer is connected from 100,000, and the contact area of the spacer 132 is only about 7,850 square nanometers. The contact area has been reduced to 4% of the original area of the 18th century. Thick, the heart is; if the conformal layer is too thick relative to the width of the recess, it may be as shown in FIG. Generally, it is clipped off, and the profit-generating method is used to generate the phase-order material of the phase-changing material, and the percentage of the contact area can be reduced with the =/. As an example, for a column having a width of about meters, the conformal layer is preferably between about 2 s $ μt, preferably about 10 nm... 5 to about 20 nm, /, , 'A contact area between about 4 〇 and about 5 nm wide, preferably about 25 nm wide. For a pillar having a width of 25 # meters, the conformal layer is preferably between about 2.5 and about 10 nanometers, preferably about $ nanometer, and is left at about 20 to about 5 Taifeng Palace + M > , ^ One of the reduced contact areas between the rafts, preferably about 15 nm wide. Many other examples are conceivable; in general, the contact area width is preferably at least 5 nanometers wide, and more preferably at least Π) nanometer wide. In the embodiment having a large feature size, the reduced concave is in the reduced size. The inclusion of a dielectric rupture antifuse over one of the pole bodies of the P-spear may be a turning of FIG. 3, and the dielectric rupture anti-solvent 23 may be formed after the formation of the spacer 13 2 . The dielectric rupture antifuse 123 is preferably grown by one of oxide, nitride or nitriding by thermally growing the telluride layer 121 to an elevated temperature in an atmosphere containing oxygen and/or nitrogen. Layer of matter. When a large voltage is applied across the dielectric rupture anti-fuse enthalpy 23, it encounters a dielectric scallop, and one or more electrically conductive rupture regions are formed through the anti-solvent 123 to concentrate the current. The use of a dielectric rupture anti-fuse for a similar purpose is described in U.S. Patent No. 1,2008,040, filed on Jan. The non-volatile memory unit of the layer and the phase change material is owned by the person in charge of the case and is hereby incorporated by reference in its entirety. A detailed example will be provided to describe the fabrication of a monolithic three dimensional memory array formed in accordance with a preferred embodiment. For the sake of completeness; specific process conditions, dimensions, methods and materials will be provided. However, it is to be understood that such details are not intended to be limiting. Many of these details may be modified or deleted, and such results are still within the scope of the invention. The example system will detail the fabrication of a single memory level formed over a substrate. Additional memory layers can be stacked, each formed monolithically on the underlying memory layer. Turning to Figure 4a, the formation of the memory begins on a substrate 1 〇〇. The substrate 1 can be any semiconductor substrate known in the prior art, such as a single crystal, such as a stone-like or 矽_锗_carbon IV-IV compound, a Ιπ_ν compound, a Η-VII compound, An epitaxial layer overlying such a substrate, or any other semi- & bulk material. The substrate can include an integrated circuit fabricated therein. An insulating layer 102 may be formed on the substrate 100. The insulating layer 1〇2 is an oxidized stone, a ratified fossil, a high dielectric film, a stone-carbon-oxygen-hydrogen film, or any other suitable insulating material. The first conductor 200 is formed on the substrate and the insulator. An adhesive layer is sandwiched between the insulating layer 102 and the conductive layer 106 to assist in bonding the conductive layer 106 to the insulating layer 102. Adhesion layer 104 can be formed of any suitable material such as titanium nitride. 17 200840033 The lower layer is to break the depositor conductive layer 106. Conductive; g ιη6 1 scoop 衽 As is known in the art, the enamel layer 106 may comprise tungsten. Suitable conductive materials; for example, conductive layer 106, all layers of conductor 200 have been deposited, and the layers are patterned and etched using substantially parallel and "etching processes" to form the extended: two planes The conductor 200, as shown in the figure, is a cross-section of the implementation, and the photoresist is (4), and the photoresist is removed by the technique of removing the photoresist. The layers are then processed using standard process technology. ::Coming 'dielectric filling material 1〇8 is deposited on the conductor track 2〇〇 material ^b dielectric f filling (4) (10) can be any known electrical insulating material, for example, Jielei temporary Jiji _ square, soil material Xiao 108 may be a high-density plasma deposition method deposited by cerium oxide. The conductor at the top of the conductor 2 = 0 = 1 mass / true charge material 108 is removed to expose the dielectric filler / The top of the conductor of the knife is 200, leaving a substantially flat surface. The resulting structure is shown in Figure 4a. Such removal of the dielectric to form the flat surface can be accomplished, for example, in the prior art. Chemical mechanical research is performed on any process known as the Bi-coating process or the etch-back process. In Figure 4b, a vertical pillar will be formed over the finished stalk bean 200. To save space, the substrate 1 〇〇 is not shown in Figure 4b +, it will be assumed to exist. Preferably, in these After the planarization process of the conductor track, a barrier layer 11 is deposited to serve as the first layer. Any suitable conductive material can be used for the barrier layer; for example, titanium nitride can be used. The thickness of the (11) 11 较佳 is preferably from about 2 to 18 200840033 and about 200 angstroms. Next, the semiconductor material to be patterned into pillars is deposited. Any suitable semiconductor material such as ruthenium, iridium or iridium may be For the sake of simplicity, the following description will generally consider the semiconductor material as germanium, but it should be understood that other semiconductors or semiconductor alloys are not excluded from the outer region. During the germanium deposition, the home position doping is performed by providing a donor gas flow such as a phosphorus n-type dopant atom. The bottom heavily doped region 112 may have a thickness of between about 1 Å and about 100 Å. Between, preferably, about 2 The region 114 is pure germanium and is deposited without the addition of dopants. This region can be formed by any deposition method known in the art. In one embodiment, the tantalum is deposited without deliberate blending. Miscellaneous, but still having the drawback of exhibiting a mild n-type. Phosphorus can easily diffuse and explore the surface during deposition; therefore, phosphorus from region 112 will diffuse to some extent in region U4. The bonding thickness of 114 is preferably between about 15 Å and about 5,000 angstroms, preferably about 4,000 angstroms. The deposited semiconductor region (1) 卩 114 is patterned along with the underlying barrier layer ιι and The money is engraved to form a columnar & outline. The pillars should have approximately the same pitch and width as the lower conductor 200 such that the pillars are formed on top of the -conductor. A little misalignment can be tolerated. The pillars 300 can be formed using any suitable pre-jade and etching coating. For example, the photoresist can be sunk, using a pattern of imaging techniques, and then the photoresist is removed. Alternatively, a hard mask such as dioxin 19 200840033 can be formed on the top of the semiconductor layer stack with a bottom anti-reflective coating layer (BARC), followed by etching and etching. Similarly, a dielectric anti-reflective coating (DARC) can be used as a hard mask.曰The lithography imaging techniques are described in the December 5, 2003 by Chen, the US patent application No. 1g/72m36, using an alternative phase shift with a reticle feature with an internal unprinted window; Or the U.S. Patent Application No. 1/815,312, filed by Chen on April 2, 2004, with a reticle feature with a collateral-free phase-shifting window, both of which are transferred by the case = owned by Ya This is incorporated by reference, and the lithographic imaging techniques are advantageous for use in performing any lithographic imaging to form a memory array. The width of the material 300 can be as desired, for example, between about 25 nanometers and about 5 inches, and is, for example, about 45, 90 or 130 nanometers. The beryllium filling material 1 〇 8 is deposited to cover the semiconductor pillar 3 (10) butyl /, ' to fill the gap therebetween. Next, the Imperial "Baobei material of the column 300 is removed through a flattening process, and the top of the column 3〇〇 separated by the filling material 1〇8 is exposed, and left A real,: surface. Removal and planarization of the overfill of the ruthenium can be performed by any of the processes known in the art, such as chemical mechanical polishing processes or rework processes. The above structure is shown in Figure 4b. Referring to Fig. 4C, after the planarization process, a selective etch is performed to recess the pillars 300 filling the top surface of the dielectric to form the recesses 11. I know 115. The depth of the recess volume 115 is between about 1 〇〇 and about 10,000 angstroms, and is about 500 angstroms deeper than the ground. At the same time, some of the pillar height is lost during the planarization process 20 200840033, so the subsequent etchback process has a height of between about 1000 and about 44 angstroms, preferably about 3,000. Ai. Next, ion implantation is performed to heavily dope the top region 116 of the pillar with a p-type dopant such as boron. The bottom heavily doped n-type region 112, the intermediate pure germanium region 114, and the top heavily doped region U6 form a vertically oriented p-i-n diode. The resulting structure is shown in Figure 4c. Next, a thin layer of cobalt (not shown) of from about 20 to about 1 angstrom is deposited. The cobalt layer can be deposited by any conventional method such as sputtering. Other metals forming metal halides, including chromium, nickel, platinum, rhodium, palladium, iridium or titanium, may be used in place of cobalt. For the sake of simplicity, this specification will detail the use of cobalt, but it should be understood that any of the other metals described above may be suitably substituted. Selectively, a cover layer of about 200 angstroms, preferably titanium or titanium nitride, is deposited on the cobalt layer (not shown). The titanium or titanium nitride coating layer facilitates the subsequent conversion of the cobalt layer to cobalt telluride. Turning to Figure 4d, a tempering action is performed at a suitable temperature to cause the cobalt layer to react with the polycrystalline germanium of the exposed diodes, and a cobalt antimonide resist is formed only in contact with the germanium at the top of the diodes. The barrier layer 121 does not form a telluride where the cobalt layer contacts the dielectric fill material 108. For example, the tempering action can be performed in a rapid thermal tempering system at a temperature of about 4 to about 7 degrees Celsius for about 20 to about 100 seconds, preferably at a temperature of about 500 degrees Celsius. The fire action is about 30 seconds. The cap layer (if present) and the unreacted portion of the cobalt layer can be removed by a selective wet etch 21 200840033. Preferably, after the selective wet type engraving, the second tempering action is performed to turn "four" into a final more stable state. The Shixi Huagu layer (2) acts as a barrier layer to prevent contact between the heavily doped Shixia region 116 and the chalcogen compound to be deposited. Cobalt telluride is an advantageous option for providing the present barrier layer. Compared to other materials with similar conductivity, the decomposing has a lower thermal conductivity and thus provides more heat to the chalcogenide layer to assist in its phase transition. As early as possible (the regions 112, 114 and 116 are amorphous and deposited in subsequent tempering. This crystallization occurs when the yttrium is in contact with the bismuth layer ΐ2ι, so the crystallization The diode will be formed of high quality, low defect, low resistivity germanium as before the stylized voltage is applied. A thin layer of the conformal dielectric material 130 is deposited in the dielectric layer. The electric material fills the top surface 113, the sidewall of the recess volume, and the top surface of the pillar 2 . The dielectric material uo has a different etching property than the dielectric filler 1〇8 and has good etching selectivity. A good step covering the dielectric material. A material with a good step coverage will deposit on the horizontal and vertical surfaces at approximately the same thickness. If the dielectric filler > 108 is oxidized Further, the tantalum nitride is an advantageous option for providing the conformal dielectric material 130. In an alternative embodiment, the dielectric fill material and the conformal dielectric material 2 may be the same, for example, two Cerium oxide can be used as a conformal Electrical material 130. As described earlier, the relationship between the width of the pillar 3〇〇 and the conformal dielectric thickness 1 q A ^ m ^ 9 is determined by the chalcogen compound and the columnar top Preferably, the contact area between the surfaces is reduced. Preferably, the width of the concave portion reduced by 2240040033 is at least 5 nanometers, preferably ιηηη. For example, if the width of the pillars 300 is Preferably, the thickness of the conformal dielectric layer 13 系 is between about 10 nm and about 42 nm, more preferably between about 20 nm and about 40 nm. For example, about % nanometer. Turning to Fig. 4e, an anisotropic etching is performed on the conformal dielectric layer 13A, which is a conformal dielectric such as the columnar top surface and the horizontal surface of the filled top surface. The layer 130 is removed, but leaving a conformal dielectric layer 13 on the vertical surface of the recess volume, for example. Conventional spacer etching conditions can be used 'which typically uses fluorocarbon-based chemistry such as CF4/CHf3 After the anisotropic etch, the spacers 132 formed by the conformal dielectric layer 13 所示 shown in FIG. 4d are retained to define the reduction. The concave volume 119. If both the conformal dielectric material 13 〇 and the dielectric filling material 108 are cerium oxide, the anisotropic etching is stopped immediately after the detection of J and the lower bismuth cobalt layer i 2 丨 is exposed. , = = to be incorporated - selective dielectric rupture anti-fuse (not shown), should be formed; this dielectric rupture anti-fuse can be thermally grown in the telluride layer 1 2 1 μ > ^ ^ Above. In a consistent embodiment, the cerium oxide serving as a dielectric rupture antifuse is exposed to a rapid thermal tempering system by a cobalt sulphide layer 121, preferably in Celsius. Between 570 degrees and about 800 degrees, holding about $20 <a , , , , , , , ' In an alternative embodiment, the present anti-solvent, hydrazine can be obtained. However, the reduced recess volume 1 19 is further reduced by the thickness of the n 糸 layer, since ☆ 匕, if necessary, the thickness of the gap Π 2 should be adjusted accordingly. As shown in Fig. 4f, a phase change material layer 122, preferably a compound material, is formed in the reduced recess volume 119. After filling the reduced recess volume 119 of 200840033, the additional phase change material 122 thickness should be deposited such that the total thickness of the phase change material layer ranges from about 2 Torr to about angstroms. The phase change material 122 can be any chalcogenide material, for example, any suitable germanium (Ge), antimony (sb), and tellurium (Te) compounds; such compounds are referred to as a GST material. The phase change layer 122 can be formed by any conventional method. One of the most commonly used chalcogenide materials

GeJl^Te5,具有一熔化溫度為攝氏61〇度。使用傳統方法 來結晶化矽所需之溫度大致上超過攝氏61〇度。鍺及矽_鍺 合金之結晶化溫度較矽低,且使用於柱狀物3〇〇中以降低 形成目W及接下來各記憶體層所需之溫度可能是較佳的。 一導電性化學機械研磨終止材料層丨24較佳地被沉積 於该相變層122上。任何合適材料都可被使用於該化學機 械研磨終止層,·氮化鈦係較佳的。此化學機械研磨終止層 124之厚度較佳地係介於約5〇〇至約1〇〇〇埃之間,例如, 約800埃厚。 接著,化學機械研磨終止層124及相變層122被圖案 化並钱刻,較佳地係以短柱狀物3 〇2形式進行。圖案化柱 狀物300所使用之相同光罩可被重複使用於本微影成像製 程中。Chen等人於2005年3月31日所提申之美國專利申 請案號1 1/097,496,、、遮蓋重複性重疊及對準標記以允許 在一垂直結構中重複使用光罩〃中描述到在重複使用光罩 時可能會遭遇問題之避免方法,該專利申請案由本案受讓 人所擁有並在此將其整合參考之。理想上,化學機械研磨 終止層124及相變材料122之短柱狀物3〇2及柱狀物 24 200840033 係完吴地對準,但只有在該蝕刻相變材料構件i22重疊間 隙壁132時才是必要的。因此,間隙壁132可容許實質未 對準的柱狀物300及短柱狀物3〇2。部分對準係示於圖4f。 餃刻後;丨笔貝填充材料108被沉積於短柱狀物3〇2 之上及其間,以填充其間的空隙。例如化學機械研磨之平 坦化製程移除過度填充物並且曝露出一實質平坦表面處的 化學機械研磨終止層124。請注意的是,化學機械研磨終 止層124不是必要的,並且在一些實施例中可被省略。然 而,其提供一些優勢。雖然理想上一旦曝露出化學機械研 磨終止層124就立刻停止該化學機械研磨製程,但實際上 會有某種程度的過度平坦化,而層124的一些厚度會被移 除。實務上,這個厚度可達500埃或更多,也可能無法均 勻的遍佈於一晶圓各處。因為該化學機械研磨係執行於氮 化鈦層124,並非硫屬化合物丨22上,硫屬化合物1S2的 厚度係相當均勻的遍佈於該晶圓各處,以提供裝置均句 度。此外,硫屬化合'物係難以研磨拋光及清洗;這個可藉 由一氮化鈦化學機械研磨終止層124之使用而被避開。 頂部導體接著被形成。頂部導體較佳地係由與底部導 綈200相同的材料及方式所構成。例如,氮化鈦黏附層404 及鎢導電層406可被沉積於該介電質填充材料1〇8中露出 短柱狀物302之平坦表面上。接著,鎢層4〇6及氮化鈦層 4 0 4被圖案化及#刻以形成圖4 f所示由左至右延伸而橫跨 該頁之實質平行且實質共平面的導體400。 圖4 f所示結構係一苐一記憶體層。本結構可被許多方 25 200840033 法改變。例如,为一 物122德Μ — 所不的一替代例中,沉積硫屬化合 後接者沉積例如氣化鈇(此層充當硫屬化合物a】及 -上方導體之間的化學阻障物,且此層厚度自至 H佳地’厚度介於約⑽至約細埃之間)之阻障物層 “曰406被沉積在阻障物層】26上。導電層々%、 阻障物層U6及硫屬化合物122被圖案化及 部導體400。許多其它架構都是可行的。 成頁 接著’不是在圖4f就是在圖5實施例中,一介電材料 (未顯不)被沉積於導體執冑4〇〇之上及其間。該介電材料 可為例如氧化石夕、氮切或氮氧化石夕之任何已知的電性絕 緣材料。在-較佳實施例中,高密度電漿沉積氧化物被使 用以充當本介電材料。 儘管剛剛所描述之陣列結構在一些重要方法上不同於 Herner等人於美國專利號6,952,〇3〇,其後稱之為該,〇3〇 專利(由本案受讓人所擁有並在此將其整合參考之)及 該’510 _請案及該’53G巾請案巾所描述之陣列結構,但是 這些申請案及本專利之製造方法料被使用。基於清晰起 見,這些申請案及專利之製造細節未全部被納入,但並沒 有要排除它們的教示。 圖4f及圖5所示的結構中之每一個係一第一記憶體 層。額外的記憶體層可被單片地形成於本記憶體層之上以 形成一單片式三維記憶體陣列。在一些實施例中,一層間 的介電質係分開不共用導體之記憶體層。在其它實施例 中,導體可被共用;例如,頂部導體4〇〇可充當下一記憶 26 200840033 體層之底部導體。 一單片式三維記憶體陣列係其内多記憶體層被形成於 例如一晶圓之不具内插基板之單一基板上者。相對地,堆 疊式記憶體係藉由在獨立基板上形成記憶體層並膠黏彼此 堆登δ玄些g己丨思體層來架構之,如同Leedy於美國專利號 5,9 1 5,1 67,、、三維結構記憶體"中所述。該些基板可於黏 結前被薄化或自該些記憶體層中移除,但若該些記憶體層GeJl^Te5 has a melting temperature of 61 degrees Celsius. The temperature required to crystallize hydrazine using conventional methods is substantially over 61 degrees Celsius. The crystallization temperature of the ruthenium and osmium alloys is relatively low, and it may be preferable to use them in the column 3 to reduce the temperature required for forming the W and the subsequent memory layers. A conductive chemical mechanical polishing termination material layer 24 is preferably deposited on the phase change layer 122. Any suitable material can be used for the chemical mechanical polishing stop layer, and titanium nitride is preferred. The thickness of the CMP stop layer 124 is preferably between about 5 Å and about 1 Å, for example, about 800 Å thick. Next, the chemical mechanical polishing stop layer 124 and the phase change layer 122 are patterned and etched, preferably in the form of short pillars 3 〇 2 . The same reticle used to pattern the pillars 300 can be reused in the lithographic imaging process. U.S. Patent Application Serial No. 1 1/097,496, filed on March 31, 2005, the disclosure of the disclosure of the entire disclosure of A method of avoiding problems may be encountered when reusing the reticle, which is owned by the assignee of the present application and incorporated herein by reference. Ideally, the chemical mechanical polishing stop layer 124 and the short pillars 3〇2 of the phase change material 122 and the pillars 24 200840033 are aligned, but only when the etched phase change material member i22 overlaps the spacers 132. It is necessary. Therefore, the spacer 132 can accommodate the substantially unaligned pillars 300 and the short pillars 3〇2. A partial alignment is shown in Figure 4f. After the dumpling is engraved; the enamel filling material 108 is deposited on and between the short pillars 3〇2 to fill the gap therebetween. A chemical mechanical polishing process, for example, removes excess filler and exposes a chemical mechanical polishing stop layer 124 at a substantially planar surface. It is noted that the chemical mechanical polishing termination layer 124 is not necessary and may be omitted in some embodiments. However, it offers some advantages. Although it is desirable to stop the CMP process as soon as the CMP finish 124 is exposed, there is actually some degree of excessive planarization and some of the thickness of layer 124 is removed. In practice, this thickness can reach 500 angstroms or more, and it may not be evenly distributed throughout a wafer. Since the CMP is performed on the titanium nitride layer 124, not on the chalcogen compound 丨22, the thickness of the chalcogenide compound 1S2 is fairly uniform throughout the wafer to provide device uniformity. In addition, the chalcogenide 'system is difficult to grind and polish; this can be avoided by the use of a titanium nitride CMP mechanical stop layer 124. The top conductor is then formed. The top conductor is preferably constructed of the same material and manner as the bottom guide 200. For example, a titanium nitride adhesion layer 404 and a tungsten conductive layer 406 may be deposited on the flat surface of the dielectric fill material 1 露出 8 exposing the short pillars 302. Next, the tungsten layer 4〇6 and the titanium nitride layer 104 are patterned and patterned to form substantially parallel and substantially coplanar conductors 400 extending from left to right as shown in Fig. 4f. The structure shown in Figure 4f is a memory layer. This structure can be changed by many parties. For example, in an alternative to an object 122, a deposition of a chalcogenide compound deposits, for example, a gasification enthalpy (this layer acts as a chalcogen compound a) and a chemical barrier between the upper conductors, And the thickness of the layer is from the barrier layer "the thickness of about (10) to about fine (about) is about (about 10) to about fine), the barrier layer "曰 406 is deposited on the barrier layer" 26. Conductive layer 、%, barrier layer U6 And the chalcogenide compound 122 is patterned and the portion of the conductor 400. Many other configurations are possible. The page is followed by 'not in Figure 4f or in the embodiment of Figure 5, a dielectric material (not shown) is deposited on the conductor The dielectric material may be any known electrically insulating material such as oxidized stone, nitrogen cut or nitrous oxide. In the preferred embodiment, the high density plasma is used. The deposited oxide is used to serve as the present dielectric material. Although the array structure just described differs from Herner et al. in U.S. Patent No. 6,952, 〇3, in some important methods, hereinafter referred to as the 〇3 〇 patent. (owned by the assignee of the case and integrated here by reference) and the '510 _ The case and the array structure described in the '53G towel request case, but these applications and the manufacturing methods of this patent are intended to be used. For the sake of clarity, the manufacturing details of these applications and patents are not fully incorporated, but The teachings of Figures 4f and 5 are each a first memory layer. Additional memory layers can be formed monolithically over the memory layer to form a monolithic A three-dimensional memory array. In some embodiments, the dielectric between one layer separates the memory layers that do not share the conductor. In other embodiments, the conductors can be shared; for example, the top conductor 4 can serve as the next memory 26 200840033 Bottom conductor of a bulk layer. A monolithic three-dimensional memory array in which multiple memory layers are formed on a single substrate, such as a wafer, without interposer substrates. In contrast, stacked memory systems are implemented on separate substrates. The memory layers are formed and glued to each other to form a layer of δ 玄 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Said. The plurality of substrate may be thinned or removed from the plurality of memory layer before junction sticky, but if the plurality of memory layers

最初被形成於獨立基板上,這類記憶體並不是真的單片式 三維記憶體陣列。 形成於一基板上之單片式三維記憶體陣列包括在該基 板上方一第一高度處所形成之至少一第一記憶體層以及在 一不同於該第一高度之第二高度處所形成之一第二記憶體 層。二、四、八或甚至任意數量的記憶體層可以用此種多 層陣列方式形成於該基板上方。在其它實施例中,只有單 -記憶體層如所述地被形成,而沒有額外的堆疊式記憶體 層被形成於該第一記憶體層上方。 雖已在此描述詳細的製造方法,但形成該些相同結構 之其它方法可被使用,而結果落在本發明範圍内。 前述詳細說明只描述本發明採用許多形式中的—些。 基於此理由,本詳細說明是要舉例說明,並非要:° 只有包含所有等效例之下列申靖喜 彳^專心圍是要定義本發明 固叭間早說 圖以至lg係根據—較佳實施例顯示形成—記憶體單 27 200840033 元之各階段剖面圖。 圖2a至2c係說明各種實施例中該保形介電質層之柱 狀物寬度、厚度及該縮減的凹部體積之尺寸之間的二係剖 面圖。 圖3係包含一介電質破裂抗熔絲之另—實施例之剖面 圖。 圖4a至4f係根據一實施例顯示在一單片式三維記情 體陣列中形成一記憶體層之各階段剖面圖。 " 圖5係根據一貫施例顯示在一單片式三維記憶體陣列 中的一記憶體層之剖面圖。 【主要元件符號說明】 100 基板 102 絕緣層 104 、 404 氮化鈦黏附層 106 、 406 鎢導電層 108 介電質填充材料 110 、 126 阻障物層 112 底部重度摻雜n型 113 介電質填充頂部表 114 中間本徵區域 115 凹部體積 116 頂部重度摻雜ρ型 117 柱狀頂部表面 119 縮減的凹部體積 28 200840033 120 形成石夕化物的金屬層 121 矽化物層 122 相變材料 124 化學機械研磨終止層 123 介電質破裂抗熔絲 132 間隙壁 200 底部導體 300 柱狀物 302 短柱狀物 400 頂部導體 29Originally formed on a separate substrate, this type of memory is not really a monolithic three-dimensional memory array. The monolithic three-dimensional memory array formed on a substrate includes at least one first memory layer formed at a first height above the substrate and a second formed at a second height different from the first height Memory layer. Two, four, eight or even any number of memory layers can be formed over the substrate in such a multi-layer array. In other embodiments, only the single-memory layer is formed as described, and no additional stacked memory layers are formed over the first memory layer. Although detailed manufacturing methods have been described herein, other methods of forming the same structures can be used, and the results fall within the scope of the present invention. The foregoing detailed description describes only the invention in many forms. For the sake of this reason, the detailed description is intended to be illustrative, and is not intended to: "only the following Shen Jingxi 彳 专 包含 包含 包含 包含 包含 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专 专Forming a section of each stage of the memory single 27 200840033 yuan. Figures 2a through 2c are two-dimensional cross-sectional views illustrating the width, thickness, and dimensions of the reduced recess volume of the conformal dielectric layer in various embodiments. Figure 3 is a cross-sectional view of another embodiment including a dielectric rupture antifuse. 4a through 4f are cross-sectional views showing stages of forming a memory layer in a monolithic three-dimensional essay array, in accordance with an embodiment. " Fig. 5 is a cross-sectional view showing a memory layer in a monolithic three-dimensional memory array according to a conventional embodiment. [Main component symbol description] 100 substrate 102 insulating layer 104, 404 titanium nitride adhesion layer 106, 406 tungsten conductive layer 108 dielectric filling material 110, 126 barrier layer 112 bottom heavily doped n-type 113 dielectric filling Top Table 114 Intermediate Intrinsic Region 115 Concave Volume 116 Top Heavy Doped p-Type 117 Column Top Surface 119 Reduced Concave Volume 28 200840033 120 Metal Layer 121 Forming Lithium Compound 122 Phase Change Material 124 Chemical Mechanical Grinding Termination Layer 123 dielectric rupture antifuse 132 spacer 200 bottom conductor 300 pillar 302 short pillar 400 top conductor 29

Claims (1)

200840033 十、申請專利範圍: 1.一種非揮發性記憶體單元,其係包含: 一柱狀物’其包括一導雷和主道μ u y包和+導體材料,該柱狀物具 有一柱狀側壁; 位在δ亥柱狀物上方之一介電曾η pm ^^八+供μ ;丨电貝間隙壁,該介電質間隙 壁具有一外側壁及一内伽辟,甘a 門側i,其中,該外側壁係對準著該 柱狀側壁且該内侧壁界定一縮減的凹部體積; 一相變材料’其中’―部分相變材料係在該縮減的凹 部體積内;以及 環繞該柱狀物及該介電質間隙壁之一介電質填充材 料; 其中,該介電質間隙壁係由一不同於該介電質填充材 料之第二介電質材料所形成。 2.根據中請專利範圍第丨項之非揮發性記憶體單元, 其中’該介電質填充材料係二氧化石夕,而該第二介電質材 料係氮化矽。 3·根據申請專利範圍第丨項之非揮發性記憶體單元, 其中,該柱狀物包括一垂直定向二極體。 4·根據申請專利範圍第3項之非揮發性記憶體單元, 其中,該垂直定向二極體係一由半導體材料所形成之口小^ 一極體。 5·根據申請專利範圍第4項之非择發性記憶體單元, 其進一步包括位於該垂直定向二極體及該相變材料之間並 且與該垂直疋向二極體接觸之一矽化物或矽化物_鍺化物 30 200840033200840033 X. Patent application scope: 1. A non-volatile memory unit comprising: a column comprising a guide and a main channel μ uy package and a + conductor material, the column having a column shape a side wall; a dielectric layer above the δ hai column has been η pm ^^ 八 + for μ; 丨 electric baffle wall, the dielectric spacer has an outer side wall and an inner gamma, Gan a door side Wherein the outer sidewall is aligned with the cylindrical sidewall and the inner sidewall defines a reduced recess volume; a phase change material 'where' - a portion of the phase change material is within the reduced recess volume; and surrounding And a dielectric filling material of the pillar and the dielectric spacer; wherein the dielectric spacer is formed by a second dielectric material different from the dielectric filling material. 2. The non-volatile memory unit of claim 3, wherein the dielectric filler material is dioxide dioxide and the second dielectric material is tantalum nitride. 3. The non-volatile memory unit according to the scope of the patent application, wherein the pillar comprises a vertically oriented diode. 4. The non-volatile memory unit according to item 3 of the patent application, wherein the vertically oriented dipole system is a small body formed of a semiconductor material. 5. The non-selective memory unit according to claim 4, further comprising a telluride or a contact between the vertically oriented diode and the phase change material Telluride_锗化30 200840033 6.根據申請專利範圍第5項之非揮發性記憶體單元, 其中’該矽化物或矽化物-鍺化物層係矽化鈦、矽化鈦_錯 化物、矽化鈷、或矽化鈷_鍺化物。 7·根據申請專利範圍第3項之非揮發性記憶體單元, 其中,該相變材料及該垂直定向二極體係串接於一底部導 體及一頂部導體之間。 8·根據申請專利範圍第丨項之非揮發性記憶體單元, 其中’ σ亥相變材料係一硫屬化合物。 9 ·根據申睛專利範圍第$項之非揮發性記憶體單元, 其中’該硫屬化合物包括一鍺銻碲化合物材料。 10.—種單片式三維記憶體陣列,其係包括: a)—第一記憶體層,該第一記憶體層包括: I) 複數個柱狀物,每一個柱狀物包括一導電或半導體 材料並具有一柱狀側壁; II) 複數個介電質間隙壁,每一個介電質間隙壁位在該 些柱狀物的其中一者的上方,每一個介電質間隙壁具有一 外側壁及一内側壁,其中,每一個間隙壁之外侧壁係對準 著該些柱狀物的其中一者之柱狀側壁且每一個内側壁界定 一縮減的凹部體積; iii) 複數個相變構件,其中,該些相變構件中的每一個 的一部分係位在該縮減的凹部體積内;以及 iv) —環繞該些柱狀物及該些介電質間隙壁之介電質填 充材料’其中,該些介電質間隙壁係由一不同於該介電質 31 200840033 填充材料之第二介電質材料所形成;以及 層0 b)在戎弟-記憶體層上方單片地形成_第二記憶體 =根據巾請專利範圍第1(^之單片式三維記憶 二,:Γ狀物中的每—個包括一垂直定向二極體。 12. 根據申請專利範 列,1巾, 昂11項之早片式三維記憶體陣 單元,每一個筮^ ^ 乂匕括複數個弟一記憶體 …第一體單元包括該些柱狀物的其中之- 及该些相變構件的其中之一。 〃甲 13. 根據申請專利範圍第 列,其中,每一個第 員之早片式二維記憶體陣 定向-匕體早元進一步包括位於該垂直 疋Π 一極體及該相變 又柯抖之間之-矽化物或鍺化物層。 .根據申請專利範圍第 列,复Φ _ L 員之早片式二維記憶體陣 J其中,该些相變構件中的每伽勺紅 ,„ 15 &祕+ τ刃母一個包括一硫屬化合物。 列 •根據申請專利範圍第u 其中,該硫屬化合物俜一錯/::人片式二維記憶體陣 货、鍺錦蹄化合物材料。 列 6·根據申請專利範圍第 复由 員之早片式二維記憶體陣 ”中,該鍺銻碲化合物材料係Ge2Sb2Te5。 I7· 一種記憶體層,其係包括·· 複數個柱狀物,每_個# 、.. 料並且具有一柱狀側壁; ^ “或半導體材 柱狀:1:個介電質間隙壁,每一個介電質間隙壁位在該- 側壁及-内側-ϋ 質間隙壁具有-外 内側土 ’纟中’每一個間隙壁之外側壁係對準著 32 200840033 該些柱狀物的其中一者之柱狀側壁且每一個内側壁界定一 縮減的凹部體積; 複數個相變構件,其中,該些相變構件中的每一個的 一部分係位在該縮減的凹部體積内;以及 一環繞該些柱狀物及該些介電質間隙壁之介電質填充 材料,其中,該些介電質間隙壁係由一不同於該介電質填 充材料之第二介電質材料所形成。 18·根據申請專利範圍第17項之記憶體層,其中,該 些柱狀物中的每一個包括一垂直定向二極體。 19·根據申請專利範圍第17項之記憶體層,其中,該 些相變構件中的每一個包括一硫屬化合物。 ,20·根據申凊專利範圍第17工員之記憶體層,其中,該 硫屬化合物係一鍺銻碲化合物材料。 .21.一種形成一可切換的半導體構件之方法,該方法包 一…括-導電或半導體材料、第—介電質填充材料 及凹部體積之一柱狀物,豆中,兮筮人+併 , ,、甲邊弟一介電質填充材料 王哀繞该柱狀物並且具有一填 曰士 L , 丨衣向,其中,該柱狀物 具有一柱狀頂部表面,其中, 右 μ 狀頂部表面相對於該填 充頂口Ρ表面係凹陷的,且1中 、 栌w 其中该凹部體積具有側壁並佔 豕…充頂部表面及該柱狀頂部表面間的空間; 在。亥填充頂部表面、該也 表面h报士 , 一凹σ卩體積側壁及該柱狀頂部 矛面上形成一保形介電質材料層; 以異向钱刻將部分的保 汁仏彡丨包貝層自該填充頂部表面 33 200840033 及,亥柱狀頂部表面中移除,#中,一由該保形介電質材料 所形成之間隙壁保留在該些凹部體積側壁上,以界定一在 该間隙壁内之縮減的凹部體積; 沉積—相變材料,其中’ 一部分相變材料係位在該縮 減的凹部體積内。 22.根據申請專利範圍第21項之方法,其中,該柱狀 物包括一包括該半導體材料之垂直定向二極體。 23 _根據申請專利範圍第22項之方法,其中,該二極 月豆及該相麦材料係串接於一底部導體及一頂部導體之間。 24·根據申請專利範圍第22項之方法,其中,形成該 柱狀物、邊第一介電質填充材料及該凹部體積包括: 沉積該半導體材料; I虫刻該半導體材料以形成該柱狀物; 沉積該第一介電質填充材料以覆蓋並環繞該柱狀物; 平坦化以曝露出一部分柱狀物; 遥擇性钱刻該柱狀物以形成該凹部體積;及 推雜一部分柱狀物以形成該垂直定向二極體。 25.根據申請專利範圍第24項之方法,其進一步包括 在/儿積。亥相全材料之别先在該縮減的凹部體積内之二極體 上方形成一介電質破裂抗熔絲。 26·根據申請專利範圍第25項之方法,該相變材料係 接觸著該介電質破裂抗熔絲。 27·根據申請專利範圍第24項之方法,其進一步包括 在沉積该相變材料之前先在該柱狀頂部表面處形成一矽化 34 200840033 物或發化物-鍺化物層。 28.根據申請專利範圍第27項之方法,其中,該矽化 物或秒化物-鍺化物層係石夕化鈦、石夕化鈦_鍺化物、石夕化鈷、 或砍化銘-鍺化物。 29·根據申請專利範圍第28項之方法,其中,該半導 體材料係非結晶沉積並接觸該矽化物或矽化物-鍺化物以進 行結晶化。 r 3〇·根據申請專利範圍第21項之方法,其中,該相變 f 材料係一硫屬化合物。 3 1 ·根據申請專利範圍第3〇項之方法,其中,該硫屬 化合物包括一鍺銻碲化合物材料。 32·根據申請專利範圍第31項之方法,其中,該鍺銻 蹄化合物材料包括Ge2Sb2Te5。 3 3 ·種形成一單片式三維記憶體陣列之方法,該方法 包括: a)以下列方法在一基板上方形成一第一記憶體層,該 X 法包括: 0形成複數個柱狀物,每一個柱狀物包括一導電或半 體材料 第一介電質填充材料及複數個凹部體積,其 中,該第一介電質填充材料環繞每一個柱狀物並且具有一 填充頂部表面,其中,每_個柱狀物具有—柱狀頂部表面, /、中每一個柱狀頂部表面相對於該填充頂部表面係凹陷 並且其中,每一個凹部體積具有側壁並佔據該填充頂 P表面及该些柱狀頂部表面的其中之一柱狀頂部表面之間 35 200840033 的空間; ii)在該填充頂部矣而 、^二凹部體積側壁及該必柱狀 頂部表面上形成—保形介電質材料層; -柱狀 叫以異向钱刻將部分的保形介電質層自該填充頂部表 面及該些柱狀頂部表面中移除,#中,由該保形介電質材 ㈣形成^複數個間_保留在該些凹部體積側壁上,以 界疋在每一個間隙壁内之縮減的凹部體積; iv)沉積一相變材料,其中,一部分相變材料係位在每 一個縮減的凹部體積内; b)在該第一記憶體層上方單片地形成一第二記憶體 〇 34·根據申請專利範圍第33項之方法,其中,每一個 柱狀物包括一包括該半導體材料之垂直定向二極體。 35·根據申請專利範圍第34項之方法,其中,形成該 柱狀物、該第一介電質填充材料及該凹部體積包括: 沉積該半導體材料; I虫刻該半導體材料以形成該柱狀物; 〉儿積该第一介電質填充材料以覆蓋並環繞該柱狀物; 平坦化以曝露出一部分柱狀物; 選擇性蝕刻該柱狀物以形成該凹部體積;及 摻雜一部分柱狀物以形成該些垂直定向二極體。 36·根據申請專利範圍第33項之方法,其中,該相變 材料係一硫屬化合物。 3 7 ·根據申請專利範圍第3 6項之方法,其中,該琉屬 36 200840033 化合物包括一鍺銻碲化合物材料。 十一、圖式: 如次頁 376. The non-volatile memory unit according to claim 5, wherein the telluride or telluride-telluride layer is titanium telluride, titanium telluride-patterned, cobalt telluride, or cobalt telluride-telluride. 7. The non-volatile memory unit of claim 3, wherein the phase change material and the vertically oriented dipole system are connected in series between a bottom conductor and a top conductor. 8. The non-volatile memory unit according to the scope of the patent application, wherein the 'sigma phase change material is a monochalcogenide compound. 9. A non-volatile memory unit according to item 0 of the scope of the patent application, wherein the 'chalcogenide compound comprises a monoterpene compound material. 10. A monolithic three-dimensional memory array, comprising: a) a first memory layer, the first memory layer comprising: I) a plurality of pillars, each pillar comprising a conductive or semiconducting material And having a columnar sidewall; II) a plurality of dielectric spacers, each of the dielectric spacers being above one of the pillars, each dielectric spacer having an outer sidewall and An inner side wall, wherein the outer side wall of each of the spacers is aligned with the cylindrical side walls of one of the pillars and each of the inner side walls defines a reduced recess volume; iii) a plurality of phase change members, Wherein a portion of each of the phase change members is within the reduced recess volume; and iv) a dielectric filler material surrounding the pillars and the dielectric spacers The dielectric spacers are formed by a second dielectric material different from the dielectric material of the dielectric 31 200840033; and the layer 0 b) is formed monolithically over the 戎-memory layer _ second memory Body = according to the towel, the patent scope is 1 (^ The monolithic three-dimensional memory two: each of the cymbals includes a vertical directional diode. 12. According to the patent application list, 1 towel, ang 11 early-type three-dimensional memory array unit, each A 筮^^ 复 复 复 ... ... ... ... 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一The first slice of the two-dimensional memory array orientation of the first member of the first member further includes a telluride or telluride layer between the vertical 疋Π one body and the phase change and the coma. According to the scope of the patent application, the early two-dimensional memory array J of the Φ _ L member, wherein each of the phase change members has a red spoon, „ 15 & secret + τ blade mother includes a chalcogen According to the scope of the patent application, the chalcogen compound is wrong/:: human slice two-dimensional memory array, 锗 蹄 化合物 compound material. Column 6 · According to the scope of the patent application In the early two-dimensional memory array, the bismuth compound The system is Ge2Sb2Te5. I7· A memory layer comprising a plurality of pillars, each _#, .. material and having a columnar sidewall; ^ "or semiconductor material column: 1: dielectric The spacers, each of the dielectric spacers are located in the side wall and the inner side - the interstitial spacer has an outer outer side soil '纟' and each of the spacers is aligned with the outer side wall 32 200840033 a cylindrical side wall and each inner side wall defining a reduced recess volume; a plurality of phase change members, wherein a portion of each of the phase change members is within the reduced recess volume; a dielectric filling material surrounding the pillars and the dielectric spacers, wherein the dielectric spacers are formed by a second dielectric material different from the dielectric filling material form. 18. The memory layer of claim 17, wherein each of the pillars comprises a vertically oriented diode. 19. The memory layer of claim 17, wherein each of the phase change members comprises a chalcogenide compound. 20. The memory layer of the 17th worker according to the scope of the patent application, wherein the chalcogenide compound is a compound material. A method of forming a switchable semiconductor component, the method comprising: a conductive or semiconducting material, a first dielectric filler material, and a pillar of a volume of the recess, the bean, the scorpion + , a, a younger brother, a dielectric filling material, wraps around the column and has a filling of a gentleman L, the orientation of the garment, wherein the pillar has a cylindrical top surface, wherein, the right μ-shaped top The surface is recessed relative to the surface of the filling top opening, and wherein the recess volume has sidewalls and occupies a space between the top surface and the columnar top surface; Filling the top surface, the surface h, the concave σ卩 volume sidewall and the columnar top spear surface forming a conformal dielectric material layer; The shell layer is removed from the filled top surface 33 200840033 and the columnar top surface, wherein a spacer formed by the conformal dielectric material remains on the sidewalls of the recessed volume to define a The reduced recess volume within the spacer; a deposition-phase change material in which a portion of the phase change material is within the reduced recess volume. 22. The method of claim 21, wherein the column comprises a vertically oriented diode comprising the semiconductor material. The method according to claim 22, wherein the bipolar moon bean and the phase wheat material are connected in series between a bottom conductor and a top conductor. The method according to claim 22, wherein the forming the pillar, the first dielectric filler material, and the recess volume comprises: depositing the semiconductor material; I insectizing the semiconductor material to form the pillar Depositing the first dielectric filler material to cover and surround the pillar; planarizing to expose a portion of the pillar; arranging the pillar to form the recess volume; and pushing a portion of the pillar Forming the vertically oriented diode. 25. According to the method of claim 24, which further comprises a product. The dielectric phase first forms a dielectric rupture antifuse above the dipole in the reduced recess volume. 26. The method according to claim 25, wherein the phase change material is in contact with the dielectric rupture antifuse. The method of claim 24, further comprising forming a deuterated 34 200840033 or a hair-mudide layer at the columnar top surface prior to depositing the phase change material. 28. The method according to claim 27, wherein the telluride or sec-deuterated layer is a Titanium, a Titanium, a Telluride, a Shihua, or a Chess . The method of claim 28, wherein the semiconductor material is amorphously deposited and contacted with the telluride or telluride-telluride for crystallization. The method of claim 21, wherein the phase change f material is a monochalcogenide compound. The method of claim 3, wherein the chalcogenide compound comprises a monoterpene compound material. 32. The method of claim 31, wherein the hoof compound material comprises Ge2Sb2Te5. 3 3 . A method of forming a monolithic three-dimensional memory array, the method comprising: a) forming a first memory layer over a substrate in the following manner, the X method comprising: 0 forming a plurality of pillars, each a pillar comprising a first dielectric fill material of a conductive or half-material material and a plurality of recessed volumes, wherein the first dielectric fill material surrounds each of the pillars and has a filled top surface, wherein each Each of the pillars has a columnar top surface, and each of the columnar top surfaces is recessed relative to the top surface of the fill and wherein each recess volume has a sidewall and occupies the surface of the fill top P and the columns a space between one of the cylindrical top surfaces of the top surface 35 200840033; ii) forming a layer of conformal dielectric material on the top of the fill, the sidewalls of the recessed volume, and the surface of the pillared top surface; The column is called an anisotropically engraved part of the conformal dielectric layer from the top surface of the filling and the top surface of the column, #, the shape of the conformal dielectric material (four) is formed Retaining on the sidewalls of the recessed volume to define a reduced recess volume within each of the spacers; iv) depositing a phase change material in which a portion of the phase change material is within each of the reduced recess volumes; The method of claim 33, wherein each of the pillars comprises a vertical alignment diode including the semiconductor material. . 35. The method of claim 34, wherein forming the pillar, the first dielectric filler material, and the recess volume comprises: depositing the semiconductor material; I insectating the semiconductor material to form the pillar Storing the first dielectric filler material to cover and surround the pillar; planarizing to expose a portion of the pillar; selectively etching the pillar to form the recess volume; and doping a portion of the pillar Forming the vertically oriented diodes. The method according to claim 33, wherein the phase change material is a monochalcogenide compound. 3 7 · The method according to claim 36, wherein the genus 36 200840033 compound comprises a quinone compound material. XI. Schema: as the next page 37
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