TWI572027B - Resistive memory device and method for manufacturing the same - Google Patents

Description

Resistive memory element and method of manufacturing same

The present invention relates to a resistive memory device and a method of fabricating the same, and more particularly to a resistive memory device having improved electronic characteristics and a method of fabricating the same.

Memory components, such as non-volatile memory components, are typically designed to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cell planes to achieve the structure of memory components with higher storage capacity. For example, some three-dimensional stacked NAND (NAND) type flash memory structures have been proposed.

Resistive random-access memory (RRAM or ReRAM) is one of the types of non-volatile memory. Resistive memory has received much attention due to its simple Metal-Insulator-Metal (MIM) structure and promising scalability. Depending on the type of dielectric material, from perovskites to transition metal oxides to chalcogenides, different forms of variable resistors Memory has been revealed. However, conventional resistive memory elements still produce defects such as seams and voids in the metal layer during the filling step of the manufacturing process. Figure 1 is a diagram showing a portion of a conventional resistive memory device with defects. As shown in FIG. 1, a patterned dielectric layer 12 having via holes is formed on a bottom electrode 11, and a barrier layer 13 is formed along sidewalls and a bottom surface of the via hole of the patterned dielectric layer 12, and A metal layer 14 fills the vias, and then a grinding and oxidation process is performed to form a metal oxide as a memory layer of the resistive memory device. In the conventional metal filling step, defects such as the seam 14a and the void 14b are easily generated in the metal layer 14, particularly at the central portion of the metal layer 14. Defects such as seams 14a and/or voids 14b may cause a weaker region inside the metal layer 14 (e.g., the region where the seam is created is more susceptible to oxidation than other regions of the metal layer 14), after the oxidation process The resistance value of the weaker region will vary, thus reducing the reliability of the electronic properties of the resistive memory component.

Therefore, the related industry has no desire to develop and manufacture a resistive memory element that has both a reliable structure and excellent electronic characteristics.

The present invention relates to a resistive memory element and a method of fabricating the same. The resistive memory element of the embodiment provides a simple and reliable structure to reduce the size of the contact hole (i.e., the annular metal oxide) and greatly enhance the electronic characteristics of the memory element.

According to an embodiment, a resistive memory device is provided, comprising a bottom electrode having a patterned dielectric layer formed on the bottom electrode A barrier layer is formed on the sidewalls and the bottom surface of the via hole as a liner, an annular metal layer is formed on the sidewalls and the bottom surface of the barrier layer, and an annular metal oxide is formed on the upper surface of the annular metal layer.

According to an embodiment, a method for fabricating a resistive memory device is provided, comprising: providing a bottom electrode, forming a patterned dielectric layer having a via hole on the bottom electrode, forming a barrier layer on the sidewall and bottom surface of the via hole The upper layer is formed with an annular metal layer on the sidewalls and the bottom surface of the barrier layer, and an annular metal oxide is formed on the upper surface of the annular metal layer.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.

2‧‧‧Resistive memory components

11, 21, 71‧‧‧ bottom electrode

12, 22, 72‧‧‧ patterned dielectric layer

22t, 72t‧‧‧ patterned dielectric layer upper surface

13, 23, 73, 73’, 73” ‧ ‧ barrier layers

23s, 73s‧‧ ‧ sidewall of the barrier layer

23b, 73b‧‧‧ bottom surface of the barrier layer

23t, 73t‧‧‧ upper surface of the barrier layer

14‧‧‧metal layer

14a‧‧‧Seam

14b‧‧‧ holes

24, 74, 74', 74" ‧ ‧ annular metal layers

24t, 74t‧‧‧ upper surface of the annular metal layer

25, 75‧‧‧ Ring Metal Oxide

26, 74h‧‧ hole

27‧‧‧Intermediate

72v‧‧‧through hole

77‧‧‧Baffle oxide

78‧‧‧ conductive oxide

Side wall of Vs‧‧ hole

Vb‧‧‧ bottom surface of the through hole

IL, IL'‧‧‧ insulation

ML‧‧‧ conductor

ML', ML"‧‧‧ conductive layer

Figure 1 is a diagram showing a portion of a conventional resistive memory device with defects.

2A is a schematic cross-sectional view of a resistive memory device in accordance with an embodiment of the present disclosure.

2B is a top view of a resistive memory element in accordance with an embodiment of the present disclosure.

Figure 3A shows the operation of a conventional resistive memory device, including the process of initial formation, setup, and reset.

Figure 3B shows the operation of one of the resistive memory elements of an embodiment, including the process of initial formation, setting, and resetting.

Fig. 4 is a graph showing the initial resistance of a conventional and exemplary resistive memory device in which an oxidation process is performed by RTO in the related experiments.

Fig. 5 is a graph showing the relationship between the formation voltage of the resistive memory element and the initial resistance of the embodiment in the formation process, wherein the annular metal oxide is formed at different RTO process temperatures.

Figure 6 shows an analog operation of the initial formation, setting and reset of the resistive memory element of one embodiment, wherein the operating conditions are 5V/500μA.

7A to 7F illustrate a first method of fabricating a resistive memory device according to an embodiment of the present disclosure.

8A to 8F illustrate a second method of fabricating a resistive memory device according to an embodiment of the present disclosure.

Embodiments of the disclosure disclose a resistive memory element and a method of fabricating the same. The resistive memory element of the embodiment can be widely applied to various resistive memory (e.g., variable resistance memory, ReRAM) arrays. According to an embodiment, the resistive memory element provides a simple and reliable structure to reduce the size of the contact hole (i.e., the ring metal oxide) and to enhance the electronic characteristics of the resistive memory element. Furthermore, the resistive memory element of the embodiment exhibits a high initial resistance, representing that the embodiment is good and uniform. Oxide.

It should be noted that the disclosure does not show all possible embodiments, and other embodiments not disclosed in the disclosure may also be applied. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting. In addition, the description in the embodiments, such as the detailed structure, the process steps, the material application, and the like, are for illustrative purposes only and are not intended to limit the scope of the disclosure. The details of the steps and the various elements of the structure of the embodiments may be varied and modified as needed in accordance with the actual application process without departing from the spirit and scope of the disclosure.

2A is a schematic cross-sectional view of a resistive memory device in accordance with an embodiment of the present disclosure. 2B is a top view of a resistive memory element in accordance with an embodiment of the present disclosure. As shown in FIGS. 2A and 2B, a resistive memory device 2 includes a bottom electrode 21, and a patterned dielectric layer 22 is formed on the bottom electrode 21 and has a via, a The barrier layer 23 is formed on the sidewall Vs and the bottom surface Vb of the via hole as a liner, and a ring-shaped metal layer 24 is formed on the sidewall 23s and the bottom surface 23b of the barrier layer 23, and an annular metal oxide A ring-shaped metal oxide 25 is formed on the upper surface 24t of the annular metal layer 24.

According to an embodiment, the annular metal oxide formed on the upper surface 24t of the annular metal layer 24 defines a hole 26, a medium layer 27 such as an insulation or a conductive layer. ) fills the hole 26 (the method of which is detailed later). In one embodiment, an upper electrode (not shown) It may be formed on the annular metal oxide 25, wherein the upper electrode and the annular metal oxide 25 produce a self-rectified property.

In one embodiment, the upper surface 23t of the barrier layer 23 is lower than the upper surface 22t of the patterned dielectric layer 22. In one embodiment, the upper surface 24t of the annular metal layer 24 is lower than the upper surface 22t of the patterned dielectric layer 22. In one embodiment, the upper surface 25t of the annular metal oxide 25 is substantially flush with the upper surface 22t of the patterned dielectric layer 22 (as shown in FIG. 2A), or slightly higher than the patterned dielectric layer 22. Upper surface 22t.

It is noted that the detailed structure of the resistive memory element may be slightly modified and modified depending on the fabrication procedure of the actual application. The structure of Fig. 2A shows only one of the embodiments, and some elements of the structure may exist but are not shown in Fig. 2A. For example, the resistive memory device may further include a barrier oxide (for example, titanium oxide TiOx) (not shown in FIG. 2A), and the barrier oxide is formed on the barrier layer 23 after the oxidation process. Surface 23t.

The bottom electrode 21 of the embodiment is made of a conductive material such as a metal or semiconductor material. The metal capable of producing the bottom electrode 21 is, for example, Yb, Tb, Y, Y, Sc, Hf, Zr, Al, Al (Ta), (titanium (Ti), niobium (Nb), chromium (Cr), vanadium (V), zinc (Zn), tungsten (W), molybdenum (Mo), copper (Cu), antimony (Re), Ruthenium (Ru), cobalt (Co), nickel (Ni), rhodium (Rh), palladium (Pd), platinum (Pt), etc., but the disclosure is not limited thereto. In one embodiment, the bottom electrode 21 is, for example, layered. Tungsten silicide (WSix) is deposited on a semiconductor layer such as N+ polysilicon or P+ polysilicon to avoid spalling of the tungsten carbide layer. According to an embodiment, the patterned dielectric layer 22 includes an oxide such as hafnium oxide or a nitride. According to an embodiment, the annular metal layer 24 is, for example, but not limited to, comprising tungsten (W), tungsten telluride (WSi), titanium (Ti), titanium nitride (TiN), hafnium (Hf), aluminum (Al), Cobalt telluride (CoSi), nickel (NiSi), copper (Cu), zirconium (Zr), niobium (Nb), tantalum (Ta) or other suitable materials. According to an embodiment, the annular metal oxide 25 is, for example, but not limited to, tungsten oxide (WOx), tantalum tungsten oxide (WSiOx, WxSiyOz or WSixOy), cobalt oxide (CoxSiyOz), niobium nitric oxide (NixSiyOz), Titanium oxide (TiOx), nickel oxide (NiOx), aluminum oxide (AlOx), copper oxide (CuOx), zirconium oxide (ZrOx), niobium oxide (NbOx), tantalum oxide (TaOx), titanium oxynitride (TiNO) or others Suitable materials. The materials listed above are for illustrative purposes only, and the materials of the elements in the examples may be adjusted and changed according to the needs of the actual application.

Furthermore, the annular metal layer 24 may utilize chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering process, or the like. Suitable for the formation of processes. In one embodiment, the thickness Tm of the annular metal layer 24 is in the range of about tens of Å to hundreds of Å. Furthermore, the annular metal oxide 25 can be formed by rapid thermal oxidation (RTO), wet chemical oxidation, plasma electrolytic oxidation (PEO) or other suitable processes. In one embodiment, the thickness Tmo of the annular metal oxide 25 is in the range of about 100 Å to 400 Å.

According to the present disclosure, the resistive memory element of the embodiment has reliability Structure and improved electronic properties. A variable resistance memory (ReRAM) having a metal oxide layer (i.e. memory layer) of tungsten oxide (WOx) is taken as an example. Figure 3A shows the operation of a conventional resistive memory device, including the processes of initial forming, setting (SET), and reset (RESET). Figure 3B shows the operation of one of the resistive memory elements of an embodiment, including the processes of initial forming, setting (SET), and resetting (RESET). Please refer to both Figures 3A and 3B. In FIGS. 3A and 3B, a variable resistance memory (ReRAM) including tungsten oxide (WOx) is provided as a metal oxide layer (i.e. memory layer) for testing to compare characteristics. A conventional resistive memory element (i.e., the metal layer 14 as shown in Fig. 1 completely fills the via hole of the barrier layer 13, and the grown metal oxide layer completely covers the metal layer 14). One of the initial forming processes has a very low initial resistance (eg, about 1K to 10K ohms) and a higher initial current (eg, about 3 milliamps to 6 milliamps) to be low. The starting resistance is pulled to a higher resistance for operation.

As shown in FIG. 3B, the resistive memory device of the embodiment (eg, a ring-shaped WOx ReRAM) can reach a reset state (RESET state) by applying a positive current, wherein the operation is increased from a low resistance value. To a high resistance value. Moreover, the resistive memory device of the embodiment can also reach a set state (SET state) by applying a negative current, wherein the operation is reduced from a high resistance value to a low resistance value. Furthermore, the resistive memory device of the embodiment exhibits a high initial resistance (for example, in the range of about 1 mega ohm to 1 giga ohm), which means that the resistive memory has good And a uniform oxide. Furthermore, the power of the embodiment Resistive memory components require only a relatively low initial current (eg, from about 0.4 milliamps to 0.6 milliamps) for operation.

Compared with the conventional resistive memory component (such as WOx ReRAM in FIG. 3A), the resistive memory component of the embodiment can also successfully perform the SET process and the reset process (RESETprocess), but The forming process shows a higher initial resistance and a lower current can be operated. Further, defects such as no seams and/or voids are generated in the metal layer of the resistive memory element of the embodiment, so that the problem of variation in resistance value of the conventional resistive memory element can be avoided. Therefore, the electronic characteristics and operational stability of the resistive memory element of the embodiment can be greatly increased. Table 1 below is a series of experimental data from a series of conventional and exemplary resistive memory elements.

In addition, the resistive memory element of the embodiment is more controllable The initial resistance, whose initial resistance value changes with the temperature of the oxidation process. If the oxidation of the annular metal layer 24 is carried out by a rapid thermal oxidation (RTO) process. According to the experimental results, it can be observed that the resistive memory element (for example, the ring-shaped WOx ReRAM) of the embodiment having the annular metal layer and the annular metal oxide exhibits a more sensitive process window and a process window according to the process temperature of the RTO. Controllable starting resistance.

Fig. 4 is a graph showing the initial resistance of a conventional and exemplary resistive memory device in which an oxidation process is performed by RTO in the related experiments. In Fig. 4, curves (1) and (2) represent annular metal oxides 25 formed at 400 ° C and 500 ° C, respectively, in the resistive memory device of the embodiment, and the initial resistances of the curves (1) and (2) There are obvious differences. In Fig. 4, curves (3) and (4) represent the formation of metal oxides at 400 ° C and 500 ° C in conventional resistive memory devices, respectively, and the initial resistance exhibited by the two is almost the same.

Figure 5 is a graph showing the formation voltages of the resistive memory elements of the embodiment during formation versus the initial resistance, wherein the annular metal oxide is formed at different RTO process temperatures. In Fig. 5, the curve (5) represents that the resistive memory device of the embodiment has the ring-shaped metal oxide 25 formed at an RTO process temperature of 400 ° C, and the initial resistance (Rin) corresponding to the formation voltage is about 8.25 × 10 ⁷ Ω. The curve (6) represents that the resistive memory element of the embodiment has the ring-shaped metal oxide 25 formed at an RTO process temperature of 450 ° C, which corresponds to a starting resistance (Rin) of the formation voltage of about 5.4 × 10 ⁸ Ω. Curve (7) represents that the resistive memory device of the embodiment has a toroidal metal oxide 25 formed at an RTO process temperature of 500 ° C, which corresponds to a starting resistance (Rin) of a formation voltage of about 1.63 × 10 ⁹ Ω. According to the experimental results, the initial resistance of the resistive memory element of the embodiment changes correspondingly with the temperature change of the oxidation process for forming the annular metal oxide 25. Furthermore, as shown in Fig. 5, the formation voltage system increases as the initial resistance increases. That is, the higher the initial resistance, the higher the formation voltage. Note that the RTO process temperature set forth in this experiment is for illustrative purposes only and is not limiting. Other suitable RTO process temperatures may also be selected as the oxidation process temperature of the examples. In one embodiment, the annular metal oxide 25 can be formed via an oxidation process having an oxidation process temperature between 400 ° C and 600 ° C.

When the resistive memory device of the embodiment is applied to an actual array structure, the electronic characteristics of the structure can be significantly improved. Figure 6 shows the initial operations of forming, setting (SET) and resetting (RESET) of the resistive memory elements of one embodiment, with operating conditions of 5V/500μA (ECL experimental data). As shown in Fig. 6, the forming state, the SET state, and the RESET state can be clearly distinguished. When the resistive memory device of the embodiment is applied to a 1T1R (1 transistor, 1 resistance) array, the overall array can exhibit more excellent electronic characteristics due to the improved structure of the resistive memory device of the embodiment.

The following is a description of the manufacturing method of the two applicable resistive memory elements (having a ring memory layer), but for illustrative purposes only, the disclosure is not limited to the two methods.

7A to 7F illustrate a first method of fabricating a resistive memory device according to an embodiment of the present disclosure. As shown in FIG. 7A, a patterned dielectric layer 72 having a via 72v is formed on a bottom electrode 71 and a barrier layer 73 (e.g., TiN) is deposited on the patterned dielectric layer 72 and formed on the sidewall Vs of the via 72v and the bottom surface Vb as the same liner. As shown in FIG. 7B, an annular metal layer (e.g., tungsten) 74 is deposited on sidewalls 73s and bottom surfaces 73b of the barrier layer 73 (by CVD, PVD, ALD, sputtering, or other suitable process), wherein the annular metal layer The 74 series defines a hole 74h. As shown in Fig. 7C, an insulating layer (e.g., a dielectric layer, such as an oxide) IL is deposited on the annular metal layer 74 and fills the holes 74h. As shown in Fig. 7D, the insulating layer IL, the annular metal layer 74, and the barrier layer 73 are planarized, for example, by chemical mechanical polishing (CMP) to form the insulator IL'. As shown in Fig. 7E, the barrier layer 73' is then etched back (and the insulator IL' can also be selectively etched back). As shown in FIG. 7F, the annular metal layer 74' is oxidized by an oxidation process (eg, RTO, wet chemical oxidation, plasma electrolytic oxidation, or other suitable process) to form an annular metal oxide 75 in the annular metal layer 74. "At the top surface 74t.

According to the manufacturing method illustrated in FIGS. 7A to 7F, a barrier oxide (for example, TiOx) 77 is also formed on the upper surface 73t of the barrier layer 73" during the oxidation process (FIG. 7F), wherein The barrier oxide 77 and the annular metal oxide 75 are simultaneously formed. In one embodiment, the upper surface of the insulator IL' after the oxidation process is higher than the upper surface 74t of the annular metal layer 74". Moreover, in one embodiment, the upper surface 72t of the patterned dielectric layer 72 is higher than the upper surface 73t of the barrier layer 73" and higher than the upper surface 74t of the annular metal layer 74".

8A to 8F illustrate a second method of fabricating a resistive memory device according to an embodiment of the present disclosure. The same and/or similar reference numerals are used for the same and/or similar elements in FIGS. 8A to 8F as in FIGS. 7A to 7F. Like 8A As shown in FIG. 7A, a patterned dielectric layer 72 having a via 72v is formed on a bottom electrode 71, and a barrier layer 73 (eg, TiN) is deposited on the patterned dielectric layer 72. And formed on the side wall Vs of the through hole 72v and the bottom surface Vb as the same lining. As shown in FIG. 8B (same as FIG. 7B), an annular metal layer (eg, tungsten) 74 is deposited on sidewalls 73s and bottom surfaces 73b of barrier layer 73 (by CVD, PVD, ALD, sputtering, or other suitable process). Wherein the annular metal layer 74 defines a hole 74h.

As shown in Fig. 8C, a conductor (e.g., a metal layer) ML is deposited on the annular metal layer 74 and fills the holes 74h. As shown in Fig. 8D, the conductor ML, the annular metal layer 74, and the barrier layer 73 are planarized, for example, by chemical mechanical polishing (CMP) to form a conductive layer ML'. As shown in Fig. 8E, the barrier layer 73' and the conductive layer ML' are then etched back. As shown in FIG. 8F, the annular metal layer 74' is oxidized by an oxidation process (eg, RTO, wet chemical oxidation, plasma electrolytic oxidation, or other suitable process) to form the annular metal oxide 75 in the annular metal layer 74. "At the upper surface 74t, and simultaneously forming a conductive oxide 78 on the upper surface of the conductive layer ML". According to the manufacturing method illustrated in FIGS. 8A to 8F, a barrier oxide (for example, TiOx) 77 is also formed on the upper surface 73t of the barrier layer 73" during the oxidation process (Fig. 8F), wherein The barrier oxide 77, the annular metal oxide 75 and the conductive oxide 78 are simultaneously formed. In one embodiment, the upper surface of the conductive layer ML" after the oxidation process is higher than the upper surface 74t of the annular metal layer 74". In one embodiment, the upper surface 72t of the patterned dielectric layer 72 is higher than the upper surface 73t of the barrier layer 73", and is higher than the upper surface 74t of the annular metal layer 74", and is also higher than the conductive layer ML" surface.

According to the above embodiment, the resistive memory device of the embodiment can be widely applied to various resistive memory (e.g., variable resistance memory, ReRAM) arrays. According to an embodiment, the resistive memory element provides a simple and reliable structure to reduce the size of the contact hole (i.e., the annular metal oxide) and also enhances the electrical characteristics of the resistive memory element. For example, defects such as no seams and/or voids can be created in the metal layer of the resistive memory device of the embodiment, and a higher (and controllable) starting resistance (Rin) can be obtained. The initial resistance of the resistive memory device of the embodiment can be adjusted and controlled accordingly by varying the temperature of the oxidation process. Furthermore, the formation voltage increases as the initial resistance (Rin) increases (ie, the higher the initial resistance, the higher the formation voltage). In addition, the manufacturing method of the resistive memory element of the embodiment provides a simple manufacturing process, and adopts a non-time consuming and non-expensive program, which is suitable for mass production in production.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

2‧‧‧Resistive memory components

22‧‧‧ patterned dielectric layer

25‧‧‧Circular metal oxides

27‧‧‧Intermediate

Claims (10)

A resistive memory device includes at least: a bottom electrode; a patterned dielectric layer having a via formed on the bottom electrode; and a barrier layer formed on the barrier layer a sidewall of the through hole and a bottom surface as a liner; a ring-shaped metal layer formed on the sidewall and a bottom surface of the barrier layer; and a ring-shaped metal oxide Forming at an upper surface of the annular metal layer and an upper surface of the barrier layer; wherein the upper surface of the annular metal layer and the upper surface of the barrier layer are lower than one of the patterned dielectric layers Upper surface. The resistive memory device of claim 1, further comprising a barrier oxide formed on the upper surface of the barrier layer. The resistive memory device of claim 1, wherein the annular metal layer defines a hole in the through hole, and a medium layer fills the hole. The resistive memory device of claim 3, wherein the intermediate layer is a conductive layer, and the conductive layer and the barrier layer comprise the same material. A method for manufacturing a resistive memory device, comprising at least: providing a bottom electrode; Forming a patterned dielectric layer on the bottom electrode, the patterned dielectric layer having a via; forming a barrier layer on the sidewall and a bottom surface of the via as a liner; forming an annular metal layer (ring-shaped metal layer) on the sidewall and a bottom surface of the barrier layer; and forming a ring-shaped metal oxide on an upper surface of the annular metal layer and on the barrier layer a surface; wherein the upper surface of the annular metal layer and the upper surface of the barrier layer are lower than an upper surface of the patterned dielectric layer. The manufacturing method of claim 5, wherein the annular metal layer defines a hole in the through hole, and the method further comprises filling a medium layer in the hole. The manufacturing method of claim 6, wherein the intermediate layer is an insulation, and the step of filling the insulator in the hole comprises: depositing an insulating layer on the annular metal layer and filling Filling the hole; and planarizing the insulating layer, the annular metal layer, and the barrier layer to form the insulator. The manufacturing method of claim 6, further comprising: etch back the upper surface of the barrier layer; and forming the annular metal oxide by oxidizing the annular metal layer; wherein the insulating An upper surface is higher than the upper surface of the annular metal layer. The manufacturing method of claim 8, further comprising: forming a barrier oxide at the upper surface of the barrier layer by oxidation, wherein the barrier oxide and the annular metal oxide It is formed at the same time. The manufacturing method of claim 6, wherein the intermediate layer is a conductive layer, and the step of filling the conductive layer in the hole comprises: depositing a conductor on the annular metal layer and filling Filling the hole; and planarizing the conductor, the annular metal layer and the barrier layer to form the conductive layer.