JP6102121B2 - Resistance change element and method of forming resistance change element - Google Patents

Description

  The present invention relates to a variable resistance nonvolatile switching element (hereinafter referred to as “resistance change element”) and a method for manufacturing the same. In particular, a resistance change element formed inside the multilayer wiring layer, a memory composed of the resistance change element formed inside the multilayer wiring layer, and a resistance change element formed inside the multilayer wiring layer The present invention relates to a semiconductor device equipped with a field programmable gate array (FPGA) configured by using the method and a method of forming a resistance change element in a multilayer wiring layer.

  2. Description of the Related Art Semiconductor devices including silicon devices have been integrated and reduced in power by miniaturization based on a scaling law known as “Moore's law”. Up to now, highly integrated devices have been developed at a pace of “4 times integration in 3 years”. In recent years, the gate length Lg of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) has become 20 nm or less. Due to soaring lithography processes and physical limitations of device dimensions, further device integration and lower power consumption are based on scaling rules. An approach different from miniaturization is required. That is, it is required to improve device performance in a highly integrated device by using a method different from miniaturization based on scaling.

  Factors for the soaring lithography process include soaring manufacturing equipment prices and mask set prices. Further, factors that determine the physical limit of the device dimension include an operation limit caused by miniaturization of the device dimension and a dimension variation limit.

  In recent years, it is expected to use a “back-end device” as a method for improving device performance regardless of “miniaturization based on scaling law”. A “back-end device” is an active element mounted in a multilayer wiring layer of ULSI. In particular, MRAM (Magnetic Random) is used as a storage device that uses a nonvolatile variable resistance switching element with low power consumption. Access memory), PRAM (phase change random access memory), ReRAM (resistive random access memory), etc. When mounted on a conventional CMOS semiconductor device, a “back-end device” composed of variable resistance switching elements can be used as a non-volatile memory or as a non-volatile switch. It is expected as a means for reducing power consumption of a semiconductor device by omitting power required for maintenance.

  “Back-end devices”, for example, non-volatile memories composed of resistance change elements such as MRAM, PRAM, and ReRAM increase the mounting capacity as semiconductor devices become smaller and have a larger storage capacity. It is expected that.

  On the other hand, as a “logic device” positioned between the “gate array” and the “standard cell”, there is a rewritable programmable logic device called “FPGA”. The FPGA performs “switching of switching elements” after manufacturing the “logic device” chip, and allows the customer to select an arbitrary circuit configuration. It is expected that such “logic circuit switching” in the FPGA is performed by using a variable resistance element mounted in a multilayer wiring layer as a variable resistance nonvolatile switching element. When an FPGA is configured using variable resistance elements that can be mounted in a multilayer wiring layer, the power consumption can be reduced while improving the degree of freedom of the circuit.

  As a variable resistance nonvolatile switching element (resistance change element) suitable for the use of a “logic circuit switching” switch in an FPGA, a resistance change element using an ionic conductor constituting a ReRAM, that is, NanoBridge (NanoBridge ( NEC registered trademark). The ion conductor used in the variable resistance element is a solid electrolyte in which ions can freely move by an applied electric field.

  The operation principle of the variable resistance switching element used in each of the MRAM, PRAM, and ReRAM, which are storage devices using a nonvolatile variable resistance switching element, will be described below. 9, 10, and 12 show examples of configurations of the MRAM, PRAM, and ReRAM. In addition, FIG. 11 shows an example of the configuration of an FRAM (Ferroelectric RAM).

  The MRAM uses the characteristic that the magnetization generated in the ferromagnetic body by the magnetic field applied from the outside remains in the ferromagnetic body even after the external magnetic field is removed. In the MRAM cell, a structure in which two magnetic layers are stacked with an insulator interposed therebetween is used. Of the two ferromagnetic layers, the magnetization direction of one magnetic layer (fixed layer) is set as the reference magnetization direction, and the magnetization direction of the other magnetic layer (free layer) is changed according to stored data. The magnetoresistance varies depending on the coincidence / mismatch of the magnetization directions between the two ferromagnetic layers. Data is stored by utilizing the fact that the value of the current flowing through the storage element portion varies depending on the difference in magnetic resistance.

  Therefore, when writing data, the magnetization direction of the magnetic layer for data storage (free layer) is set according to the data to be stored, and the direction of the magnetic field applied from the outside to the magnetic layer for data storage (free layer) To decide.

  As a data writing method for the MRAM cell, a current is supplied to a “write wiring” provided separately from the memory cell, and a magnetic field generated by the current flowing through the “write wiring” is changed to the magnetic layer for data storage (free Layer). When the direction of the current flowing through the “write wiring” is reversed, the direction of the generated magnetic field is also reversed. As a result, the magnetization direction of the magnetic layer (free layer) for data storage can be reversed. A method using a magnetic field generated by a current flowing through the “write wiring” is called a current magnetic field writing method.

  The magnetization direction of the magnetization free layer (free layer) due to the spin torque injected from the magnetization invariant layer (fixed layer) by passing a current directly through the structure in which two magnetic layers are stacked with an insulating film in between The “spin injection magnetization reversal method” is also used.

  The PRAM utilizes the characteristic that the resistance value changes as a result of the phase change material changing to a crystalline state (low resistance) or an amorphous state (high resistance) by an externally applied current. In the PRAM cell, a structure having a phase change layer sandwiched between two electrodes is used. The resistivity varies greatly depending on the difference between the crystalline / amorphous phases of the “resistance change element film” made of the phase change material. Data is stored by utilizing the fact that the current flowing through the storage element varies with the difference in resistivity between the two phases of crystal / amorphous. Data writing is performed according to the data to be stored, phase change from “low resistance crystalline state” to “high resistance amorphous state”, or “high resistance amorphous state” to “low resistance crystalline state”. The current value and the pulse width that cause the phase change to are determined and set to either the “low resistance crystalline state” or the “high resistance amorphous state”.

Exemplary phase change material, may be mentioned chalcogenide alloy, germanium, antimony, chalcogenide alloys (Ge ₂ Sb ₂ Te ₅₎ consisting of tellurium is that typically, in general, the phase change material (Ge ₂ Sb ₂ Te ₅ ) is described as “GST”.

  When the GST in the “low resistance crystalline state” is heated to a high temperature exceeding 600 ° C., its crystallinity is lost, and then, when cooled, the phase changes to the “high resistance amorphous state”. On the other hand, when the GST in the “high resistance amorphous state” is heated to a temperature higher than the crystallization temperature, but below the melting point, and kept in the heated state, re-crystallization proceeds and “low resistance” It returns to the “crystalline state”.

  In PRAM, when the phase change material (GST) is in the “low resistance crystalline state”, it represents “1” and is called “set state”, and the phase change material (GST) is in the “high resistance amorphous state”. Represents “0” and is referred to as “reset state”.

  When rewriting from the “reset state” to the “set state”, that is, when causing a phase change from the “high resistance amorphous state” to the “low resistance crystal state”, as a set programming current pulse, A small current for a long time. Since the “high resistance amorphous state” shows a large resistance value, even a “small current” can generate Joule heat necessary for heating to a temperature above the crystallization temperature. Then, re-crystallization proceeds to restore the “low resistance crystal state”.

  When rewriting from the “set state” to the “reset state”, that is, when causing a phase change from the “low resistance crystalline state” to the “high resistance amorphous state”, as a reset programming current pulse, A large electric current is passed through for a short time. In the “low-resistance crystal state”, a small resistance value is exhibited, so that a “large current” is passed to generate Joule heat required for heating to a high temperature exceeding 600 ° C. When reaching a high temperature exceeding 600 ° C., the phase change to the “high resistance amorphous state” proceeds, so that the resistance value increases rapidly and the state where the generated Joule heat increases rapidly is avoided. The width of the current pulse is set in a short time.

  In the PRAM, when the data is written, the set programming current pulse or the reset programming current pulse is applied to the storage element, thereby rewriting from the “reset state” to the “set state” and from the “set state” to the “reset state”. Reversible to reversibly.

  In ReRAM, a conductive path is formed inside the variable resistance element film due to the voltage and current applied from the outside, and is turned on. Conversely, the conductive material formed inside the variable resistance element film The characteristic that the resistance value changes depending on whether the sexual path disappears and is set to the “OFF” state is used. In the ReRAM cell, a structure having a resistance change element film sandwiched between two electrodes is used. Utilizing the electric field induced giant resistance change effect (Colosal Electro-Resistance), for example, an electric field is applied to generate a filament inside a resistance change element film made of a metal oxide, or conductive between two electrodes. The sexual path is formed and set to the “ON” state. On the other hand, by subsequently applying an electric field in the opposite direction, the filament disappears, or the conductive path formed between the two electrodes disappears, and an “OFF” state is set. By reversing the direction of the applied electric field, switching between the “ON” state and the “OFF” state, in which the resistance values between the two electrodes are greatly different, is performed. Data is stored by utilizing the fact that the current flowing through the storage element differs according to the difference in resistance value between the “ON” state and the “OFF” state. When writing data, select the voltage value, current value, and pulse width that cause the transition from the “OFF” state to the “ON” state and the transition from the “ON” state to the “OFF” state according to the data to be stored. Generation or disappearance of a filament for data storage, or formation or disappearance of a conductive path.

  As a type of variable resistance non-volatile switching element used in the configuration of ReRAM, as a resistance change element that has a high possibility of improving the degree of freedom of the “circuit” used in the configuration of the “memory cell” of ReRAM. The resistance value between the electrodes sandwiching the variable resistance element film using metal ion migration in the conductor and "metal precipitation by reduction of metal ions" and "metal ion generation by metal oxidation" by electrochemical reaction Non-Patent Document 1 discloses a non-volatile switching element that reversibly changes and performs switching. The nonvolatile switching element disclosed in Non-Patent Document 1 includes an “ion conductive layer” made of an ionic conductor and a “first electrode” and a “first electrode” provided in contact with each of the two surfaces of the “ion conductive layer”. Second electrode ”. The “first metal” constituting the “first electrode” and the “second metal” constituting the “second electrode” constituting the nonvolatile switching element oxidize the metal and generate metal ions. The standard generation Gibbs energy ΔG in the process is different.

  In the non-volatile switching element disclosed in Non-Patent Document 1, the “first metal” constituting the “first electrode” and the “second metal” constituting the “second electrode” Selection has been made.

  When the “bias voltage” that causes the transition from the “OFF” state to the “ON” state is applied between the “first electrode” and the “second electrode”, the “first electrode” and the “ion conduction layer” At the interface, the “first metal” constituting the “first electrode” is oxidized by an electrochemical reaction induced by an applied “bias voltage” to generate metal ions, and “ion conduction” A metal that can supply metal ions to the layer is employed.

  When a “bias voltage” that causes a transition from the “ON” state to the “OFF” state is applied between the “first electrode” and the “second electrode”, the “first electrode” is applied to the surface of the “second electrode”. When the “metal” is deposited, the “first metal” deposited on the surface of the “second electrode” is oxidized by the electrochemical reaction induced by the applied “bias voltage”. Metal ions are generated and dissolved in the “ion conductive layer” as metal ions, but the “second metal” constituting the “second electrode” is oxidized depending on the applied “bias voltage”. The process of generating metal ions is not induced and a metal is employed.

  The switching operation in the metal bridge type resistance change element that achieves the “ON” state and the “OFF” state by “forming the metal bridge structure” and “dissolving the metal bridge structure” will be briefly described.

  In the transition process (set process) from the “OFF” state to the “ON” state, when the first electrode is grounded and a negative voltage is applied to the second electrode, the first electrode and the ion conductive layer have an interface between the first electrode and the ion conductive layer. The metal of the electrode becomes metal ions and dissolves in the ion conductive layer. On the other hand, on the second electrode side, using the electrons supplied from the second electrode, metal ions in the ion conductive layer are deposited as metal in the ion conductive layer. A metal bridge structure is formed by the metal deposited in the ion conductive layer, and finally, a metal bridge connecting the first electrode and the second electrode is formed. By electrically connecting the first electrode and the second electrode by metal bridge, the switch is turned on.

  On the other hand, in the transition process (reset process) from the “ON” state to the “OFF” state, when the first electrode is grounded and a positive voltage is applied to the second electrode with respect to the switch in the “ON” state, The metal constituting the metal becomes metal ions and dissolves in the ion conductive layer. As the dissolution proceeds, a part of the “metal cross-linking structure” constituting the metal cross-linking is cut. Finally, when the metal bridge connecting the first electrode and the second electrode is cut, the electrical connection is cut and the switch is in the “OFF” state.

  As the dissolution of the metal proceeds, the “metal bridge structure” constituting the conduction path becomes narrower, the resistance between the first electrode and the second electrode increases, and the first electrode and the ion conductive layer At the interface, the dissolved metal ions are reduced and deposited as metal, so the concentration of metal ions contained in the “ion conductive layer” decreases and the inter-electrode capacitance changes as the relative permittivity changes. The electrical characteristics change from the stage before the electrical connection is completely disconnected, and the electrical connection is finally disconnected.

  Further, when a negative voltage is applied to the second electrode while grounding the first electrode again to the metal bridge type resistance change element that has been changed (reset) to the “OFF” state, the “OFF” state is changed to “ON”. The transition process (set process) to the state proceeds. That is, in the metal bridge type resistance change element, the transition process (set process) from the “OFF” state to the “ON” state and the transition process (reset process) from the “ON” state to the “OFF” state are reversible. Can be done automatically.

  In addition, in the transition process (set process) from the “OFF” state to the “ON” state, the second electrode is grounded and a positive voltage is applied to the first electrode, while the “ON” state is switched to “OFF”. As shown in FIG. 8, the transition process to the state (reset process) employs a procedure of applying a negative voltage to the first electrode by grounding the second electrode with respect to the switch in the “ON” state. A reversible switching operation can also be performed.

  Non-Patent Document 1 discloses a configuration of a two-terminal switching element in which two electrodes are arranged via an ion conductor to control a conduction state between the two electrodes, and a switching operation thereof. ing.

  The two-terminal switching element to which the variable resistance element described above is applied has a feature that the size is smaller than that of a semiconductor switch such as a MOSFET and the resistance in the “ON” state is small. This feature is considered promising for application to programmable logic devices. Further, in the resistance change type switching element, the conductive state (“ON” state or [OFF] state) is maintained as it is without applying the voltage used for the set operation and the reset operation after the set operation and the reset operation. The Therefore, the variable resistance switching element can be applied as a switching element constituting a nonvolatile memory element.

  When configuring a nonvolatile memory element, for example, a memory cell is configured with one selection element such as a transistor and one switching element as a basic unit. A plurality of the memory cells are arranged in the vertical direction and the horizontal direction, respectively, to form a “cell matrix”. Arranging memory cells in a matrix makes it possible to select an arbitrary memory cell from among a plurality of memory cells arranged in a matrix with word lines and bit lines. Then, the conduction state (“ON” state or [OFF] state) of the switching element of the selected memory cell is sensed, and information “1” or “0” is determined based on the “ON” state or [OFF] state of the switching element. It is possible to read which is stored. A non-volatile memory can be realized.

  Non-Patent Document 1 describes metal ion movement in an ion conductor (a solid electrolyte in which ions can move according to an applied electric field), and electrochemical reaction, that is, generation of metal ions by oxidation of metal (oxidation reaction). A switching element (solid electrolyte switch) using “formation of metal bridge” and “dissolution of metal bridge” due to metal precipitation (reduction reaction) due to reduction of metal ions is disclosed. The switching element disclosed in Non-Patent Document 1 includes an ion conductive layer, and a first electrode (active electrode) and a second electrode (inactive electrode) provided to face each other across the ion conductive layer. . In the “metal bridge formation” process, the first electrode serves to supply metal ions to the ion conductive layer. On the other hand, in the “dissolution of metal bridge” process, generation of metal ions (oxidation reaction) due to oxidation of the metal constituting the second electrode does not occur, and generation of metal ions due to oxidation of the metal constituting the metal bridge proceeds.

M. Tada, K. Okamoto, T. Sakamoto, M. Miyamura, N. Banno, and H. Hada, "Polymer Solid-Electrolyte (PSE) Switch Embedded on CMOS for Nonvolatile Crossbar Switch", IEEE TRANSACTION ON ELECTRON DEVICES, Vol 58, No. 12, pp.4398-4405, (2011).

  The variable resistance element described above functions as a “switching element” employed in a “memory cell” having a 1T1R (1 transistor-1 resistor) configuration, which is a basic unit when configuring a nonvolatile memory element. When constructing a high-density “cell matrix” by arranging “memory cells” of 1T1R (1 transistor-1 resistor) configuration in a matrix, on the semiconductor substrate on which the transistors used as the selection elements are fabricated It is necessary to arrange “resistance change elements” provided in the multilayer wiring layer at a high density. When switching a “resistance change element” that functions as a two-terminal switching element, a “set voltage” or “reset voltage” is applied between two electrodes of each “resistance change element”. In the “resistance change element” provided in the multilayer wiring layer, the “set voltage” is applied to the lower electrode of the “resistance change element” provided in the lower layer via the “contact plug” from the “upper wiring layer”, Or apply “reset voltage”.

  In each “resistance change element”, the “resistance change element” provided in the multilayer wiring layer by electrically arranging the “contact plug”, which electrically connects the lower electrode and the “upper wiring layer”. The present inventors have conceived that it is possible to arrange them at a higher density. A “contact plug” that electrically connects the lower electrode of the “resistance change element” and the “upper wiring layer” is formed in a via hole that vertically penetrates the interlayer insulating film. Therefore, even if the alignment accuracy at the time of forming the etching mask is high, the “process” in the process of forming a via hole by anisotropic etching of the interlayer insulating film, for example, in the etching step such as “control of side etching amount” The present inventors have found that “variation in conditions” causes a short circuit between the upper electrode of the “resistance change element” and the “contact plug”.

  The "resistance change element" provided in the multilayer wiring layer itself is miniaturized, the "area" required for the layout of the "resistance change element" and "contact plug" is made as small as possible, and the arrangement density of the "resistance change element" is higher. Densification is desired. However, when a finer “resistance change element” is formed, a short circuit between the upper electrode of the “resistance change element” and the “contact plug” is likely to occur. The present inventors have found the problem of being an obstacle.

  The present invention solves the above-described problems in further increasing the density. The object of the present invention is to adopt a novel configuration capable of effectively preventing the occurrence of a short circuit between the upper electrode of the “resistance change element” and the “contact plug”, and at a high density in the multilayer wiring layer. An object of the present invention is to provide a “resistance change element” capable of arranging an element, a semiconductor device using the “resistance change element”, and a method of forming the “resistance change element”.

  In order to increase the reliability of the “resistance change element” provided in the multilayer wiring layer, the present inventors first made a “resistance change element” by using a passivation film (protective insulating film) for improving oxidation resistance and moisture resistance. It has been found that it is effective to adopt a configuration that covers the side surface of "." After forming a passivation film (protective insulating film) that covers the side surface of the “resistance change element”, the upper electrode (first electrode) of the “resistance change element” and the upper part of the passivation film (protective insulating film) are covered. Thus, a first interlayer insulating film is formed. A first contact plug is formed in the via hole formed in the first interlayer insulating film. At this time, if the arrangement of the first contact plug is selected so that the side wall of the first contact plug is in contact with the side surface of the passivation film (protective insulating film), the upper electrode (first resistance variable element) It has been found that a passivation film (protective insulating film) is inserted between the side surface of the first electrode) and the side wall portion of the first contact plug, and the two can be kept electrically separated.

  When the arrangement of the first contact plug is selected, it is possible to effectively prevent the occurrence of a short circuit between the upper electrode of the “resistance change element” and the “contact plug”, and at the same time, the “resistance change element” and “ It has also been found that the “area” required for the layout of the “contact plug” can be reduced, and the elements can be arranged at high density in the multilayer wiring layer.

  The inventors of the present application have completed the present invention and solved the problem based on the knowledge described above for the problem found by the present inventors.

That is, the variable resistance element according to the present invention is
A resistance change element provided in a wiring layer on a semiconductor substrate,
The wiring layer has a first interlayer insulating film,
The variable resistance element is
A resistance change film;
A first electrode formed in contact with the upper surface of the variable resistance film;
A protective insulating film that covers the side surface of the variable resistance element, including the variable resistance film and the first electrode, is formed.
A first interlayer insulating film is formed so as to cover at least the upper part of the first electrode of the variable resistance element and the upper part of the protective insulating film,
A first contact plug is formed in the via hole formed in the first interlayer insulating film,
The variable resistance element is characterized in that a side wall portion of a first contact plug is in contact with a side surface of the protective insulating film.

  When the protective insulating film is formed of a SiN film, the effect of the present invention is remarkable.

The first contact plug formed in the via hole is
It is preferable that the plug portion is made of a metal mainly composed of copper and a barrier metal layer covering the periphery of the plug portion.

in addition,
The resistance change film of the resistance change element is formed on an insulating barrier film that covers the upper surface of the lower copper wiring,
The insulating barrier film covering the upper surface of the lower copper wiring has an opening,
The upper surface of the lower copper wiring is preferably in contact with the lower surface of the variable resistance film of the variable resistance element through the opening.

that time,
The insulating barrier film covering the upper surface of the lower copper wiring is preferably a SiN film or a SiCN film.

The resistance change film of the resistance change element is formed on an insulating barrier film that covers the upper surface of the lower copper wiring,
The first contact plug may be configured to penetrate through the insulating barrier film and to be in contact with the upper surface of the lower copper wiring located below the penetration portion.

The first electrode is made of a metal mainly composed of Ru,
The variable resistance film may be configured to be a film made of a solid electrolyte.

Alternatively, in the variable resistance element according to the present invention,
The variable resistance film may also employ a configuration including an oxide.

The wiring layer has a second interlayer insulating film formed on the first interlayer insulating film,
An upper copper wiring is formed in the second interlayer insulating film,
The first contact plug formed in the first interlayer insulating film is integrated with the upper copper wiring formed in the second interlayer insulating film, and a form in which the first contact plug is formed is selected. be able to.

In particular, an upper surface protective film is formed on the upper surface of the first electrode,
It is desirable to select a configuration in which the protective insulating film covers the side surfaces of the resistance change film, the first electrode, and the upper surface protective film.

  When the above configuration is selected, the side surfaces of the variable resistance film and the first electrode are protected by the protective insulating film, and the upper surface is protected by the upper surface protective film, thereby improving the oxidation resistance and moisture resistance. The effect of increases.

  By adopting the configuration of the variable resistance element according to the present invention, upper and lower wiring layers constituting a multilayer wiring layer while maintaining high reliability of the variable resistance element provided in the wiring layer on the semiconductor substrate. It is possible to fabricate a contact plug that electrically connects the resistance change elements in an arrangement closest to the resistance change element. As a result, it is easy to increase the arrangement density of the resistance change elements. It is easy to increase the capacity of a “cell matrix” composed of memory cells to be used, and it is possible to avoid a decrease in manufacturing yield.

FIG. 1 is a cross-sectional view schematically showing a configuration example of a resistance change element according to the first embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. FIG. 2 is a cross-sectional view schematically showing a configuration example of a variable resistance element according to the second embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. FIG. 3 is a cross-sectional view schematically showing a configuration example of the variable resistance element according to the third embodiment of the present invention, which is used as a nonvolatile switching element provided in the multilayer wiring layer of the semiconductor device. FIG. 4 is a cross-sectional view schematically showing a configuration example of a resistance change element according to the fourth embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. FIG. 5 is a cross-sectional view schematically showing a configuration example of a resistance change element according to the fifth embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. FIG. 6 is a cross-sectional view schematically showing a configuration example of a resistance change element according to the sixth embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. FIG. 7A shows an example of a process for manufacturing a resistance change element according to the seventh embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. It is sectional drawing which shows typically step A1 in a series of processes of the manufacturing process of a resistance change element. FIG. 7B shows an example of a process for manufacturing a variable resistance element according to the seventh embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. It is sectional drawing which shows typically step A2 in a series of processes of the manufacturing process of a resistance change element. FIG. 7C shows an example of a process for manufacturing a variable resistance element according to the third embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. It is sectional drawing which shows step A3 typically in a series of processes of the manufacturing process of a resistance change element. FIG. 12D shows an example of a process for manufacturing a variable resistance element according to the third embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. It is sectional drawing which shows step A4 typically in a series of processes of the manufacturing process of a resistance change element. FIG. 12E shows an example of a process for manufacturing a variable resistance element according to the third embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. It is sectional drawing which shows step A5 typically in a series of processes of the manufacturing process of a resistance change element. FIG. 12F shows an example of a process for manufacturing a variable resistance element according to the third embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. It is sectional drawing which shows step A6 typically in a series of processes of the manufacturing process of a resistance change element. FIG. 7G shows an example of a process for manufacturing a variable resistance element according to the seventh embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. It is sectional drawing which shows step A7 typically in a series of processes of the manufacturing process of a resistance change element. FIG. 7H shows an example of a process for manufacturing a variable resistance element according to the seventh embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device. It is sectional drawing which shows step A8 typically in a series of processes of the manufacturing process of a resistance change element. FIG. 13 is a diagram for explaining the switching process in the copper filament variable resistance element. The upper part shows the transition process (set process) from the “OFF” state to the “ON” state, and the lower part shows from the “ON” state. It is a figure explaining the transition process (reset process) to an "OFF" state, respectively. FIG. 9 is a diagram schematically illustrating an example of the configuration of an MRAM (Magnetic RAM). FIG. 10 is a diagram schematically illustrating an example of the configuration of a PRAM (Phase-change RAM). FIG. 11 is a diagram schematically illustrating an example of a configuration of an FRAM (Ferroelectric RAM). FIG. 12 is a diagram schematically illustrating an example of the configuration of a ReRAM (Resistive RAM). FIG. 13 is a diagram schematically showing a structure in which “second electrodes” of two “two-terminal switches” are integrated, showing an example of a switching element adopting a “three-terminal switch” configuration.

  Hereinafter, the present invention will be described in more detail.

(First embodiment)
A semiconductor device using the variable resistance element according to the first embodiment of the present invention as a nonvolatile switching element provided in a multilayer wiring layer will be described with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration example of a resistance change element according to the first embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device.

  As shown in FIG. 1, the resistance change element 99 according to the first embodiment is formed in a wiring layer on a semiconductor substrate (not shown). The wiring layer provided with the resistance change element 99 has a first interlayer insulating film 98. The resistance change element 99 includes a first electrode 102 and a resistance change film 101. In the variable resistance element 99, the side surfaces of the first electrode 102 and the variable resistance film 101 are covered with a protective insulating film 103.

  The first interlayer insulating film 98 is formed so as to cover the upper surface of the first electrode 102 and the protective insulating film 103 that covers the side surfaces of the first electrode 102 and the variable resistance film 101 in the variable resistance element 99. Has been. In addition, a first contact plug 104 is formed in the first interlayer insulating film 98. The side wall surface of the first contact plug 104 and the side surface of the protective insulating film 103 are in contact with each other. However, the side surface of the first electrode 102 and the side wall surface of the first contact plug 104 are electrically separated by the protective insulating film 103.

  The resistance change element 99 according to the first embodiment includes a resistance change film 101 and two electrodes sandwiching the resistance change film 101; a “first electrode” and a “second electrode”.

For example, the variable resistance element 99 according to the first embodiment is
The variable resistance film 101 is formed using a film made of a solid electrolyte, and used as an “ion conductive layer”;
“Underlying copper wiring” (not shown) is used as a “first electrode” that functions as an “ion supply layer” that generates copper ions by electrochemical reaction and supplies them into the “ion conducting layer”;
When the first electrode 102 in contact with the upper surface of the resistance change film 101 is used as a “second electrode”, a copper filament deposition type resistance change element using a solid electrolyte film can be formed.

At this time, the first electrode 102 used as the “second electrode” is an electrode containing a metal whose absolute value of standard generation Gibbs energy ΔG of oxidation (a process in which metal ions are generated from metal) is smaller than that of copper. is there. Ru, Pt, or the like can be used as a metal having a smaller absolute value of standard generation Gibbs energy ΔG of oxidation (a process in which metal ions are generated from metal) than copper. For example, a laminated structure of Ru (lower layer) / Ta (upper layer) may be used as the first electrode 102. On the other hand, TaO, TaSiO, SiO ₂ , ZrO ₂ , HfO ₂ , TiO ₂ , Al ₂ O ₃ , an organic polymer film, and SiO are included as a solid electrolyte constituting the resistance change film 101 that functions as an “ion conductive layer”. An organic polymer film or the like can be used.

  The resistance change film 101 formed using the solid electrolyte film and the protective insulating film 103 covering the side surfaces of the first electrode 102 can be formed using a SiN film.

When the variable resistance element 99 according to the first embodiment is a “copper filament deposition type variable resistance element” having the above-described configuration, the first interlayer insulating film 98 is used as a “second electrode”. The upper surface of the first electrode 102 and the protective insulating film 103 are in direct contact, but the resistance change film 101 is not in direct contact. In that case, the first interlayer insulating film 98 can be composed of a SiO ₂ film, a SiOC film, or a laminated film thereof.

  By forming the protective insulating film 103 using the SiN film, when the first interlayer insulating film 98 is formed, the oxidation proceeds from the side surface of the first electrode 102 and the first insulating film 103 is in contact with the resistance change film 101. A situation in which metal oxide is generated on the lower surface of the electrode 102 can be prevented.

  In addition, when moisture enters the solid electrolyte from the side surface of the resistance change film 101, when the resistance change element 99 is in the “high resistance state”, the penetrated moisture becomes a cause of generation of “leakage current”.

In addition, when moisture enters the solid electrolyte from the side surface of the resistance change film 101, the intruded moisture (H ₂ O) is oxidized by the copper filament formed inside the resistance change film 101, and the resistance change film 101. This causes oxidation of the upper surface of the lower wiring layer in contact (copper wiring layer) or oxidation of the lower surface of the first electrode 102 in contact with the resistance change film 101. That is, the oxidation caused by the invading moisture (H ₂ O) is one of the causes of the failure that causes the resistance state of the variable resistance element 99 to fluctuate. By forming the protective insulating film 103 using the SiN film, moisture can be prevented from entering the solid electrolyte from the side surface of the resistance change film 101, and the occurrence of the defect can be suppressed.

  As a method for forming the SiN film used for forming the protective insulating film 103, it is preferable to select a film formation method that does not deteriorate the resistance change characteristics of the resistance change element. In order to cover the side surfaces of the first electrode 102 and the resistance change film 101, an isotropic deposition method having excellent step coverage characteristics, for example, a plasma CVD method or a plasma ALD method is used. The thickness of the SiN film deposited on the side surfaces of the first electrode 102 and the resistance change film 101 is preferably selected in the range of 10 nm to 50 nm.

  As a result of employing the isotropic deposition method, the SiN film is deposited on the upper surface of the first electrode 102 in addition to the side surfaces of the first electrode 102 and the resistance change film 101. When the SiN film deposited on the upper surface of the first electrode 102 is selectively removed by employing an anisotropic dry etching method, the SiN film deposited on the side surfaces of the first electrode 102 and the resistance change film 101 Remains. As a result, the protective insulating film 103 is formed using the SiN film.

  The resistance change element 99 according to the first embodiment is a “copper filament deposition type resistance change element” configured by a laminated structure of a “lower wiring layer”, a resistance change film 101, and a first electrode 102. In this case, programming (switching) can be performed by applying a predetermined programming voltage between the “lower wiring layer” and the first electrode 102.

After the formation of the first interlayer insulating film 98, a via hole for forming the first contact plug 104, which is disposed closest to the protective insulating film 103 of the variable resistance element 99, is formed. At that time, using a resist mask having an opening corresponding to the shape of the lowermost hole of the via hole, from the upper surface of the first interlayer insulating film 98 toward the lower surface of the first interlayer insulating film 98, An anisotropic etching method, for example, a dry etching method is employed to perform anisotropic etching of the insulating material constituting the first interlayer insulating film 98. The anisotropic etching conditions of the insulating material (for example, SiO ₂ film, SiOC film) constituting the first interlayer insulating film 98 are conditions having selectivity with respect to the SiN film constituting the protective insulating film 103. Select.

  In the process of performing anisotropic etching from the upper surface of the first interlayer insulating film 98 to the lower surface of the first interlayer insulating film 98, side etching also proceeds slightly. As a result, the shape of the side wall of the via hole to be formed shows a slight taper.

  If side etching does not proceed at all, the side wall of the via hole to be formed maintains exactly the same shape as the opening of the resist mask, and the via hole on the lower surface of the first interlayer insulating film 98 is maintained. The outer edge of the side wall is closest to the bottom of the protective insulating film 103, but the protective insulating film 103 of the resistance change element 99 and the opening of the resist mask are aligned so as to make “point contact”. .

Actually, as a result of a slight side etching, the shape of the side wall of the via hole to be formed shows a slight taper. Therefore, near the lower surface of the first interlayer insulating film 98, the side surface of the protective insulating film 103 is partially exposed on the side wall surface of the via hole, showing a slight taper. The anisotropic etching conditions of the insulating material (for example, SiO ₂ film, SiOC film) constituting the first interlayer insulating film 98 are selected as conditions having selectivity with respect to the SiN film constituting the protective insulating film 103. Thus, the “side etching” on the side surface of the protective insulating film 103 exposed on the side wall surface of the via hole does not substantially proceed.

  Since the side surface of the protective insulating film 103 is partially exposed on the side wall surface of the via hole to be formed, when the first contact plug 104 is formed inside the via hole, as shown in FIG. The side surface of the formed first contact plug 104 comes into contact with the side surface of the insulating film 103.

  As the first contact plug 104, a copper plug covered with a barrier metal can be used. As the barrier metal, Ta, TaN, or a laminated structure thereof can be used.

  Since the variable resistance element according to the first embodiment employs a configuration in which the side surface is covered with a protective insulating film made of a SiN film, when the first contact plug 104 is formed at a position adjacent to the variable resistance element 99. Since the protective insulating film 103 exists, the first electrode 102 of the variable resistance element 99 and the first contact plug 104 can be prevented from being electrically short-circuited.

(Second Embodiment)
A semiconductor device using the variable resistance element according to the second embodiment of the present invention as a nonvolatile switching element provided in a multilayer wiring layer will be described with reference to the drawings. FIG. 2 is a cross-sectional view schematically showing a configuration example of a variable resistance element according to the second embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device.

  As shown in FIG. 2, the resistance change element 299 according to the second embodiment is formed in a wiring layer on a semiconductor substrate (not shown). The wiring layer in which the variable resistance element 299 is provided has a first interlayer insulating film 211. The resistance change element 299 includes a first electrode 202, a resistance change film 201, and a second electrode 205. In the variable resistance element 299, the side surfaces of the first electrode 202 and the variable resistance film 201 are covered with a protective insulating film 203.

  The first interlayer insulating film 211 includes the first electrode 202, the second electrode 205, and the protective insulating film 203 that covers the side surfaces of the first electrode 202 and the resistance change film 201 in the resistance change element 299. It is formed to cover. In addition, a first contact plug 204 is formed in the first interlayer insulating film 211. The side wall surface of the first contact plug 204 and the side surface of the protective insulating film 203 are in contact with each other. However, the side surface of the first electrode 202 and the side wall surface of the first contact plug 204 are electrically separated by the protective insulating film 203.

  The bottom of the first contact plug 204 is in contact with the upper surface of the second electrode 205, and the second electrode 205 is electrically connected to the first contact plug 204.

  A resistance change element 299 according to the second embodiment includes a resistance change film 201 and two electrodes sandwiching the resistance change film 201; a first electrode 202 and a second electrode 205.

When the configuration of an oxygen deficient resistance change element is selected as the resistance change element 299 according to the second embodiment, the resistance change film 203 is made of an oxide. The resistance change film 203 can be formed using TaO, TaSiO, ZrO ₂ , HfO ₂ , TiO ₂ , SiO ₂ , Al ₂ O _3, or a laminated structure thereof. The first electrode 204 in contact with the upper surface of the resistance change film 203 and the second electrode 205 in contact with the lower surface of the resistance change film 203 are, for example, Pt, Ru, Ir, Ti, Ta, Hf, Zr, Al, W, Can be formed using these nitrogen compounds.

When the resistance change element 299 according to the second embodiment is an oxygen deficient resistance change element, the protective insulating film 203 is formed of a SiN film or a SiCN film. On the other hand, the first interlayer insulating film 211 is formed of a SiO ₂ film or a SiOC film.

  By forming the protective insulating film 203 using a SiN film or a SiCN film, when the first interlayer insulating film 211 is formed, oxidation proceeds from the side surface of the first electrode 203, and the upper surface of the resistance change film 201. It is possible to prevent a metal oxide from being generated on the lower surface of the first electrode 203 in contact with the first electrode 203.

  In addition, when moisture enters the oxide from the side surface of the resistance change film 201, when the resistance change element 299 is in the “high resistance state”, the penetrated moisture becomes a cause of generation of “leakage current”.

  Further, when the side surface is not covered with the protective insulating film 203, when oxygen is desorbed from the side surface of the oxide film constituting the resistance change film 201 when the first interlayer insulating film 211 is formed, oxidation is performed. The average oxidation number in the vicinity of the side surface of the object film changes from the average oxidation number of the oxide film. As a result, this becomes one of the factors that cause the occurrence of a defect that causes the resistance state of the variable resistance element 299 to fluctuate. By covering the side surface with the protective insulating film 203, the occurrence of the defect can be suppressed.

  When the resistance change element 299 is an oxygen deficient resistance change element including a stacked structure of the second electrode 205, the resistance change film 201, and the first electrode 202, the second electrode 205 and the first electrode Programming (switching) can be performed by applying a predetermined programming voltage between the electrodes 202. For example, by applying a predetermined voltage to the first electrode 202 after the second electrode 205 is grounded, the switching operation of the oxygen deficient resistance change element, from “high resistance state” to “low resistance state”. “Set operation” and “reset operation” from “low resistance state” to “high resistance state” can be performed.

After the formation of the first interlayer insulating film 211, a via hole for forming the first contact plug 204 that is disposed closest to the protective insulating film 103 of the variable resistance element 299 is formed. At that time, using a resist mask having an opening corresponding to the shape of the lowermost hole of the via hole, from the upper surface of the first interlayer insulating film 211 toward the lower surface of the first interlayer insulating film 211, An anisotropic etching method, for example, a dry etching method is employed to perform anisotropic etching of the insulating material constituting the first interlayer insulating film 211. The anisotropic etching conditions of the insulating material (for example, SiO ₂ film, SiOC film) constituting the first interlayer insulating film 211 are conditions having selectivity with respect to the SiN film constituting the protective insulating film 103 Select.

  In the process of performing anisotropic etching from the upper surface of the first interlayer insulating film 211 toward the lower surface of the first interlayer insulating film 198, side etching also proceeds slightly. As a result, the shape of the side wall of the via hole to be formed shows a slight taper.

  If side etching does not proceed at all, the sidewall of the via hole to be formed maintains exactly the same shape as the opening of the resist mask, and the via hole on the lower surface of the first interlayer insulating film 211 is maintained. The outer edge of the side wall is closest to the bottom of the protective insulating film 203, but the protective insulating film 203 of the resistance change element 299 and the opening of the resist mask are aligned so as to make “point contact”. .

Actually, as a result of a slight side etching, the shape of the side wall of the via hole to be formed shows a slight taper. Therefore, near the lower surface of the first interlayer insulating film 211, the side surface of the protective insulating film 203 is partially exposed on the side wall surface of the via hole, which shows a slight taper. The anisotropic etching conditions of the insulating material (for example, SiO ₂ film, SiOC film) constituting the first interlayer insulating film 211 are selected so as to have selectivity with respect to the SiN film constituting the protective insulating film 203. Therefore, the “side etching” on the side surface of the protective insulating film 203 exposed on the side wall surface of the via hole does not substantially proceed.

  Since the side surface of the protective insulating film 203 is partially exposed on the side wall surface of the via hole to be formed, when the first contact plug 204 is formed inside the via hole, as shown in FIG. The side wall surface of the formed first contact plug 204 comes into contact with the side surface of the insulating film 203.

  As the first contact plug 204, a copper plug covered with a barrier metal can be used. As the barrier metal, Ta, TaN, or a laminated structure thereof can be used.

  Even in the variable resistance element according to the second embodiment, the side surface of the variable resistance element is covered with a protective insulating film made of a SiN film. Therefore, when the first contact plug 204 is formed at a position adjacent to the variable resistance element 299. Since the protective insulating film 203 exists, the first electrode 202 of the variable resistance element 299 and the first contact plug 204 can be prevented from being electrically short-circuited.

  By selecting the configuration shown in FIG. 2, the second electrode 205 can be electrically connected to the upper copper wiring via the first contact plug 204 and grounded.

(Third embodiment)
A semiconductor device using the variable resistance element according to the third embodiment of the present invention as a nonvolatile switching element provided in a multilayer wiring layer will be described with reference to the drawings. FIG. 3 is a cross-sectional view schematically showing a configuration example of the variable resistance element according to the third embodiment of the present invention, which is used as a nonvolatile switching element provided in the multilayer wiring layer of the semiconductor device.

  As shown in FIG. 3, the variable resistance element 399 according to the third embodiment is formed in a wiring layer on a semiconductor substrate (not shown). The wiring layer provided with the variable resistance element 399 has a first interlayer insulating film 311. The resistance change element 399 includes a first electrode 302, a resistance change film 301, and a second electrode 315. The first electrode 302, the resistance change film 301, and the second electrode 315 included in the resistance change element 399 form a stacked structure, and the side surfaces thereof are covered with the protective insulating film 303.

  The resistance change element 399 is formed on the upper surfaces of the lower copper wiring 307 and the lower interlayer insulating film 310. A part of the second electrode 315 is in contact with and electrically connected to the upper surface of the lower-layer copper wiring 307. Further, the protective insulating film 303 covering one side surface of the laminated structure is also formed at a position where the bottom surface is in contact with the upper surface of the lower copper wiring 307.

  The first interlayer insulating film 311 covers the first electrode 302 of the resistance change element 399 and the side surface of the laminated structure including the first electrode 302, the resistance change film 301, and the second electrode 315. The insulating film 303 is formed so as to cover it. In addition, the first interlayer insulating film 311 is formed so as to cover the upper surfaces of the lower copper wiring 307 and the lower interlayer insulating film 310.

  A first contact plug 304 is formed in the first interlayer insulating film 311. The side wall surface of the first contact plug 304 and the side surface of the protective insulating film 303 are in contact with each other. However, the side surface of the first electrode 302 and the side wall surface of the first contact plug 304 are electrically separated by the protective insulating film 303.

  The bottom of the first contact plug 304 is in contact with the upper surface of the lower copper wiring 307, so that the second electrode 315 is electrically connected to the first contact plug 304 via the lower copper wiring 307. Has been.

  A resistance change element 399 according to the third embodiment includes a resistance change film 301 and two electrodes sandwiching the resistance change film 301; a first electrode 302 and a second electrode 315.

When the configuration of an oxygen deficient resistance change element is selected as the resistance change element 399 according to the third embodiment, the resistance change film 301 is made of an oxide. The resistance change film 301 can be formed using TaO, TaSiO, ZrO ₂ , HfO ₂ , TiO ₂ , SiO ₂ , Al ₂ O _3, or a laminated structure thereof. The first electrode 302 in contact with the upper surface of the resistance change film 301 and the second electrode 315 in contact with the lower surface of the resistance change film 301 are, for example, Pt, Ru, Ir, Ti, Ta, Hf, Zr, Al, W, Can be formed using these nitrogen compounds.

When the resistance change element 399 according to the third embodiment is an oxygen deficient resistance change element, the protective insulating film 303 is formed of a SiN film or a SiCN film. On the other hand, the first interlayer insulating film 311 is formed of a SiO ₂ film or a SiOC film. The lower interlayer insulating film 310 is also formed of a SiO ₂ film or a SiOC film.

  The metal 308 of the lower copper wiring 307 is buried in the wiring groove for the lower copper wiring formed in the lower interlayer insulating film 310 via the barrier metal 309. When the metal 308 of the lower-layer copper wiring 307 is a metal material mainly composed of copper, the barrier metal 309 that covers the side and bottom surfaces of the wiring groove is a conductive material having a barrier property against copper diffusion. It is a membrane. As the barrier metal 309, a refractory metal such as tantalum, tantalum nitride, titanium nitride, or tungsten carbonitride, a nitride thereof, or a stacked film thereof can be used.

  Since the second electrode 315 in contact with the lower surface of the resistance change film 301 is also a conductive film having a barrier property against copper diffusion, the metal 308 of the lower copper wiring 307 is a metal mainly composed of copper. In the case of the material, diffusion of copper ions into the oxide constituting the resistance change film 301 is also prevented.

  As the first contact plug 304, a copper plug 305 covered with a barrier metal 306 can be used. As the barrier metal 306, Ta, TaN, or a laminated structure thereof can be used.

  By forming the protective insulating film 303 using a SiN film or a SiCN film, oxidation proceeds from the side surface of the first electrode 303 and the side surface of the second electrode 315 when the first interlayer insulating film 311 is formed. In addition, it is possible to prevent a metal oxide from being generated on the lower surface of the first electrode 303 in contact with the upper surface of the resistance change film 301 and the upper surface of the first electrode 315 in contact with the upper surface of the resistance change film 301.

  In addition, when moisture enters the oxide from the side surface of the resistance change film 301, when the resistance change element 399 is in the “high resistance state”, the penetrated moisture becomes a cause of generation of “leakage current”.

  Further, when the side surface is not covered with the protective insulating film 303, when oxygen is desorbed from the side surface of the oxide film constituting the resistance change film 301 when the first interlayer insulating film 311 is formed, oxidation occurs. The average oxidation number in the vicinity of the side surface of the object film changes from the average oxidation number of the oxide film. As a result, it becomes one of the factors that cause the occurrence of a defect that causes the resistance state of the variable resistance element 399 to fluctuate. By covering the side surfaces with the protective insulating film 303, occurrence of the defect can be suppressed.

  When the resistance change element 399 is an oxygen-deficient resistance change element including a stacked structure of the second electrode 315, the resistance change film 301, and the first electrode 302, the second electrode 315 and the first electrode Programming (switching) can be performed by applying a predetermined programming voltage between the electrodes 302. For example, by applying a predetermined voltage to the first electrode 302 after the second electrode 315 is grounded, the switching operation of the oxygen deficient resistance change element, from “high resistance state” to “low resistance state”. “Set operation” and “reset operation” from “low resistance state” to “high resistance state” can be performed.

After the formation of the first interlayer insulating film 311, a via hole for forming the first contact plug 304 that is disposed closest to the protective insulating film 303 of the variable resistance element 399 is formed. At that time, using a resist mask having an opening corresponding to the shape of the bottom end of the via hole, from the upper surface of the first interlayer insulating film 311 toward the lower surface of the first interlayer insulating film 311, An anisotropic etching method, for example, a dry etching method is employed to perform anisotropic etching of the insulating material constituting the first interlayer insulating film 311. The anisotropic etching conditions of the insulating material (for example, SiO ₂ film, SiOC film) constituting the first interlayer insulating film 311 are conditions having selectivity with respect to the SiN film constituting the protective insulating film 303. Select. At that time, the anisotropic etching conditions of the insulating material (for example, SiO ₂ film, SiOC film) constituting the first interlayer insulating film 311 are the metal 308 of the lower copper wiring 307 and the metal material mainly composed of copper. In contrast, it is also a condition having selectivity.

  In the process of performing anisotropic etching from the upper surface of the first interlayer insulating film 311 toward the lower surface of the first interlayer insulating film 311, side etching also proceeds slightly. As a result, the shape of the side wall of the via hole to be formed shows a slight taper.

  If the side etching does not proceed at all, the side wall of the via hole to be formed maintains the same shape as the shape of the opening of the resist mask, and the via hole on the lower surface of the first interlayer insulating film 311 is maintained. The outer edge of the side wall is closest to the bottom of the protective insulating film 303, but the protective insulating film 303 of the resistance change element 399 and the opening of the resist mask are aligned so as to make “point contact”. .

Actually, as a result of a slight side etching, the shape of the side wall of the via hole to be formed shows a slight taper. Therefore, near the lower surface of the first interlayer insulating film 311, the side surface of the protective insulating film 303 is partially exposed on the side wall surface of the via hole, showing a slight taper. The anisotropic etching conditions of the insulating material (for example, SiO ₂ film, SiOC film) constituting the first interlayer insulating film 311 are selected so as to have selectivity with respect to the SiN film constituting the protective insulating film 303. Thus, the “side etching” to the side surface of the protective insulating film 303 exposed on the side wall surface of the via hole does not substantially proceed.

  Since the side surface of the protective insulating film 303 is partially exposed on the side wall surface of the via hole to be formed, when the first contact plug 304 is formed inside the via hole, as shown in FIG. The side surface of the formed first contact plug 304 is in contact with the side surface of the insulating film 303.

The conditions for selectively etching the second electrode 315 in the process of patterning the laminated structure composed of the first electrode 302, the resistance change film 301, and the second electrode 315 used to form the resistance change element 399 are as follows. It is desirable that the conditions be selective with respect to the metal 308 of the lower copper wiring 307, the metal material mainly composed of copper, and Ta and TaN used for the barrier metal 309 of the lower copper wiring 307. . At the same time, the condition for selectively etching the second electrode 315 may be a condition having selectivity with respect to an insulating material (for example, SiO ₂ film, SiOC film) constituting the lower interlayer insulating film 310. desirable.

By adopting selective etching conditions that satisfy the above conditions, the insulating material (for example, the barrier metal 309 of the lower copper wiring 307, the metal 308 of the lower copper wiring 307, and the lower interlayer insulating film 310) , SiO ₂ film, SiOC film) can be used as an etching stopper to pattern the second electrode 315.

During the step of depositing an insulating material (for example, SiO ₂ film, SiOC film) constituting the first interlayer insulating film 311, the barrier metal 309 of the lower copper wiring 307 and the upper surface of the metal 308 of the lower copper wiring 307 are For example, a SiO ₂ film or a SiOC film is deposited using a plasma CVD method. At that time, the metal 308 of the lower-layer copper wiring 307 and the surface of the metal material mainly composed of copper may be slightly oxidized. In the process of forming the via hole in the first interlayer insulating film 311, the conditions for etching the insulating material (for example, SiO ₂ film, SiOC film) constituting the first interlayer insulating film 311 are as follows: Although it is possible to remove the copper oxide film existing on the surface of the metal 308 by etching, it is desirable that the metal material containing copper as a main component has a selectivity.

  Since the copper oxide film existing on the surface of the metal 308 of the lower copper wiring 307 has been removed by etching, the portion where the bottom surface of the first contact plug 304 and the surface of the metal 308 of the lower copper wiring 307 are in contact with each other. , “Inter-metal junction” is formed through a barrier metal 306, which can be represented by copper / (Ta, TaN, or a laminated structure thereof) / copper. The “metal-to-metal junction” functions as an “ohmic connection”, and when the diameter of the bottom surface of the first contact plug 304 is 100 nmφ, it is between the first contact plug 304 and the underlying copper wiring 307. Are connected with a contact resistance of about 1 to 5Ω.

  When a plurality of resistance change elements are arranged so that the laminated structure including the first electrode 302, the resistance change film 301, and the second electrode 315 is in contact with the surface of the metal 308 of the lower copper wiring 307, the electrode resistance is reduced. The structure which connects the 2nd electrode 315 of a some resistance change element to a common electric potential can be achieved, reducing.

(Fourth embodiment)
A semiconductor device using the variable resistance element according to the fourth embodiment of the present invention as a nonvolatile switching element provided in a multilayer wiring layer will be described with reference to the drawings. FIG. 4 is a cross-sectional view schematically showing a configuration example of a resistance change element according to the fourth embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device.

  As shown in FIG. 4, the variable resistance element 499 according to the fourth embodiment is mounted in a copper wiring layer formed on a semiconductor substrate. The multilayer wiring layer provided with the resistance change element 499 includes a first interlayer insulating film 498 and a second interlayer insulating film 416 located above the first interlayer insulating film 498. A resistance change element 499 according to the fourth embodiment includes a first electrode 402 and a resistance change film 401. The first electrode 402 and the resistance change film 401 included in the resistance change element 499 form a laminated structure, and are formed on the first insulating barrier film 411 that covers the surface of the lower copper wiring layer 407. Has been. A side surface of the laminated structure of the first electrode 402 and the resistance change film 401 is covered with a protective insulating film 403.

  The resistance change film 401 is in contact with the surface of the metal 408 of the lower copper wiring layer 407 through a hole opened in the first insulating barrier film 411. Therefore, in the opened hole portion, the lower surface of the resistance change film 401 is in contact with the surface of the metal 408 of the lower copper wiring layer 407, and the upper surface of the resistance change film 401 is in contact with the first electrode 402. Yes.

  The metal 408 of the lower copper wiring 407 is buried in the wiring groove for the lower copper wiring formed in the lower interlayer insulating film 410 via the barrier metal 409. The metal 408 of the lower layer copper wiring 407 is a metal material mainly composed of copper, and covers the side and bottom surfaces of the wiring groove. The barrier metal 409 is a conductive film having a barrier property against copper diffusion. It is. As the barrier metal 409, a refractory metal such as tantalum, tantalum nitride, titanium nitride, or tungsten carbonitride, a nitride thereof, or a stacked film thereof can be used.

  The first insulating barrier film 411 that covers the surface of the lower copper wiring layer 407 prevents the diffusion of copper from the surface of the lower copper wiring layer 407, so that a SiN film, a SiCN film, a SiC film, or the like, or They are formed by their laminated structure. The protective insulating film 403 is formed using a SiN film.

  The resistance change element 499 according to the fourth embodiment constitutes a copper filament deposition type resistance change element. The metal 408 of the lower-layer copper wiring 407 made of a metal material mainly composed of copper functions as an “ion supply layer” that generates copper ions and supplies them into the resistance change film 401 by an electrochemical reaction. . At that time, the “copper” forming the metal 408 of the lower-layer copper wiring 407 may contain metals such as Al, Ti, tin (Sn), and Mg as impurities.

The resistance change film 401 is formed of a solid electrolyte capable of conducting copper ions and is used as an “ion conductive layer”. As a solid electrolyte capable of conducting copper ions, it can be used _{TaO, TaSiO, SiO 2, ZrO} 2, HfO 2, TiO 2, Al 2 O 3, an organic polymer film, or an organic polymer film containing SiO.

  The first electrode 402 is an electrode including a metal whose absolute value of the standard generation Gibbs energy ΔG of oxidation (a process in which metal ions are generated from a metal) is smaller than that of copper. Ru, Pt, or the like can be used as a metal having a smaller absolute value of standard generation Gibbs energy ΔG of oxidation (a process in which metal ions are generated from metal) than copper. The first electrode 402 may constitute a laminated structure composed of a lower layer portion in contact with the resistance change film 401 and an upper layer portion laminated on the lower layer portion. In this case, the lower layer portion is made of copper, It is formed of a metal having a small absolute value of standard generation Gibbs energy ΔG of oxidation (a process in which metal ions are generated from metal). For example, a stacked structure of Ru (lower layer) / Ta (upper layer) may be used as the first electrode 402.

  That is, the resistance change film 401 made of a solid electrolyte is an “ion conductive layer”, the copper wiring 408 of the lower copper wiring layer 407 is a “first electrode” that functions as an “ion supply layer”, and the first electrode 402 is “ A resistance change element of a copper filament deposition type, which is a “second electrode”, is configured.

In the configuration shown in FIG. 4, the side wall surface of the hole opened in the first insulating barrier film 411 has no taper, and the opening is formed using an anisotropic etching method. The film thickness t ₂ of the resistance change film 401 formed in the hole opened in the first insulating barrier film 411 is formed on the upper surface of the surrounding first insulating barrier film 411. The resistance change film 401 is thicker than the film thickness t ₁ . As a result, the upper surface of the resistance change film 401 is in a state where there is no substantial step between the inside of the opened hole and the region of the upper surface of the first insulating barrier film 411 around the hole. In other words, the depth of the opened hole corresponds to the film thickness t ₃ of the first insulating barrier film 411, and “buried growth” satisfying the relationship of t ₂ = (t ₁ + t ₃ ) is satisfied. Has been achieved.

  The first electrode 402 is formed to have a uniform film thickness on the upper surface of the resistance change film 401 that is substantially “flattened” by using an isotropic deposition method, for example, a sputtering method. It is possible.

  The first interlayer insulating film 498 covers the first electrode 402 of the variable resistance element 499 and the protective insulating film 403 that covers the side surface of the laminated structure including the first electrode 402 and the variable resistance film 401. Is formed. In addition, the first interlayer insulating film 498 is formed so as to cover the upper surface of the first insulating barrier film 411 that covers the upper surfaces of the lower-layer copper wiring 407 and the lower-layer interlayer insulating film 410. Yes. After the upper surface of the formed first interlayer insulating film 498 is planarized, a second interlayer insulating film 416 is formed to cover the planarized first interlayer insulating film 498.

The first interlayer insulating film 498 is formed using a SiO ₂ film, and the second interlayer insulating film 416 is formed using a SiOC film.

  A wiring groove for forming an upper copper wiring layer is formed in the second interlayer insulating film 416, and a via hole for forming the first contact plug 404 is integrally formed in the first interlayer insulating film 498. Has been. At that time, the bottom of the via hole for forming the first contact plug 404 passes through the first insulating barrier film 411 and opens to the surface of the metal 408 of the lower copper wiring layer 407.

When a wiring groove for forming an upper copper wiring layer is formed in the second interlayer insulating film 416, the etching conditions of the SiOC film constituting the second interlayer insulating film 416 are set according to the first interlayer insulating film 498. The conditions are such that the SiO ₂ film constituting the film has selectivity. As a result, the SiO ₂ film constituting the first interlayer insulating film 498 can be used as an etching stopper, and the bottom surface of the wiring trench for forming the upper copper wiring layer to be formed is connected to the second interlayer insulating film 416. Located at the interface with the first interlayer insulating film 498. On the other hand, prior to the production of the wiring trench for forming the upper copper wiring layer, the second interlayer insulating film 416, the first interlayer insulating film 498, and the first insulating barrier film 411 are sequentially and selectively anisotropically formed. The via hole is formed by reactive etching.

After the formation of the second interlayer insulating film 416 is completed, a via hole for forming the first contact plug 404 that is disposed closest to the protective insulating film 403 of the variable resistance element 499 is formed. At that time, a resist mask having an opening corresponding to the shape of the lowermost hole of the via hole is used, and the second interlayer insulating film 416, the first interlayer insulating film 498, and the first insulating barrier film are used. 411 is sequentially and selectively anisotropically etched. At this time, an anisotropic etching method, for example, a dry etching method is employed from the upper surface of the first interlayer insulating film 498 toward the lower surface of the first interlayer insulating film 498 to thereby form the first interlayer insulating film 498. An anisotropic etching is selectively performed on the insulating material and the SiO ₂ film. The selective anisotropic etching conditions of the insulating material and SiO ₂ film constituting the first interlayer insulating film 498 are selected so as to have selectivity with respect to the SiN film constituting the protective insulating film 403. Yes.

  In the process of performing anisotropic etching from the upper surface of the first interlayer insulating film 498 toward the lower surface of the first interlayer insulating film 498, side etching also proceeds slightly. As a result, the shape of the side wall of the via hole to be formed shows a slight taper.

  If side etching does not proceed at all, the side wall of the via hole to be formed maintains the same shape as the shape of the opening of the resist mask, and the via hole on the lower surface of the first interlayer insulating film 498 is maintained. The outer edge of the side wall is closest to the bottom of the protective insulating film 403, but the protective insulating film 403 of the resistance change element 499 and the opening of the resist mask are aligned so as to make “point contact”. .

Actually, as a result of a slight side etching, the shape of the side wall of the via hole to be formed shows a slight taper. Therefore, near the lower surface of the first interlayer insulating film 498, the side surface of the protective insulating film 403 is partially exposed on the side wall surface of the via hole, which shows a slight taper. As a selective anisotropic etching condition for the insulating material and SiO ₂ film constituting the first interlayer insulating film 498, a condition having selectivity for the SiN film constituting the protective insulating film 403 is selected. The “side etching” on the side surface of the protective insulating film 403 exposed on the side wall surface of the via hole does not substantially proceed. Finally, the first insulating barrier film 411 formed of the SiCN film is selectively anisotropically etched, but is exposed to the side wall surface of the via hole, and the side surface of the protective insulating film 403 formed of the SiN film “Side etching” is only slightly progressed.

  Since the side surface of the protective insulating film 403 is partially exposed on the side wall surface of the via hole to be formed, when the first contact plug 404 is manufactured inside the via hole, as shown in FIG. The side wall surface of the formed first contact plug 404 is in contact with the side surface of the insulating film 403. However, the side surface of the first electrode 402 and the side wall surface of the first contact plug 404 are electrically separated by the protective insulating film 403.

  The metal 405 of the first contact plug 404 is formed through the barrier metal 406 in the wiring groove for forming the upper copper wiring layer and the via hole for forming the first contact plug 404 that are integrally formed. A first contact plug 404 embedded and integrated with the upper copper wiring is formed. The metal 405 of the first contact plug 404 is a metal material mainly composed of copper, and covers the side and bottom surfaces of the wiring trench and via hole. The barrier metal 406 has a barrier property against copper diffusion. It is a conductive film. As the barrier metal 406, a refractory metal such as tantalum, tantalum nitride, titanium nitride, or tungsten carbonitride, a nitride thereof, or a stacked film thereof can be used.

  The upper copper wiring layer thus fabricated and the upper surface of the second interlayer insulating film 416 are flattened and then covered with the second insulating barrier film 413. The second insulating barrier film 413 covering the surface of the upper copper wiring layer is a SiN film, a SiCN film, a SiC film, or the like in order to prevent copper diffusion from the surface of the upper copper wiring layer. It is formed with a laminated structure.

  When the configuration shown in FIG. 4 is selected, the first contact plug 404 integrated with the upper copper wiring layer is formed at the closest position so as to be in contact with the protective insulating film 403 of the resistance change film 401. At that time, the surface of the lower copper wiring layer 407 is covered with the first insulating barrier film 411 to prevent the diffusion of copper. Further, the lower copper wiring layer 407 used for the “first electrode” of the copper filament deposition type resistance change element 499 is connected to the upper copper wiring layer via a first contact plug 404. When the potential is applied at the time of switching, it is effective in reducing the layout area of the upper copper wiring layer.

(Fifth embodiment)
A semiconductor device using the variable resistance element according to the fifth embodiment of the present invention as a nonvolatile switching element provided in a multilayer wiring layer will be described with reference to the drawings. FIG. 5 is a cross-sectional view schematically showing a configuration example of a resistance change element according to the fifth embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device.

  As shown in FIG. 5, the variable resistance element 599 according to the fifth embodiment is mounted in a copper wiring layer formed on a semiconductor substrate. The multilayer wiring layer in which the variable resistance element 599 is provided includes a first interlayer insulating film 512 and a second interlayer insulating film 516 located above the first interlayer insulating film 512. A resistance change element 599 according to the fifth embodiment includes a first electrode 502 and a resistance change film 501. The first electrode 502 and the resistance change film 501 included in the resistance change element 599 have a laminated structure, and are on the first insulating barrier film 511 that covers the surfaces of the lower copper wiring layers 507a and 507b. Is formed. The side surface of the stacked structure of the first electrode 502 and the resistance change film 501 is covered with a protective insulating film 503.

  The resistance change film 501 is in contact with the surface of the metal 508b of the lower copper wiring layer 507b through a hole opened in the first insulating barrier film 511. Therefore, in the opened hole portion, the lower surface of the resistance change film 501 is in contact with the surface of the metal 508b of the lower copper wiring layer 507b, and the upper surface of the resistance change film 501 is in contact with the first electrode 502. Yes.

  In the lower interlayer insulating film 510, a lower copper wiring layer 507a is formed separately from the lower copper wiring layer 507b. The bottom surface of the first contact plug 504 formed integrally with the upper copper wiring layer is formed of the metal 508a of the lower copper wiring layer 507a through the opening formed in the first insulating barrier film 511. It touches the surface.

  The metal grooves 508b of the lower copper wiring 507b are buried in the wiring grooves for the lower copper wiring, which are formed in the lower interlayer insulating film 510, via the barrier metal 509b, respectively. The metal 508a of the lower layer copper wiring 507a is buried therethrough. The metal 508b of the lower copper wiring 507b is a metal material mainly composed of copper, and covers the side and bottom surfaces of the wiring groove. The barrier metal 509b is a conductive film having a barrier property against copper diffusion. It is. Further, the metal 508a of the lower copper wiring 507a is a metal material mainly composed of copper, and the barrier metal 509a covering the side and bottom surfaces of the wiring groove is a conductive material having a barrier property against copper diffusion. It is a sex membrane. As the barrier metal 509b and the barrier metal 509a, a refractory metal such as tantalum, tantalum nitride, titanium nitride, or tungsten carbonitride, a nitride thereof, or a stacked film thereof can be used.

  The first insulating barrier film 511 that covers the surfaces of the lower copper wiring layers 507b and 507a is formed of an SiN film, an SiCN film, and an SiC film in order to prevent copper from diffusing from the surface of the lower copper wiring layers 507b and 507a. Or a stacked structure thereof. The protective insulating film 403 is formed using a SiN film.

  The resistance change element 599 according to the fifth embodiment constitutes a copper filament deposition type resistance change element. The metal 508b of the lower copper wiring 507b made of a metal material mainly composed of copper functions as an “ion supply layer” that generates copper ions by an electrochemical reaction and supplies the copper ions into the resistance change film 501. . At that time, the “copper” forming the metal 508b of the lower-layer copper wiring 507b may contain metals such as Al, Ti, tin (Sn), and Mg as impurities.

The resistance change film 501 is formed of a solid electrolyte capable of conducting copper ions and is used as an “ion conductive layer”. As a solid electrolyte capable of conducting copper ions, it can be used _{TaO, TaSiO, SiO 2, ZrO} 2, HfO 2, TiO 2, Al 2 O 3, an organic polymer film, or an organic polymer film containing SiO.

  The first electrode 502 is an electrode containing a metal having a smaller absolute value of standard generation Gibbs energy ΔG of oxidation (a process in which metal ions are generated from metal) than copper. Ru, Pt, or the like can be used as a metal having a smaller absolute value of standard generation Gibbs energy ΔG of oxidation (a process in which metal ions are generated from metal) than copper. The first electrode 502 may constitute a laminated structure composed of a lower layer portion in contact with the resistance change film 501 and an upper layer portion laminated on the lower layer portion. In this case, the lower layer portion is made of copper, It is formed of a metal having a small absolute value of standard generation Gibbs energy ΔG of oxidation (a process in which metal ions are generated from metal). For example, a laminated structure of Ru (lower layer) / Ta (upper layer) may be used as the first electrode 502.

  That is, the resistance change film 501 made of a solid electrolyte is an “ion conductive layer”, the copper wiring 508 b of the lower copper wiring layer 507 b is a “first electrode” that functions as an “ion supply layer”, and the first electrode 502 is “ A resistance change element of a copper filament deposition type, which is a “second electrode”, is configured.

In the structure shown in FIG. 5, the side wall surface of the hole opened in the first insulating barrier film 511 covering the upper surface of the lower copper wiring layer 507b has no taper, and the formation of the opening is anisotropic. Etching method is used. The film thickness t ₂ of the resistance change film 501 formed in the hole opened in the first insulating barrier film 511 is formed on the upper surface of the surrounding first insulating barrier film 511. The resistance change film 501 is thicker than the film thickness t ₁ . As a result, the upper surface of the resistance change film 501 is in a state where there is no substantial step between the inside of the opened hole and the region of the upper surface of the first insulating barrier film 511 around the hole. In other words, the depth of the opened hole corresponds to the film thickness t ₃ of the first insulating barrier film 511, and “buried growth” satisfying the relationship t ₂ = (t ₁ + t ₃ ) is satisfied. Has been achieved.

  The first electrode 502 is formed to have a uniform film thickness on the upper surface of the resistance change film 501 that is substantially “flattened” by using an isotropic deposition method, for example, a sputtering method. It is possible.

  Of the variable resistance element 599, the first interlayer insulating film 512 covers the first electrode 502 and the protective insulating film 503 that covers the side surface of the stacked structure including the first electrode 502 and the variable resistance film 501. Is formed. In addition, the first interlayer insulating film 512 is formed so as to cover the upper surface of the first insulating barrier film 511 that covers the upper surfaces of the lower copper insulating layer 507a and the lower interlayer insulating film 510. ing. After the upper surface of the formed first interlayer insulating film 512 is planarized, a second interlayer insulating film 516 is formed to cover the planarized first interlayer insulating film 512.

The first interlayer insulating film 512 is formed using a SiO ₂ film, and the second interlayer insulating film 516 is formed using a SiOC film.

  A wiring groove for forming an upper copper wiring layer is formed in the second interlayer insulating film 516, and a via hole for forming the first contact plug 504 is integrally formed in the first interlayer insulating film 512. Has been. At that time, the bottom of the via hole for forming the first contact plug 504 passes through the first insulating barrier film 511 and opens to the surface of the metal 508a of the lower copper wiring layer 507a.

When the wiring groove for forming the upper copper wiring layer is formed in the second interlayer insulating film 516, the etching conditions of the SiOC film constituting the second interlayer insulating film 516 are set according to the first interlayer insulating film 512. The conditions are such that the SiO ₂ film constituting the film has selectivity. As a result, the SiO ₂ film constituting the first interlayer insulating film 512 can be used as an etching stopper, and the bottom surface of the wiring trench for forming the upper copper wiring layer to be formed is connected to the second interlayer insulating film 516. Located at the interface with the first interlayer insulating film 512. On the other hand, prior to the formation of the wiring trench for forming the upper copper wiring layer, the second interlayer insulating film 516, the first interlayer insulating film 512, and the first insulating barrier film 511 are selectively anisotropically sequentially formed. The via hole is formed by reactive etching.

After finishing the formation of the second interlayer insulating film 516, the first interlayer insulating film 516 reaches the surface of the metal 508a of the lower copper wiring layer 507a, which is disposed in proximity to the protective insulating film 503 of the resistance change element 599. A via hole for forming the contact plug 404 is formed. At that time, using a resist mask having an opening corresponding to the shape of the bottom end of the via hole, the second interlayer insulating film 516, the first interlayer insulating film 512, and the first insulating barrier film are used. 511 is sequentially and selectively anisotropically etched. At that time, an anisotropic etching method, for example, a dry etching method is employed from the upper surface of the first interlayer insulating film 512 toward the lower surface of the first interlayer insulating film 512 to thereby form the first interlayer insulating film 512. An anisotropic etching is selectively performed on the insulating material and the SiO ₂ film. The selective anisotropic etching conditions for the insulating material and the SiO ₂ film constituting the first interlayer insulating film 512 are selected so as to have a selectivity with respect to the SiN film constituting the protective insulating film 503. Yes.

  In the process of performing anisotropic etching from the upper surface of the first interlayer insulating film 512 toward the lower surface of the first interlayer insulating film 512, side etching also proceeds slightly. As a result, the shape of the side wall of the via hole to be formed shows a slight taper.

  If side etching does not proceed at all, the side wall of the via hole to be formed maintains exactly the same shape as the opening of the resist mask, and the via hole on the lower surface of the first interlayer insulating film 512 is maintained. The outer edge of the side wall is closest to the bottom of the protective insulating film 503, but the protective insulating film 503 of the resistance change element 599 and the opening of the resist mask are aligned so as to make “point contact”. .

Actually, as a result of a slight side etching, the shape of the side wall of the via hole to be formed shows a slight taper. Therefore, near the lower surface of the first interlayer insulating film 512, the side surface of the protective insulating film 503 is partially exposed on the side wall surface of the via hole, showing a slight taper. The selective anisotropic etching conditions for the insulating material and the SiO ₂ film constituting the first interlayer insulating film 512 are selected so as to have selectivity with respect to the SiN film constituting the protective insulating film 503. The “side etching” on the side surface of the protective insulating film 503 exposed on the side wall surface of the via hole does not substantially proceed. Finally, the first insulating barrier film 511 formed of the SiCN film is selectively anisotropically etched, but the side surface of the protective insulating film 503 formed of the SiN film is exposed on the side wall surface of the via hole. “Side etching” is only slightly progressed.

  Since the side surface of the protective insulating film 503 is partially exposed on the side wall surface of the via hole to be formed, when the first contact plug 504 is formed inside the via hole, as shown in FIG. The side surface of the formed first contact plug 504 comes into contact with the side surface of the insulating film 503. However, the side surface of the first electrode 502 and the side wall surface of the first contact plug 504 are electrically separated by the protective insulating film 503.

  The metal 505 of the first contact plug 504 is formed through the barrier metal 506 in the wiring groove for forming the upper copper wiring layer and the via hole for forming the first contact plug 504 that are integrally formed. A first contact plug 504 that is embedded and integrated with the upper copper wiring is formed. The metal 505 of the first contact plug 504 is a metal material mainly composed of copper, and covers the side and bottom surfaces of the wiring grooves and via holes. The barrier metal 506 has a barrier property against copper diffusion. It is a conductive film. As the barrier metal 506, a refractory metal such as tantalum, tantalum nitride, titanium nitride, or tungsten carbonitride, a nitride thereof, or a stacked film thereof can be used.

  The upper copper wiring layer thus fabricated and the upper surface of the second interlayer insulating film 516 are planarized and then covered with the second insulating barrier film 513. The second insulating barrier film 513 covering the surface of the upper copper wiring layer is a SiN film, a SiCN film, a SiC film, or the like in order to prevent copper from diffusing from the surface of the upper copper wiring layer. It is formed with a laminated structure.

  When the configuration shown in FIG. 5 is selected, the first contact plug 504 integrated with the upper copper wiring layer is formed at the closest position so as to be in contact with the protective insulating film 503 of the resistance change film 501. At that time, the lower copper wiring layer 507b and the lower copper wiring layer 507a are formed separately, and the upper copper wiring layer and the lower copper wiring layer 507a are connected via the first contact plug 504. Electrically connected.

  Further, in the configuration shown in FIG. 5, the upper copper wiring layer is formed so as to cover the upper part of the first electrode 502 that is used as the “second electrode” of the resistance change element 599 of the copper filament deposition type. Yes. This has the effect of increasing the degree of freedom of the layout position of the upper copper wiring layer with respect to the resistance change element 599 of the copper filament deposition type.

(Sixth embodiment)
A semiconductor device using the variable resistance element according to the sixth embodiment of the present invention as a nonvolatile switching element provided in a multilayer wiring layer will be described with reference to the drawings. FIG. 6 is a cross-sectional view schematically showing a configuration example of a resistance change element according to the sixth embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device.

  The variable resistance element according to the sixth embodiment shown in FIG. 6 is configured in the form of a three-terminal solid electrolyte switch. Specifically, two resistance change elements of a copper filament deposition type using a resistance change film made of a solid electrolyte are connected in a form schematically shown in FIG. 13 through a common “second electrode”. And functions as a three-terminal solid electrolyte switch.

  The resistance change element 699 shown in FIG. 6 functions as an “ion supply layer” with two copper wirings of the copper wiring 608a of the lower copper wiring layer 610a and the copper wiring 608b of the lower copper wiring layer 610b. It is used as a “first electrode” to constitute a three-terminal solid electrolyte switch. The resistance change film 603 is formed of a solid electrolyte and functions as an “ion conductive layer”. The “first electrode” 604 in contact with the upper surface of the resistance change film 603 has a laminated structure including a first upper electrode 604a and a second upper electrode 604b. Of the “first electrode” 604, the first upper electrode 604 a is in contact with the upper surface of the resistance change film 603. An upper surface protective film 607 is provided on the upper surface of the “first electrode” 604, that is, on the upper surface of the second upper electrode 604 b.

  The resistance change film 603 and the “first electrode” 604 of the resistance change element 699 are formed on the upper surface of the first insulating barrier film 601.

  The resistance change film 603 is formed on the surface of the copper wiring 608a of the lower copper wiring layer 610a and the surface of the copper wiring 608b of the lower copper wiring layer 610b through the holes opened in the first insulating barrier film 601. Is in contact with Therefore, in the opened hole portion, the lower surface of the resistance change film 603 is the “first electrode” functioning as the “ion supply layer”, that is, the copper wiring 608 a of the lower copper wiring layer 610 a and the lower copper wiring. The layer 610b is in contact with the copper wiring 608b, and the upper surface of the resistance change film 603 is in contact with the first electrode 604 functioning as the “second electrode”. Therefore, the resistance change element 699 is a three-terminal solid electrolyte switch in which two “copper filament deposited resistance change elements” are connected in parallel via the “second electrode”.

  Side surfaces of the resistance change film 603, the first upper electrode 604 a and the second upper electrode 604 b, and the upper surface protective film 607 are covered with a protective insulating film 605. As a result, at least the resistance change film 603, the side surfaces of the first upper electrode 604a and the second upper electrode 604b are covered with the protective insulating film 605, and the upper surface of the second upper electrode 604b is covered with the upper surface protective film 607. It has become.

  For example, it is preferable to select an organic polymer film containing SiO as the solid electrolyte used for forming the resistance change film 603. The first upper electrode 604a can be formed using Ru, and the second upper electrode 604b can be formed using Ta or TaN.

  The upper surface protective film 607 is preferably formed using the same material as the protective insulating film 605. The protective insulating film 605 and the upper surface protective film 607 prevent the resistance change film 603, the first upper electrode 604a, and the second upper electrode 604b from being oxidized by oxygen in the process of forming the first interlayer insulating film 602. In addition, the insulating film has a function of preventing moisture from entering. Further, when an oxide film exhibiting ion conductivity is employed as the solid electrolyte for forming the resistance change film 603, the protective insulating film 605 is an insulating film having a function of preventing desorption of oxygen from the solid electrolyte. It is. The protective insulating film 605 and the upper surface protective film 607 are preferably formed using, for example, a SiN film, a SiCN film, or the like.

  The lower copper wiring layer 610a is made of a copper wiring 608a embedded in a first wiring groove formed in the lower interlayer insulating film 611 via a barrier metal 609a. The lower copper wiring layer 610b is made of a copper wiring 608b embedded in a second wiring groove formed in the lower interlayer insulating film 611 via a barrier metal 609b. A first insulating barrier film 601 is formed on the upper surfaces of the lower copper wiring layer 610a and the lower copper wiring layer 910b. The first insulating barrier film 601 functions as a barrier film that prevents diffusion of copper from the upper surface of the lower copper wiring layer 610a and the lower copper wiring layer 610b. For the formation of the first insulating barrier film 601, it is preferable to use a SiN film, a SiCN film, or the like.

  The first interlayer insulating film 602 covers the upper surface of the first insulating barrier film 601. Further, a second interlayer insulating film 616 is formed on the first interlayer insulating film 602. At that time, the third interlayer insulating film 616 is formed on the planarized upper surface of the first interlayer insulating film 602.

  In the second interlayer insulating film 616, an upper copper wiring layer 615a and an upper copper wiring layer 615b are formed. The upper copper wiring layer 615a and the upper copper wiring layer 615b formed in the second interlayer insulating film 616 are formed through the first interlayer insulating film 602 and the first insulating barrier film 601, respectively. The first contact plugs 625a and 625b are integrally formed.

  The upper copper wiring layer 615a and the first contact plug 625a penetrate through the wiring groove formed in the second interlayer insulating film 616, the second interlayer insulating film 602, and the first insulating barrier film 601. It consists of a copper wiring 614a embedded in a via hole to be formed via a barrier metal 913a. A via hole for the first contact plug 625a formed integrally with the wiring groove for the upper copper wiring layer 615a is formed through the opening formed in the first insulating barrier film 601 through the lower copper wiring. The surface of the copper wiring 608a of the wiring layer 610a is opened.

  The upper copper wiring layer 615b and the first contact plug 625b penetrate through the wiring groove formed in the second interlayer insulating film 616, the second interlayer insulating film 602, and the first insulating barrier film 601. It consists of a copper wiring 614b embedded in a via hole to be formed via a barrier metal 613b. A via hole for the first contact plug 625b, which is formed integrally with the wiring groove for the upper copper wiring layer 615b, is formed through the opening formed in the first insulating barrier film 601 through the lower copper wiring layer 601b. The surface of the copper wiring 608b of the wiring layer 610b is opened.

  The surfaces of the upper copper wiring layer 615a and the upper copper wiring layer 615b are formed in order to prevent copper diffusion from the copper wiring 614a of the upper copper wiring layer 615a and the copper wiring 914b of the upper copper wiring layer 615b. The insulating barrier film 612 is covered. Similar to the second insulating barrier film 601, it is preferable to use a SiN film, a SiCN film, or the like for the formation of the second insulating barrier film 612.

  The barrier metal 609a of the lower copper wiring layer 610a is formed of a copper wiring 608a in order to prevent copper, which is the main component of the copper wiring 608a of the lower copper wiring layer 610a, from diffusing into the lower interlayer insulating film 611. It is the electroconductive film which has the barrier property which coat | covers the side surface and bottom face of this. The barrier metal 609b of the lower copper wiring layer 610b is formed of a copper wiring 608b to prevent copper, which is the main component of the copper wiring 608b of the lower copper wiring layer 610b, from diffusing into the lower interlayer insulating film 611. It is the electroconductive film which has the barrier property which coat | covers the side surface and bottom face of this.

  Similarly, in the barrier metal 613a of the upper copper wiring layer 615a, copper which is the main component of the copper wiring 614a of the upper copper wiring layer 615a is contained in the second interlayer insulating film 616 and the first interlayer insulating film 602. In order to prevent diffusion into the conductive film, it is a conductive film having a barrier property that covers the side surface and the bottom surface of the copper wiring 614a. In the barrier metal 613b of the upper copper wiring layer 615b, copper, which is the main component of the copper wiring 614b of the upper copper wiring layer 615b, diffuses into the first interlayer insulating film 602 in the second interlayer insulating film 616. In order to prevent this, it is a conductive film having a barrier property covering the side and bottom surfaces of the copper wiring 614b.

  The barrier metal 609a of the lower copper wiring layer 610a, the barrier metal 609b of the lower copper wiring layer 610b, the barrier metal 613a of the upper copper wiring layer 615a, and the barrier metal 613b of the upper copper wiring layer 615b are protected against copper diffusion. Conductive film having a barrier property, for example, refractory metal such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten carbonitride (WCN), nitrides thereof, or a laminate thereof A membrane is used.

In the variable resistance element according to the sixth embodiment shown in FIG. 6, the first interlayer insulating film 602 and the second interlayer insulating film 616 are formed of different insulating materials. A SiO ₂ film is used to form the first interlayer insulating film 602, and a SiOC film or a SiOCH film is used to form the second interlayer insulating film 616.

The lower interlayer insulating film 611 can be formed using a SiO ₂ film, a SiOC film, or a SiOCH film.

  As shown in FIG. 6, in the hole region opened in the first insulating barrier film 601, in addition to the lower copper wiring layer 610a and the lower copper wiring layer 610b, the lower interlayer insulating film 611 is also exposed. ing. In the step of opening holes in the first insulating barrier film 601, under the etching conditions of the SiCN film, a part of the exposed lower interlayer insulating film 611 is also etched away to form a recess. A resistance change film 603 is formed so as to fill the recess.

  The resistance change film 603 formed in the recess contacts the barrier metal 609a of the lower copper wiring layer 610a or the barrier metal 609b of the lower copper wiring layer 610b. At that time, the resistance change film 603 is sandwiched between the first electrode 604 functioning as the “second electrode” and the barrier metal 609a of the lower copper wiring layer 610a or the barrier metal 609b of the lower copper wiring layer 610b. The configuration does not function as a resistance change element of a metal filament deposition type.

  Therefore, the structure in which the resistance change film 603 is sandwiched between the first electrode 604 functioning as the “second electrode” and the copper wiring 608a of the lower copper wiring layer 610a, and the resistance change film 603 is the “second electrode”. Only the structure sandwiched between the first electrode 604 that functions as the copper wiring 608b of the lower copper wiring layer 610b functions as an independent “copper filament deposited resistance change element”. As illustrated in FIG. 6, the resistance change film 603 includes a first electrode 604 functioning as a “second electrode”, an area Sa of a portion sandwiched by the copper wiring 608 a of the lower copper wiring layer 610 a, and a resistance change. The area Sb of the portion where the film 603 is sandwiched between the first electrode 604 functioning as the “second electrode” and the copper wiring 608b of the lower copper wiring layer 610b can be set independently. In other words, the resistance change film 603 is a “copper filament composed of a portion sandwiched between the first electrode 604 functioning as the“ second electrode ”and the copper wiring 608a of the lower copper wiring layer (first copper wiring) 610a. The resistance value of the “deposition type resistance change element” in the “ON” state, the first electrode 604 in which the resistance change film 603 functions as the “second electrode”, and the lower copper wiring layer (first copper wiring) 610b The resistance value in the “ON” state of the “copper filament deposition type resistance change element” composed of the portion sandwiched between the copper wirings 608b can be set independently.

In the opening of the hole, the side wall surface of the first insulating barrier film 601 shows a taper. In order to form the tapered side wall surface, the first insulating barrier film 601 is etched using an isotropic etching method, for example, a reactive dry etching method. The reactive dry etching conditions used for isotropic etching of the first insulating barrier film 601 are selective to the copper wiring 608a and the barrier metal 609a, and the copper wiring 608b and the barrier metal 609b. A condition having is selected. On the other hand, under the selected reactive dry etching conditions, for example, the SiO ₂ film constituting the lower interlayer insulating film 611 is also slightly etched. As a result, a part of the lower interlayer insulating film 611 is also removed by etching to form a recess.

  A resistance change occurs in the opening of the hole and the upper surface of the first insulating barrier film 601 around the hole including the side wall surface of the recess to be formed and the tapered side wall surface of the first insulating barrier film 601. A solid electrolyte film used for forming the film 603 is deposited with a uniform film thickness. Therefore, the solid electrolyte film used for forming the resistance change film 603 is deposited by using an isotropic deposition method having excellent step coverage, for example, a plasma CVD method or a sputtering method. The barrier metal 609a of the lower copper wiring layer 610a and the barrier metal 609b of the lower copper wiring layer 610b that are exposed on the side wall surface of the recess have a reverse taper shape, and the side wall surface of the reverse taper shape is also solid electrolyte membrane. Covered with.

  On the upper surface of the resistance change film 603, Ru used for forming the first upper electrode 604a is deposited with a uniform film thickness. Therefore, Ru used for forming the first upper electrode 604a is deposited by using an isotropic deposition method having excellent step coverage, for example, a sputtering method. TaN used to form the second upper electrode 604b is deposited on the upper surface of the first upper electrode 604a with a uniform film thickness. Therefore, TaN used for forming the second upper electrode 604b is deposited using an isotropic deposition method having excellent step coverage, for example, a sputtering method or a plasma CVD method.

  The recess formed in the opening of the hole includes a solid electrolyte film used for forming the resistance change film 603, Ru used for forming the first upper electrode 604a, and TaN used for forming the second upper electrode 604b. In the process of sequentially depositing using an isotropic deposition method, the “tapered corner” having an inversely tapered shape gradually becomes “buried”.

  In the variable resistance element according to the sixth embodiment shown in FIG. 6, when the deposition of TaN used for forming the second upper electrode 604b is finished, a recess remains on the upper surface of the deposited TaN film. The shape of the side wall is a smooth curved surface. A SiN film used to form the upper surface protective film 607 is deposited on the upper surface of the second upper electrode 604b with a uniform film thickness. Therefore, the SiN film used for forming the upper surface protective film 607 is deposited using an isotropic deposition method having excellent step coverage, for example, a plasma CVD method or a sputtering method.

  The laminated structure composed of the resistance change film 603, the first upper electrode 604a and the second upper electrode 604b, and the upper surface protective film 607 deposited on the upper surface of the first insulating barrier film 601 is patterned, and then the laminated structure. An insulating protective film 605 is formed to cover the side surfaces of the film. A SiN film is used to form the insulating protective film 605.

Used for forming the upper surface protective film 607 and the insulating protective film 605 formed of the SiN film, and the first interlayer insulating film 602 covering the upper surface of the first insulating barrier film 601 formed of the SiCN film. The SiO ₂ film is deposited using an isotropic deposition method having excellent step coverage, for example, a plasma CVD method or a sputtering method.

At this time, the portion corresponding to the upper part of the laminated structure covered with the upper surface protective film 607 and the insulating protective film 605 in the upper surface of the SiO ₂ film used for forming the first interlayer insulating film 602 is Compared with the region corresponding to the upper part of the upper surface of the insulating barrier film 601, a convex portion is formed. Prior to the formation of the second interlayer insulating film 616, the SiO ₂ film used for forming the first interlayer insulating film 602 is planarized. Specifically, the upper surface of the deposited SiO ₂ film is subjected to a polishing process by using, for example, a CMP method to be planarized.

  An SiOC film used for forming the second interlayer insulating film 616 is formed on the upper surface of the planarized first interlayer insulating film 602 by using an isotropic deposition method such as a plasma CVD method. accumulate. The deposited SiOC film has a uniform film thickness and a flat upper surface, and is used as the second interlayer insulating film 616.

When forming a wiring groove for forming an upper copper wiring layer in the second interlayer insulating film 616, the etching conditions of the SiOC film constituting the second interlayer insulating film 616 are set according to the first interlayer insulating film 602. The conditions are such that the SiO ₂ film constituting the film has selectivity. As a result, the SiO ₂ film constituting the first interlayer insulating film 612 can be used as an etching stopper, and the bottom surface of the wiring trench for forming the upper copper wiring layer to be formed is connected to the second interlayer insulating film 616. Located at the interface with the first interlayer insulating film 602. On the other hand, prior to the formation of the wiring trench for forming the upper copper wiring layer, the second interlayer insulating film 616, the first interlayer insulating film 602, and the first insulating barrier film 601 are selectively anisotropically sequentially. The via hole is formed by reactive etching.

After the formation of the second interlayer insulating film 616, the surface of the metal 608a of the lower copper wiring layer 610a and the lower copper wiring, which are disposed close to the protective insulating film 605 of the resistance change element 699 Via holes for forming the first contact plug 625a and the first contact plug 625b reaching the surface of the metal 608b of the layer 610b are formed. At this time, a resist mask having an opening corresponding to the shape of the lowermost hole of the via hole is used, and the second interlayer insulating film 616, the first interlayer insulating film 602, and the first insulating barrier film are used. 601 is sequentially anisotropically etched selectively. At this time, an anisotropic etching method, for example, a dry etching method is employed from the upper surface of the first interlayer insulating film 602 toward the lower surface of the first interlayer insulating film 602 to thereby form the first interlayer insulating film 602. An anisotropic etching is selectively performed on the insulating material and the SiO ₂ film. The selective anisotropic etching conditions of the insulating material and the SiO ₂ film that constitute the first interlayer insulating film 602 are selected so that the SiN film that constitutes the protective insulating film 605 has selectivity. Yes.

  In the process of performing anisotropic etching from the upper surface of the first interlayer insulating film 602 toward the lower surface of the first interlayer insulating film 602, side etching also proceeds slightly. As a result, the shape of the side wall of the via hole to be formed shows a slight taper.

  If side etching does not proceed at all, the side wall of the via hole to be formed maintains exactly the same shape as the opening of the resist mask, and the via hole on the lower surface of the first interlayer insulating film 602 is maintained. The outer edge of the side wall is closest to the bottom of the protective insulating film 605, but the protective insulating film 605 of the resistance change element 699 and the opening of the resist mask are aligned so as to make “point contact”. .

Actually, as a result of a slight side etching, the shape of the side wall of the via hole to be formed shows a slight taper. Therefore, near the lower surface of the first interlayer insulating film 602, the side surface of the protective insulating film 605 is partially exposed on the side wall surface of the via hole, which shows a slight taper. As the selective anisotropic etching conditions for the insulating material and the SiO ₂ film constituting the first interlayer insulating film 602, a condition having selectivity with respect to the SiN film constituting the protective insulating film 605 is selected. The “side etching” on the side surface of the protective insulating film 605 exposed on the side wall surface of the via hole does not substantially proceed. Finally, the first insulating barrier film 601 formed of the SiCN film is selectively anisotropically etched, but the side surface of the protective insulating film 605 formed of the SiN film is exposed on the side wall surface of the via hole. “Side etching” is only slightly progressed.

  Since the side surface of the protective insulating film 605 is partially exposed on the side wall surface of the via hole to be formed, when the first contact plug 625a and the first contact plug 625b are formed inside the via hole, FIG. 6, the side surfaces of the formed first contact plug 625 a and the first contact plug 625 b are in contact with the side surfaces of the protective insulating film 605. However, the side surfaces of the first upper electrode 604a and the second upper electrode 604b and the side wall surfaces of the first contact plug 625a and the first contact plug 625b constituting the first electrode 604 are protected by the protective insulating film 605. Are electrically separated.

  The variable resistance element according to the sixth embodiment shown in FIG. 6 is configured in the form of a three-terminal solid electrolyte switch. Specifically, two resistance change elements of a copper filament deposition type using a resistance change film made of a solid electrolyte are connected in a form schematically shown in FIG. 13 through a common “second electrode”. And functions as a three-terminal solid electrolyte switch.

  The variable resistance element 699 according to the sixth embodiment illustrated in FIG. 6 uses the first electrode 604 configured by the first upper electrode 604a and the second upper electrode 604b as a common “second electrode”. The two copper wirings, ie, the copper wiring 608a of the lower copper wiring layer 610a and the copper wiring 608b of the lower copper wiring layer 610b, are each used as a “first electrode” that functions as an “ion supply layer”. One “copper filament deposition type resistance change element” is configured. At that time, the two “copper filament deposition type resistance change elements” are connected in a form schematically shown in FIG. 13 to form a three-terminal solid electrolyte switch. The “first electrode” of the two “copper filament deposition type resistance change elements”, that is, the two copper wirings of the copper wiring 608a of the lower copper wiring layer 610a and the copper wiring 608b of the lower copper wiring layer 610b, respectively, The upper copper wiring layer 615a and the upper copper wiring layer 615b are electrically connected via the first contact plug 625a and the first contact plug 625b. Therefore, a three-terminal solid electrolyte switch in which the area layout of the upper copper wiring layer 615a and the upper copper wiring layer 615b is kept small can be formed.

(Seventh embodiment)
A semiconductor device using the variable resistance element according to the seventh embodiment of the present invention as a nonvolatile switching element provided in a multilayer wiring layer will be described with reference to the drawings. 7A to 7H schematically illustrate a configuration example of a resistance change element according to the seventh embodiment of the present invention, which is used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device, and a manufacturing process thereof. FIG.

  7A to 7H show the manufacturing process, and the variable resistance element according to the seventh embodiment is configured in the form of a two-terminal solid electrolyte switch. In the manufacturing process illustrated in FIGS. 7A to 7H, semiconductor elements (not shown) constituting the semiconductor device itself are formed on the surface of the semiconductor substrate prior to the production of the multilayer wiring layer.

  7A to 7H, a semiconductor device is formed on the surface of the semiconductor device substrate 1, and a multilayer wiring layer and a nonvolatile switching element provided in the multilayer wiring layer are used. Steps A1 to A8 of the manufacturing process of the variable resistance element according to the embodiment will be described.

(Step A1)
Step A1 uses the “first electrode” functioning as the “ion supply layer” in the production of the “first wiring” corresponding to the lower wiring layer and the resistance change element shown in FIG. 7A. This is a step of forming an opening in the insulating barrier film 7 covering the surface of “1 wiring”.

First, an interlayer insulating film 2, a barrier insulating film 3, and an interlayer insulating film 4 are formed in this order on the semiconductor device substrate 1. For example, as the “insulating material used for forming the interlayer insulating film 2”, a silicon oxide film having a thickness of 300 nm is used, and as the “insulating material used for forming the barrier insulating film 3”, a SiN film having a thickness of 50 nm is used. As the insulating material used for forming the interlayer insulating film 4, a 200 nm thick SiO ₂ film is selected.

Subsequently, a wiring groove for forming a “first wiring” is formed in the interlayer insulating film 4, the barrier insulating film 3, and the interlayer insulating film 2. The wiring groove forming process
A resist mask formation processing step of forming a resist mask having openings of a predetermined pattern on the interlayer insulating film 4 by using a photolithography method;
Using the resist mask as an etching mask layer and performing anisotropic etching on the laminated film by dry etching; and an etching process step;
A resist removal processing step of removing the resist mask after forming the wiring trench by anisotropic etching is included.

  Thereafter, the metal 5 is buried in the wiring trench through the barrier metal 6 to form the “first wiring”. The metal 5 of the “first wiring” is used as an “ion supply layer”. Therefore, the metal material which has copper as a main component, for example, copper, is used. The barrier metal 6 prevents the diffusion of copper used for the metal 5. Therefore, for example, a stacked structure of TaN (film thickness 5 nm) / Ta (film thickness 5 nm) is used as the barrier metal 6.

  A barrier metal 6 having a laminated structure of TaN (film thickness 5 nm) / Ta (film thickness 5 nm) is coated on the bottom and side walls of the wiring groove with a uniform film thickness. Therefore, an isotropic deposition method, for example, an RF sputtering method is used to form a deposited film having the laminated structure on the upper surface of the interlayer insulating film 4, the bottom portion of the wiring groove, and the side wall portion. Copper used for the metal 5 uses the barrier metal 6 as an underlayer, and is formed so as to bury the inside of the wiring trench by using, for example, a plating method. Thereafter, for example, using a CMP (Chemical-Mechanical Polishing) method, the stacked structure of copper and TaN (film thickness 5 nm) / Ta (film thickness 5 nm) formed on the upper surface of the interlayer insulating film 4 is removed. The upper surface of the “first wiring” formed in the wiring groove is planarized.

  Subsequently, an insulating barrier film 7 that covers the upper surface of the “first wiring” and the upper surface of the interlayer insulating film 4 is formed. The insulating barrier film 7 prevents the diffusion of copper used for the metal 5 of the “first wiring”. Therefore, for example, a 30 nm-thick SiCN film is selected as the “insulating material used for forming the insulating barrier film 7”.

  Of the “first wiring” corresponding to the lower wiring layer, the “first wiring” used as the “first electrode” functioning as the “ion supply layer” when the variable resistance element is manufactured An opening is formed in the insulating barrier film 7 covering the surface of the metal 5 of “one wiring”.

  It should be noted that no opening is formed in the insulating barrier film 7 that covers the surface of the other “first wiring” that is not used to manufacture the variable resistance element. Therefore, when step A1 is completed, the “first wiring” corresponding to the lower wiring layer, except for some “first wirings” used for the production of the variable resistance element, is the insulating barrier film 7. It is held in a state covered with.

  In the step of forming the opening in the insulating barrier film 7 covering the surface of the metal 5 of the “first wiring”, the resist mask having the opening is used to expose the opening of the resist mask. The insulating barrier film 7 is isotropically etched by using an isotropic dry etching method, for example, a reactive dry etching method.

In the isotropic etching process of the SiCN film used as the insulating barrier film 7, CF ₄ / Ar gas flow rate = 25: 50 sccm, pressure 0.53 [Pa], source power 400 W as reactive dry etching conditions. The condition of substrate bias power of 90 W can be employed.

  By using the reactive dry etching method, the etching of the sidewall surface of the opening formed in the SiCN film proceeds. Therefore, side etching of the upper part of the SiCN film, which is covered with the resist mask, around the opening of the resist mask proceeds, and the side wall surface of the formed opening has a tapered shape. At that time, by reducing the source power or increasing the substrate bias power, the `` ionicity '' at the time of etching is improved, and the contribution of the `` reactive ion etching '' process increases. The “taper angle” of the side wall surface of the “taper shape” can be reduced.

  In order to reduce the “taper angle” of the “tapered” side wall surface by utilizing side etching to the side wall surface of the opening to be formed, the etching time is reduced when the SiCN film having a film thickness of 30 nm is etched. The time when the film can be etched by 35 nm can be set. That is, the “taper angle” of the “tapered” side wall surface can be reduced by setting the etching time to a time during which “over-etching” proceeds and increasing the side etching amount on the upper part of the SiCN film. .

  The “over-etching process” for reducing the “taper angle” of the “tapered shape” side wall surface can also be performed using the “etch-back” method.

  For example, by utilizing the “etch back” function attached to the sputtering apparatus, the substrate is heated to 350 ° C. under a reduced pressure atmosphere, and the “etching and etching” of the SiCN film exposed on the side wall surface of the opening to be formed is performed. "Back" can be performed. Specifically, in a heat chamber mounted in the sputtering apparatus, heat treatment can be performed in a reduced pressure atmosphere to perform the desired “etch back”.

It is also possible to “etch back” the SiCN film exposed on the side wall surface of the opening to be formed using an RF etching method using a non-reactive gas. Specifically, RF etching using a non-reactive gas uses Ar gas as a non-reactive gas in an RF etching chamber, Ar gas flow rate = 30 sccm, pressure 1.3 [Pa], source power It can be performed under the conditions of 290 W and substrate bias power of 130 W. At that time, when the RF etching time of the SiO ₂ film formed by the plasma CVD method is performed, the etching time of the desired SiCN film is set by setting the ₂ nm SiO ₂ film to an etching time. Is achieved.

  By making the side wall surface of the opening formed in the SiCN film into a “tapered shape” having a small “taper angle”, in the next step A2, the opening is provided with a metal Ti film, a solid electrolyte film 9, and a first When a laminated structure including the upper electrode 10 and the second upper electrode 11 is formed, “step coverage” on the side wall surface of the opening can be improved.

(Step A2)
Step A2 includes a titanium oxide film 8 for preventing oxidation of the surface of the metal (copper wiring) 5 of the “first wiring” and a solid electrolyte film used as an “ion conductive layer” in the production of the resistance change element shown in FIG. 7B. 9. Step of sequentially forming the first upper electrode 10 and the second upper electrode 11 constituting the first electrode functioning as the “second electrode” on the upper surface of the insulating barrier film 7 and the formed opening. It is.

  On the surface of the metal (copper) 5 of the “first wiring”, the “tapered” sidewall surface of the opening, and the upper surface of the insulating barrier film 7 exposed in the opening formed in the insulating barrier film 7 A 1 nm-thick metal Ti film is deposited by DC sputtering. The metal Ti film functions as an “oxidation sacrificial layer” that prevents the surface of the metal (copper) 5 of the “first wiring” from being oxidized during the process of forming the solid electrolyte film 9.

  In the resistance change element according to the seventh embodiment, the solid electrolyte membrane 9 used as the “ion conductive layer” is a “porous polymer membrane” made of a porous polymer mainly composed of silicon, oxygen, and carbon. Forming. A “porous polymer film” made of a porous polymer mainly composed of silicon, oxygen, and carbon is, for example, an RF plasma method using, as a raw material, a cyclic siloxane type organic monomer disclosed in International Publication No. 2011/058947. Is deposited by a “polymerization reaction” of the organic monomer. In the process of “polymerization reaction” of the organic monomer by the RF plasma method, oxygen plasma is generated due to decomposition of the organic monomer. The generated oxygen plasma acts on the metal Ti film and is converted into the titanium oxide film 8.

  As a result, a “porous polymer film” made of a porous polymer mainly composed of silicon, oxygen, and carbon is deposited on the titanium oxide film 8 converted from the metal Ti film. In the deposition process of the “porous polymer film” by the RF plasma CVD method, the deposition conditions are RF power 50 to 300 W, temperature 350 ° C., mixed gas with He, pressure 1.0 to 6.0 [Torr]. You can choose from a range.

  When manufacturing the variable resistance element according to the seventh embodiment, specifically, when using a 12-inch plasma CVD reactor, the conditions of He gas flow rate = 500 sccm, pressure 400 [Pa], and RF power 80 W are selected. , “Porous polymer membrane” can be formed. Using the above deposition conditions, a “porous polymer film” having a film thickness of 5 nm is deposited using a cyclic siloxane type organic monomer as a raw material, and used for forming the solid electrolyte film 9.

Actually, after adopting the above deposition conditions and depositing a “porous polymer film” having a film thickness of 5 nm using a cyclic siloxane type organic monomer as a raw material, a cross-sectional TEM (Transmission Electron Microscope) observation is performed. As a result, it was confirmed that a titanium oxide film having a thickness of 2.0 nm was formed from a metal Ti film having a thickness of 1 nm. The density of metallic Ti is 4.506 g / cm ³ , but the density of crystalline titanium oxide (IV), for example, anatase TiO ₂ is 3.84 g / cm ³ , rutile TiO _2. The density of is 4.26 g / cm ³ . In consideration of this point, a 2.0 nm thick titanium oxide film formed from a 1 nm thick metal Ti film is assumed to be an anatase type titanium (IV) oxide film.

  Depending on the apparatus configuration of the RF plasma CVD apparatus used and the deposition conditions, the oxidizing power by oxygen plasma may exceed the oxidizing power in the above-described deposition conditions. In that case, the surface of the metal (copper) 5 of the “first wiring” can be prevented from being oxidized by increasing the thickness of the metal Ti film that functions as the “oxidation sacrificial layer”.

  Conversely, when the deposition conditions that suppress the generation of oxygen plasma, for example, the RF power is lowered or the raw material flow rate is increased, the generation of oxygen plasma accompanying the decomposition of the raw material organic monomer is suppressed. In this case, even if the thickness of the metal Ti film that functions as the “oxidation sacrificial layer” is reduced, the oxidation of the surface of the metal (copper) 5 of the “first wiring” can be suppressed.

  Furthermore, when the deposition conditions that sufficiently suppress the generation of oxygen plasma can be selected, the “first wiring” metal (during the “porous polymer film” deposition process, even if the deposition of the metal Ti film is omitted. The oxidation of the surface of (copper) 5 does not proceed substantially. That is, when the surface of the metal (copper) 5 is covered with the thin film of the “porous polymer film” while the oxidation of the surface of the metal (copper) 5 of the “first wiring” does not proceed substantially, The oxygen plasma can no longer act on the surface of the metal (copper) 5. As a result, even if the deposition of the metal Ti film is omitted, the oxidation of the surface of the metal (copper) 5 of the “first wiring” does not substantially proceed during the deposition process of the “porous polymer film”.

  After completing the deposition process of “porous polymer film” and forming the titanium oxide film 9 and the solid electrolyte film 9, the first upper electrode 10 and the second upper electrode 11 are formed on the solid electrolyte film 9. They are formed in this order. The first upper electrode 10 in contact with the upper surface of the solid electrolyte membrane 9 functions as a “second electrode” of the resistance change element. For example, a Ru film having a thickness of 10 nm is used for manufacturing the first upper electrode 10. The second upper electrode 11 covers the upper surface of the first upper electrode 10, and “etching stop layer” is formed in the etching process for forming a hole in the SiN film used for forming the upper surface protective film 12 in the via hole forming process described later. Function as. Therefore, for example, a Ta film having a film thickness of 25 nm is used for manufacturing the second upper electrode 11.

The “porous polymer film” made of a porous polymer mainly composed of silicon, oxygen, and carbon used as the solid electrolyte film 9 induces desorption of contained oxygen when held at a high temperature under reduced pressure. There is a case. When the desorbed oxygen reacts with Ru used to form the first upper electrode 10, an interface film layer of “RuO ₂ ” is formed at the interface between the first upper electrode 10 and the solid electrolyte film 9.

An interface coating layer of “RuO ₂ ” is formed at the interface between the first upper electrode 10 functioning as the “second electrode” of the copper filament deposition type resistance change element and the solid electrolyte film 9 functioning as the “ion conductive layer”. Is formed, it inhibits “precipitation of copper atoms”. Accordingly, a Ru film having a thickness of 10 nm is selected by selecting a deposition condition that does not induce desorption of oxygen contained in a “porous polymer film” made of a porous polymer mainly composed of silicon, oxygen, and carbon. Film deposition is performed. For example, the DC sputtering method is applied, the conditions of DC power 0.2 kW, Ar gas, and pressure 0.27 [Pa] are selected using Ru as a target, and the Ru film is deposited at room temperature. For the deposition of the Ta film used for the production of the second upper electrode 11, for example, the DC sputtering method is applied, and the conditions of DC power 0.2 kW, Ar gas, and pressure 0.27 [Pa] are selected using Ta as a target And at room temperature.

  In the forming process of the titanium oxide film 8 having a thickness of 2.0 nm, the solid electrolyte film 9 having a thickness of 5 nm, the first upper electrode 10 having a thickness of 10 nm, and the second upper electrode 11 having a thickness of 25 nm, all are isotropic. A simple deposition method is adopted. Therefore, as shown in FIG. 7B, the bottom surface of the opening formed in the insulating barrier film 7 having a thickness of 30 nm, the “tapered” side wall surface of the opening, and the upper surface of the insulating barrier film 7 are covered. A laminated structure having a total film thickness of 42 nm is formed uniformly.

(Step A3)
Step A3 is the second upper electrode of the first upper electrode 10 and the second upper electrode 11 constituting the first electrode functioning as the “second electrode” when the variable resistance element shown in FIG. 7C is manufactured. 11, a SiN film deposition process, and a titanium oxide film 8, a solid electrolyte film 9, a first upper electrode 10, a second upper electrode 11, and an upper surface protective film 12 used for forming an upper surface protective film 12 provided on the upper surface of This patterning step includes a step of depositing a SiO ₂ film (hard mask film) 13 used as a hard mask.

A SiN film having a film thickness of 30 nm, which is used for forming the upper surface protective film 12, is deposited on the upper surface of the Ta film used for manufacturing the second upper electrode 11. Thereafter, an SiO ₂ film (hard mask film) 13 having a thickness of 200 nm is deposited for use as a hard mask in the patterning step.

The SiN film having a thickness of 30 nm used for forming the upper surface protective film 12 can be deposited by using a plasma CVD method using SiH ₄ and N ₂ as source gases. At that time, the film formation temperature in the plasma CVD method can be selected from a range of 200 ° C. to 400 ° C., but is selected to 200 ° C., and the SiN film is formed using high-density plasma. Yes. As a result of selecting this deposition condition, isotropic deposition is performed, and the film of the SiN film deposited on the bottom surface of the opening, the “tapered” sidewall surface of the opening, and the insulating barrier film 7 is deposited. The thickness is substantially equal.

A 200 nm thick SiO ₂ film (hard mask film) 13 used as a hard mask film is also deposited by plasma CVD. Although the growth temperature is selected to be 200 ° C., the deposited film thickness is 200 nm, which is much thicker than the step 30 nm between the bottom surface region of the opening and the upper region of the insulating barrier film 7, and therefore, as shown in FIG. In addition, the step is buried, and the thickness of the bottom region of the opening is larger than the thickness of the region above the insulating barrier film 7.

(Step A4)
Step A4 uses a hard mask made of SiO ₂ film (hard mask film) 13 to form the upper surface protective film 12, the second upper electrode 11, the first upper electrode 10, the solid electrolyte film 9, and the titanium oxide film 8, It comprises a step of sequentially performing selective etching and patterning, and then a step of selectively etching away the SiO ₂ film (hard mask film) 13 used as a hard mask. Finally, when the patterning of the upper surface protective film 12, the second upper electrode 11, the first upper electrode 10, the solid electrolyte film 9, and the titanium oxide film 8 is completed, the stacked structure shown in FIG. To be formed in the opening region.

_{On the} hard mask made of the SiO ₂ film (hard mask film) 13, a photoresist mask (not shown) matching the patterning shape of the resistance change element portion is formed. Using the photoresist mask, the SiO ₂ film (hard mask film) 13 is dry-etched until the surface of the SiN film used for forming the upper surface protective film 12 appears. Thereafter, oxygen plasma ashing and organic peeling are performed to remove the photoresist mask. The SiO ₂ film (hard mask film) 13 patterned in accordance with the patterning shape of the variable resistance element portion is used as a hard mask in the subsequent patterning process.

In the dry etching process of the SiO ₂ film (hard mask film) 13, a dry etching method in which side etching does not proceed, that is, an anisotropic dry etching method is employed. For example, a general parallel plate type dry etching apparatus can be used for the dry etching process of the SiO ₂ film (hard mask film) 13. At this time, as the dry etching conditions for the SiO ₂ film (hard mask film) 13, a condition having selectivity with respect to the SiN film used for forming the upper surface protective film 12 is selected. For example, dry etching of the SiO ₂ film (hard mask film) 13 is performed under the conditions of a gas flow rate of CF ₄ = 140 sccm, a pressure of 6.6 [Pa], a source power of 1200 W, and a substrate bias power of 700 W. When the dry etching of the SiO ₂ film (hard mask film) 13 having a thickness of 200 nm is completed, the etching is preferably stopped on the upper surface of the SiN film having a thickness of 30 nm. In order to avoid the residue of the SiO ₂ film (hard mask film) 13, an etching time during which a part of the 30 nm-thickness SiN film is also etched can be selected.

  When removing the photoresist mask, an oxygen plasma ashing method is used. The upper surface of the second upper electrode 11, the first upper electrode 10, and the ion conductive layer 9, which are covered with the SiN film 12, are subjected to oxygen plasma. There is no exposure.

After removing the photoresist mask, the patterned SiO ₂ film (hard mask film) 13 is used as a hard mask to protect the upper surface protective film 12, the second upper electrode 11, the first upper electrode 10, and the solid electrolyte film 9 The titanium oxide film 8 is sequentially selectively etched and patterned.

A dry etching method in which side etching does not proceed, that is, an anisotropic dry etching method is adopted even in a dry etching process of a 30 nm-thickness SiN film used for forming the upper surface protective film 12. In addition, an etching condition having selectivity is selected for the metal Ta film having a film thickness of 25 nm used for forming the second upper electrode 11. For example, a parallel plate type dry etching apparatus is used, and dry etching of the SiN film 12 is performed with CF ₄ / Ar gas flow rate = 25/50 sccm, pressure 0.53 [Pa], source power 400 W, and substrate bias power 90 W. Can be done under conditions.

A dry etching method in which side etching does not proceed, that is, an anisotropic dry etching method is adopted even in the dry etching process of the metal Ta film having a film thickness of 25 nm used for forming the second upper electrode 11. Further, an etching condition having selectivity is selected for the metal Ru film having a film thickness of 10 nm used for forming the first upper electrode 10. For example, a parallel plate type dry etching apparatus is used, and dry etching of a metal Ta film with a film thickness of 25 nm is performed with a Cl ₂ gas flow rate = 50 sccm, a pressure of 0.53 Pa, a source power of 400 W, and a substrate bias power of 60 W. Can be done under conditions.

A dry etching method in which side etching does not proceed, that is, an anisotropic dry etching method is employed even in a dry etching process of a 10 nm-thick metal Ru film used for forming the first upper electrode 10. Further, an etching condition having selectivity is selected for the “porous polymer film” having a film thickness of 5 nm used for forming the solid electrolyte film 9. For example, a parallel plate type dry etching apparatus is used, and dry etching of a metal Ru film having a thickness of 10 nm is performed by using a Cl ₂ / O ₂ gas flow rate = 5/40 sccm, a pressure of 0.53 [Pa], and a source power of 900 W. The substrate bias power can be 100 W.

Side etching does not proceed even in the dry etching step of the “porous polymer film” having a thickness of 5 nm and the dry etching step of the titanium oxide film 8 having a thickness of 2.0 nm, which are used for forming the solid electrolyte membrane 9. A dry etching method, that is, an anisotropic dry etching method is employed. Further, etching conditions having selectivity are selected for the SiCN film having a thickness of 30 nm, which is used for forming the lower insulating barrier film 7. For example, dry etching of a “porous polymer film” having a film thickness of 5 nm using a parallel plate type dry etching apparatus is performed by Cl ₂ / CF ₄ / Ar gas flow rate = 45/15/15 sccm, pressure 1.3 [Pa], source power 800 W, substrate bias power 60 W. The dry etching of the 2.0 nm-thick titanium oxide film 8 is performed under the conditions of Cl ₂ / O ₂ gas flow rate = 20/160 sccm, pressure 0.5 [Pa], source power 600 W, and substrate bias power 160 W. it can. That is, by intentionally using chlorine gas (Cl ₂ ), the selectivity to the SiCN film having a film thickness of 30 nm, which is used for forming the lower insulating barrier film 7, is increased, so that the sub-trench or the like Occurrence is suppressed. When the patterning of the solid electrolyte film 9 and the titanium oxide film 8 constituting the “ion conductive layer” is finished, the “porous” film having a film thickness of 5 nm is formed on the upper surface of the insulating barrier film 7 excluding the resistance change element forming region. The high-quality polymer film ”and the 2.0 nm-thick titanium oxide film 8 do not remain.

After the above series of patterning steps is completed, the patterned SiO ₂ film (hard mask film) 13 used as a hard mask is selectively removed by etching. The film thickness of the patterned SiO ₂ film (hard mask film) 13 is slightly larger than the film thickness in the resistance change element forming region, particularly in the central region of the opening. The selective etching of the SiO ₂ film (hard mask film) 13 is performed under a condition having high selectivity with respect to the SiCN film used for forming the exposed insulating barrier film 7.

At that time, in the region where the upper surface of the insulating barrier film 7 is exposed, the SiCN film used for forming the insulating barrier film 7 may be slightly etched but is exposed. The conditions for selective etching of the SiO ₂ film (hard mask film) 13 are selected so that the film thickness of the SiCN film is in the range of _{20 to 30} nm.

The film thickness of the patterned SiO ₂ film (hard mask film) 13 is slightly larger than the film thickness in the resistance change element forming region, particularly in the central region of the opening. Therefore, while the SiO ₂ film (hard mask film) 13 in the central region of the opening is removed by etching, in the surrounding region, the surface of the SiN film used for forming the upper surface protective film 12 is exposed for a certain period of time. Become. At that time, the SiN film exposed for a certain period of time may be subjected to slight etching, but the SiO ₂ film so that the thickness of the etched SiN film is at least in the range of _{20 to 30} nm. Conditions for selective etching of (hard mask film) 13 are selected.

In order to maintain high selectivity with respect to the SiCN film and the SiN film, for example, the selective etching of the SiO ₂ film (hard mask film) 13 is performed by CF ₄ gas flow rate = 140 sccm, pressure 6.6 [Pa], and source power 1200 W. The substrate bias power can be 700 W.

When the selective etching of the SiO ₂ film (hard mask film) 13 used as the hard mask is completed, the patterned upper surface protective film 12, the second upper electrode 11, the first upper electrode 10, the solid electrolyte shown in FIG. A laminated structure including the film 9 and the titanium oxide film 8 is formed in the opening region where the variable resistance element is manufactured. The angle formed between the side wall surface of the laminated structure and the upper surface of the underlying insulating barrier film 7 is approximately 90 °.

(Step A5)
Step A5, as shown in FIG. 7E, the upper surface and the side wall surface of the laminated structure comprising the patterned upper surface protective film 12, the second upper electrode 11, the first upper electrode 10, the solid electrolyte film 9, and the titanium oxide film 8, In addition, this is a step of depositing a protective insulating film 14 that covers the upper surface of the insulating barrier film 7 exposed around the periphery. For example, a 30 nm-thickness SiN film is used as the protective insulating film 14.

The protective insulating film 14 uses an isotropic deposition method so as to cover the upper surface and the side wall surface of the laminated structure and the upper surface of the insulating barrier film 7 exposed in the periphery with a uniform film thickness. Is deposited. For example, a SiN film having a thickness of 30 nm used as the protective insulating film 14 is formed using a plasma CVD method, using SiH ₄ and N ₂ as source gases, using a high-density plasma at a substrate temperature of 200 ° C. be able to. Since a reducing gas such as NH ₃ or H ₂ is not used, it is composed of a porous polymer mainly composed of silicon, oxygen, and carbon, which is used as the solid electrolyte film 9 in the film forming gas stabilization process immediately before film formation. contained in the "porous polymeric membrane" in, H acts on oxygen (O), in avoiding the occurrence of the reaction that is converted to H ₂ O.

  The SiN film used as the protective insulating film 14 is excellent in adhesion with the SiCN film used as the insulating barrier film 7 and the SiN film used as the upper surface protective film 12. Specifically, Si—N bonds are formed at the interface with the SiN film deposited on the surface of the SiCN film used as the insulating barrier film 7, and the two can be integrated. Further, Si—N bonds are also formed at the interface between the SiN film used as the upper surface protective film 12 and the SiN film deposited on the upper and end surfaces of the SiN film.

  Therefore, the protective insulating film 14 covering the side wall surface of the laminated structure is integrated with the SiCN film used as the insulating barrier film 7 and the SiN film used as the upper surface protective film 12. It effectively prevents moisture penetration, oxygen penetration, or oxygen detachment from the side wall surface of the structure. Therefore, it is possible to improve the yield and reliability of the resistance change element finally manufactured.

(Step A6)
In step A6, as shown in FIG. 7F, the protective insulating film 14 covering the side wall surface of the laminated structure is left, the upper surface of the upper surface protective film 12, and the insulating barrier film 7 around the laminated structure are formed. This is a step of removing the SiN film covering the upper surface by etching.

At that time, the etching of the SiN film covering the side wall surface of the laminated structure does not proceed, and the upper surface of the upper surface protective film 12 and the upper surface of the insulating barrier film 7 around the laminated structure are covered. In order to selectively etch only the film, an anisotropic dry etching method is employed. The anisotropic dry etching of the SiN film covering the upper surface of the upper surface protective film 12 and the upper surface of the insulating barrier film 7 around the laminated structure uses a parallel plate type dry etching apparatus, for example, CF ₄ / Ar gas flow rate = 25/50 sccm, pressure 0.53 [Pa], source power 400 W, substrate bias power 90 W.

  Instead of the above-mentioned “anisotropic dry etching” method, an “anisotropic etch-back” method is adopted, and the upper surface of the upper protective film 12 and the insulating barrier film 7 around the laminated structure are formed. It is also possible to use a method of selectively etching back the SiN film covering the upper surface and leaving the SiN film covering the side wall surface of the laminated structure.

  For example, etch back can be performed by introducing Ar gas into a growth reactor and applying a substrate bias using a plasma CVD apparatus. At that time, if it is possible to set conditions for the progress of “anisotropic etchback”, the upper surface of the upper surface protective film 12 and the upper surface of the insulating barrier film 7 around the laminated structure are covered. It is possible to selectively etch back the SiN film and leave the SiN film covering the side wall surface of the laminated structure.

In step A7, which will be described later, as shown in FIG. 7F, after removing the SiN film except for the SiN film covering the side wall surface of the laminated structure, the second interlayer insulating film is utilized by using the plasma CVD method. A SiO ₂ film to be used for the fabrication is deposited. It is possible to perform "anisotropic etchback" by introducing Ar gas into the growth reactor and applying a substrate bias using a plasma CVD apparatus used for depositing the SiO ₂ film. If so, it is possible to obtain the form shown in FIG. 7F by performing an “anisotropic etchback” process prior to the deposition of the SiO ₂ film. In that case, there is no need to purchase a dedicated “parallel plate type dry etching apparatus” used in the “anisotropic dry etching” process of step A6, and the cost of manufacturing equipment required for manufacturing the resistance change element is reduced. To contribute. It also contributes to reducing the product cost of semiconductor devices equipped with variable resistance elements.

(Step A7)
Step A7, as shown in FIG. 7G, covers the upper surface of the laminated structure upper surface protective film 12, the protective insulating film 14 covering the side wall surface of the laminated structure, and the upper surface of the insulating barrier film 7 around the laminated structure, This is a step of forming the first interlayer insulating film 15 that has been subjected to planarization. The first interlayer insulating film 15 is configured to be in direct contact with the insulating barrier film 7.

In the variable resistance element according to the seventh embodiment, the upper surface protective film 12 having a laminated structure, the protective insulating film 14 covering the side wall surface of the laminated structure is formed using a SiN film, and the insulating barrier film 7 is On the other hand, the first interlayer insulating film 15 is formed using a silicon oxide (SiO ₂ ) film.

This is an isotropic deposition method so as to cover the upper surface protective film 12 of the laminated structure, the protective insulating film 14 covering the sidewall surface of the laminated structure, and the upper surface of the insulating barrier film 7 around the laminated structure. A silicon oxide film is deposited using a plasma CVD method (not shown). The outer edge portion of the laminated structure formed on the upper surface of the insulating barrier film 7 has a step Δh ₁ of (2.0 nm + 5 nm + 10 nm + 20 nm + 30 nm) = 67.0 nm with respect to the upper surface of the insulating barrier film 7. The central portion of the laminated structure formed in the opening has a height Δh _{2 of} (2.0 nm + 5 nm + 10 nm + 20 nm + 30 nm−30 nm) = 37.0 nm with reference to the upper surface of the insulating barrier film 7. The thickness of the silicon oxide film deposited on the central portion of the laminated structure, the outer edge portion of the laminated structure, and the upper surface of the surrounding insulating barrier film 7 having a difference in height is at least 5 of the step Δh ₁ . Double, for example, about 450 nm is selected. At this time, as the thickness of the step increases, the step of filling gradually progresses. Therefore, the difference in height (step) remaining on the upper surface of the deposited silicon oxide film is reduced, but the planarization is not performed. Not complete.

  Therefore, the surface of the deposited silicon oxide film is subjected to a planarization process, for example, a polishing process using a CMP method.

When a silicon oxide film having a film thickness of about 450 nm is deposited using the plasma CVD method, for example, the conditions used for depositing the SiO ₂ film (hard mask film) 13 in step A3 can be employed.

  In the flattening process on the surface of the deposited silicon oxide film, for example, a polishing process using a CMP method, the polishing amount is set to about 300 nm for the silicon oxide film having a film thickness of about 450 nm, and the silicon after the polishing process is set. The thickness of the oxide film can be adjusted to 150 nm on the upper surface portion of the insulating barrier film 7.

  In the polishing process of the silicon oxide film using the CMP method, polishing can be performed using a general colloidal silica or ceria-based slurry as an abrasive.

(Step A8)
In step A8, as shown in FIG. 7H, a second interlayer insulating film 16 and a third interlayer insulating film 17 are formed on the upper surface of the first interlayer insulating film 15 made of the silicon oxide film subjected to the planarization process. And “second wiring” corresponding to the upper wiring layer formed in the second interlayer insulating film 16 and the third interlayer insulating film 17 stacked on the first interlayer insulating film 15. And a step of forming a “plug” formed in the first interlayer insulating film 15 and integrated with the “second wiring”.

In the resistance change element according to the seventh embodiment, a 150 nm-thickness silicon oxide (SiO ₂ ) film is used for the first interlayer insulating film 15, while the second interlayer insulating film 16 For example, a SiOC film with a thickness of 150 nm is used, and a SiO ₂ film with a thickness of 100 nm is used for the third interlayer insulating film 17.

Both the SiOC film used for forming the second interlayer insulating film 16 and the SiO ₂ film used for forming the third interlayer insulating film 17 can be deposited using the plasma CVD method. .

When depositing the SiOC film using the plasma CVD method, for example, the deposition conditions disclosed in Japanese Patent Application Laid-Open No. 2004-221275 can be employed. When depositing the SiO ₂ film using the plasma CVD method, for example, the conditions used for depositing the SiO ₂ film (hard mask film) 13 in step A3 can be employed.

  The “plug” integrated with the “second wiring” is in contact with the upper surface of the copper wiring 5 of the “first wiring” through the opening provided in the insulating barrier film 7 and changes in resistance with the “second wiring”. The “first wiring” functioning as the “first electrode” of the element is electrically connected.

  A dual damascene via-first method is applied to manufacture the “plug” integrated with the “second wiring”.

  First, a “plug” is formed at a position corresponding to the upper surface of the metal (copper wiring) of the “first wiring” corresponding to the lower wiring layer and the upper portion of the electrical contact portion adjacent to the protective insulating film 14 of the resistance change element. A resist mask having an opening corresponding to the shape of the bottom of the via hole used for forming the via hole is formed on the upper surface of the third interlayer insulating film 17. Using the resist mask, the third interlayer insulating film 17, the second interlayer insulating film 16, and the first interlayer insulating film 15 are anisotropically etched in order by a dry etching method to obtain a third interlayer insulating film. A via hole that penetrates the insulating film 17, the second interlayer insulating film 16, and the first interlayer insulating film 15 and reaches the upper surface of the insulating barrier film 7 that covers the surface of the metal (copper wiring) 5 of the “first wiring”. Form.

After removing the resist mask used for forming the via hole, a resist mask having an opening corresponding to the pattern of the wiring groove for forming the “second wiring” is formed on the upper surface of the third interlayer insulating film 17. Form. Using the resist mask, the third interlayer insulating film 17 and the second interlayer insulating film 16 are anisotropically etched stepwise by a dry etching method. In “stepwise dry etching”, the etching condition of the SiOC film forming the second interlayer insulating film 16 is selected to have a selectivity with respect to the SiO ₂ film. As a result, the first interlayer insulating film 15 made of the SiO ₂ film functions as an etching stopper layer in the etching process of the SiOC film forming the second interlayer insulating film 16. Further, in the etching process of the SiOC film forming the second interlayer insulating film 16, the progress of the side etching on the side wall surface of the third interlayer insulating film 17 made of the SiO ₂ film is suppressed. As a result, a wiring trench for forming the “second wiring” 18 is formed by “stepwise dry etching” of the third interlayer insulating film 17 and the second interlayer insulating film 16.

The resist mask used for forming the wiring trench is removed. Thereafter, a condition having selectivity with respect to the SiOC film and the SiO ₂ film is selected, and the insulating barrier film 7 made of the SiCN film exposed to the bottom of the via hole is dry-etched, and “ The surface of the metal (copper wiring) 5 of the “first wiring” is exposed.

  A metal 18a is buried in a via hole integrated with the formed wiring groove via a barrier metal 18b to form a “plug” integrated with the “second wiring”. For the metal 18a used for forming the “plug” integrated with the “second wiring” corresponding to the upper wiring layer, a metal material containing copper as a main component, for example, copper is used. The barrier metal 18b prevents copper diffusion. Therefore, for example, a stacked structure of TaN (film thickness 5 nm) / Ta (film thickness 5 nm) is used as the barrier metal 18b.

  A barrier metal 18b having a laminated structure of TaN (film thickness 5 nm) / Ta (film thickness 5 nm) is coated with a uniform film thickness on the side wall and bottom of the via hole integrated with the wiring groove. Therefore, by using an isotropic deposition method, for example, RF sputtering, the deposited film having the laminated structure is formed on the sidewall of the via hole integrated with the upper surface of the third interlayer insulating film 17 and the wiring trench. Form on the bottom and bottom. Copper used for the metal 18a uses the barrier metal 18b as an underlayer, and is formed so as to bury the inside of the via hole integrated with the wiring groove by using, for example, a plating method. Thereafter, for example, using a CMP (Chemical-Mechanical Polishing) method, a laminated structure of copper and TaN (film thickness 5 nm) / Ta (film thickness 5 nm) formed on the upper surface of the third interlayer insulating film 17 is formed. The upper surface of the “second wiring” formed in the wiring trench is flattened by removing.

After the formation of the third interlayer insulating film 17, a via hole for forming a “plug” is formed. At this time, a resist mask having an opening corresponding to the shape of the lowermost hole of the via hole is used, and the third interlayer insulating film 17, the second interlayer insulating film 16, and the first interlayer insulating film 15 are used. Are sequentially anisotropically etched. At this time, an anisotropic etching method, for example, a dry etching method is employed from the upper surface of the first interlayer insulating film 15 toward the lower surface of the first interlayer insulating film 15 to thereby form the first interlayer insulating film 15. An anisotropic etching is selectively performed on the insulating material and the SiO ₂ film. The selective anisotropic etching conditions for the insulating material and SiO ₂ film constituting the first interlayer insulating film 15 are selected so as to be selective with respect to the SiN film constituting the protective insulating film 14. Yes.

  In the process of performing anisotropic etching from the upper surface of the first interlayer insulating film 15 toward the lower surface of the first interlayer insulating film 15, side etching also proceeds slightly. As a result, the shape of the side wall of the via hole to be formed shows a slight taper.

Thereafter, in order to produce a wiring trench for forming the “second wiring”, the third interlayer insulating film 17 and the second interlayer insulating film 16 are made of SiO ₂ film when “stepwise dry etching” is performed. Even in the dry etching process of the third interlayer insulating film 17, side etching slightly proceeds on the side wall of the via hole.

  If side etching does not proceed at all, the side wall of the via hole to be formed maintains the same shape as the shape of the opening of the resist mask, and the via hole on the lower surface of the first interlayer insulating film 15 is maintained. The outer edge of the side wall is closest to the bottom of the protective insulating film 14, but the protective insulating film 14 and the opening of the resist mask are aligned so as to make “point contact”.

Actually, as a result of a slight side etching, the shape of the side wall of the via hole to be formed shows a slight taper. Therefore, near the lower surface of the first interlayer insulating film 15, the side surface of the protective insulating film 14 is partially exposed on the side wall surface of the via hole, showing a slight taper. Insulating material constituting first interlayer insulating film 15 and third interlayer insulating film 17, selective anisotropic etching conditions for SiO ₂ film, insulating material constituting second interlayer insulating film 17, SiOC As a selective anisotropic etching condition of the film, a condition having selectivity with respect to the SiN film constituting the protective insulating film 14 is selected, and the side surface of the protective insulating film 14 exposed on the side wall surface of the via hole is exposed. The “side etching” to the substrate does not proceed substantially. Finally, the first insulating barrier film 7 formed of the SiCN film is selectively anisotropically etched, but is exposed to the side wall surface of the via hole, and the side surface of the protective insulating film 14 formed of the SiN film “Side etching” is only slightly progressed.

  Since the side surface of the protective insulating film 14 is partially exposed on the side wall surface of the via hole to be formed, when a “plug” is formed inside the via hole, as shown in FIG. 7H, the protective insulating film 14 The side wall surface of the formed “plug” is in contact with the side surface of. However, the side surfaces of the first upper electrode 10 and the second upper electrode 11 and the side wall surface of the “plug” constituting the first electrode are electrically separated by the protective insulating film 14.

  In addition, the formation method of the protective insulating film employ | adopted with the resistance change element concerning this invention can be confirmed from the state after manufacture. Specifically, the cross section of the device of the product adopting the variable resistance element is observed with a TEM to confirm that the variable resistance element is formed in the multilayer wiring layer. Furthermore, it is confirmed by cross-sectional TEM observation that a resistance change film constituting the resistance change element or a protective insulating film is formed on the side surface of the electrode. Further, it is confirmed that the protective insulating film does not extend in the horizontal direction, and it is confirmed that the protective insulating film is not used as an interlayer insulating film. Furthermore, in addition to TEM, a protective insulating film is obtained by performing composition analysis such as EDX (Energy Dispersive X-ray Spectroscopy), EELS (Electron Energy-Loss Spectroscopy). It is possible to confirm the insulating material used as

  Specifically, when the resistance change element formed on the copper wiring is a switching element using a resistance change film made of a solid electrolyte, the solid electrolyte film functioning as the “ion conductive layer” is oxygen, Alternatively, it can be specified whether the film contains carbon. When the variable resistance film constituting the variable resistance element is a phase change film or a variable resistance element using a magnetic material, the element is used to determine whether the material described in this specification is used. Judgment is made by analyzing the composition of the cross section. In addition, when confirming that the protective insulating film is formed on the side surface of the laminated structure constituting the variable resistance element and identifying whether it is a SiN film, it is preferable to perform the composition analysis by surface analysis. . Further, it is possible to identify from the cross-sectional structure that the first interlayer insulating film and the second interlayer insulating film located above the first interlayer insulating film have a direct contact with each other.

  In the preferred embodiments and embodiments described above, ReRAM using a “copper filament deposition type resistance change element” that employs a solid electrolyte layer as the resistance change film, or a resistance change film made of a metal oxide is employed. The present invention is described in detail for the case of constructing a defective ReRAM. Instead of the above-described configuration, a resistance change element employing a film other than a solid electrolyte or metal oxide as the resistance change film, for example, a resistance change element using a magnetic material, an MRAM or a spin element, or a phase change element The present invention may be applied to a configuration of a PRAM or the like that employs a variable resistance change layer (GST).

  The preferred embodiments and the embodiments have been exemplified to describe the variable resistance element and the method for manufacturing the variable resistance element according to the present invention. However, these embodiments and the embodiments are technical It is an example selected for the purpose of specifically explaining the principle, and the technical scope of the present invention is not meant to be limited to these specific examples.

  For example, a technique applied to a semiconductor device having a CMOS circuit, which is a field of use that is the background of the invention made by the present inventor, will be described in detail, and a mode in which a resistance change element is formed on a copper wiring on a semiconductor substrate will be described. did. The technical idea of the present invention is not limited to the “form in which the resistance change element is formed on the copper wiring on the semiconductor substrate”. The technical idea of the present invention is a memory circuit such as DRAM (Dynamic RAM), SRAM (Static RAM), flash memory, FRAM (Ferro Electric RAM), MRAM (Magnetic RAM), resistance change type memory, bipolar transistor, etc. The present invention can also be applied to a semiconductor product having a logic circuit, a semiconductor product having a logic circuit such as a microprocessor, or a copper wiring of a board or a package on which these are listed simultaneously.

  In addition, the multilayer wiring layer in which the variable resistance element according to the present invention is formed is bonded to a semiconductor device such as an electronic circuit device, an optical circuit device, a quantum circuit device, a micromachine, and a MEMS (Micro Electro Mechanical Systems). It can also be applied to. In addition, the variable resistance element according to the present invention has been described with a focus on the case where the switch function is used. However, the variable resistance element according to the present invention is used for a memory element using both non-volatility and variable resistance characteristics. You can also.

  The present invention has been described above by exemplifying typical embodiments and embodiments. However, the technical scope of the present invention is not limited to the above-described representative embodiments and embodiments. When implementing the present invention, various modifications that can be understood by those skilled in the art can be made within the scope (technical scope) of the present invention.

  The variable resistance element according to the present invention can be used as a nonvolatile switching element provided in a multilayer wiring layer of a semiconductor device.

Claims (10)

A resistance change element provided in a wiring layer on a semiconductor substrate,
The wiring layer has a first interlayer insulating film,
The variable resistance element is
A resistance change film;
A first electrode formed in contact with the upper surface of the variable resistance film;
A protective insulating film that covers the side surface of the variable resistance element, including the variable resistance film and the first electrode, is formed.
A first interlayer insulating film is formed so as to cover at least the upper part of the first electrode of the variable resistance element and the upper part of the protective insulating film,
A first contact plug is formed in the via hole formed in the first interlayer insulating film,
The side wall portion of the first contact plug is in contact with the side surface of the protective insulating film covering the side surface of the variable resistance element,
The protective insulating film covering the side surface of the variable resistance element does not cover the top of the first electrode of the variable resistance element,
The first electrode of the variable resistance element is in contact with a protective insulating film that covers the side surface of the variable resistance element only on its side surface ,
The resistance change element, wherein the first electrode in contact with the protective insulating film and the first contact plug are not electrically connected . The resistance change element according to claim 1, wherein the protective insulating film is formed of a SiN film. The first contact plug formed in the via hole is
2. The variable resistance element according to claim 1, wherein the variable resistance element is composed of a plug portion formed of a metal containing copper as a main component and a barrier metal layer covering the periphery of the plug portion. The resistance change film of the resistance change element is formed on an insulating barrier film that covers the upper surface of the lower copper wiring,
The insulating barrier film covering the upper surface of the lower copper wiring has an opening,
The resistance change element according to claim 1, wherein the upper surface of the lower copper wiring is in contact with the lower surface of the resistance change film of the resistance change element through the opening. 5. The variable resistance element according to claim 4, wherein the insulating barrier film covering the upper surface of the lower copper wiring is a SiN film or a SiCN film. The resistance change film of the resistance change element is formed on an insulating barrier film that covers the upper surface of the lower copper wiring,
The first contact plug penetrates the insulating barrier film and is in contact with the upper surface of the lower copper wiring located under the penetrating portion. The variable resistance element according to one item. The first electrode is made of a metal mainly composed of Ru,
The variable resistance element according to claim 6, wherein the variable resistance film is a film made of a solid electrolyte. The variable resistance element according to claim 1, wherein the variable resistance film includes an oxide. The wiring layer has a second interlayer insulating film formed on the first interlayer insulating film,
An upper copper wiring is formed in the second interlayer insulating film,
The first contact plug formed in the first interlayer insulating film is formed integrally with the upper copper wiring formed in the second interlayer insulating film. The resistance change element according to any one of claims 1 to 6. An upper surface protective film is formed on the upper surface of the first electrode,
The variable resistance element according to claim 1, wherein the protective insulating film covers side surfaces of the variable resistance film, the first electrode, and the upper surface protective film.