JP2008072031A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device using W that has favorable compatibility with a CMOS process as a material for a resistance variable type memory cell, and to obtain a large capacity nonvolatile semiconductor storage device at low cost utilizing its oxide. <P>SOLUTION: The nonvolatile semiconductor storage device comprises a resistance variable type memory cell having a WO<SB>3</SB>film 3 which is a resistor formed in a W plug 2 and an upper electrode or a lower electrode composed of a W plug. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an improvement in a nonvolatile semiconductor memory device including a resistance change type memory cell.

  At present, the cost reduction and performance improvement of electronic devices including computers are remarkable. At the same time, a large amount of memory is required to communicate and store a large amount of data such as images, photos, videos, and music. In particular, a low-cost, high-density SoC (system on chip) memory is required. It is said that.

  Recently, a trial result of a non-volatile ReRAM (resistive random access memory) including a resistance change type memory cell using NiO has been announced (for example, see Non-Patent Document 1).

NiO is a material familiar to the Si process, and its resistance change has been confirmed in the material, and is attracting attention as a promising candidate for post flash memory. It has also been demonstrated that an element in which Cu ₂ O is formed on the end face of the Cu plug is prototyped and the element operates as a ReRAM (see, for example, Non-Patent Document 2).

  By the way, wiring made of Cu is accompanied by electromigration (EM) and stress migration (SM), which is mainly caused by movement of Cu at the Cu wiring / barrier insulating film interface. (For example, see Non-Patent Document 3).

  In addition, it has been reported that the upper surface of a Cu wiring is covered with W to improve resistance to EM and SM (for example, see Non-Patent Document 3 and Non-Patent Document 4).

  Furthermore, when Cu oxide is formed on the surface of the Cu wiring, it is known that if a barrier insulating film is formed thereon, the Cu oxide becomes a source of Cu ions (for example, non-patent) According to the literature 4, it has been clarified that Cu oxide on the Cu surface shortens the time-dependent dielectric-breakdown (TDDB) life of the Cu wiring.

Thus, it has been found that the reliability of the Cu wiring is impaired by forming the Cu oxide on the surface of the Cu wiring or the end face of the Cu plug.
I. G. Beak et al. , IEDM Tech. Digest. p587, 2004. A. Chen et al. , IEDM Tech. Digest 31.3, 2005 Tatsuyuki Saito et al., Semiconductor Interface Technology No. 154 Committee, 49th Workshop Material (H.17.5.11) p7 T.A. Saito et al. , J .; J. et al. A. P. 43 No. 5 p2447 (2004). I. G. Beak et al. , IEDM Tech. Digest. 31.4, 2005.

  The present invention intends to realize a low-cost and large-capacity nonvolatile semiconductor memory device using W having high affinity with the CMOS process as a material of the resistance change type memory cell and using its oxide.

As described above, it is known to form a resistance change type memory cell made of Cu ₂ O in the Cu plug portion, and when Cu oxide is formed on the surface of the Cu wiring or the end face of the Cu plug, the reliability is improved. Is also known to decrease.

Therefore, the present inventors have conceived that WO _x is generated on the end face of the W plug to form a resistance change type memory cell, and as a result of repeated experiments, a very favorable result has been obtained.

  At present, W is often used as a plug to connect the drain of the transistor and the lowermost wiring in CMOS, and by using it as a cap layer of Cu wiring, it suppresses the diffusion of Cu and extends the EM and SM life. It is effective to do.

  For this reason, the nonvolatile semiconductor memory device according to the present invention includes a resistor made of W oxide formed on the end face of the contact plug, and an upper electrode or a lower electrode made of the contact plug. It comprises a resistance change type memory cell configured.

  By adopting the above means, since the resistance change type memory cell is configured by the resistance change element provided with the resistor made of W oxide on the end face of the W plug or the end face of the contact plug, the end face of the Cu plug. Compared with the resistance change type memory cell based on the conventional technology in which the resistance element made of Cu oxide is provided to form a resistance change element, the reliability of the wiring is not deteriorated due to the Cu oxide. Greatly improved.

  In addition, the cell area per bit is determined by the end face area of the contact plug as in the other inventions in which the resistor is formed using the end face of the contact plug, so that a large-capacity SoC can be easily realized. it can.

  Further, since W is a familiar material in the CMOS manufacturing process, the additional process required to realize the resistance change type memory cell according to the present invention is small, and it is inexpensive and has a high density nonvolatile memory. Can be realized easily.

  Furthermore, in the resistance change type memory cell, the high resistance → low resistance switch is on the order of one digit in microseconds, and the low resistance → high resistance switch is on the order of two digits in nanoseconds. Compared to the above, high-speed reading and rewriting are possible.

  Manufacturing a nonvolatile semiconductor memory device according to the present invention is simple, and can be easily realized, for example, in a process of manufacturing a CMOS.

FIG. 1 is a side view for explaining a principal part of an example of a resistance change type memory cell according to the present invention. In FIG. 1, 1 is a drain in CMOS, 2 is a plug made of W, and 3 is made of W. WO ₃ film formed by oxidizing the end face of the plug 2, 4 is an upper electrode, and 5 is a first layer wiring.

As shown in the drawing, in the current CMOS, the W plug 2 is frequently used to connect the drain 1 and the first layer (lowermost layer) wiring 5 in the transistor. oxidizing the second end surfaces to form a WOx film 3, the WO _x film 3 on the example Pt, Au, Ru, TiN, Ti, upper electrode made of a material selected from Al, etc. (topelectrode: TEL) 4 a As a result, a resistance change type memory cell having a W / WO _x / TEL structure is formed.

According to experiments, it has been confirmed that a set operation and a reset operation can be reliably performed with respect to a nonvolatile semiconductor memory device including a resistance change type memory cell having a W / WO _x / Pt structure.

2 and 3 are diagrams showing IV characteristics for explaining the operation of setting and resetting a resistance change type memory cell having a W / WO _x / Pt structure according to the present invention. FIG. In this case, FIG. 3 shows a case where bipolar operation is performed, and in each figure, the vertical axis represents current and the horizontal axis represents bias voltage.

  In the case of the unipolar operation of FIG. 2, when the bias voltage applied to the memory cell in the high resistance state is increased, a current suddenly starts to flow around 1.5 V, and this is the set state. In the case of unipolar operation, the current limit is 20 mA, current compliance is applied so that no more current flows, the bias voltage is increased to 3V, and then returned to 0V. In this case, the current takes a low resistance state path as indicated by arrow A.

  Next, when a bias voltage is applied to the memory cell in the low resistance state, it has a peak near 0.5 V and no current flows suddenly, which is a reset state.

  In this way, switching between high resistance → low resistance and low resistance → high resistance is performed by repeating the set operation and the reset operation.

  In the case of the bipolar operation in FIG. 3, a negative bias voltage is applied to the memory cell in the high resistance state to change to the low resistance state. This is the set state.

  Next, the change from the low resistance state to the high resistance state is such that when a positive bias voltage is applied to the memory cell in the low resistance state, it becomes difficult for current to flow from around 0.6 V. Switch to the resistance state. This is the reset state.

  As described above, switching to the set operation and the reset operation can be realized by applying voltages opposite to each other.

Here, the WO _x film in the memory cell used in the experiment was formed by oxidizing the W surface by performing RTA (rapid thermal annealing) in an oxygen atmosphere at 500 ° C. for 1 minute.

If a resistance change type memory cell having a W / WO _x / TEL structure is manufactured using a W plug, a high-density nonvolatile semiconductor memory device can be realized at low cost, and the cell area per bit is W plug. Therefore, the capacity can be increased in accordance with the miniaturization of the CMOS.

  In addition, the additional process for manufacturing the resistance change type memory cell is less, and the Re RAM has many advantages such as high-speed reading and rewriting as compared with the flash memory.

  In this embodiment, the lower electrode is selected from a W plug, the W oxide formed by oxidizing the end face of the W plug is a resistor, and the upper electrode is selected from Pt, Ir, Ru, Ti, TiN, Al, Ta, W, etc. Composed of metal.

  FIGS. 4 to 11 are side view for explaining the principal part showing the resistance change type memory cell in the process step for explaining the process of manufacturing the embodiment 1, and will be described below with reference to the drawings.

See Fig. 4 (1)
A salicide film 13 is formed on the surface of, for example, the drain 12 in the silicon semiconductor substrate 11 in which a transistor is formed by applying a normal technique, and then an insulating film made of, for example, SiO ₂ is formed by applying a CVD method. A film 14 is deposited.
(2)
A contact opening 15 is formed in the insulating film 14 on the drain 12 by applying a photolithography method and a dry etching method.

Refer to FIG. 5 (3)
By applying the CVD method, a W film is deposited on the entire surface including the inside of the contact opening 15, and then by chemical mechanical polishing of the W film to fill the contact opening 15 by applying the CMP method. Planarization is performed so that only the W film remains. The W plug 16 is formed through this process.

Refer to FIG. 6 (4)
By applying the RTA method in an oxygen atmosphere, thermal oxidation is performed at 500 ° C. for 1 minute to form WO _x , in this case, a WO ₃ film 17 on the end face of the W plug 16.

See FIG. 7 (5)
By applying the sputtering method, a Pt film that is a metal film for the upper electrode is formed on the entire surface.

See FIG. 8 (6)
By applying the photolithography method and the dry etching method, the Pt film is patterned to form the upper electrode 18.

Refer to FIG. 9 (7)
By applying the CVD method, an interlayer insulating film 19 made of SiO ₂ is formed on the entire surface.

Refer to FIG. 10 (8)
By applying a photolithography method and a dry etching method, the interlayer insulating film 19 is etched to form a wiring groove 20 that exposes the surface of the upper electrode 18.

Refer to FIG. 11 (9)
By applying the sputtering method, a barrier film 21 made of Ta and a seed film (not shown) made of Cu are formed in the wiring groove 20, and then Cu is filled in the wiring groove 20 by applying a plating method. A film is formed, and then polishing for planarizing the Cu film by applying a CMP method is performed to form the first layer wiring 22.

  In the first embodiment, the resistance change type memory cell is formed by using the end face of the W plug 16 formed on the drain 12 of the transistor. However, a W plug that connects the lower layer wiring and the upper layer wiring can also be used.

In this embodiment, the lower electrode is constituted by a W plug, the W oxide formed by oxidizing the end face of the W plug is a resistor, and the upper electrode is constituted by a barrier film provided for forming a first layer wiring. Therefore, the layer configuration of the memory cell is W plug / WO _x film / barrier film.

  FIGS. 12 to 15 are side view for explaining the principal part showing the resistance change type memory cell in the process steps for explaining the process of manufacturing the embodiment 2. Hereinafter, the process will be described with reference to the drawings.

See FIGS. 12 and 13 (1)
In the present embodiment, the process up to the step of forming the WO ₃ film 17 by oxidizing the end face of the W plug 16 is the same as that in the first embodiment, but immediately thereafter, the metal film for the upper electrode as in the first embodiment. The interlayer insulating film 19 made of SiO ₂ is formed on the entire surface by applying the CVD method without providing the film.

See FIG. 14 (2)
By applying the photolithography method and the dry etching method, the interlayer insulating film 19 is etched to form the wiring trench 20 that exposes the surface of the WO ₃ film 17.

Refer to FIG. 15 (3)
By applying the sputtering method, a barrier film 21 made of Ta and a seed film (not shown) made of Cu are formed in the wiring groove 20, and then Cu is filled in the wiring groove 20 by applying a plating method. A film is formed, and then polishing for planarizing the Cu film by applying a CMP method is performed to form the first layer wiring 22. In addition to Ta, TaN, TiN, Ti, or the like can be used as the material of the barrier film 21, and Al can be used as the material of the wiring 22 in addition to Cu.

  In the second embodiment, the resistance change type memory cell is formed by using the end face of the W plug 16 formed on the drain 12 of the transistor. However, as in the first embodiment, the W plug connecting the lower layer wiring and the upper layer wiring is used. You can also

In this embodiment, the lower electrode is composed of a W plug, the W oxide formed by oxidizing the end face of the W plug is a resistor, and the upper electrode is composed of a first layer wiring. Therefore, the layer configuration of the memory cell is W plug / WO _x film / Cu wiring.

  FIGS. 16 to 19 are side view for explaining the principal part showing the resistance change type memory cell in the process steps for explaining the process of manufacturing the embodiment 3, and will be described below with reference to the drawings.

See FIG. 16 and FIG. 17 (1)
In this embodiment, the process up to the step of forming the wiring groove 20 in the interlayer insulating film 19 and forming the barrier film 21 in the wiring groove 20 is the same as that of the first embodiment, and then the resist process and the dry etching method are applied. Therefore, the WO ₃ film 17 is exposed by etching the barrier film 21 on the bottom surface of the wiring groove 20.

See FIG. 18 (2)
By applying the sputtering method, a seed film (not shown) made of Cu is formed in the wiring trench 20 including the WO ₃ film 17, and then the plating trench is applied to fill the wiring trench 20. A film is formed. Needless to say, this Cu film is in direct contact with the WO ₃ film 17.

See FIG. 19 (3)
Polishing for flattening the Cu film by applying the CMP method is performed to form the first layer wiring 22.
Note that Al may be used as the material for the wiring 22 in addition to Cu.

  In the third embodiment, the resistance change type memory cell is formed using the end face of the W plug 16 formed on the drain 12 of the transistor. However, as in the first embodiment, the W plug connecting the lower layer wiring and the upper layer wiring is used. You can also

In this embodiment, a salicide film 13 in which a lower electrode is formed on the surface of the drain 12, a WO ₃ film in which a resistance change film is formed on the salicide film 13, and a W plug 16 are formed in the upper electrode. Therefore, the layer structure of the memory cell is salicide (WSi ₂ ) film / WO _x film / W plug.

  20 to 25 are side view for explaining the principal part showing the resistance change type memory cell in the process steps for explaining the process of manufacturing the embodiment 4, and will be described below with reference to the drawings.

See FIGS. 20 and 21 (1).
By applying the CVD method, a W film that covers the surface of the drain 12 of the transistor is formed, and then the RTA method is applied in an Ar atmosphere, and annealing is performed at 400 ° C. for 1 minute to salicide. A film 13 is produced.

See FIG. 22 (2)
By applying the CVD method, the insulating film 14 made of SiO ₂ is formed on the entire surface including the salicide film 13, and then, by applying the photolithography method and the dry etching method, the insulating film on the drain 12 is insulated. A contact opening 15 is formed in the film 14, and then a W film having a thickness of about 30 nm is formed by applying a CVD method.

See FIG. 23 (3)
By applying the dry etching method, the W film is etched back, and the unnecessary W film, that is, the W film on the insulating film 14 is removed.

See FIG. 24 (4)
An RTA method is applied in an O ₂ atmosphere, annealing is performed at 500 ° C. for 1 minute, and the W film at the bottom of the contact opening 15 is oxidized to generate the WO ₃ film 17.

See FIG. 25 (5)
By applying the CVD method, a W film is deposited on the entire surface including the inside of the contact opening 15, and then, by applying the CMP method, the W film is polished to fill the contact opening 15. Planarization is performed so that only the W film remains, and a W plug 16 is formed.

In the fourth embodiment, the salicide film 13 made of WSi ₂ is formed as the lower electrode, but the material can be silicide such as TiSi ₂ , NiSi, CoSi in addition to WSi ₂ .

In this embodiment, a Cu plug is used as the lower electrode, a W oxide formed on the surface of the Cu plug as the variable resistance layer, and a barrier film of the upper wiring as the upper electrode. Therefore, the layer structure of the memory cell is Cu plug / WO _x film / barrier film.

  FIG. 26 to FIG. 29 are side view for explaining the principal part showing the resistance change type memory cell in the process steps for explaining the process for fabricating the embodiment 5, and will be described below with reference to the drawings.

See FIG. 26 (1)
After the first layer wiring 22 is formed, a Cu diffusion prevention film 23 made of SiN or SiC is formed, and then an insulating film 24 made of SiO ₂ is formed by applying a CVD method, By applying the lithography method and the dry etching method, the insulating film 24 on the first layer wiring 22 is etched to form the opening for the conductive plug, and then by applying the sputtering method, Ta Alternatively, a barrier metal film made of TaN and a Cu seed film are deposited, and then a Cu film is formed on the Cu seed film by applying a plating method, and a Cu film is applied by applying a CMP method. The Cu plug 25 is formed by planarization, and then a W film is selectively grown only on the end face of the Cu plug 25 by applying a CVD method.

(2) By applying the RTA method, the W film is oxidized to form the WO ₃ film 26 under the condition of 500 ° C. for 1 minute in the O ₂ atmosphere.

See FIG. 28 (3)
The insulating film 27 made of SiO ₂ is formed on the entire surface by applying the CVD method, and then the insulating film 27 is etched by applying the photolithography method and the dry etching method to obtain the WO ₃ A wiring groove 28 for exposing the end face of the film 26 is formed.

See FIG. 29 (4)
By applying the sputtering method, a barrier film 29 made of Ta and a seed film (not shown) made of Cu are formed in the wiring groove 28, and then Cu is filled in the wiring groove 28 by applying a plating method. A second layer wiring 30 is formed by forming a film and then performing polishing for planarizing the Cu film by applying a CMP method.

  In this embodiment, Ta is used as the barrier film 29. However, TaN, Ti, and TiN can be used in addition to this, and Cu is used as the wiring 30. Alternatively, Al can be used. good.

In this embodiment, a Cu plug is used as the lower electrode, a W oxide formed on the surface of the Cu plug as the variable resistance layer, and an upper wiring as the upper electrode. Therefore, the layer configuration of the memory cell is Cu plug / WO _x film / upper wiring (Cu).

  30 to 32 are side view for explaining the principal part showing the resistance change type memory cell in the process steps for explaining the process of manufacturing the embodiment 6, and will be described below with reference to the drawings.

See FIG. 30 (1)
Formation of first layer wiring 22, formation of SiN layer 23, formation of insulating film 24, formation of Cu plug 25, formation of WO ₃ film 26, formation of insulating film 27, formation of wiring groove 28, formation of barrier film 29 Since the process up to the formation is exactly the same as that of the embodiment 5, the description thereof is omitted, and the subsequent process will be described.

See FIG. 31 and FIG. 32 (2)
By applying the resist process and the dry etching method, the WO ₃ film 26 is exposed by etching the barrier film 29 made of Ta on the bottom surface of the wiring groove 20.

(3)
By applying the sputtering method, a seed film (not shown) made of Cu is formed in the wiring trench 20 including the WO ₃ film 26, and then the plating trench is applied to fill the wiring trench 20 A film is formed. Needless to say, this Cu film is in direct contact with the WO ₃ film 26.

(4)
Polishing for flattening the Cu film by applying the CMP method is performed to form the second layer wiring 30.
Note that the wiring 30 may be made of Al in addition to Cu.

  In the present embodiment, Ta is used as the barrier layer 29, but TaN, Ti, or TiN may be used in addition.

  The description of each of the above embodiments has mainly clarified the manufacturing process of a single memory cell. Next, a semiconductor memory device in which memory cells are integrated and its operation will be described.

  FIG. 33 is a cutaway side view of a principal part showing a semiconductor memory device constructed by integrating resistance change type memory cells composed of one transistor and one resistance change element. In the figure, 31 is a gate connected to a word line. A representative cell selection transistor, 32 is a source, 33 is a drain, 34 is a resistance change element represented by a resistor formed on the plug end face, WL is a word line, BL is a bit line, and GND is ground. .

  FIG. 34 is an equalization circuit diagram showing the vicinity of the memory cell in the semiconductor memory device shown in FIG. 33. The parts indicated by the same symbols as those used in FIG. 33 represent the same or equivalent parts. Shall.

  In the drawing, one end of the resistance change element 34 is connected to the bit line BL 1, and the other end is connected to the drain 33 of the cell selection transistor 31. The source 32 of the cell selection transistor 31 is connected to the ground line GL1, and the gate is connected to the word line WL1.

  35 is an equivalent circuit diagram showing a semiconductor memory device in which the memory cells described with reference to FIG. 34 are arranged in an array, and a plurality of word lines WL1, WL2, WL3,... Arranged in the column direction are arranged in the column direction. It is arranged as a signal line common to a plurality of memory cells. In addition, a plurality of bit lines BL1, BL2, BL3, BL4,... Arranged in the row direction are arranged as signal lines common to the memory cells arranged in the row direction.

  A memory cell surrounded by a dotted line in FIG. 35 will be described as an example, and a rewriting operation from a high resistance state to a low resistance state, that is, a case of performing setting will be described.

  FIG. 36 is a diagram showing applied voltage (horizontal axis) vs. current (vertical axis) for explaining the operation of the memory cell. In the figure, the set indicates a solid line, and the reset indicates a characteristic indicated by a broken line. .

  Here, the resistance value of the variable resistance element 34 in the high resistance state is RH, and the resistance value in the low resistance state is RL.

  The bit line selection transistor 35 connected to the selected memory cell is turned on, and a bias voltage is applied to the selected bit line BL1. The gate voltage of the transistor 35 is adjusted so that the resistance of the channel in the bit line selection transistor 35 is sufficiently small compared to RH and becomes a resistance RL ′ that is not negligible compared to RL.

  At the same time, a voltage is applied to the word line WL1 connected to the gate of the cell selection transistor 31 connected to the resistance change element 34, and the resistance RL of the resistance change element 34 in which the channel resistance of the cell selection transistor 31 is in the low resistance state. The value should be negligibly small compared to.

  The absolute value of the bias voltage applied to the selected bit line BL1 is about the same as or slightly larger than the absolute value of the voltage required for setting, and is about 2 V when the variable resistance element 34 has the characteristics shown in FIG.

  By setting the ground line GL1 connected to the selected memory cell to 0V, a current path from the bias voltage of the bit line BL1 to the ground potential via the bit line selection transistor 35, the cell selection transistor 31, and the resistance change element 34 is formed. The bias voltage is distributed to the channel resistances of the resistance change element 34 and the bit line selection transistor 35 according to the ratio between the resistance of the resistance change element 34 and the channel resistance of the bit line selection transistor 35.

  Since RH is sufficiently larger than RL ′ and the channel resistance of the cell selection transistor 31, almost all of the bias voltage is distributed to the resistance change element 34, and the resistance change element 34 is rewritten to the resistance RL in the low resistance state.

  When the resistance change element 34 is set to the low resistance RL, the voltage ratio allocated to the channel resistance of the resistance change element 34 and the bit line selection transistor 31 is RL: RL ′, so that, for example, RL ′ = 2RL is set. In this case, 1/3 of the bias voltage is distributed to the resistance change element 34.

  Since RL ′ can be set to an arbitrary value within the possible range in terms of the performance of the bit line selection transistor 31, the voltage applied to the resistance change element 34, that is, the current flowing through the resistance change element 31 is changed to the gate of the bit line selection transistor 31. If the bias voltage is set to an arbitrary value depending on the voltage and then the bias voltage is returned to 0 V, the writing to the low resistance state corresponding to the current limit value is completed.

  Next, writing (reset) from low resistance to high resistance will be described. A point to be noted in reset writing is that a voltage higher than that required for resetting must be applied to the variable resistance element 31 in the low resistance state, so that the cell selection transistor 31 and the bit line selection transistor 35 are not connected. The gate voltage is adjusted so that both channel resistances are sufficiently smaller than the low resistance value RL in the resistance change element 31.

  In addition, almost all the bias voltage is distributed to the resistance change element 34 at the moment when the resistance change element 2 is switched to the high resistance RH. Therefore, the bias voltage must be smaller than the voltage required for setting. Incidentally, when the element characteristic is seen in FIG. 36, it is about 1V.

  In the reset process, the gate voltage is adjusted so that the channel resistances of the cell selection transistor 31 and the bit line selection transistor 35 are sufficiently smaller than the low resistance value RL of the resistance change element 34, and the bit line is adjusted. The bias voltage applied to BL1 is set to be equal to or higher than the reset voltage and lower than the set voltage. Thereafter, the reset is completed by returning the bias voltage to 0V.

  Needless to say, the semiconductor memory device described as the seventh embodiment can be modified in many ways.

  FIG. 37 is a cutaway side view of a principal part showing a semiconductor memory device constructed by integrating resistance change type memory cells comprising one transistor and one resistance change element, and is indicated by the same symbol as that used in FIG. The parts shall represent the same or equivalent parts.

  The difference between the present embodiment and the seventh embodiment is that a variable resistance element 34 represented by a resistor is formed between the drain 33 of the transistor and the contact plug.

  FIG. 38 is a cutaway side view of a principal part showing a semiconductor memory device constructed by integrating resistance change type memory cells each composed of one transistor and one resistance change element, and is indicated by the same symbol as that used in FIG. The parts shall represent the same or equivalent parts.

  In this embodiment, a resistance change element 34 typified by a resistor is formed on the end face of a contact plug connecting multilayer wirings.

  Since the present invention can be implemented in many forms including the above-described embodiment, it will be exemplified as an additional note hereinafter.

(Appendix 1)
A non-volatile semiconductor comprising: a resistance body made of W oxide formed in a contact plug; and a resistance change type memory cell comprising an upper electrode or a lower electrode made of the contact plug. Storage device.

(Appendix 2)
In the resistance change type memory cell according to (Appendix 1), the resistor is a W oxide formed on an end face of a W plug, the lower electrode is a W plug, and the upper electrode is a barrier metal of an upper layer wiring. The nonvolatile semiconductor memory device according to (Appendix 1).

(Appendix 3)
The nonvolatile semiconductor memory device according to (Appendix 1), wherein the upper electrode is an upper layer wiring.

(Appendix 4)
In the resistance change type memory cell according to (Appendix 1), the resistor is a W oxide formed on an end face of a contact plug connecting a drain and a lower layer wiring of a transistor, a salicide film having a lower electrode formed on a drain surface, an upper part The nonvolatile semiconductor memory device according to (Appendix 1), wherein the electrode is a contact plug.

(Appendix 5)
In the resistance change type memory cell according to (Appendix 1), the resistor is a W oxide formed on an end face of a Cu plug, the lower electrode is a Cu plug, and the upper electrode is a barrier metal of an upper layer wiring. The nonvolatile semiconductor memory device according to (Appendix 1).

(Appendix 6)
(Appendix 1) The variable resistance metal cell according to (Appendix 1) is characterized in that the resistor is a W oxide formed on the end face of the Cu plug, the lower electrode is a Cu plug, and the upper electrode is an upper layer wiring (Appendix 1) The nonvolatile semiconductor memory device described.

It is principal part side explanatory drawing showing an example of the resistance change type memory cell by this invention. FIG. 4 is a diagram showing IV characteristics for explaining the setting and resetting operations of a resistance change type memory cell having a W / WO _x / Pt structure according to the present invention. FIG. 4 is a diagram showing IV characteristics for explaining the setting and resetting operations of a resistance change type memory cell having a W / WO _x / Pt structure according to the present invention. FIG. 3 is a side view for explaining a principal part of a resistance change type memory cell in a process essential point for explaining a process for producing Example 1; FIG. 3 is a side view for explaining a principal part of a resistance change type memory cell in a process essential point for explaining a process for producing Example 1; FIG. 3 is a side view for explaining a principal part of a resistance change type memory cell in a process essential point for explaining a process for producing Example 1; FIG. 3 is a side view for explaining a principal part of a resistance change type memory cell in a process essential point for explaining a process for producing Example 1; FIG. 3 is a side view for explaining a principal part of a resistance change type memory cell in a process essential point for explaining a process for producing Example 1; FIG. 3 is a side view for explaining a principal part of a resistance change type memory cell in a process essential point for explaining a process for producing Example 1; FIG. 3 is a side view for explaining a principal part of a resistance change type memory cell in a process essential point for explaining a process for producing Example 1; FIG. 3 is a side view for explaining a principal part of a resistance change type memory cell in a process essential point for explaining a process for producing Example 1; FIG. 11 is a side view for explaining a main part of a resistance change type memory cell in a process key point for explaining a process of manufacturing Example 2; FIG. 11 is a side view for explaining a main part of a resistance change type memory cell in a process key point for explaining a process of manufacturing Example 2; FIG. 11 is a side view for explaining a main part of a resistance change type memory cell in a process key point for explaining a process of manufacturing Example 2; FIG. 11 is a side view for explaining a main part of a resistance change type memory cell in a process key point for explaining a process of manufacturing Example 2; FIG. 10 is a side view for explaining a main part of a resistance change type memory cell in a process key point for explaining a process of manufacturing Example 3; FIG. 10 is a side view for explaining a main part of a resistance change type memory cell in a process key point for explaining a process of manufacturing Example 3; FIG. 10 is a side view for explaining a main part of a resistance change type memory cell in a process key point for explaining a process of manufacturing Example 3; FIG. 10 is a side view for explaining a main part of a resistance change type memory cell in a process key point for explaining a process of manufacturing Example 3; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 4; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 4; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 4; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 4; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 4; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 4; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 5; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 5; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 5; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 5; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 6; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 6; FIG. 10 is an explanatory side view of a principal part showing a resistance change type memory cell at a process point for explaining a process for producing Example 6; 1 is a cutaway side view showing a main part of a semiconductor memory device configured by integrating resistance change type memory cells composed of one transistor and one resistance change element. FIG. 34 is an equalization circuit diagram showing the vicinity of a memory cell in the semiconductor memory device shown in FIG. 33. FIG. 35 is an equalization circuit diagram showing a semiconductor memory device in which the memory cells described with reference to FIG. 34 are arranged in an array. It is a diagram showing the applied voltage (horizontal axis) versus current (vertical axis) for explaining the operation of the memory cell. 1 is a cutaway side view showing a main part of a semiconductor memory device configured by integrating resistance change type memory cells composed of one transistor and one resistance change element. 1 is a cutaway side view showing a main part of a semiconductor memory device configured by integrating resistance change type memory cells composed of one transistor and one resistance change element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Drain in CMOS 2 Plug made of W ₃ WO ₃ film formed by oxidizing end face of plug 2 made of W 4 Upper electrode 5 First layer wiring

Claims (5)

A non-volatile semiconductor comprising: a resistance body made of W oxide formed in a contact plug; and a resistance change type memory cell comprising an upper electrode or a lower electrode made of the contact plug. Storage device. 2. The resistance change type memory cell according to claim 1, wherein the resistor is a W oxide formed on an end face of the W plug, the lower electrode is a W plug, and the upper electrode is a barrier metal of an upper layer wiring. Item 12. A nonvolatile semiconductor memory device according to Item 1. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the upper electrode is an upper layer wiring. 2. The resistance change memory cell according to claim 1, wherein the resistor is a W oxide formed on an end face of a contact plug connecting the drain and lower layer wiring of the transistor, a salicide film having a lower electrode formed on the drain surface, and an upper electrode. The nonvolatile semiconductor memory device according to claim 1, wherein the contact plug is a contact plug. 2. The resistance change type memory cell according to claim 1, wherein the resistor is a W oxide formed on an end face of a Cu plug, the lower electrode is a Cu plug, and the upper electrode is a barrier metal of an upper wiring. Item 12. A nonvolatile semiconductor memory device according to Item 1.

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