TW201131670A - Manufacturing method and structure of surface mount diode component of silicon chip-substrate integrated packaging - Google Patents

Manufacturing method and structure of surface mount diode component of silicon chip-substrate integrated packaging Download PDF

Info

Publication number
TW201131670A
TW201131670A TW099106657A TW99106657A TW201131670A TW 201131670 A TW201131670 A TW 201131670A TW 099106657 A TW099106657 A TW 099106657A TW 99106657 A TW99106657 A TW 99106657A TW 201131670 A TW201131670 A TW 201131670A
Authority
TW
Taiwan
Prior art keywords
substrate
diffusion
wafer
manufacturing
electrodes
Prior art date
Application number
TW099106657A
Other languages
Chinese (zh)
Other versions
TWI402923B (en
Inventor
Wen-Bin Huang
Wen-Hu Wu
Original Assignee
Formosa Microsemi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Formosa Microsemi Co Ltd filed Critical Formosa Microsemi Co Ltd
Priority to TW099106657A priority Critical patent/TW201131670A/en
Publication of TW201131670A publication Critical patent/TW201131670A/en
Application granted granted Critical
Publication of TWI402923B publication Critical patent/TWI402923B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Dicing (AREA)

Abstract

The present invention discloses a manufacturing method and a structure of a surface mount diode component of silicon chip-substrate integrated packaging. The manufacturing method comprises the steps of sintering and fusing a chip, which has gone through the diffusion process, and a high-strength substrate, which is high-temperature resistant, to make an integrated packaging; then treating the chip by etching and ditching process, stuffing process with insulation material and surface metallization process, so as to construct a plurality of electrodes on the same plane; and after finishing the fabrication of all the functional circuits, slicing the integrated packaging to sever a plurality of directly applicable single surface mount diode components. Compared with the conventional diode component manufacturing method which executes packaging and testing processes after finishing the fabrication of all the functional circuits and the segmentation of forming single chips, the present invention has the advantages of simplifying the manufacturing process and reducing the working hour while the chip remains hard to be broken during the manufacturing process and fits the global trend demanding weightlessness, thinness, shortness and smallness.

Description

201131670 六、發明說明: 【發明所屬之技術領域】 本發明為一種與二極體右關μ m 有關的構造及其製造方法,特別是 指一種矽晶片與基板共構表面對宜 再衣面姑者型二極體元件製造方法及 構造。 . 【先前技術】 . 舉凡工業、家電、電力牟#、六、s • n父通、商業、航空、電腦通 訊到軍事職,都可見到電力電子使㈣獅,在電力電子技 術領域中,常棚表面黏著型二極奴縣賴各種需求。 如第-圊所示’前述表面黏著型二極體耕的概要製造方 法如下··對-本質材料為石夕的石夕晶圓片1〇〇,進行侧⑼、 設置絕緣層搬、以及表面金屬化1〇3等功能線路製作製程 後,切割石夕晶圓片m成單-晶粒,再於單—晶粒的兩極上各 • *別延伸設置—電氣接腳105後封裝106,如此便可製成常見 的表面黏著型二極體元件。 - 糾’前述習知表蹄著型二極體元件的結構可依前述電 . 氣接_及所填充的絕緣層不同而有不_實施態樣: , 如第二圖所示,該表面黏著型二極體元件之晶粒】的電氣 接腳2可以分別設置在位於晶粒i左右兩侧的兩極,而設置在 晶粒1外層的封裝層3則可以是填充於晶粒J外部的玻璃。 或者,如第三圖所示,該表面黏著型二極體元件之晶粒! 201131670 的兩極分別設置於晶粒]的上下兩側,其中一電氣接腳2設置 在晶粒1的下方電極處,另外,再在晶粒1的上方電極處打線 接合設置另一電氣接腳2,並在晶粒]外部填充保護晶粒1的 玻璃或是環氧樹脂(ePoxy)封裝層3。 另外,如第四圖所示,該表面黏著型二極體元件之晶粒] 的兩極分別設置於晶粒]的上下兩侧,並在晶粒1上下兩側各 銲接設置一電氣接腳2,並將電氣接腳2彎折至同一侧以方便 使用,並再用環氧樹脂(ePoxy)作為封裝3以包覆、固定及保 護晶粒1與電氣接腳2。 雖然,前述三種電氣接腳2與封裝層3的實施態樣,都具 有可以保護晶粒〗的功用’但是’攻種將石夕晶圓片切割成晶粒 1後,再一一針對每一晶粒1設置電氣接腳2與封裝保護的封 裝層3,不僅相當耗費工時,也容易增加成本。再者,前述矽 晶圓片在進^亍姓※彳時’也很谷易因為石夕晶圓片的柯料強度不 夠、剛性不足,而發生開溝I虫刻、或研磨加工碎裂的問題。 因此,對於表面黏著型二極體元件的製作廠商而言,如何 改善^夕晶圓片材料強度不夠、晶粒需要封敕保護、間化表面黏 著型二極體的製作製程等,都是亟需馬上解決的問題。 有鑑於此,本發明人乃累積多年相關領域的研究以及實 驗,特創作出一種「矽晶片與基板共構表面黏著型二極體元件 製造方法及構造」,可以改善習知表面黏著型二極體因剛性不 足,容易加工碎裂的問題,而且無需封裝的工序,可縮小元件 201131670 體積’並能降低製作成本 【發明内容】 本發明之目㈣在提供—種與基板共構表面黏著 型二極體元件製造方法及構造」,可以加強二極體的材料強 度,避免加工破裂的情形,以達到簡化製程、縮小尺寸、降低 製作成本的目的。 爲達成上述目的,本發明「石夕晶片與基板共構表面黏著型 :鐘讀製造方法及構造」,其帽造方法係包括下列步驟: 弟一步驟:將-擴散後晶片與—可耐高温之高強度基板層疊燒 絲接後,令舰後W與基板軸—共構體。 第-^ .轉散後㈣表面進行糊溝,以形成複數 隔離私’使擴散後晶片上形成複數個建構在同一 平面上相互隔離排列的電極。 第三步驟:在擴散後晶片上的複數隔離溝槽内填人絕緣物質, 令魏_销—平面上的紐彳目絲緣隔離。 四對上述擴散後晶片之電極表面金屬化,以延伸電極 的電氣特性’完成所有的功能線路製作。 第五步驟:職彳如與基板所形成之共賴行網’以 ㈣出複數個單—個體 二 每冓朗—平面上且相互絕緣隔離的電極,使 母一早一個體形成可以直接應用的單—表面黏著 201131670 型二極體元件。 上述製程中,若擴散後晶片為單面擴散型,則可以令前述 單一表面黏著型二極體元件建構在同一平面上且相互絕緣隔 離的兩個電極為P/P或N/N電極,形成雙向表面黏著型二極體 元件。 以下再針對本發明各製程之詳細實施方式作進一步的說 明,其中: 前述第一步驟中,為使擴散後晶片與基板容易燒結熔接, 因此,可以進一步在擴散後晶片與基板之間設置一耐高溫之合 金焊材,以供擴散後晶片與基板能相互熔接接合。 該基板實施時,基板的材質可以是非導體,例如:陶瓷、 玻璃等,並且在陶瓷等基板頂面可以設置金屬化的接合層,以 達到與擴散後晶片谷易層豐燒結炼接的目的。前述陶乾基板頂 面接合層實施時,可以利用印刷方式製成厚膜接合層,或者利 用電鍍方式製成薄膜接合層。 再者,為達到更好的散熱效果,該基板實施時,其材質也 可以是導體,例如:金、銀、銅、鐵、鋁等金屬,或是較高阻 值半導體等;此基板的材質如果為導體或是半導體實施例時, 底部需設置一保護層,以保護擴散後晶片,並達到防潮絕緣的 效果。由於基板相對於擴散後晶片比較不易變形、剛性強,所 以在擴散後晶片與基板燒結熔接共構後,若擴散後晶片蝕刻開 溝過深,或是該擴散後晶片研磨過薄時,在後續製程中擴散後 201131670 而且具有縮小 晶片也不容易發生斷裂問題,因此較不怕碰撞, .體積的功效。 前述第三步驟在擴散後晶片上的複數隔離溝槽内填入絕 緣物質實鱗’可以填充_或是絲化料各射以達到隔 離電極的實施方式實施設置。201131670 VI. Description of the Invention: [Technical Field] The present invention relates to a structure related to the right-off μm of a diode and a manufacturing method thereof, and particularly to a method for co-fabricating a surface of a tantalum wafer and a substrate. Method and structure for manufacturing a diode element. [Prior Art] . For all industries, home appliances, electric power, #6, s n n-pass, commercial, aviation, computer communications to military positions, you can see the power electronics (four) lion, in the field of power electronics technology, often The surface of the shed is attached to the two-pole slave county. As shown in the first section, the above-mentioned surface-adhesive diode cultivation method is as follows: · The --essential material is Shi Xi's Shi Xi wafer 1〇〇, the side (9), the insulating layer is moved, and the surface is provided. After the metallized 1〇3 and other functional circuit fabrication processes, the silicon wafers m are cut into single-die, and then on the two sides of the single-die, *the extension is set--the electrical pin 105 is packaged 106, so A common surface-adhesive diode component can be fabricated. - Correction of the structure of the above-mentioned conventional hoof-shaped diode element can be made according to the above-mentioned electricity and gas-filled insulation layers, and the surface is adhered as shown in the second figure. The electric pins 2 of the die of the diode element can be respectively disposed on the two poles on the left and right sides of the die i, and the encapsulation layer 3 disposed on the outer layer of the die 1 can be the glass filled on the outer side of the die J. . Or, as shown in the third figure, the surface of the surface-adhesive diode element! The two poles of 201131670 are respectively disposed on the upper and lower sides of the die, wherein one electrical pin 2 is disposed at the lower electrode of the die 1, and further, another electrical pin 2 is wire-bonded at the upper electrode of the die 1. And protecting the glass 1 or the epoxy resin (ePoxy) encapsulation layer 3 on the outside of the crystal grains. In addition, as shown in the fourth figure, the two electrodes of the surface-adhesive diode element are respectively disposed on the upper and lower sides of the die, and an electrical pin 2 is soldered on the upper and lower sides of the die 1. And the electrical pin 2 is bent to the same side for convenient use, and epoxy resin (ePoxy) is used as the package 3 to cover, fix and protect the die 1 and the electrical pin 2. Although the foregoing three types of electrical pins 2 and the implementation of the encapsulation layer 3 have the function of protecting the crystal grains, 'but' the seeds are cut into the crystal grains 1 and then one by one. The die 1 is provided with the electrical pin 2 and the encapsulation layer 3 protected by the package, which is not only time-consuming but also easy to increase the cost. In addition, the above-mentioned enamel wafers are also in the case of the surname of the 彳 彳 彳 也 也 也 因为 因为 因为 因为 因为 因为 因为 因为 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石problem. Therefore, for the manufacturer of the surface-adhesive diode element, how to improve the strength of the material of the wafer material, the need for the sealing of the crystal grain, and the manufacturing process of the interlayer-adhesive diode are all 亟Issues that need to be resolved immediately. In view of the above, the present inventors have accumulated research and experiments in related fields for many years, and have created a "manufacturing method and structure of a co-fabricated surface-adhesive diode element of a germanium wafer and a substrate", which can improve the conventional surface-adhesive dipole. The problem is that the rigidity of the body is insufficient, the problem of chipping is easy to be processed, and the process of packaging is not required, and the volume of the component 201131670 can be reduced and the manufacturing cost can be reduced. [Invention] The object of the present invention is to provide a surface-bonding type with the substrate. The manufacturing method and structure of the polar body component can strengthen the material strength of the diode and avoid the situation of processing cracking, so as to simplify the process, reduce the size, and reduce the manufacturing cost. In order to achieve the above object, the present invention "the stone-like wafer and the substrate co-fabricated surface-adhesive type: clock-making manufacturing method and structure", the cap making method comprises the following steps: a first step of the process: the - diffusion of the wafer and - can withstand high temperature After the high-strength substrate is laminated and fired, the ship's rear W and the substrate axis are co-constituted. After the divergence, the surface of the (4) surface is etched to form a plurality of isolated electrons, so that a plurality of electrodes are formed on the wafer after diffusion to be arranged in isolation on the same plane. The third step: filling the insulating spacers in the plurality of isolation trenches on the wafer after diffusion, so that the filaments on the Wei_pin-plane are isolated. Four pairs of the surface of the electrode of the above-mentioned diffused wafer are metallized, and all the functional lines are fabricated by extending the electrical characteristics of the electrode. The fifth step: the job is formed by the substrate together with the substrate to make a plurality of single-individual two-individual-in-plane and insulated and isolated electrodes, so that the mother can form a single body directly. - Surface adhesion of the 201131670 diode component. In the above process, if the wafer after diffusion is a single-sided diffusion type, the two electrodes of the single surface-adhesive diode element constructed on the same plane and insulated from each other are P/P or N/N electrodes, forming Two-way surface-adhesive diode component. The detailed implementation of each process of the present invention is further described below. In the first step, in order to facilitate the sintering and welding of the wafer and the substrate after the diffusion, a diffusion between the wafer and the substrate may be further provided after the diffusion. The high-temperature alloy welding material can be welded and joined to each other after diffusion. When the substrate is implemented, the material of the substrate may be a non-conductor, for example, ceramic, glass, or the like, and a metallized bonding layer may be disposed on the top surface of the substrate such as ceramic to achieve the purpose of sintering and refining the wafer after diffusion. When the top bonding layer of the above-mentioned ceramic substrate is implemented, a thick film bonding layer can be formed by printing, or a film bonding layer can be formed by electroplating. Furthermore, in order to achieve a better heat dissipation effect, the substrate may be made of a conductor such as gold, silver, copper, iron, aluminum or the like, or a higher resistance semiconductor; In the case of a conductor or semiconductor embodiment, a protective layer is provided on the bottom to protect the diffused wafer and achieve moisture-proof insulation. Since the substrate is less deformable and rigid than the diffused wafer, after the diffusion and co-construction of the wafer and the substrate after diffusion, if the wafer is etched too deep after diffusion, or the wafer is too thin after the diffusion, After the diffusion in the process, 201131670 and the shrinking of the wafer is not prone to breakage, so it is less afraid of collision, volumetric effect. The third step described above is carried out in such a manner that the plurality of isolation trenches on the wafer after the diffusion are filled with the insulating material and the scales can be filled or the silk material is irradiated to reach the isolation electrode.

、〜 以印刷或焊接方式 增設-金屬電極板;此金屬電極板的設置亦可以在 割後進行。 前述第四步驟中,對擴散後晶片之電極表面金屬化’其目 的是使電極易於黏著或焊接,並完朗有的魏線路製作,、金 屬化後還可以在表面金屬化的每一電極上, 第五步驟切 除此之外’為強化製程後每-個表面黏箸型二極體元件之 絕緣保護,可以在每—個表面黏著型二_元件除電極以外的 外表面上設1-絕緣層,該絕緣層實施時可以是_或液能環 乳樹脂(EP0XY)或絕緣勝,以達到絕緣保護之目的。 上这衣私中’擴散後晶片為單面擴散型,切割後可以形成 單面擴散_晶粒,可以令前述單—表轉著型二極體树 建構在同一平面上且相互絕緣隔離的兩個電極為阶或膽 ::::著型一該雙向表-著型二極 —種表面黏著型二極體元件,係包括:—單面擴散型石夕曰 粒以及-财晶減崎轉接共構之基板,其中,卿^ 底面與基板之間設置-耐高溫之合金焊材,以供㈣粒與基板 201131670 相互燒結溶接,对晶粒兩電極的四周設有填充絕緣物質之P 離溝槽讀隔出兩個建構於同-平面上之戰_雷^ 每-電極外表面設有金屬化導接層。 實施時’前述基板的柯質可以是非導體,例如:陶曼、破 璃’而且L或麵基㈣面也可以設置金屬化的接八 層,以達到與擴散後晶片容易層疊燒結熔接的目的。而且,; 述基板頂面接合層實施時,可以是以印刷方式製成的厚膜接八 層’或者電鍍方式奴_轉合層。 ^ 、再者,為達到更好的散熱效果,絲板實施時,其材質也 巧*以是導體,例如:金、费、如 ^ 、 、〜、,同、鐵、鋁等,或者以較高阻值 + W替代:此基板的材質如果為導體或半導體之實施例時, 為確保達龍職錢騎觀緣的縣’金屬基板底 部可敦置-保護層。此外,實施時,也可以視 在前述金屬化導接層的外表面 ,,:衣而 1、、★ 面U —枝組W金屬電極 板’以達到容易加工組裝的目的。~ Adding a metal electrode plate by printing or soldering; the setting of this metal electrode plate can also be performed after cutting. In the fourth step, the surface of the electrode of the diffused wafer is metallized', the purpose of which is to make the electrode easy to adhere or solder, and to make a complete Wei line, and after metallization, it can also be on each electrode of the surface metallization. The fifth step is to remove the insulation protection of each surface-bonded diode component after the strengthening process, and the insulation can be provided on the outer surface of each surface-bonding type _ component except the electrode. In the layer, the insulating layer can be implemented as _ or liquid energy ring resin (EP0XY) or insulation to achieve the purpose of insulation protection. In this clothing privately, the wafer after diffusion is a single-sided diffusion type, which can form a single-sided diffusion_die after cutting, which can make the aforementioned single-table-turning diode trees be constructed on the same plane and insulated from each other. The electrode is a step or a biliary:::: a type of the two-way table-type two-pole-type surface-adhesive diode element, including: - single-sided diffusion type stone 曰 曰 以及 and - 财 晶A substrate is formed by co-construction, wherein a high-temperature resistant alloy welding material is disposed between the bottom surface of the substrate and the substrate, so that the (four) particles and the substrate 201131670 are mutually sintered and sintered, and a P-filling insulating material is disposed around the two electrodes of the crystal grain. The trench read is separated from two wars constructed on the same plane. The outer surface of each electrode is provided with a metallized conductive layer. When implemented, the substrate of the substrate may be a non-conductor, for example, Tauman, glass, and the L or the surface of the surface may be provided with a metallized layer to achieve the purpose of easy lamination and sintering of the wafer after diffusion. Further, when the substrate top surface bonding layer is implemented, it may be a thick film formed in a printed manner or an electroplated slave layer. ^, and, in order to achieve better heat dissipation, when the silk plate is implemented, its material is also a good conductor, such as: gold, fee, such as ^, , ~,, with, iron, aluminum, etc., or High resistance + W replacement: If the material of this substrate is a conductor or a semiconductor embodiment, the bottom of the metal substrate can be ensured to protect the Dalong duty. Further, at the time of implementation, it is also possible to view the outer surface of the metallized conductive layer, and the surface of the metal electrode plate of the U-branch group W for easy processing and assembly.

再者,為強化每-表面黏著型:極體元件之㈣㈣,實 施時還娜每—槪卿二驗崎㈣;^外 表面上设置-絕緣層’該絕闕實施時可以是固 樹脂(EPOXY)或絕緣膠’以達到絕緣保護之目的~ U 、上述製程中,若擴散後晶片為雙面擴散型,切割後可以形 成雙面擴散型石夕晶粒,故可以令前述i —在二+ 衣面姑著型二極體元 件建構在同一平面上且相互絕緣隔離的兩個電極為州電 201131670 極,形成單向表面黏著型二極體元件。 本單向表面黏著型二極體元件製程實施例與前述步驟不 同之處,是由於擴散後晶片為雙面擴散型,擴散後晶片必須八 隔成PPNNPP....·.·複數電極,@此在進行第三步驟時,不^ 在N/N間的溝槽内填入絕緣物質,以便在進行第四步驟日持 同時對N/N間的溝槽、以及p ' N電極面作金屬化;此_ 間空出的溝槽可在第四步驟之前以侧開溝或黃光 設置之。. 、衣狂 此實施例中,由於第四步驟對擴散後晶片之電極表面金屬 化時’金屬化部位亦包含麵間的溝槽表面,因此在 五步驟切割前,再對膽間的溝槽内填入絕緣物質,則第五 步驟切割後’即可分離出複數個單—表面黏著型二極體, -表面黏著型二極體之表面均具有兩個建構在同—平面 ===雇電極,使每—單—表面黏著型二極體可以直 峨方式 如下藉由上述步驟所製成之單向表面黏著型二極體元件結構 I種表面黏著型二_元件’係包括:一雙面擴散型石夕晶 及-_矽晶粒底面燒結炫接共構之基板’其中,該石夕晶 粒底面與基板之間設置 κ 板相互燒叫容接,且石"』 于材’以供矽晶粒與基 之 70 曰曰粒兩極的四周;設有填充絕緣物質 201131670 隔離溝槽,以分隔出兩個建構於同一平面上之P/N電極,且每 一電極表面金屬化設置導接層,該導接層由其中一電極延伸到 其側邊之隔離溝槽與絕緣物質之間。本實施例單向之表面黏著 型二極體元件的其他實施方式,與前述雙向表面黏著型二極體 元件之實施例相同,在此不另贅述。 相較於習知技術,本發明「矽晶片與基板共構表面黏著型 二極體元件製造方法及構造」,可以簡化表面黏著型二極體的 製程,以達到縮短工時的目的,而且製造時擴散後晶片不僅不 易破裂,其切割成型之後的表面黏著型二極體元件還可以直接 應用,具有縮小體積、使用方便的功效。 【實施方式】 以下依據本發明之技術手段,列舉出適於本發明之實施方 式,並配合圖式說明如後: 如第五至第七圖所示,本發明「矽晶片與基板共構表面黏 著型二極體元件製造方法及構造」,該製造方法係包括下列步 驟: 第一步驟200 :將一擴散後晶片10與一可耐高溫之高強度基 板20層疊燒結熔接後,令擴散後晶片10與基 板20形成一共構體30。 第二步驟20]:如第五、第八圖所示,對該擴散後晶片_1〇的 表面進行蝕刻開溝,以形成複數隔離溝槽,使 10 201131670 擴政後阳片10上形成複數個建構在同一平面 上相互隔離排列的電極U。 第二步驟202 :如第五、第六R张_ $九騎^麵散後^10上的 複數隔離溝槽内填入絕緣物質12,令複數建 第四步驟703 . — t面上的電極11相互絕緣隔離。 ϋ五、第十圖所示’對擴散後晶片10之電 極11表面金屬化,以延伸電極11的電氣特 ^ 性,完成所有的功能線路製作。 第五步驟204:如第五、第十— 乐十圖所不,將擴散後晶片10與 基板2〇所形成之共構體3〇進行切割,以分離 出複數個單—個體,如第十二圖所示,每一單 一個體表面均具有兩個建構在同—平面上且 相互絕緣隔離的電極11 ’使每-單-個體形成 可以直接應用的單-表面黏著型二極體元件 40 〇 上迷製程中,若擴散後晶片1〇為單面擴散型,切 散型^ m ’則可以令前述單—表面黏著型 版建構在同一平面上且相互絕緣隔離的兩個電極】 Ρ/Ρ 或 Ν/Ν 電極⑴、112( ,、、、 表面黏著$二_元件。w丨切騎外形成雙向 以下再針對本發明各製程之詳細實施方式作 明,其中: 201131670 ΘΒ 如第五至第七圖所示,前述第—步驟 片〗0與基板20容易燒結熔接 4使擴政反 曰曰 片ίο與絲心間妓―在擴散後 散後晶片10與基板20能相互燒結熔拯。 ’、’、 該基板2〇實施時,基板2()的材質加是非導體,例如. 陶曼、玻璃等,並且在該.或玻璃基板2。触可以設置金 屬化的接合層21,以治慎擴散後 、 的目的。前述基板20頂面接合Η〜士4層魏结炫接 HU施時,可以利用 式製成厚難合層,或者利料射式製成_接合層。 再者,為達到更好的散熱效果,該基板 質也可以是導體,例如:金、銀、銅、鐵、轉金屬,或= 較南阻值丰導體寺替代,此基板2〇的材質如果為導體或半導 體實施例時’為確保達物_胞片1Q以及防潮絕緣的 效果’基板20庵部需設置—保護層22。 由方、基板:0相對方>擴散後晶片]〇比較不易變形、剛性 強’所以在擴散後晶片1〇與基板2〇燒結溶接共構後,若擴散 後晶片川蝕刻開溝過深,或是該擴散後晶片1〇研磨過薄時, 擴散後晶>1丨()也不容易發生斷裂問題,因此較不怕碰撞,而 且具有縮小體積的功效。 如第五、第九圖所示,前述第三步驟202在擴散後晶片 10上的複數隔_槽内填Λ‘絕緣物f ]2,實施時,可以填充 玻璃或是長氧化層等各種可以達到隔離電極n的實施方式實 201131670 施設置。 如第五、第+ 片⑺表面金屬L圖所示,前述第四步驟203巾,對擴散後晶 成所有的功其目的是使電極11易於黏著或焊接,並完 電極丨丨上,' 衣作,至屬化後還可以在表面金屬化的每一 楚 ' ^"刷或南溫焊接方式增設一金屬電極板13,如 弟十一圖所示;jf八® ^ 切割後進;r 主屬電極板13的設置亦可以在第五步驟2 〇4 如第五、第十_ 丁一圖所不,除此之外,為強化製程後每一單 固二,面黏著型二極體元件4〇之絕緣保護,可以在每一個 二面翁型—域元件W除電極n以外的外表面上增加設置 一絕緣層.該絕緣㈣實施時可以是固_液_氧樹脂 (EPOXY)或絕緣擦,以達到絕緣保護之目的。 、如第五、第十三圖所示,上述製程中,若擴散後晶片⑺ 為雙面擴散型,切概可以形成雙面擴散财晶粒啊請一併 參閱第第十颂),則可以令前述單—表面黏著型二_元件 40的兩個電極u為P/N電極lu、112,並建構在同_平面上 相互絕緣隔離,即形成單向表面黏著型二極體元件。 如第五、第十四圖所示,本單向表面黏著型二極體元件穿』 程貫施例與前述步驟不同之處,是由於擴散後晶片1〇為雙面 擴散型’擴散後晶片10必須分隔成PPNNPP……複數^極 ni、⑴、112、112 ’因此在進行第三步驟202時,不必在 N/N間112、112的溝槽内填入絕緣物質]2,以便在進行苐四 201131670 步驟2〇3時能同時對咖間的溝槽、以及 邮金屬化;此_間,溝槽、】12 開溝或黃光顯影製程設置之。 、㈣_ 如第五、第十五圖所示,此實施例中, 對擴散後晶片表面金屬化時, 二四步驟加 1丨2、】丨2咖騎絲,批在電極 需再對_電極m、m門.,'签 々驟2(M切*J前, ,_ , . ~間日、]溝槽内填入絕緣物質12,如第 ”、七_示,則第五步驟2〇4切割後,即可分離 f Γ表面黏著型m件丨G,且每-單—表面黏著型_ 件之表面均具有兩個建構在同—平面上相互絕緣隔離 2刚電極⑴、】】2,使每—單—個體形成可以直接應用的 表面黏著型二極體元件40。 為強化製裎後每-表面黏著型二極體元件4〇之絕緣保 護’可以31擇在每—個表面黏著型二極體元件4〇除電極η以 _:表面上增加設置-絕緣層60,該絕緣層6〇實施時可以 疋U紅%氧祕脂(ΕΡΟχγ)或絕緣膠等,以達到絕緣保護 之目的。 錯由上述步驟,本發明硬晶片與基板20共構表面黏著型 二極體τΐ件4G結構可以分為單向及雙向二極體_構造,以 下作更進一步的說明: (1)雙向表面黏著型二極體元件40結構如下: 如第十―、十八、十九圖所示,—種表面黏著型二極體元 201131670 件4〇,係包括:一單面擴散型石夕晶粒ι]〇以及— 110底面燒結雜之基錢,其中,晶㈣底面與^ 如之間妓-耐高溫之合金焊材5Q,以㈣晶粒m鮮板 相互燒結接合;所述㈣粒⑽兩電極之四㈣設有填充 絕緣物質!2之隔離溝槽,以分隔出兩個建構於同—平面上之 ㈣極m、ηι或丽.電極112、112,且每一電極^外表 面設有金屬化導接層14。 (2)單向表面黏著型二極體元件4〇結構如下: 如第十七至十九圖所不,—種表面黏著型二極體元件4〇, 係包括:-雙面擴散型石夕晶粒12〇以及一與該石夕晶粒⑼底面 燒結溶接共構之基板2〇,射,财晶粒12()絲與基板如 之間設置-耐高溫之合金焊材5G,以供抑日粒與基板2〇相互Furthermore, in order to strengthen the per-surface adhesion type: (4) (4) of the polar body component, the implementation of the time is also every 槪 槪 二 验 验 验 四 (4); ^ on the outer surface of the set - insulation layer 'this can be implemented as a solid resin (EPOXY ) or insulating rubber 'to achieve the purpose of insulation protection ~ U, in the above process, if the diffusion of the wafer is double-sided diffusion type, after cutting can form a double-sided diffusion type of stone crystal, so that the above i - in two + The two electrodes on the same plane and insulated from each other are made up of the 201131670 pole, forming a unidirectional surface-adhesive diode component. The unidirectional surface-adhesive diode device process embodiment differs from the previous steps in that the wafer is double-sided diffusion type after diffusion, and the wafer must be divided into PPNNPP after diffusion....··········· When the third step is performed, the insulating material is not filled in the trench between N/N, so that the trench between the N/N and the surface of the p'N electrode are simultaneously made in the fourth step. The vacant trenches may be provided with side trenches or yellow light before the fourth step. In this embodiment, since the fourth step is to metallize the electrode surface of the wafer after diffusion, the metallization portion also includes the groove surface between the faces, so before the five-step cutting, the groove between the gallbladders Filling the insulating material inside, the fifth step after cutting can be separated into a plurality of single-surface-adhesive diodes, and the surface of the surface-adhesive diode has two structures in the same plane ===employed The electrode, such that the surface-adhesive diode of the unidirectional surface-adhesive diode structure formed by the above steps can be directly smashed as follows: The surface diffusion type Shi Xijing and the - 矽 矽 矽 矽 矽 矽 烧结 烧结 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 ' 矽 ' ' ' For the periphery of the 矽 grain and the base of the 曰曰 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 a conductive layer, the conductive layer is composed of one of the electrodes Extending between the isolation trench on the side and the insulating material. Other embodiments of the one-way surface-adhesive diode element of the present embodiment are the same as the embodiment of the two-way surface-adhesive diode element, and are not described herein. Compared with the prior art, the present invention "the method and structure for fabricating a surface-bonded diode component of a germanium wafer and a substrate" can simplify the process of the surface-adhesive diode to achieve the purpose of shortening the working time and manufacturing. After the diffusion, the wafer is not easy to be broken, and the surface-adhesive diode component after the cutting and molding can be directly applied, and has the advantages of reduced volume and convenient use. [Embodiment] Hereinafter, according to the technical means of the present invention, embodiments suitable for the present invention are listed, and the following description is made in conjunction with the following: As shown in the fifth to seventh embodiments, the present invention "co-fabricated surface of the wafer and the substrate" The manufacturing method and structure of the adhesive diode component comprises the following steps: First step 200: laminating a diffused wafer 10 and a high-temperature resistant high-strength substrate 20, and then diffusing the wafer 10 forms a comon 30 with the substrate 20. The second step 20]: as shown in the fifth and eighth figures, the surface of the diffused wafer_1〇 is etched to form a plurality of isolation trenches, so that 10 201131670 is expanded to form a plurality of positive films 10 Electrodes U are arranged to be arranged in isolation on the same plane. The second step 202: fill the insulating material 12 in the plurality of isolation trenches on the 10th and the fifth R sheets _ $9, and after the surface is removed, the fourth step 703. 11 insulated from each other. In the fifth and tenth diagrams, the surface of the electrode 11 of the wafer 10 after diffusion is metallized, and the electrical characteristics of the electrode 11 are extended to complete the fabrication of all the functional lines. The fifth step 204: as in the fifth, tenth, and tenth graphs, the comon 3〇 formed by the diffusion of the wafer 10 and the substrate 2〇 is cut to separate a plurality of single-individuals, such as the tenth As shown in the second figure, each single individual surface has two electrodes 11' constructed on the same plane and insulated from each other, so that each-single-individual forms a single-surface-adhesive diode element 40 that can be directly applied. In the process of the above process, if the wafer 1〇 is a single-sided diffusion type after diffusion, the cut-off type ^ m ' can make the two-surface adhesion type plates be constructed on the same plane and insulated from each other by two electrodes] Ρ/Ρ Or Ν/Ν electrodes (1), 112 ( , , , , surface adhesion $ _ components. w 丨 cut outside the formation of the two-way and below for the detailed implementation of the various processes of the present invention, wherein: 201131670 ΘΒ such as the fifth to the As shown in the seventh figure, the first step sheet 0 and the substrate 20 are easily sintered and welded 4 to make the expansion reaction sheet ίο and the silk core. After the diffusion, the wafer 10 and the substrate 20 can be sintered together. , ', when the substrate 2 is implemented, the material of the substrate 2 () Adding a non-conductor, for example, Tauman, glass, etc., and on the glass substrate 2. The contact can be provided with a metallized bonding layer 21 for the purpose of careful diffusion. The top surface of the substrate 20 is bonded to the substrate 4 When the layer of Wei knot is connected with the HU, it can be made into a thick and difficult layer, or a ray joint can be made into a _ joint layer. Furthermore, in order to achieve better heat dissipation, the substrate can also be a conductor, for example : gold, silver, copper, iron, metal, or = replace the south resistance value of the conductor. If the material of the substrate is a conductor or a semiconductor embodiment, 'to ensure the material_cell 1Q and moisture-proof insulation. Effect 'The top of the substrate 20 is required to be provided - the protective layer 22. The square, the substrate: 0 opposite side > the wafer after diffusion] is less susceptible to deformation and strong in rigidity, so after the diffusion, the wafer 1〇 and the substrate 2 are sintered and fused together. After that, if the wafer is etched too deep after the diffusion, or if the wafer is too thin after the diffusion, the diffusion crystal >1丨() is not prone to the fracture problem, so it is less afraid of collision and has a shrinkage. The effect of volume. As shown in the fifth and ninth In the third step 202, after the diffusion, the plurality of spacers in the wafer 10 are filled with the 'insulator f'2, and when implemented, the glass or the long oxide layer can be filled with various embodiments that can reach the isolation electrode n. As shown in the fifth and fifth (7) surface metal L diagrams, the fourth step 203 of the foregoing step, after the diffusion, crystallizes all the work for the purpose of making the electrode 11 easy to adhere or solder, and the electrode is placed on the electrode. 'clothing, after the genus can also be used in the surface metallization ^ ^ " " brush or South temperature welding method to add a metal electrode plate 13, as shown in the eleventh figure; jf eight ® ^ cutting backward; r The setting of the main electrode plate 13 can also be performed in the fifth step 2 〇4, such as the fifth and tenth, but in addition, in order to strengthen the single solid two after the process, the surface-adhesive diode Insulation protection of the body element 4〇, an insulating layer may be added on the outer surface of each dihedral type domain element except the electrode n. The insulation (4) may be solid-liquid_oxygen resin (EPOXY) when implemented. Or insulated to achieve insulation protection. As shown in the fifth and thirteenth drawings, in the above process, if the wafer (7) is a double-sided diffusion type after diffusion, it can form a double-sided diffusion grain, please refer to the tenth 颂), then The two electrodes u of the aforementioned single-surface-adhesive two-element 40 are P/N electrodes lu, 112, and are constructed to be insulated from each other on the same plane, that is, to form a unidirectional surface-adhesive diode element. As shown in the fifth and fourteenth figures, the unidirectional surface-adhesive diode component is different from the foregoing steps in that the wafer 1 is a double-sided diffusion type after diffusion. 10 must be divided into PPNNPP ... complex ^ pole ni, (1), 112, 112 ' Therefore, in the third step 202, it is not necessary to fill the trenches of the N / N between 112, 112 into the insulating material] 2, in order to proceed苐四201131670 Step 2〇3 can simultaneously be used for the groove between the coffee room, as well as the metallization of the post; this _, groove,] 12 trench or yellow light development process set. (4) _ As shown in the fifth and fifteenth figures, in this embodiment, when the surface of the wafer after diffusion is metallized, two or four steps are added, and the electrode is required to be re-applied to the electrode. m, m gate., 'signing step 2 (M cut * J before, , _ , . ~ between the day, the groove) filled with insulating material 12, such as the first, seven_ show, then the fifth step 2〇 4 After cutting, the surface of the f Γ surface-adhesive type 丨G can be separated, and the surface of each-single-surface-adhesive type has two structures which are insulated from each other on the same plane. 2 rigid electrodes (1), 】 2 So that each-single-individual can form a surface-adhesive diode element 40 that can be directly applied. In order to strengthen the insulation protection of each surface-bonded diode element after the crucible is made, it can be adhered to each surface. The diode element 4 removes the electrode η from the surface of the _: surface-insulating layer 60, and the insulating layer 6 〇 can be 疋U red% oxygen secret grease (ΕΡΟχγ) or insulating glue to achieve insulation protection According to the above steps, the structure of the surface-bonded diode τ 4 4G of the hard wafer and the substrate 20 of the present invention can be divided into one-way and two-way diodes. _Structure, the following is further explained: (1) The structure of the bidirectional surface-adhesive diode element 40 is as follows: As shown in the tenth, eighteenth, and nineteenth, the surface-adhesive diode element 201131670 4〇, the system includes: a single-sided diffusion type Shixi grain ι] 〇 and - 110 bottom sintering mixed base money, wherein the crystal (four) bottom surface and ^ such as 妓 - high temperature alloy welding material 5Q, to (4) The grain m fresh plates are sintered and joined to each other; the four (four) electrodes of the (four) particles (10) are provided with an isolation trench filled with an insulating material! 2 to separate two (four) poles m, ηι or 丽 which are constructed on the same plane The electrodes 112, 112, and the outer surface of each electrode is provided with a metallized conductive layer 14. (2) The unidirectional surface-adhesive diode element 4〇 structure is as follows: as shown in the seventeenth to nineteenth, a surface-adhesive diode element 4〇, comprising: a double-sided diffusion type 夕 晶粒 晶粒 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与12 () between the wire and the substrate such as - high temperature alloy welding material 5G, for the suppression of the grain and the substrate

Ul ’所树晶粒12Q兩電極之四周均設有填充絕緣物質 12之隔離溝槽,以分隔出兩個建構於同—平面上之膽電極 U ’且母—電極11外表面金屬化設置導接層Μ,該導接層!4 由其中f;fe 11延伸到其側邊之隔離溝槽與絕緣物質U之 貝叫,前述基板2〇的材質可以是非導體,例如··陶究、 玻璃等而且’麵莞等基板2〇頂面也可以設置金屬化的接 口層21’以達到與擴散後晶片1()容易層疊燒結炼接的目的。 而且則迷陶莞等基板2〇頂面接合層21實施時,可以是以印 刷方式衣成的厚膜接合層21,或者獅驗方式製成的薄膜 201131670 接合層21。 再者,為達到更好的散熱效果,該基板20實施時,其材 質也可以是導體,例如··金、銀、銅、鐵、鋁等,或可使用較 高阻值半導體替代;此基板20的材質如果為導體或半導體之 實施例時,為確保達到保護擴散後晶片10以及防潮絕緣的效 果,金屬基板20底部需設置一保護層22。此外,實施時,也 可以視實際組裝需要,在前述金屬化導接層14的外表面再設 置一方便組裝的金屬電極板13,以達到容易加工組裝的目的。 再者,為強化每一表面黏著型二極體元件40之絕緣保 護,實施時還可以在每一個表面黏著型二極體元件40除電極 1]以外的外表面上設置一絕緣層60,該絕緣層60實施時可以 是固態或液態環氧樹脂(EPOXY)或絕緣膠,以達到絕緣保護之 目的。 上述各名稱係為方便描述本發明之技術内容所定,而非用 以限制本案之權利範圍;是以,舉凡依據本案之創作精神所作 的等效元件轉換、替代,均應涵蓋在本案之保護範圍内·謹此 聲明。 201131670 【圖式簡單說明】 第一圖係習知表面黏著型二極體之製造流程圖。 第二圖係習知表面黏著型二極體之結構側視圖,用以表示電氣 接腳没置在位於晶粒左右兩側的兩極。 苐三圖係習知表面黏著型二極體之結構側視圖,用以表示晶粒 的兩極分別設置於晶粒的上下兩側,其中—電氣接腳設 • 置在純的下方電極處m㈣上方電極處打線 • 接合設置另一電氣接腳之示意圖。 知表面黏著型二極體之結構側視圖,用以表示晶粒 的兩極分別言史置於晶粒的上下兩側,並在晶粒上下兩側 各銲接設置一電氣接腳,並將電氣接腳彎折簡一側之 示意圖。 第五圖係本發日狀製造步驟流程圖。 第六圖係表示本發明由-擴散後w與-基板層疊燒結成共 Φ 構體之立體分解圖。 . 第七_、麵本發明由―擴散後w與—基錢疊燒結成共 構體之剖面示意圖。 —_表讀散後晶#為單面擴散型,且同-平面上相互絕 第、同離的兩個i極為p/p電極之共構體剖面示意圖。 圖係絲擴散後晶片為單面擴散型,且複數隔離溝槽内填 巴表物貝’令複數建構在同-平面上的P/P電極相互 絕緣隔離之共構體剖面示意圖。 17 201131670 第十圖係表示擴散後晶片為單面擴散型,且電極表面金屬化之 共構體剖面示意圖。 第十一圖係表示擴散後晶片為單面擴散型,且表面金屬化的每 一電極設置有一金屬電極板之共構體剖面示意圖。 第十二圖係表示擴散後晶片為單面擴散型的單一個體矽晶片 與基板共構表面黏著型二極體元件結構剖面示意圖。 弟十二圖係表不擴散後晶片為雙面擴散型5將電極分隔為P /N 兩極之共構體剖面示意圖。 第十四圖係表示擴散後晶片為雙面擴散型,且擴散後晶片表面 金屬化部包含N/N電極間的溝漕表面之共構體剖面示 意圖。 第十五圖係表示擴散後晶片為雙面擴散型,且於電極間 的溝漕内填入絕緣物質之共構體剖面示意圖。 第十六圖係表示擴散後晶片為雙面擴散型,且表面金屬化的每 一電極設置有一金屬電極板之共構體剖面示意圖。 弟十七圖係表不擴散後晶片為雙面擴散型的單一個體石夕晶片 與基板共構表面黏著型二極體元件結構剖面示意圖。 第十八圖係表示本創作單一個體矽晶片與基板共構表面黏著 型二極體元件的俯視圖。 第十九圖係表示本創作單一個體矽晶片與基板共構表面黏著 型二極體元件的側視圖。 201131670 【主要元件符號說明】 1 〇擴散後晶片 110單面擴散型矽晶粒 120雙面擴散型矽晶粒 11電極 111 P電極 112N電極 12絕緣物質 13電極板 14導接層 20基板 21接合層 22保護層 30共構體 40表面黏著型二極體元件 50焊材 60絕緣層 200第一步驟 201第二步驟 202第三步驟 203第四步驟 204第五步驟Ul's tree 12Q two electrodes are provided with isolation trenches filled with insulating material 12 to separate two bile electrodes U' constructed on the same plane and metallization of the outer surface of the mother-electrode 11 Connect layer, the conductive layer! 4 The material of the substrate 2〇 from which the f;fe 11 extends to the side of the isolation trench and the insulating material U may be a non-conductor, for example, ceramics, glass, etc. The metallized interface layer 21' may also be provided on the top surface to achieve the purpose of easy lamination and sintering of the wafer 1 after diffusion. Further, when the top surface bonding layer 21 of the substrate 2 such as the ceramics is used, the thick film bonding layer 21 which is printed by the printing method or the film 201131670 bonding layer 21 which is made by the lion test method may be used. Furthermore, in order to achieve a better heat dissipation effect, when the substrate 20 is implemented, the material thereof may also be a conductor, such as gold, silver, copper, iron, aluminum, etc., or may be replaced by a higher resistance semiconductor; When the material of 20 is an embodiment of a conductor or a semiconductor, a protective layer 22 is provided at the bottom of the metal substrate 20 in order to ensure the effect of protecting the wafer 10 and the moisture-proof insulation after diffusion. In addition, during implementation, a metal electrode plate 13 which is conveniently assembled may be disposed on the outer surface of the metallized conductive layer 14 for the purpose of easy processing and assembly. Furthermore, in order to strengthen the insulation protection of each surface-adhesive diode element 40, an insulating layer 60 may be disposed on the outer surface of each of the surface-adhesive diode elements 40 except the electrode 1]. The insulating layer 60 can be implemented as a solid or liquid epoxy resin (EPOXY) or an insulating paste for the purpose of insulation protection. The above names are intended to describe the technical content of the present invention, and are not intended to limit the scope of the present invention; therefore, the equivalent component conversion and substitution according to the creative spirit of the case should be covered in the scope of protection of the present case. Inside, please declare. 201131670 [Simple description of the diagram] The first diagram is a manufacturing flow chart of a conventional surface-adhesive diode. The second figure is a side view of the structure of a conventional surface-adhesive diode to indicate that the electrical pins are not placed on the two poles on the left and right sides of the die. The third figure is a side view of the structure of the surface-adhesive diode, which is used to indicate that the two poles of the die are respectively disposed on the upper and lower sides of the die, wherein the electrical pin is disposed above the pure lower electrode m (four) Wire the electrode • Join the schematic diagram of another electrical pin. A side view of the structure of the surface-adhesive diode is used to indicate that the two poles of the die are respectively placed on the upper and lower sides of the die, and an electrical pin is soldered on the upper and lower sides of the die, and the electrical connection is made. A schematic diagram of the side of the foot bent. The fifth figure is a flow chart of the manufacturing process of the present invention. Fig. 6 is a perspective exploded view showing the present invention in which a w-and-substrate is laminated and sintered into a co-Φ structure. Seventh, the present invention is a schematic cross-sectional view of a constitutive body formed by a "diffusion" of w and a base. —_表读散后晶# is a one-sided diffusion type, and the two-electrode p/p electrodes of the same plane are separated from each other in the same plane. After the diffusion of the filaments, the wafer is a single-sided diffusion type, and the complex isolation trenches are filled with the surface of the spacers to form a cross-sectional view of the composite structures in which the P/P electrodes on the same plane are insulated from each other. 17 201131670 The tenth figure shows the cross-section of the co-structure where the wafer is single-sided diffusion type and the surface of the electrode is metallized. The eleventh figure shows a cross-sectional view of a co-structure in which a metal electrode plate is provided with a metal electrode plate for each surface of the surface after metallization. The twelfth figure is a schematic cross-sectional view showing the structure of the surface-bonded diode element of the single-element wafer with the substrate being diffused and the single-sided diffusion type. The twelfth figure shows that the wafer is a double-sided diffusion type, and the electrode is divided into a cross-section of the P/N two-pole. Fig. 14 is a view showing the cross-sectional view of the wafer after the diffusion is a double-sided diffusion type, and the surface of the wafer after metallization is diffused to include the surface of the gully between the N/N electrodes. The fifteenth diagram shows a cross-sectional view of the co-structure in which the wafer is diffused and the insulating material is filled in the trench between the electrodes. The sixteenth figure shows a cross-sectional view of a co-structure in which a metal electrode plate is provided with a metal electrode plate for each electrode whose surface is metallized after diffusion. The seventeenth figure shows a cross-sectional view of the structure of the surface-bonded diode component of the single-element slab of the double-sided diffusion type. Figure 18 is a plan view showing the creation of a single individual tantalum wafer and substrate co-fabricated surface-adhesive diode element. The nineteenth figure is a side view showing the creation of a single individual germanium wafer and a substrate co-fabricated surface-adhesive diode element. 201131670 [Description of main component symbols] 1 〇 Diffusion wafer 110 single-sided diffusion type 矽 grain 120 double-sided diffusion type 矽 grain 11 electrode 111 P electrode 112N electrode 12 insulating material 13 electrode plate 14 conductive layer 20 substrate 21 bonding layer 22 protective layer 30 common body 40 surface-adhesive diode element 50 solder material 60 insulating layer 200 first step 201 second step 202 third step 203 fourth step 204 fifth step

Claims (1)

201131670 七、申請專利範圍: 1、一種矽晶片與基板共構表面黏著型二極體元件之製造方法, 該製造方法係包括下列步驟: 第一步驟:將一擴散後晶片與一可耐高溫之高強度基板層疊 燒結溶接後,令擴散後晶片與基板形成·-共構體; 第二步驟:對該擴散後晶片的表面進行蝕刻開溝,以形成複 數隔離溝槽,使擴散後晶片上形成複數個建構在 同一平面上相互隔離排列的電極; 第三步驟:在擴散後晶片上的複數隔離溝槽内填入絕緣物 質,令複數建構在同一平面上的電極相互絕緣隔 離, 第四步驟:對擴散後晶片之電極表面金屬化,以延伸電極的 電氣特性,完成所有的功能線路製作; 第五步驟:將擴散後晶片與基板所形成之共構體進行切割, 以分離出複數個單一個體,每一單一個體表面均 具有兩個建構在同一平面上且相互絕緣隔離的 電極,使每一單一個體形成可以直接應用的單一 表面黏著型二極體元件。 2、如申請專利範圍第丨項所述之砍晶片與基板共構表面黏著型二 極體元件之製造方法,其中1擴散後晶片為單面擴散型·.以令 複數個建構在同一平面上相互隔離排列的電極建構在同一平 面上且相互絕緣隔離的兩個電極為P/P電極或M/N電極,形成 201131670 雙向表面黏著型二極體元件。 3、如申請專梅_酬述切^與基板共構表面黏著型二 »肢凡件之錢方法,其中,擴散後日日日片為雙面擴散型,複數 個建構在同-平面上相互隔離排列的電極為…電極, 進行第三步驟時,__溝槽内未填人絕緣物質,使— 驟同時對刪間的溝槽、以及p、N電極面作金屬化後,料201131670 VII. Patent application scope: 1. A method for manufacturing a surface-bonded diode component of a tantalum wafer and a substrate, the manufacturing method comprising the following steps: First step: a diffusion-diffused wafer and a high temperature resistant After the high-strength substrate is laminated and sintered, the wafer and the substrate are formed into a co-complex after the diffusion; the second step: etching and trenching the surface of the diffused wafer to form a plurality of isolation trenches to form on the wafer after diffusion a plurality of electrodes which are arranged to be mutually isolated on the same plane; the third step: filling the plurality of isolation trenches on the wafer after the diffusion into the insulating material, so that the plurality of electrodes constructed on the same plane are insulated from each other, the fourth step: Metallizing the surface of the electrode after diffusion, and completing all the functional circuit fabrication by extending the electrical characteristics of the electrode; Step 5: cutting the comon formed by the diffusion of the wafer and the substrate to separate a plurality of single entities Each single individual surface has two electrodes constructed on the same plane and insulated from each other, so that each A single individual forms a single surface-adhesive diode component that can be directly applied. 2. The method for manufacturing a surface-bonded diode component of a chip-and-substrate co-fabrication as described in the scope of the patent application, wherein the wafer after diffusion is a single-sided diffusion type, so that the plurality of structures are constructed on the same plane. The electrodes which are arranged in isolation on the same plane and are insulated from each other are P/P electrodes or M/N electrodes, forming a 201131670 bidirectional surface-adhesive diode element. 3. For example, if you apply for a special _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The electrodes arranged are ... electrodes. When the third step is performed, the insulating material is not filled in the trench, so that the trenches and the p and N electrode surfaces are metallized at the same time. 五步驟切騎,對_ _溝槽内填域緣物質,令第五步驟 切割後,分離出複數個單一表面勒著型二極體元件,且每一單 一表面黏著型二極體元件之表面均具有兩個建構在同一平面 上相互絕緣隔離的P/N電極。 4、如申請專利1 請第2或第3項所述之抑日片與基板共構表面點 2型二_树之製造方法,其中,擴散後晶片與基板之間進 一步設置-耐高溫之合金焊材,以供擴散後;與基板相互燒 結熔接。 5、 如申請專利範圍第2或第3項所述之㈣片與基板共構表面黏 著型二極體元件之製造方法,其中,基板的材質為非導體。 6、 如申請專利範圍第2成第3項所述之碎晶片與基板共構表面黏 著型二極體元狀製造方法,其巾,基滅f騎體或半導 體,且基板底部設置/保護層。 7、 :申請專利範圍第2或第3項所述之料片與基板共構表面黏 者型-極體元件之製造方法,其中,絕緣物質為玻璃'氧化層。 8、 如申請專利|_ 2 Μ 3項所述之料片與基板共構表面黏 201131670 在表面金屬化的每—電極 著型二極體元件之製造方法,其中 上由設置一延伸金屬特性的金屬電極板。 9、如申請專概圍第2或第3 第五步驟後,在每—個單 的外表面上設置一絕緣保護 著型二極體元件之製造方法之石W與基板共構表面黏 一表面黏著型二極體除電極以外 的絕緣層。 10 一種表面黏箸型二極體元 以及-盥該矽%括:一單面擴散型矽晶粒 和广而 粒底面燒辦接共構之基板,其中,晶 粒底面與基板之間設置 , 忉呵,皿之合金焊材,以供矽晶片與 土反目互大疋結士谷接’且石夕晶粒兩電極的四周設有填充絕緣物 質之隔離溝槽’以分隔出兩個建構於同一平面上之p/p或跳 電極,且每—雜外表φ設有金屬化導接層。 11 種表面4著型—極體元件,係包括:—雙面擴散型咬晶粒 以及-與騎底面.雜共構之基板,其中,該發晶 粒底面與基板之間設置—耐高溫之合金焊材,以㈣晶粒與 基板相互燒結接合:切晶粒兩電_四周設有填充絕緣物 質之隔離溝槽,以分隔出兩個建構於同-平面上之P/N電極, 且母一電極外表面金屬化設置導接層,該導接層由其中—電 在L伸到其側邊之隔離溝槽與絕緣物質之間。 !2、如申請專利範圍第10或第n項所述之表面黏著型二極體元 件其中,基板材質為非導體或較高阻值之半導體。 13、如申請專利範圍第10或第II項所述之表面黏著型二極體元 201131670The five-step cutting is performed, and the _ _ trench is filled with the margin material, and after the fifth step is cut, a plurality of single surface-stretching diode elements are separated, and the surface of each single surface-adhesive diode component is separated. Each has two P/N electrodes constructed to be insulated from each other on the same plane. 4. As claimed in claim 1, the method for manufacturing a surface-integrated surface type 2 bis-tree of the substrate and the substrate according to the second or third aspect, wherein the diffusion-resistant wafer and the substrate are further provided with a high-temperature resistant alloy After the welding material is used for diffusion; the substrate is sintered and welded to each other. 5. A method of manufacturing a (4) sheet and substrate co-fabricated surface-adhesive diode element according to the second or third aspect of the patent application, wherein the material of the substrate is a non-conductor. 6. A method for fabricating a surface-bonded diode of a broken wafer and a substrate as described in claim 2, claim 3, wherein the substrate is provided with a substrate or a semiconductor, and the substrate is provided with a protective layer. . 7. The method of manufacturing a surface-adhesive-polar element of a web and a substrate according to the second or third aspect of the patent application, wherein the insulating material is a glass oxide layer. 8. If the application of the patent|_ 2 Μ 3 of the material and the substrate co-structure surface adhesion 201131670 The surface metallization of each electrode-type diode component manufacturing method, wherein the surface is provided by an extended metal characteristic Metal electrode plate. 9. If the second step or the third step of the application is applied, a method for manufacturing the insulating protective diode component is provided on the outer surface of each of the single surfaces. An insulating layer other than the electrode of the adhesive type diode. 10 A surface-adhesive diode element and a substrate comprising: a single-sided diffusion type germanium grain and a wide-grained bottom-fired substrate, wherein a bottom surface of the crystal grain is disposed between the substrate and the substrate, Hehe, the alloy welding material of the dish, for the 矽 wafer and the soil opposite to each other, the 士 谷 谷 接 且 且 且 且 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石The p/p or jump electrodes on the same plane, and each of the miscellaneous outer surfaces φ is provided with a metallized conductive layer. 11 kinds of surface 4-type polar body components, including: - double-sided diffusion type bite die and - a substrate that is grounded and hetero-co-structured, wherein the bottom surface of the hair die is disposed between the substrate and the substrate - high temperature resistance Alloy welding consumables, (4) sinter bonding between the die and the substrate: dicing the two sides of the die _ surrounded by isolation trenches filled with insulating material to separate the two P/N electrodes constructed on the same plane, and the mother An outer surface of the electrode is metallized with a conductive layer, the conductive layer being between the isolation trench and the insulating material extending from the side to the side. 2. The surface-adhesive diode component according to claim 10 or n, wherein the substrate material is a non-conductor or a higher resistance semiconductor. 13. The surface-adhesive diode element as described in claim 10 or II of the patent application 201131670 件,其中,基板為底部設置保護層之導體或半導體。 14、如申請專利範圍第10或第11項所述之表面黏著型二極體元 件,其中,二極體元件在電極以外的表面設置絕緣層。 23The substrate is a conductor or a semiconductor provided with a protective layer at the bottom. The surface-adhesive diode element according to claim 10, wherein the diode element is provided with an insulating layer on a surface other than the electrode. twenty three
TW099106657A 2010-03-08 2010-03-08 Manufacturing method and structure of surface mount diode component of silicon chip-substrate integrated packaging TW201131670A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW099106657A TW201131670A (en) 2010-03-08 2010-03-08 Manufacturing method and structure of surface mount diode component of silicon chip-substrate integrated packaging

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW099106657A TW201131670A (en) 2010-03-08 2010-03-08 Manufacturing method and structure of surface mount diode component of silicon chip-substrate integrated packaging

Publications (2)

Publication Number Publication Date
TW201131670A true TW201131670A (en) 2011-09-16
TWI402923B TWI402923B (en) 2013-07-21

Family

ID=49225975

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099106657A TW201131670A (en) 2010-03-08 2010-03-08 Manufacturing method and structure of surface mount diode component of silicon chip-substrate integrated packaging

Country Status (1)

Country Link
TW (1) TW201131670A (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3489961A (en) * 1966-09-29 1970-01-13 Fairchild Camera Instr Co Mesa etching for isolation of functional elements in integrated circuits
JPS5718348B2 (en) * 1974-06-07 1982-04-16
US4667189A (en) * 1984-04-25 1987-05-19 Energy Conversion Devices, Inc. Programmable semiconductor switch for a display matrix or the like and method for making same
JPS6260234A (en) * 1985-09-09 1987-03-16 Fuji Electric Co Ltd Manufacture of semiconductor diode element
WO2001071819A2 (en) * 2000-03-20 2001-09-27 Sarnoff Corporation Surface pin device
US7829909B2 (en) * 2005-11-15 2010-11-09 Verticle, Inc. Light emitting diodes and fabrication methods thereof

Also Published As

Publication number Publication date
TWI402923B (en) 2013-07-21

Similar Documents

Publication Publication Date Title
CN104051337B (en) Manufacturing method and testing method for chip package of stereoscopically-stacked integrated circuit system
CN106531700B (en) A kind of chip-packaging structure and its packaging method
TW201133769A (en) Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
TW201101452A (en) Semiconductor device packages with electromagnetic interference shielding
TW201041054A (en) Electronic component manufacturing method and packaging structure thereof
CN103855122B (en) Encapsulation vertical power device and its manufacture method including compression stress
CN105957845A (en) Chip packaging structure with electromagnetic shield and manufacturing method thereof
TW200910571A (en) Multi-chip module package
CN106783783A (en) Power-type paster semiconductor element
CN103227276B (en) Light emitting semiconductor device and manufacture method thereof
JP6185449B2 (en) Solar cell and manufacturing method thereof
US10062820B2 (en) Interposer
US10892253B2 (en) Semiconductor device manufacturing method and semiconductor device
CN109801883A (en) A kind of fan-out-type stacking encapsulation method and structure
TW201242098A (en) LED package and method for manufacturing the same
TW201251074A (en) Solar cell module and method of manufacturing solar cell module
JP6773104B2 (en) Light emitting element and light emitting device
JP2013030793A (en) Manufacturing method of semiconductor device
TW201131670A (en) Manufacturing method and structure of surface mount diode component of silicon chip-substrate integrated packaging
CN102201368B (en) Production method and structure of silicon chip and substrate co-constructed surface adhesive diode element
CN109935556A (en) The manufacturing method of light-emitting diode encapsulation structure, heat-radiating substrate and heat-radiating substrate
TWI297923B (en)
TW201212132A (en) A method of semiconductor package with die exposure
US8404565B2 (en) Manufacturing method and structure of a surface-mounting type diode co-constructed from a silicon wafer and a base plate
US20130087197A1 (en) Concentrated photovoltaic solar cell packaging using laminated substrates and an open window overmolding process

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees