201101452 i μ— 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體封裝件，且特別是有 於一種具有電磁干擾防護罩之半導體封震件。 負 【先前技術】 半導體元件已經逐漸變得更加複雜，部分原因3 於半導體元件的需求漸漸趨向小尺寸及高處理逮度疋雖 然擁有小尺寸及高處理速度特性之半導體元件具^夕 優點’此些特性亦造成許多間題。具體來說，當時脈二 度（clock speed)增加時，可能會增加信號準位間之轉 換’導致電磁放射之料增加，且使得電磁放射的頻率 更南或波長更短。電磁放射可由來源半導體元件發出， 且可〜響，近之半導體元件。當位於鄰近半導體元件之 電^放射IBJ於&程度時，此些電磁放射可能影響半 體元件之運作。此現象有時被稱為電磁干i inteFfeFence，EMI)° 當半導體元 M k,J、a守，由於半導體元件位於電子系統中之整 度增加’使得電磁干擾之問題更加惡化。因此，位 近之半導體元件之電磁放射亦更趨嚴重。 本连^低包磁干擾之—種方法為遮蔽半導體封裝件内之 & a π件具體來說，可使用固定於封膠體之外部且 封膠接的導電殼體來遮蔽半導體元件。當由 ，丨、合、生 χ出之電磁放射傳遞至殼體之内表面時，至 曰k伤之輕射電性短路，因而減少了通過殼體 201101452 ， ι 1 w^^^or/v 並影響鄰近半導體元件之電磁放射的程度。同理，當由 鄰近半導體元件發出之電磁放射傳遞至殼體之外表面 時，亦會發生相似之電性短路，進而降低封膠體内之半 導體元件之電磁干擾。 雖然導電殼體可降低電磁干擾，使用殼體卻會造成 許多缺點。殼體通常是利用黏著劑而固定於半導體封裝 件之外部。不幸的是，黏著劑的特性可能會受溫度、濕 度或其它環境條件所影響而造成殼體之剝落或掉落。此 0 外，當將殼體固定於封膠體上時，殼體之尺寸與形狀應 符合封膠體之尺寸與形狀，且其誤差程度需相當微小。 在定位殼體及封膠體時，為了使殼體與封膠體之尺寸及 形狀相符合，可能會使得製造過程更為昂貴及費時。此 外，不同尺寸及形狀之半導體元件需要不同的殼體，更 增加了製造與不同封膠體相符合之殼體的製造成本及製 造時間。 基於上述原因而需要研發半導體封裝件及相關方 〇 法。 【發明内容】 本發明係有關於一種具有電磁干擾防護罩之半導體 封裝件。一實施例中，半導體封裝件包括基板單元、半 導體元件、封膠體及電磁干擾防護罩。基板單元包括上 表面、下表面、側表面及接地元件。側表面係鄰近於基 板單元之周圍而配置之側表面，且側表面係於基板單元 之上表面與下表面之間延伸。基板單元之側表面實質上 5 201101452 * ** •^-/-TVI /-1 為平面。接地元件係鄰近於基板單元之周圍配置，並對 應内部接地導孔之餘留部（remnant)。接地元件包括連 接表面，且連接表面係電性暴露於鄰近基板單元之上表 面之處。半導體元件係鄰近於基板單元之側表面而配 置，且電性連接至基板單元。封膠體係鄰近於基板單元 之上表面而配置，且覆蓋半導體元件。封膠體包括外部 表面，且外部表面包括側表面。封膠體之側表面係實質 上對齊於基板單元之側表面。電磁干擾防護罩係鄰近於 封膠體之外部表面而配置，且電性連接至接地元件之連 接表面。接地元件提供一電性通道（electrical pathway )’以將電磁干擾防護罩上的電磁放射 (electromagnetic emission)放電至接地端。 另一實施例中，半導體封裝件包括基板單元、半 體元件、封膠體及電磁干擾防護罩。基板單元包括第導 表面、一相對於s亥弟一表面之第二表面及導電層。導“ 層係配置於第一表面與第二表面之間。接地元件係於^ 電層與第二表面之間延伸。接地元件包括一側表面，、導 側表面係鄰近於基板單元之周圍而配置。半導體_ 且 鄰近於基板單元之第一表面而配置，並電性連接 ' 單元。封膠體係鄰近於基板單元之第一表面而配置'^板 覆蓋半導體元件。封膠體包括外部表面。電磁干擾防2 罩係鄰近於封膠體之外部表面而配置，並電性連接 4 地元件之侧表面。半導體封裝件之橫向輪廓係實質上 平面’且實質上垂直於基板單元第二表面。 本發明係有關於一種具有電磁干擾防護罩之半導 201101452 1 1 ο 封裝件之形成方法。一實施例中，此方法包括下列步驟。 首先’提供包括上表面、下表面及接地導孔之基板。接 地導孔係部分地延伸於基板之上表面與下表面之間。舉 =來說，每一個接地導孔之高度係小於基板之厚度。接 著，電性連接半導體元件至基板之上表面。然後，塗佈 封裝材料（molding material)於基板之上表面上，用 以升/成封衣結構。封裝結構係覆蓋半導體元件。再者， 形成切割狹縫。_狹縫係穿透封裝結構及基板，且切 ^縫係對齊於基板。如此—來，基板係被分離而形成 =单元。封裝結構係被分離而形成封膠體，且封 係鄰近於基板單元而配置。 " 導孔之㈣部對應於接地φ U外料面。接地 板單元之周圍而配置之=接地元件係鄰— :之外部表面及接地元件之連=:磁用干=^ 擾防護罩。 〜风冤磁干 ❹ ^讓本發明之上述内容能更明顯㈣ 車父佳實施例，並配合所附圖式，作詳細說明如下下文特舉— 【實施方式】 分。吻她關之部 7 201101452 * V» Γ\ 此處所用白勺組”表示—或多個元件的集合。例 如，-組層結構可包含單層結構或多層結構。—址中的 兀件可以是指該組的成員。—組中的元件可以相同或不 同的。在 同特徵。 此 例子中 組中的元件可具有一或多個共 、如祕所用，「鄰近」這個用詞係指接近或相鄰。葬 近之π件可彼此分離或可實際上或直接彼此接觸。在一 些例子中，鄰近之元件可彼此連接或彼此—體成形。 如此處所用，「内」、「内部」、「外」、「外部」、「上」 「Γιΐ:「下」、「向下」、「垂直」、「垂直地」、「側向」、 貝」之上」及「之下」係表示數個元件之間的 :關位置。例如，該些相關位置係依據圖示而定而非指 衣造或使用時，此些元件的特定方位。 上如此處所用，「連接於」、「被連接」及「連接」此些 γ係心操作上的耗接（c〇upling)或連結⑴呢⑻。 拉接的το件可能直接地彼此減，或可間接地彼此耦 例如疋透過另一組元件而連接。 =所用’「實質地」及「實質上」之此些用詞係 曰:目田之程度。當此些用詞與-事件或情況-同使 時’係指此事件或情況精確地發生，且事件或情況之 :生與所述相當接近’例如纽處所狀製造過程中之 典型的誤差程度。 導雷所用；「導電的」及「導電度」之用詞係指傳 帝%力。導電材料—般係指對於電流具有低阻抗 3零阻抗之材料。導電度以西門子/公尺（S.m·1)為單位。 201101452 :型的導電材料之導電度係大於104 s.m-i，例如至少約 ίΓ5Γ或至少約為106s.m-1。材料之導電度有時可 義為室溫下之;電度非特別明’材料之導電度係定 日^，先參照第1圖及第2圖°第1圖及第2圖綠示依 二本兔明之一實施例之半導體封裝件1〇〇。詳細地來 第1圖繪示半導體封裝件剛之立體圖。第2圖!會示半’ 導體封裝件1GG沿著第丨圖之剖面線。 oBACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor package, and more particularly to a semiconductor seal member having an electromagnetic interference shield. Negative [Prior Art] Semiconductor components have gradually become more complicated, in part because of the demand for semiconductor components, which tend to be smaller in size and higher in processing, although semiconductor components with small size and high processing speed characteristics have advantages. These characteristics also cause many problems. Specifically, when the clock speed is increased, it may increase the conversion between signal levels, resulting in an increase in the amount of electromagnetic radiation, and making the frequency of electromagnetic radiation more south or shorter. Electromagnetic radiation can be emitted from a source semiconductor component and can be audible to near semiconductor components. Such electromagnetic emissions may affect the operation of the semiconductor components when they are located at & This phenomenon is sometimes referred to as electromagnetic dryness, EMI). When the semiconductor elements M k, J, a, the increase in the uniformity of the semiconductor components in the electronic system is made, the problem of electromagnetic interference is further deteriorated. Therefore, the electromagnetic radiation of the semiconductor components in the vicinity is also more serious. The method of low magnetic interference is to shield the & a π component in the semiconductor package. Specifically, a conductive case fixed to the outside of the encapsulant and sealed can be used to shield the semiconductor component. When the electromagnetic radiation emitted by the sputum, the sputum, and the sputum is transmitted to the inner surface of the casing, the light-radiating electrical short-circuit to the 曰k injury is reduced, thereby reducing the passage through the casing 201101452, ι 1 w^^^or/v The extent to which electromagnetic emissions of adjacent semiconductor components are affected. Similarly, when electromagnetic radiation emitted by adjacent semiconductor elements is transmitted to the outer surface of the casing, a similar electrical short circuit occurs, thereby reducing electromagnetic interference of the semiconductor components in the sealing body. Although the conductive housing reduces electromagnetic interference, the use of the housing creates many disadvantages. The housing is typically secured to the exterior of the semiconductor package with an adhesive. Unfortunately, the properties of the adhesive may be affected by temperature, humidity or other environmental conditions that cause the shell to peel or fall. In addition to this, when the casing is fixed to the sealant, the size and shape of the casing should conform to the size and shape of the sealant, and the degree of error must be relatively small. In order to position the housing and the sealant, the manufacturing process may be more expensive and time consuming in order to conform to the size and shape of the sealant. In addition, different sizes and shapes of semiconductor components require different housings, which increases the manufacturing cost and manufacturing time of the housings that conform to different sealants. For the above reasons, it is necessary to develop semiconductor packages and related methods. SUMMARY OF THE INVENTION The present invention is directed to a semiconductor package having an electromagnetic interference shield. In one embodiment, the semiconductor package includes a substrate unit, a semiconductor component, a sealant, and an electromagnetic interference shield. The substrate unit includes an upper surface, a lower surface, a side surface, and a grounding member. The side surface is a side surface disposed adjacent to the periphery of the substrate unit, and the side surface extends between the upper surface and the lower surface of the substrate unit. The side surface of the substrate unit is substantially 5 201101452 * ** • ^-/-TVI /-1 is a plane. The grounding element is disposed adjacent to the periphery of the substrate unit and corresponds to the remaining portion of the internal grounding via. The ground element includes a connection surface and the connection surface is electrically exposed to an area adjacent the upper surface of the substrate unit. The semiconductor element is disposed adjacent to a side surface of the substrate unit and electrically connected to the substrate unit. The encapsulation system is disposed adjacent to the upper surface of the substrate unit and covers the semiconductor element. The encapsulant includes an outer surface and the outer surface includes a side surface. The side surface of the sealant is substantially aligned with the side surface of the substrate unit. The electromagnetic interference shield is disposed adjacent to the outer surface of the sealant and electrically connected to the connection surface of the ground element. The grounding element provides an electrical pathway to discharge electromagnetic radiation on the electromagnetic interference shield to ground. In another embodiment, the semiconductor package includes a substrate unit, a semiconductor component, an encapsulant, and an electromagnetic interference shield. The substrate unit includes a first guiding surface, a second surface opposite to a surface of the shai, and a conductive layer. The layer is disposed between the first surface and the second surface. The grounding element extends between the second layer and the second surface. The grounding element includes a side surface, and the leading side surface is adjacent to the periphery of the substrate unit. The semiconductor is disposed adjacent to the first surface of the substrate unit and electrically connected to the 'unit. The sealing system is disposed adjacent to the first surface of the substrate unit to cover the semiconductor element. The sealing body includes an external surface. The interference shielding 2 is disposed adjacent to the outer surface of the sealing body and electrically connected to the side surface of the element 4. The lateral outline of the semiconductor package is substantially planar 'and substantially perpendicular to the second surface of the substrate unit. There is a method for forming a package with a semiconductor shield having an electromagnetic interference shield. In one embodiment, the method includes the following steps. First, 'provide a substrate including an upper surface, a lower surface, and a ground via. The via hole extends partially between the upper surface and the lower surface of the substrate. For example, the height of each ground via is less than the thickness of the substrate. And electrically connecting the semiconductor component to the upper surface of the substrate. Then, a molding material is coated on the upper surface of the substrate for lifting/forming the sealing structure. The packaging structure covers the semiconductor component. Further, forming The slit is cut. The slit penetrates the package structure and the substrate, and the slit is aligned with the substrate. Thus, the substrate is separated to form a unit. The package structure is separated to form a sealant, and the seal is sealed. Arranged adjacent to the substrate unit. " The (4) portion of the via hole corresponds to the ground plane φ U outer material plane. The grounding plate unit is placed around the grounding element = adjacent: the external surface and the grounding element are connected =: magnetic Dry = ^ 防护 防护 。 冤 冤 冤 冤 冤 冤 冤 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让 让Kiss her off the department 7 201101452 * V» Γ \ The group used here" means - or a collection of multiple components. For example, the -layer structure may comprise a single layer structure or a multilayer structure. - The conditions in the address can refer to members of the group. - The components in the group can be the same or different. In the same feature. In this example, the elements in the group may have one or more common, such as secrets, and the term "proximity" means near or adjacent. The nearby π pieces may be separated from each other or may actually or directly contact each other. In some examples, adjacent elements may be connected to each other or to each other. As used herein, "inside", "inside", "outside", "outside", "upper" "Γιΐ: "down", "down", "vertical", "vertical", "lateral", shell "Upper" and "below" mean the position between several components: off. For example, the relevant positions are based on the drawings and are not intended to be a particular orientation of such elements. As used herein, "connected", "connected" and "connected" are used for γ-centered operation (c〇upling) or connection (1) (8). The pulled τ pieces may be directly subtracted from each other or may be indirectly coupled to each other, for example, by another set of elements. = The terms used in the words "substantially" and "substantially" are: the extent of the field. When such terms are used in conjunction with an event or situation, the event or situation is precisely occurring, and the event or situation is such that the resulting degree of error is quite close to the manufacturing process. . The term "conductive" and "conductivity" is used to refer to the Emperor. A conductive material generally refers to a material that has a low impedance of zero impedance for current. The conductivity is in units of Siemens/meter (S.m·1). 201101452: The conductive material of the type has a conductivity greater than 104 s.m-i, such as at least about Γ5 Γ or at least about 106 s.m-1. The conductivity of the material can sometimes be determined at room temperature; the electrical conductivity is not particularly clear. The conductivity of the material is fixed on the day. First, refer to Figure 1 and Figure 2. Figure 1 and Figure 2 show the green The semiconductor package of one embodiment of the present invention is 〇〇. In detail, Fig. 1 is a perspective view of the semiconductor package. Fig. 2 shows a section of the semi-conductor package 1GG along the first plan. o
在所述之實施例中，半導體封裝件1〇〇之側面係實 質上為平面’且具有實質上垂直之方向，用以定義實質貝 上沿著半導體封裝件_之整體周圍延伸之橫向輪靡。、 較佳地，藉由減少或縮小半導體封裝件_之佔用面積 (footprint area)’此垂直之橫向輪廓減少了整體 體封裝件之尺寸。然、而，—般而言，半導體封t件⑽ 之橫向輪廓可為不同之形狀，例如是彎曲、傾斜、階梯 狀或為粗組織。 請參照第2圖，半導體封裝件1〇〇包括基板單元 102。基板單元102具有上表面1〇4、下表面ι〇6及側表 面142及144。側表面142及144鄰近於基板單元1〇2之 側邊且於上表面1〇4及下表面1〇6間延伸。雖然於所述 之實施例中，侧表面142及144係實質上為平面，且實 夤上垂直於上表面1〇4及下表面1〇6,但在其它的實施方 式中，侧表面142及144之形狀及方向可為不同。基板 單元102可依數種不同的方式實施，包括利用電性^接 機制（electrical interconnect)以提供基板單元1〇2 9 201101452 之上表面104及下表面間之電性通道。電性 例如是包括一組被包含於介電層中之導電層。導電幾 =由内部導孔而彼此連接，且可夾住由適合之樹脂為底 基之樹脂。此樹脂例如是由雙馬來醯亞胺 (bismaleimide)及二氮六環（triazine)，或為由環氧 树脂及聚氧化二甲苯（p〇lyphenylene〇xide)為底基之 ^旨。舉例來說’基板單幻G2可包括實質上為板狀之 間層（slab-shaped core)，且中間層係由兩組導電層 所夾住。其中—組導電層係鄰近於中間層的上表面，而 =組導電層係鄰近於中間層的下表面。在某些實施方 式中，基板單元102之厚度，亦即基板單元102之上表 面1〇4與下表面106間之距離，可介於約〇. imm至約2丽， :如是由約心至約U·，或為約0.4_至約〇.6_。 雖然未繪示於第2圖中，綠漆層（solder mask layer) 可配置於鄰近基板單元1〇2之上表面1〇4或/且下表面 106之處。 如第2圖所示，基板單元102包括接地元件1183及 18匕接地兀件u8a及n8b係實質上配置於基板單元 之周圍’且分別鄰近於側表面142及144。接地元件 118a及U8b係連接至包含於基板單元1Q2内之電性連接 機制。後續敘述中將說明接地元件118&及n8b可降低 ，磁干擾。在本實施例中，接地元件他及u8b以接 ^導孔的形式形成。更具體來說，接地元件ma及腿 ^妾地導孔於—切割製程（singuiati〇n叩恤㈣）後 、餘留。p所形成’此將於後續敘述中說明。請參照第2 201101452 < * 1 vv r\ 圖，每一個接地元件118a及118b包括上導孔墊餘留部 146a或146b、下導孔墊餘留部148a或148b及電鍍的通 道餘留部150a或150b。上導孔墊146a或146b係鄰近於 基板單元102之上表面104而配置。下導孔墊餘留部148a 或148b係鄰近於基板單元102之下表面106而配置。電 鍍的通道餘留部150a或150b係於上導孔墊餘留部146a 或146b及下導孔餘留部148a或148b間延伸。圖式中之 接地元件118a及118b係由基板單元102之上表面104 0 延伸至下表面106。然而，接地元件118a及118b亦可以 其它方式實施。 請繼續參照第2圖，接地元件118a及118b分別包 括連接表面S1及S2。連接表面S1及S2係為背向半導體 封裝件100之内部的側表面，且連接表面S1及S2鄰近 於基板單元102之周圍而配置。更具體來說，連接表面 S1及S2係實質上暴露於基板單元102之周圍且分別暴露 於鄰近於側表面142及144之處，以作為電性連接之用。 〇 在本實施例中，連接表面S1及S2係對應於上導孔墊餘 留部146a及146b、下導孔墊餘留部148a及148b以及電 鍍之通道餘留部150a及150b的作為電性用途的暴露表 面。較佳地，較大的連接面S1及S2的面積有助於提升 電性連接的可靠度及效率，以降低電磁干擾。接地元件 118a及118b係由金屬、金屬合金、金屬或合金分散於其 中之基體或其它合適之導電材料所形成。在某些實施方 式中，接地元件118a及118b之高度Hi，亦即接地元件 118a及118b之垂直長度，可實質上與基板單元102之厚 11 201101452 度相同。接地元件118a及118b之高度Hi可約為〇. lmm 至 2mm ’ 例如疋約 〇. 2ππη 至 1 · 5mni，或約 0. 4miii 至 0. 6mm。 接地元件118a及118b之寬度Wi，亦即鄰近於上表面1〇4 或下表面106之橫向長度’可介於約75μιη至275μπι，例 如是由 ΙΟΟμηι 至 250μπι，或由 Ι25μηι 至 225μιη。 如第2圖所示’半導體封裝件1〇〇亦包括半導體元 件108a、108b及108c以及電性接點ii〇a、i1〇b及u〇c。 半導體元件108a、108b及l〇8c係鄰近於基板單元1〇2 之上表面104而配置。電性接點u〇a、n〇b及u〇c係 部近於基板單元102之下表面而配置。半導體元件 108b係透過一組導線112而打線連接至基板單元1〇2。 導線112係由金或其它適合之導電材料所形成。半導體 元件108a及1〇8(：係以表面黏著（surface m〇unted)之 方式固定於基板元件1〇2上。所述之實施例中，半導體 兀件108b係為半導體晶片’且半導體元件1()8&及i〇8c 為被動元件，例如是電阻器、電容器或電感器。電性接 ’、”占ll〇a、ll〇b及110c提供半導體封裝件1〇〇輸入及輸 出之電性連接，且電性接點n〇a、丨丨此及u〇c之部分 電性接點係透過包含於基板單元1G2巾之電性連接機制 而電性連接至半導體元件1Q8a、嶋及⑽。。所述之實 ^列中1性接點110a、11〇bA11〇c中之至少一個電 中=係為接地之電性接點’且透過包含於基板單元102 木菸日性連接機制而電性連接至接地元件118a及118b。 數:明導體元件之數#並不受限於第2时所示之 置在其它之實施方式令，半導體之數量可為較多或 201101452 * * I WJJHUr/Λ 較少。此外，一般而言，半導體元件可為任意之主動元 件 '被動元件或其組合。電性接點之數量亦可不同於第2 圖中所示之數量。 請繼續參照第2圖，半導體封裝件1〇〇亦包括封膠 體114。封膠體114係鄰近於基板單元1〇2之上表面ι〇4 而配置。封膠體114及基板單元1〇2係實質上覆蓋或包 覆接地元件1183及U8b、半導體元件1〇8a、1〇8b& 1〇8c 及導線112，以提供機械穩定性以及對於氧化、濕度及盆 Ο它環境條件之保護。封膠體114係由㈣材料所形成。 封膠體114之外部表面包括鄰近封膠體114之側邊而配 置之侧表面120及122。所述之實施例中，側表面12〇及 122係實質上為平面，且實質上垂直於上表面遍及下表 面丨〇6。然而，側表面12〇及122亦可為彎曲、傾斜、階 梯狀或為祕材質。此外，側表面12G及122係實質上 ^對齊於側表面142及144。或者，側表面12()及122 ❹由、面142及144共平面。更具體來說，當例如是藉 由降低或最小化封膠體114之連接表面^及⑺之範圍， 射，丨生暴路連接表面S1及S2時，側表面12〇及122可 雷：：側表面142及144。在其它之實施方式中，當至少 %暴露部分之連接表面S1及S2時，侧表面丨2〇及丨22 =狀，及側表面12〇及122與側表面142及144之對 式可與苐2圖中所示之方式不同。 如第1圖及第2圖所示，半導體封裝件1〇〇更包括 ^:擾防護罩124。防護罩124係鄰近於封膠體ιΐ4之 表面、接地元件服及嶋之連接表面S1AS2, 201101452 以及基板單元Η)2之側表面142及144而配置。電針 擾防濩罩124係由導電材料所形成，且實質上圍繞半導 體封裝件100内之半導體元件购、祕及108c，用以 提供防f電磁干擾之保護作用。所述之實施例中，電磁 干擾防護罩124包括上部126及側部128。側部係每 封膠體114之整個周圍而延伸，且側部心 疋義半導體封裝件⑽之垂直之橫向輪廓。如第2圖所 不^部128由上部126向下延伸，並沿著基板單元102 之側表面H2及144。側部128包括一下端，且 質上對齊基板單元102之下表面⑽，或與基板單元ι〇2 ,下表面106共平面 '然而’可了解的是，在其它之實 鈿方式中，側部128之範圍，以及側部128之下端與下 表面106之對齊方式可與本實施例不同。 ” 如第2圖所示，電磁干擾防護罩124係電性連接至 接地元件118a及U8b之連接表面S1及犯。當由半導體 封裝件1士00之内部發出之電磁放射傳遞至電磁干擾防護 罩124 a守，至少一部份之電磁放射可透過接地元件 及118b被放電至接地端，藉以減少穿透電磁干擾防護罩 ^4並危害#近之半導體元件之電磁放射之程度。同理， 田由鄰近之半$體元件發出之電磁放射傳遞至電磁干擾 防濩罩124時，亦會發生相似的接地作 體縣件刚内之半導體元件108a、腦及 磁干擾。當半導體封裝件1〇〇運作時，半導體封裝件1〇〇 可配置於印刷電路板上，且透過電性接點㈣、u〇b及 〇 c而電性連接至印刷電路板。如上所述，電性接點 14 201101452 > * j wjJH-or/\ 110a、110bl 11〇c t 牵 j 點，且接地之電性接點二—個接點係為接地之 電性接 接地電壓。透過電性通道】接至印刷電路板提供之 磁干擾防護罩J24的電磁敌射放=電性接點，將衝擊電 係包括接地元件118a及ll8b，/至接地蠕。電性通道 内之其它電性連接機制。由於電'、及包含於基板單元102 端係實質上對齊於基板單元1 〇2 '干擾防護罩124的下 電性連接至印刷電路板所提供之2下表面，此下端亦可 〇 一個將電磁放射接地之電性通道。地電壓，藉以提供另 部148a及148b亦可電性連接至或者，下導孔墊餘留 電壓。 刷電路板提供之接地 所述之實施例中，電磁干擾 〇 (conformal)防護罩，且為_級脸罩^24為一全覆蓋 電磁干擾防護罩124可藉由不使心層或薄膜。較佳地’ 於鄰近於半導體封裝件1GG之外部&著劑之方式而配置 擾防護罩124係與半導體封褒件1〇^處。或者’電磁干 藉以增加可靠度及對於溫度、濕夜〇卜^直接接觸’ 抗能力。此外，電磁干擾防護| 12，條件之抵 4之全覆蓋特性使得 相似的電磁干擾防護罩及相似的隻】> %逢方法可直接應用於 不同尺寸或形狀之半導體封裝件，、 建而減少符合不同半 導體封裝件之製造成本及時間。在发^ & 系些實施例中，電磁 干擾防護罩124之厚度可介於約iUm s μιτι至5 0 0 μηι，例如是 介於約Ιμιη至5〇μηι ’或介於約 μϊϊ1至ΙΟμιη。電磁干擾 防護罩124之厚度較一般殼體少，闵二牧7 ^ 因而降低了半導體封 裝件之整體尺寸。此為所述之實施例之一優點。 201101452 1請參照第3圖。第3圖繪示第丨圖及第2圖之部分 半+體封裝件100之放大剖面圖。具體來說，第3圖繪 不種郴近於封膠體114而配置之電磁干擾防護罩124。 如第3圖所示’電磁干擾防護罩124具有多層結構， 且包括内層300及外層302。内層300鄰近於封膠體114 而配置外層3〇2係鄰近於内層3〇〇而配置且暴露於半 導體封裝件100之外部。一般而言，内層細及外層· 可由金屬I屬合金、金屬或合金分散於其中之基體或 另一種合適之導電材料所形成。舉例來說，内層300及 ^卜層302係由紹、銅、鉻、錫、金、銀、鎳、不錄鋼或 :組合所形成。内層300及外層302可由相同或不同之 ¥電材料所形成。舉例來說，内層3〇〇及外層3〇2可由 ==鎳之金屬所㈣。在—些例子中，内層及外 =:由:Γ導電材料所形成，以提供互補之功能。 J來說’具有高導電度的金屬，例如為紹、銅、全或 2二用以形成内層·，藉以提供電磁干擾防護功能。 另-方面’具有較低之導電度的金屬，例如為鎳，可用 7成外層3〇2’藉以保護内層_不受氧化、渴度或立 在此情況中，外層302除了、_ 此 村提供冑軒擾防護舰。料第3圖 中緣示兩層之結構，但在其㈣_以'/“，、弟3圖 目可為更多或更少。4的實衫式中，膜層之數 f4A圖繪示依照本發明之另—實施例 第！圖至第3圖中繪T分元件係與 牛¥體封裝件100類似，在此 201101452 不再贅述。 清參照第4A圖，止、、. +導體封裝件400包括接地元件 418a及418b，且接地开& 牛418a及418b實質上配置於基 板單元102之周圍。於冰& '來實施例中，接地元件418a及418b 為接地盲孔之餘留部， — 、， 教由基板單元102之上表面104 延伸至導電層452。導 等重層452配置於基板單元102的上 Ο 表面104與下表面1〇6 <間，且作為内部接地層之用。 具體來說’接地元件4l8a及僅包括上導孔墊餘留部 446a或446b、下導孔墊餘留部448a或44卟以及電鍍之 通道餘留部450a或45〇b。上導孔墊餘留部446a或446b 鄰近於基板單元102的上表面1〇4而配置。下導孔墊餘 留部448a或448b電性連接至導電層452,且下導孔墊餘 留部448a或448b配置於基板單元1〇2的下表面106之 〇 延伸時，接地元件418a及418b可以是其它實施態樣。 於本實施例中，接地元件418a及418b分別包括連接表 面S1’及S2’ ，且連接表面S1’及S2’分別暴露於鄰 近側表面142及144之處，以作為電性連接之用。較佳 地，連接表面S1’及S2’具有較大之面積，可加強用來 減少電磁干擾的電性元件的可靠度與效率。在某些實施 例中，接地元件418a及418b的高度H2可略小於基板單 元102的厚度，且可介於約0.1丽至1. 8mm，例如是由約 上，並與下表面106相隔一距離。電鍍之通道餘留部450a 或450b係由上導孔墊餘留部446a或446b延伸至下導孔 墊餘留部448a或448b。當接地元件418a及418b僅於基 板單元102的上表面104與下表面106之間的部分區域 17 201101452 0. 2mm至1 mm，或約0. 3mm至0. 5mm。接地元件418a及 418b的寬度W2，亦即鄰近於上表面104之側向長度。寬 度W2可介於75μηι至275μηι，例如是約為1 ΟΟμηι至 2 5 0 μηι，或約為 12 5 μηι 至 2 2 5 μηι。 如第4Α圖所示，半導體封裝件400亦包括半導體元 件408b。半導體元件408b鄰近於基板單元102之上表面 104而配置的半導體晶片。在本實施例中，半導體元件 408b以覆晶接合的方式固定於基板單元102上，例如是 透過一組銲墊而連接。半導體元件408b亦可藉由其它的 方式與基板單元102電性連接，例如是打線接合的方式。 第4B圖繪示依照本發明之另一實施例之半導體元 件460之剖面圖。半導體封裝件460之部分元件係與繪 示於第1圖至第3圖中之半導體封裝件100與第4A圖中 之半導體封裝件400相似，在此不再贅述。 請參照第4B圖，半導體封裝件460包括實質上配置 於基板單元102之周圍的接地元件462a及462b。在本實 施例中，接地元件462a及462b為接地盲孔的餘留部， 此餘留部由基板單元102的下表面106延伸至導電層 464。導電層464配置於基板單元102的上表面104與下 表面106之間，作為内部接地層之用。具體來說，每一 個接地元件462a及462b包括上導孔墊餘留部466a或 466b、下導孔墊餘留部468a或468b及電鍍之通道餘留 部470a及470b。上導孔墊餘留部466a或466b係電性連 接至導電層464,且配置於基板單元102之上表面104之 下。上導孔墊餘留部466a或466b係與基板單元102之 18 201101452 1 1 »» ι ν 上表面104相隔一距離。下導孔墊餘留部468a或468b 係鄰近於基板單元1〇2之下表面1〇6而配置。電鍍之通 道餘留部470a及470b由上導孔墊餘留部466a或466b 延伸至下導孔墊餘留部468a或468b。較佳地，接地元件 462a及462b配置於基板單元102之上表面1〇4之下的區 ο 域，因此所騰出的上表面1〇4的面積可作為電磁干擾防 護之用。接地元件462a及462b之配置可降低或最小化 了半導體封裝件460之佔用面積，進而減少了半導體封 裝件之整體尺寸。然而’在其它實施方式中，接地元件 ΓΛί 462b之位置及範圍可為不同。在本實施例中，接 地兀件462a及462b分別包括連接表面幻，，及 ==，，，及S2,，係分別於鄰近側表面 封f件-體二Γ轉露。難地，#達錢少半導體 封裝件整體尺寸之目的時，連接表面sr 有相對較大的面積，& 八 〇 件的可靠度與效率。在芊干擾的電性元 及4fi外夕古译H隹系二戶、她方式中，接地元件462a 及462b之同度Hb可略小於基板單元1〇2之厚度，且可介 =為G.lmm至umm，例如介於社2咖與_之間， 或，！於約0. 3m與〇. 5mm之間。接地元件4咖及條之 寬度WB’亦即鄰近於下表面1〇6之側向長度，可介於約 75_至275_，例如是介於約1〇_至25_ 125_ 至 225jnm。 Ί 第4C圖繪示依照本發明之另一實施例之半導 裝件彻之剖面圖。半導體封裝# 480之部分元件係盘 繪不於第1圖至第3圖中之半導體封裝件1〇〇、第圖 19 201101452 中之半導體封裝件400與第4B圖中之半導體封裝件460 相似，在此不再贅述。 請參照第4C圖，半導體封裝件480包括接地元件 482a及482b。接地元件482a及482b係實質上配置於基 板單元102之周圍。所述之實施例中，接地元件482a及 482b為於導電層484a與484b之間延伸的埋孔（buried via)或内部接地導孔之餘留部。導電層4g4a及484b係 配置於基板單元102之上表面1〇4與下表面1〇6之間， 且作為内部接地層之用。具體來說，每一個接地元件482a 及482b包括上導孔墊餘留部486a或486b。上導孔墊餘 留部486a或486b係電性連接至導電層48知，且配置於 基板單元H)2之上表面1()4之下。上導孔錢留部觸 或486b與基板單元102之上表而]^ a 工衣面1〇4相隔一距離。下導 孔墊餘留部488a或488b係雷 〆 宁尾14連接至導電層484b，且 係配置於基板單元102之下表面〗 „ A 167 1〇6之上。下導孔墊钤 留部488a或488b與基板單元1〇 餘 a w之下表面106相隔— 距離。較佳地，接地元件482a对/1。 ^及482b位於基板單元〗n9 之上表面104與下表面1〇6之鬥 ln, a ± 艾間，因此所騰出的上表& 104及下表面1〇6的區域範圍可 双向 接地το件482a及482b的配置可降 。 封裝件480的佔用面積’進而诗_ $ 導體 而減少了半導體封裝件的軟 體尺寸。然而，在其它實施方式中 ^ 平接地元件482a及 482b分別包括連接表面sr 81’ ’ ’ 及 S2’ ......... 耳奴例中，接地元件482a及 ，及S2’，，。連接矣& ，’分別暴露於鄰近側表面c 20 201101452 if /作為妹連接之用。雛地，#達成減少半導 體封裝件整體尺寸之目㈣，連接表面S1，，，及 ^㈣具有相對較大的面積，可加強用來減少電磁干 ，的電性元件的可靠度與效率。在某些實财式中 ^件】,入及482b的高度Hc可略小於基板單元102的 2:於約為0.1咖至1.6,例如介於約〇 2mm .8则1之間，或介於約0.2m與0.4mm之間。接地元件 ο 482a及482b之寬度Wc，亦即鄰近導命 丨叫迎於導电層484a或484b 至2二二可介於約75,至275_，例如是約為100_ 至250_，或約為125_至225_。 導圖至第5E崎示依照本發明之—實施例之半 -封裝件之㈣方法。為了易於說明，下列 :如B第3圖所示的半導體封裝件⑽為例作說 =而’製造方法亦可用以形成其它半導體封裝件， 例如是第4 A圖之半導押封扭杜j Λ Λ & 口严千導體封震件400、第4Β圖之半導體封 ο 、牛460以及第4C圖之半導體封裝件48〇。 請參照第5Α圖及第58圖，首先，提供基板5〇〇。 :了；曰加衣造產能’基板5〇〇包括數個基板單元，使得 某^製造方法得以平行或連續地快速進行。數個基板單 ^括基板單幻02及鄰近之基板單幻02，。基板500 長條狀’且數個基板單元可以直線或矩陣之方式而 /地排列。為了枝說明’下狀製造方法係以基板 ^ 1〇2及相關元件為例作說明。然❿，製造方法亦可 用於其它基板單元及相關元件。 ^第5Α圖及帛5Β圖所示，數個接地導孔係鄰近於 21 201101452In the illustrated embodiment, the side of the semiconductor package 1 is substantially planar and has a substantially vertical direction for defining a lateral rim extending substantially along the periphery of the semiconductor package. . Preferably, the vertical lateral profile reduces the size of the monolithic package by reducing or reducing the footprint area of the semiconductor package. However, in general, the lateral profile of the semiconductor package (10) can be of a different shape, such as curved, slanted, stepped or coarse. Referring to FIG. 2, the semiconductor package 1 includes a substrate unit 102. The substrate unit 102 has an upper surface 1〇4, a lower surface ι6, and side surfaces 142 and 144. The side surfaces 142 and 144 are adjacent to the side of the substrate unit 1〇2 and extend between the upper surface 1〇4 and the lower surface 1〇6. Although in the illustrated embodiment, the side surfaces 142 and 144 are substantially planar and substantially perpendicular to the upper surface 1〇4 and the lower surface 1〇6, in other embodiments, the side surface 142 and The shape and orientation of 144 can vary. The substrate unit 102 can be implemented in a number of different ways, including utilizing an electrical interconnect to provide an electrical path between the upper surface 104 and the lower surface of the substrate unit 1 〇 2 9 201101452. Electrical properties include, for example, a set of conductive layers included in a dielectric layer. Conductive couples = connected to each other by internal guide holes, and can hold a resin based on a suitable resin. The resin is, for example, made up of bismaleimide and triazine, or is based on an epoxy resin and p〇lyphenylene〇xide. For example, the substrate single phantom G2 may comprise a substantially slab-shaped core, and the intermediate layer is sandwiched by two sets of conductive layers. Wherein the set of conductive layers are adjacent to the upper surface of the intermediate layer, and the = set of conductive layers are adjacent to the lower surface of the intermediate layer. In some embodiments, the thickness of the substrate unit 102, that is, the distance between the upper surface of the substrate unit 102 and the lower surface 106 may be between about i.imm and about 2 丽, as: About U·, or about 0.4_ to about 〇.6_. Although not shown in Fig. 2, a powder mask layer may be disposed adjacent to the surface 1〇4 or/and the lower surface 106 of the substrate unit 1〇2. As shown in Fig. 2, the substrate unit 102 includes grounding elements 1183 and 18" grounding elements u8a and n8b are disposed substantially around the substrate unit' and adjacent to the side surfaces 142 and 144, respectively. The grounding elements 118a and U8b are connected to an electrical connection mechanism included in the substrate unit 1Q2. The following description will explain that the grounding elements 118 & and n8b can reduce magnetic interference. In the present embodiment, the grounding element and u8b are formed in the form of via holes. More specifically, the grounding element ma and the leg hole are in the after-cutting process (singuiati〇n t-shirt (4)), and remain. The formation of p will be explained in the following description. Referring to FIG. 2 201101452 < * 1 vv r\, each of the grounding members 118a and 118b includes an upper via pad remaining portion 146a or 146b, a lower via pad remaining portion 148a or 148b, and a plated remaining portion of the channel. 150a or 150b. The upper via pad 146a or 146b is disposed adjacent to the upper surface 104 of the substrate unit 102. The lower via pad remaining portion 148a or 148b is disposed adjacent to the lower surface 106 of the substrate unit 102. The plated remaining portion 150a or 150b of the plating extends between the upper via pad remaining portion 146a or 146b and the lower via remaining portion 148a or 148b. The grounding elements 118a and 118b in the drawing extend from the upper surface 104 0 of the substrate unit 102 to the lower surface 106. However, grounding elements 118a and 118b can also be implemented in other ways. Continuing to refer to Fig. 2, grounding members 118a and 118b include connecting surfaces S1 and S2, respectively. The connection surfaces S1 and S2 are side surfaces facing away from the inside of the semiconductor package 100, and the connection surfaces S1 and S2 are disposed adjacent to the periphery of the substrate unit 102. More specifically, the connection surfaces S1 and S2 are substantially exposed to the periphery of the substrate unit 102 and are exposed adjacent to the side surfaces 142 and 144, respectively, for electrical connection. In the present embodiment, the connection surfaces S1 and S2 correspond to the upper via pad remaining portions 146a and 146b, the lower via pad remaining portions 148a and 148b, and the plated path remaining portions 150a and 150b as electrical properties. The exposed surface of the use. Preferably, the area of the larger connecting faces S1 and S2 helps to improve the reliability and efficiency of the electrical connection to reduce electromagnetic interference. Grounding elements 118a and 118b are formed from a matrix or other suitable electrically conductive material in which the metal, metal alloy, metal or alloy is dispersed. In some embodiments, the height Hi of the ground elements 118a and 118b, i.e., the vertical lengths of the ground elements 118a and 118b, may be substantially the same as the thickness of the substrate unit 102 by 11 201101452 degrees. The height of the grounding elements 118a and 118b may be about l. lmm to 2 mm 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The width Wi of the grounding members 118a and 118b, i.e., the lateral length 'adjacent to the upper surface 1〇4 or the lower surface 106' may be between about 75 μm and 275 μm, for example, from ΙΟΟμηι to 250 μm, or from Ι25μηι to 225 μm. As shown in Fig. 2, the semiconductor package 1 〇〇 also includes semiconductor elements 108a, 108b and 108c and electrical contacts ii 〇 a, i1 〇 b and u 〇 c. The semiconductor elements 108a, 108b, and 8c are disposed adjacent to the upper surface 104 of the substrate unit 1A2. The electrical contacts u〇a, n〇b, and u〇c are disposed close to the lower surface of the substrate unit 102. The semiconductor element 108b is wire-bonded to the substrate unit 1〇2 through a set of wires 112. Wire 112 is formed from gold or other suitable electrically conductive material. The semiconductor elements 108a and 1b are fixed to the substrate element 1 2 by surface adhesion. In the embodiment, the semiconductor element 108b is a semiconductor wafer 'and the semiconductor element 1 ()8& and i〇8c are passive components, such as resistors, capacitors, or inductors. Electrical connections, ll〇a, ll〇b, and 110c provide semiconductor package input and output power. The electrical connection is electrically connected to the semiconductor components 1Q8a, 嶋, and (10) through the electrical connection mechanism of the substrate unit 1G2. At least one of the first contact 110a, 11〇bA11〇c in the actual column is an electrical contact that is grounded and transmitted through the solar cell connection mechanism included in the substrate unit 102. Electrically connected to grounding elements 118a and 118b. Number: The number of bright conductor elements # is not limited to the second embodiment shown in other embodiments, the number of semiconductors can be more or 201101452 * * I WJJHUr /Λ Less. In addition, in general, the semiconductor component can be any active element 'Passive components or combinations thereof. The number of electrical contacts may also differ from the number shown in Figure 2. Please continue to refer to Figure 2, the semiconductor package 1 also includes the encapsulant 114. The encapsulant 114 is adjacent Arranged on the upper surface ι 4 of the substrate unit 1 〇 2. The encapsulant 114 and the substrate unit 〇 2 substantially cover or cover the ground elements 1183 and U8b, and the semiconductor elements 1 〇 8a, 1 〇 8b & 1 〇 8c And the wire 112 to provide mechanical stability and protection against oxidation, humidity and environmental conditions of the basin. The sealant 114 is formed of (4) material. The outer surface of the sealant 114 includes a side adjacent to the sealant 114. Side surfaces 120 and 122. In the illustrated embodiment, the side surfaces 12 and 122 are substantially planar and substantially perpendicular to the upper surface over the lower surface 丨〇 6. However, the side surfaces 12 and 122 may also be Curved, slanted, stepped or secret material. Further, the side surfaces 12G and 122 are substantially aligned with the side surfaces 142 and 144. Alternatively, the side surfaces 12() and 122 are coplanar with the faces 142 and 144. Specifically, for example, by lowering or most When the sealing surface of the encapsulant 114 is in the range of (7), when the surface contact S1 and S2 are connected, the side surfaces 12 and 122 may be:: side surfaces 142 and 144. In other embodiments, When at least % of the exposed portions are joined to the surfaces S1 and S2, the side surfaces 丨2〇 and 丨22=, and the side surfaces 12〇 and 122 and the side surfaces 142 and 144 may be different from the manner shown in FIG. As shown in FIGS. 1 and 2, the semiconductor package 1 further includes a disturbing shield 124. The shield 124 is disposed adjacent to the surface of the sealant ι 4, the grounding member and the side surfaces 142 and 144 of the connection surfaces S1AS2, 201101452 and the substrate unit Η)2. The electro-acoustic tamper-proof cover 124 is formed of a conductive material and substantially surrounds the semiconductor components in the semiconductor package 100 to provide protection against electromagnetic interference. In the illustrated embodiment, the electromagnetic interference shield 124 includes an upper portion 126 and side portions 128. The side portions extend around the entire circumference of each of the encapsulants 114, and the side cores have a vertical cross-sectional profile of the semiconductor package (10). As shown in Fig. 2, the portion 128 extends downward from the upper portion 126 and along the side surfaces H2 and 144 of the substrate unit 102. The side portion 128 includes a lower end and is qualitatively aligned with the lower surface (10) of the substrate unit 102, or coplanar with the substrate unit ι2 and the lower surface 106. However, it is understood that in other embodiments, the side portion The extent of 128, and the alignment of the lower end of side portion 128 with lower surface 106 may vary from this embodiment. As shown in Fig. 2, the electromagnetic interference shield 124 is electrically connected to the connection surface S1 of the grounding members 118a and U8b and the electromagnetic radiation emitted from the inside of the semiconductor package 1 to 00 to the electromagnetic interference shield. 124 a Guard, at least a portion of the electromagnetic radiation can be discharged to the ground through the grounding element and 118b, thereby reducing the degree of electromagnetic radiation that penetrates the electromagnetic interference shield ^4 and jeopardizes the near semiconductor component. Similarly, Tian When the electromagnetic radiation emitted by the adjacent half of the body element is transmitted to the electromagnetic interference tamper-proof cover 124, a similar grounding of the semiconductor component 108a, brain and magnetic interference within the body of the device is also occurred. When the semiconductor package is 〇〇 In operation, the semiconductor package 1 can be disposed on the printed circuit board and electrically connected to the printed circuit board through the electrical contacts (4), u〇b, and 〇c. As described above, the electrical contacts 14 201101452 > * j wjJH-or/\ 110a, 110bl 11〇ct j point, and the grounding electrical contact two-contact is grounded electrical grounding voltage. Through the electrical channel] connected to the printed circuit Magnetic interference provided by the board The electromagnetic enemy of the shield J24 is an electrical contact, and the impact electric system includes the grounding elements 118a and ll8b, / to the grounding creep. Other electrical connection mechanisms in the electrical channel. Because of the electricity, and included in the substrate unit The end of the 102 is substantially aligned with the substrate unit 1 〇 2 'the lowering of the interference shield 124 is connected to the lower surface provided by the printed circuit board, and the lower end can also be connected to an electrical path for electromagnetic radiation to ground. The voltage, by which the other portions 148a and 148b are provided, can also be electrically connected to or the remaining voltage of the lower via pad. The ground provided by the brush circuit board, in the embodiment described, the electromagnetic interference (conformal) shield, and The face mask 24 is a full-coverage electromagnetic interference shield 124 which can be configured by not disposing the core layer or the film. Preferably, the interference shield 124 is disposed adjacent to the outer &lifier of the semiconductor package 1GG. With the semiconductor sealing device 1 。 ^ or 'electromagnetic dry to increase reliability and for temperature, wet night ^ ^ direct contact 'resistance. In addition, electromagnetic interference protection | 12, the full coverage of the conditions of 4 Similar electromagnetic interference Shields and similar only]>% can be directly applied to semiconductor packages of different sizes or shapes, and can be reduced to meet the manufacturing cost and time of different semiconductor packages. In the embodiments The thickness of the electromagnetic interference shield 124 may be between about iUm s μιτι to 5 0 0 μη, for example, between about ιμιη to 5〇μηι ' or between about μϊϊ1 and ΙΟμιη. The thickness of the electromagnetic interference shield 124 is higher than that of the general shell. Less body, 闵二牧7 ^ thus reducing the overall size of the semiconductor package. This is an advantage of the described embodiment. 201101452 1 Please refer to Figure 3. Fig. 3 is a cross-sectional view showing a portion of the half + body package 100 of the second and second figures. Specifically, FIG. 3 depicts an electromagnetic interference shield 124 that is disposed adjacent to the encapsulant 114. As shown in Fig. 3, the electromagnetic interference shield 124 has a multilayer structure and includes an inner layer 300 and an outer layer 302. The inner layer 300 is disposed adjacent to the encapsulant 114 and the outer layer 3〇2 is disposed adjacent to the inner layer 3〇〇 and exposed to the outside of the semiconductor package 100. In general, the inner layer of the outer layer and the outer layer may be formed of a matrix of a metal I-based alloy, a metal or an alloy dispersed therein, or another suitable electrically conductive material. For example, the inner layer 300 and the second layer 302 are formed of a combination of copper, chromium, tin, gold, silver, nickel, non-recorded steel, or a combination. The inner layer 300 and the outer layer 302 may be formed of the same or different materials. For example, the inner layer 3〇〇 and the outer layer 3〇2 can be made of == nickel metal (four). In some examples, the inner layer and the outer layer are: formed of: a conductive material to provide complementary functions. J says that a metal having a high electrical conductivity, for example, a copper, a full or a second, is used to form an inner layer, thereby providing electromagnetic interference protection. Another aspect - a metal with a lower conductivity, such as nickel, can be used to protect the inner layer with 7 outer layers 3 〇 2' _ not oxidized, thirsty or standing in this case, outer layer 302 in addition, _ this village provides胄 扰 扰 防护 防护 防护. In the third figure, the structure of the two layers is shown, but in the case of (4) _ with '/', the figure of the brother 3 can be more or less. In the solid shirt type of 4, the number of layers f4A is shown According to another embodiment of the present invention, the T-components are similar to the cow-shaped package 100, and will not be described here in 201101452. Referring to Figure 4A, the termination, the .+conductor package The device 400 includes grounding elements 418a and 418b, and the grounding & 牛 418a and 418b are disposed substantially around the substrate unit 102. In the embodiment of the ice & ', the grounding elements 418a and 418b are left of the grounding blind hole The upper portion 104 of the substrate unit 102 extends to the conductive layer 452. The conductive layer 452 is disposed between the upper surface 104 and the lower surface of the substrate unit 102, and serves as an internal ground layer. Specifically, the grounding member 418a and only the upper via pad remaining portion 446a or 446b, the lower via pad remaining portion 448a or 44A, and the plated path remaining portion 450a or 45〇b. The pad remaining portion 446a or 446b is disposed adjacent to the upper surface 1〇4 of the substrate unit 102. The lower via pad remaining portion 448a or 448b When electrically connected to the conductive layer 452 and the lower via pad remaining portion 448a or 448b is disposed between the lower surface 106 of the substrate unit 1〇2, the grounding elements 418a and 418b may be in other embodiments. In the example, the grounding members 418a and 418b respectively include the connecting surfaces S1' and S2', and the connecting surfaces S1' and S2' are respectively exposed to the adjacent side surfaces 142 and 144 for electrical connection. Preferably, The connecting surfaces S1' and S2' have a large area to enhance the reliability and efficiency of the electrical components for reducing electromagnetic interference. In some embodiments, the heights H2 of the grounding elements 418a and 418b may be slightly smaller than the substrate unit. The thickness of 102, and may be between about 0.1 and 1. 8 mm, for example, from about the same distance from the lower surface 106. The plated remaining portion 450a or 450b is formed by the upper via pad remaining portion 446a. Or 446b extends to the lower via pad remaining portion 448a or 448b. When the grounding members 418a and 418b are only in a partial region 17 between the upper surface 104 and the lower surface 106 of the substrate unit 102, 201101452 0. 2mm to 1 mm, or approximately 0. 3mm to 0. 5mm. The width of the grounding elements 418a and 418b W2, that is, the lateral length adjacent to the upper surface 104. The width W2 may be between 75 μηι and 275 μηι, such as about 1 ΟΟμηι to 2 5 0 μηι, or about 12 5 μηι to 2 2 5 μηι. As shown, the semiconductor package 400 also includes a semiconductor component 408b. The semiconductor element 408b is adjacent to the semiconductor wafer disposed on the upper surface 104 of the substrate unit 102. In the present embodiment, the semiconductor element 408b is fixed to the substrate unit 102 by flip chip bonding, for example, through a set of pads. The semiconductor device 408b can also be electrically connected to the substrate unit 102 by other means, such as wire bonding. 4B is a cross-sectional view of semiconductor component 460 in accordance with another embodiment of the present invention. Some of the components of the semiconductor package 460 are similar to those of the semiconductor package 100 shown in FIGS. 1 to 3 and the semiconductor package 400 of FIG. 4A, and are not described herein again. Referring to FIG. 4B, the semiconductor package 460 includes ground elements 462a and 462b disposed substantially around the substrate unit 102. In the present embodiment, the grounding elements 462a and 462b are the remaining portions of the grounding blind vias that extend from the lower surface 106 of the substrate unit 102 to the conductive layer 464. The conductive layer 464 is disposed between the upper surface 104 and the lower surface 106 of the substrate unit 102 as an internal ground layer. Specifically, each of the grounding members 462a and 462b includes an upper via pad remaining portion 466a or 466b, a lower via pad remaining portion 468a or 468b, and plated via remaining portions 470a and 470b. The upper via pad remaining portion 466a or 466b is electrically connected to the conductive layer 464 and disposed under the upper surface 104 of the substrate unit 102. The upper via pad remaining portion 466a or 466b is spaced apart from the upper surface 104 of the substrate unit 102 by a distance of 10 201101452 1 1 »» ι ν . The lower via pad remaining portion 468a or 468b is disposed adjacent to the lower surface 1〇6 of the substrate unit 1〇2. The plating remaining portions 470a and 470b are extended from the upper via pad remaining portion 466a or 466b to the lower via pad remaining portion 468a or 468b. Preferably, the grounding members 462a and 462b are disposed in the region ο below the upper surface 1〇4 of the substrate unit 102, so that the area of the vacated upper surface 1〇4 can be used for electromagnetic interference protection. The configuration of ground elements 462a and 462b can reduce or minimize the footprint of semiconductor package 460, thereby reducing the overall size of the semiconductor package. However, in other embodiments, the location and extent of the grounding element ΓΛί 462b can be different. In the present embodiment, the grounding members 462a and 462b respectively include a connecting surface phantom, and ==,, and S2, respectively, which are respectively exposed to the adjacent side surface. Difficultly, when the purpose of the overall size of the package is small, the connection surface sr has a relatively large area, and the reliability and efficiency of the eight pieces. In the 芊 interference electrical element and the 4fi, the same degree Hb of the grounding elements 462a and 462b may be slightly smaller than the thickness of the substrate unit 1 〇 2, and may be = G. Lmm to umm, for example between the 2 coffee and _, or,! Between about 0. 3m and 〇. 5mm. The width WB' of the grounding element 4 and the strip, i.e., the lateral length adjacent to the lower surface 1〇6, may be between about 75 Å to 275 Å, for example between about 1 〇 to 25 _ 125 至 225 纳米. Figure 4C is a cross-sectional view showing a semiconductor package in accordance with another embodiment of the present invention. Some of the components of the semiconductor package #480 are not similar to the semiconductor package 1 of FIGS. 1 to 3, and the semiconductor package 400 of FIG. 19 201101452 is similar to the semiconductor package 460 of FIG. 4B. I will not repeat them here. Referring to Figure 4C, the semiconductor package 480 includes grounding elements 482a and 482b. The grounding elements 482a and 482b are disposed substantially around the substrate unit 102. In the illustrated embodiment, the grounding elements 482a and 482b are the remaining portions of the buried via or internal ground vias extending between the conductive layers 484a and 484b. The conductive layers 4g4a and 484b are disposed between the upper surface 1〇4 and the lower surface 1〇6 of the substrate unit 102 and serve as an internal ground layer. Specifically, each of the grounding elements 482a and 482b includes an upper via pad remaining portion 486a or 486b. The upper via pad remaining portion 486a or 486b is electrically connected to the conductive layer 48 and disposed under the surface 1() 4 of the substrate unit H)2. The upper guide hole contact portion or 486b is spaced apart from the substrate unit 102 by a distance from the workpiece surface 1〇4. The lower via pad remaining portion 488a or 488b is connected to the conductive layer 484b, and is disposed on the lower surface of the substrate unit 102 „A 167 1〇6. The lower via pad retention portion 488a Or 488b is spaced apart from the surface 106 of the substrate unit 1 by the remaining aw. Preferably, the grounding element 482a is /1. ^ and 482b are located on the upper surface 104 of the substrate unit 〖n9 and the lower surface 〇6, ln, a ± A room, so the area of the upper surface & 104 and the lower surface 1 〇 6 can be vacated in two directions. The configuration of the pieces 482a and 482b can be lowered. The occupied area of the package 480 is further _ _ $ conductor The soft body size of the semiconductor package is reduced. However, in other embodiments, the grounding elements 482a and 482b respectively include the connection surfaces sr 81' ' ' and S2' ... The components 482a and, and S2', the connection 矣 &, 'are respectively exposed to the adjacent side surface c 20 201101452 if / as a sister connection. The ground, # achieve the purpose of reducing the overall size of the semiconductor package (four), the connection surface S1,,, and ^(4) have a relatively large area and can be used for reinforcement Reducing the reliability and efficiency of the electromagnetic components of the electromagnetic dry. In some real-life formulas, the height Hc of the inlet and the 482b may be slightly smaller than the 2 of the substrate unit 102: about 0.1 to 1.6, for example Between about 2 mm. 8 and 1 or between about 0.2 m and 0.4 mm. The width Wc of the grounding elements 482a and 482b, that is, adjacent to the guiding layer, greets the conductive layer 484a or 484b to 2 The two may be between about 75 and 275, for example about 100 to 250, or about 125 to 225. The map to 5E shows the method of the fourth embodiment of the invention in accordance with the invention. For ease of explanation, the following: The semiconductor package (10) shown in FIG. 3B is taken as an example = and the manufacturing method can also be used to form other semiconductor packages, for example, the semi-conducting seal of FIG. 4A. Λ Λ & 严 千 导体 导体 封 、 、 、 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请〇. : 曰 衣 衣 造 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' A plurality of substrates include a substrate single illusion 02 and an adjacent substrate single illusion 02. The substrate 500 is elongated and a plurality of substrate units can be arranged in a straight line or matrix manner. The method is described by taking the substrate ^1〇2 and related components as an example. Then, the manufacturing method can also be applied to other substrate units and related components. ^Figure 5 and Figure 5, several grounding holes are adjacent to 21 201101452
I ** i X 每一個基板單元之周圍而配置。具體來說，接地導孔 502a、502b、502c、502d及502e係鄰近於基板單一 之側邊而配置。在本實施例中，每一個隹地導孔勺^上 導孔墊、下導孔墊及電鍍之通道。上導孔墊例如上：： 孔墊546a或546b。下導孔墊例如是下導孔墊54h或、 548b。電鑛通道例如是電鑛通道550a或550b。接地I孔 502a、502b、502c、502d 及 502e 可由數插士 4 … 双種方式形成，例 如是以微影製程、化學蝕刻、雷射鑽孔或機械鑽孔之方 式形成開口。開口之電鍍可使用金屬、金屬合金 '金屬 或合金分散於其中之基體或另-種合適<導^材料而進 行。某些實施方式中，導電材料可塗佈铃或被吸引至開 口中’用以實質上以導電材料填充開口。舉例來說，^ 電材料可包括金屬、銲料或導電黏著劑。金屬可例如是 銅。銲料例如是數種熔點介於約為90SC $ θ ^ 王之易溶 之合金。導電黏著劑例如為數種具有導電填充物分佈於 其中之樹脂。填充開口可產生較大之面積，用以形成連 接表面’進而加強用以降低電磁干擾之電性連接之可靠 度及效率。雖然圖式中之接地導孔502a、502b、502c、 502d及502e係由基板500之上表面504延伸至下表面 524 ’ 然而’接地導孔 502a、502b、502c、502d 及 502e 亦可具有不同之範圍。舉例來說，接地導孔5〇2a、502b、 502c、502d及502e中之一可為接地盲孔或為内部接地導 孔。 所述之實施例中’導孔墊係為環狀，且電鍍之通道 係為具有實質上為圓形剖面之圓柱。導孔墊例如為上導 22 201101452 1 ν» u~r\Ji γύ 孔墊546a或546b。電鍍之通道例如為電鍍通道550a或 550b。然而，導孔墊及電鍍通道之形狀可為任何形狀。 舉例來說，電鍍通道可為其它種柱狀，例如為橢圓柱狀、 正方形柱狀或矩形柱狀。或者，電鑛通道具有非圓柱之 形狀。例如是圓錐狀、漏斗狀或其它漸縮之形狀。在某 些實施方式中，每一個電鍍通道之側向長度W3 (有時稱 為導孔尺寸）可介於約50 μηι至3 5 0 μιη，例如約10 0 μηι 至約3 0 0 μηι，或約1 5 0 μπι至2 5 0 μηι。每一個導孔墊之侧 〇 向長度W4 (有時稱為導孔墊尺寸）可介於約150μηι至 550μιη，例如約 200μηι 至約 500μπι，或約 250μιη 至 450μιη。當電鍍通道或導孔墊為非均勻之形狀時，側向長 度W3或W4可例如是對應於垂直方向上之側向長度。 為了加強用來減少電磁干擾的電性元件的可靠度及 效率，接地導孔係鄰近於每一個基板單元之四邊而配 置。然而，接地導孔亦可鄰近於基板單元之四邊中之部 分側邊而配置。接地導孔係可鄰近於每一個基板單元之 〇 四個角落或部分角落而配置。某些實施方式中，每一個 基板單元之最接近之接地導孔間的間隔Li (有時稱為導 孑L間隔）可介於約0. 1 mm至3mm，例如是介於約0. 2mm至 2mm，或介於約0. 5mm至1. 5mm。請參照第5B圖，每一個 基板單元之虛線邊界係定義「主動」區域，且半導體元 件係配置於主動區域内。為了減少或最小化對於半導體 元件之運作的不良衝擊，基板單元之接地導孔可距離主 動區域一間隔L2 (有時稱為排除距離）。在某些實施方式 中，間隔L2可介於約50μιη至300μιη，例如是介於約50μιη 23 至200μηι，或介於100 μηι至15 Ο μηι。然而，接地導孔之 數量及位於基板500上之位置可與第5Α圖及第5Β圖不 同。可了解的是，接地導孔亦可排列為數行，且鄰近於 每一個基板單元之周圍而配置。此外，當接地導孔為盲 孔或内部接地導孔時，不需要具有分配間隔L2。在此情 況下，接地盲孔係配置於上表面504之下。具體來說， 接地盲孔或内部接地導孔可部分或完全地配置於主動區 域内並位於半導體元件之下，用以降低或最小化半導體 元件運作之不良衝擊，並同時達到減少半導體封裝件整 體尺寸之目的。 當提供基板500之後，半導體元件108a、108b及 108c係鄰近於基板500之上表面504而配置，且半導體 元件108a、108b及108c係電性連接至基板單元102。具 體來說，半導體元件108b係透過導線112以打線接合之 方式連接至基板單元102。半導體元件108a及108c係以 表面黏著之方式固定於基板單元102上。請參照第5A 圖，基板500之下表面524係鄰近於膠帶506而配置， 且膠帶506可為單面或雙面黏著之膠帶。較佳地，膠帶 506固定基板單元102與鄰近之數個基板單元之相對位 置，使得連續之程序可於鄰近膠帶506之數個元件上進 行，而不需要翻轉元件或傳送元件至另一個載體。 然後，如第5C圖所示，封裝材料514係塗佈於基板 500之上表面504,用以實質上覆蓋或包覆接地導孔502a 及502b、半導體元件108a、108b及108c及導線112。 封裝材料514可例如包括以盼搭為底基之樹脂、以環氧 24 201101452 i為&基之樹脂、以石夕為底基之樹脂或其它適合之向 ^ '才料514亦可包括適合之填充劑，例如是粉 狀一軋化矽。封裝材料514可透過數種製模技術而塗 例如是壓墙& ρ 至拖成形、射出成形及轉注成形。當塗佈封梦 料514時n上，， 即丁我材 壯 封裝材料514係被硬化或固化，藉以形成封 、'=構526。舉例來說，可藉由降低溫度至封裝材料Μ $ 之，點以下而使得封裝材料514硬化或固化。在連續之I ** i X Configured around each substrate unit. Specifically, the ground vias 502a, 502b, 502c, 502d, and 502e are disposed adjacent to a single side of the substrate. In this embodiment, each of the grounding guide holes is provided with a guide hole pad, a lower guide hole pad, and a plating passage. The upper via pad is, for example, the upper:: hole pad 546a or 546b. The lower pilot pad is, for example, the lower via pad 54h or 548b. The electric ore channel is, for example, an electric ore channel 550a or 550b. The grounding I holes 502a, 502b, 502c, 502d, and 502e may be formed by a plurality of types of plugs, for example, by lithography, chemical etching, laser drilling, or mechanical drilling. The plating of the opening can be carried out using a metal, a metal alloy or a matrix in which the alloy or alloy is dispersed, or another suitable material. In some embodiments, the electrically conductive material can be coated or drawn into the opening' to substantially fill the opening with a conductive material. For example, the electrical material can include a metal, solder or a conductive adhesive. The metal can be, for example, copper. The solder is, for example, an alloy having a melting point of about 90 SC $ θ ^ Wang. The conductive adhesive is, for example, a resin having a conductive filler distributed therein. Filling the opening creates a larger area for forming the connection surface' and thereby enhancing the reliability and efficiency of the electrical connection for reducing electromagnetic interference. Although the ground vias 502a, 502b, 502c, 502d, and 502e in the drawing extend from the upper surface 504 of the substrate 500 to the lower surface 524', the ground vias 502a, 502b, 502c, 502d, and 502e may have different range. For example, one of the ground vias 5〇2a, 502b, 502c, 502d, and 502e may be a ground via or an internal ground via. In the embodiment described, the via hole is annular and the plated channel is a cylinder having a substantially circular cross section. The pilot pad is, for example, the upper guide 22 201101452 1 ν» u~r\Ji γύ hole pad 546a or 546b. The channel for electroplating is, for example, a plating channel 550a or 550b. However, the shape of the via pad and the plating channel can be any shape. For example, the plating channels may be other kinds of columns, such as elliptical columns, square columns or rectangular columns. Alternatively, the electric ore channel has a non-cylindrical shape. For example, it is a cone shape, a funnel shape or other tapered shape. In some embodiments, the lateral length W3 (sometimes referred to as a via size) of each plating channel can be between about 50 μηι to 3 5 0 μιη, such as about 10 0 μηι to about 3 0 0 μηι, or About 1 50 μm to 2 5 0 μη. The side length W4 (sometimes referred to as a via pad size) of each via pad may be between about 150 μm and about 550 μm, such as from about 200 μm to about 500 μm, or from about 250 μm to 450 μm. When the plating passage or the pilot pad is of a non-uniform shape, the lateral length W3 or W4 may, for example, correspond to a lateral length in the vertical direction. In order to enhance the reliability and efficiency of the electrical components used to reduce electromagnetic interference, the ground vias are arranged adjacent to the four sides of each substrate unit. However, the ground vias may also be disposed adjacent to portions of the four sides of the substrate unit. The ground vias may be disposed adjacent to the four corners or portions of the corners of each of the substrate units. I. 2mm至3mm, for example, about 0. 2mm, for example, about 0. 2mm 5毫米至1. 5毫米。 。. Referring to Figure 5B, the dashed boundary of each substrate unit defines an "active" region, and the semiconductor components are disposed in the active region. In order to reduce or minimize the adverse impact on the operation of the semiconductor device, the ground via of the substrate unit may be spaced apart from the active region by L2 (sometimes referred to as the exclusion distance). In certain embodiments, the spacing L2 can be between about 50 μm and 300 μηη, such as between about 50 μηη 23 and 200 μηι, or between 100 μηι and 15 μηηι. However, the number of ground vias and the location on the substrate 500 can be different from the 5th and 5th views. It can be understood that the ground vias can also be arranged in a plurality of rows and arranged adjacent to the periphery of each of the substrate units. Further, when the ground via is a blind via or an internal ground via, it is not necessary to have a distribution interval L2. In this case, the grounding blind hole is disposed below the upper surface 504. Specifically, the ground via hole or the internal ground via hole may be partially or completely disposed in the active region and under the semiconductor component to reduce or minimize the adverse impact of the operation of the semiconductor component, and at the same time reduce the overall semiconductor package. The purpose of the size. After the substrate 500 is provided, the semiconductor elements 108a, 108b, and 108c are disposed adjacent to the upper surface 504 of the substrate 500, and the semiconductor elements 108a, 108b, and 108c are electrically connected to the substrate unit 102. Specifically, the semiconductor element 108b is connected to the substrate unit 102 by wire bonding through the wire 112. The semiconductor elements 108a and 108c are fixed to the substrate unit 102 by surface adhesion. Referring to FIG. 5A, the lower surface 524 of the substrate 500 is disposed adjacent to the tape 506, and the tape 506 can be a single-sided or double-sided adhesive tape. Preferably, the tape 506 secures the relative position of the substrate unit 102 to a plurality of adjacent substrate units such that a continuous process can be performed on a plurality of elements adjacent to the tape 506 without the need to flip the element or transfer element to another carrier. Then, as shown in FIG. 5C, the encapsulation material 514 is applied to the upper surface 504 of the substrate 500 for substantially covering or covering the ground vias 502a and 502b, the semiconductor elements 108a, 108b and 108c, and the wires 112. The encapsulating material 514 may, for example, comprise a resin that is intended to be a base, a resin that is epoxy 24 201101452 i, a resin based on a stone base, or other suitable material that may also include a suitable material. The filler is, for example, a powdery one-rolled hydrazine. The encapsulating material 514 can be applied by several molding techniques such as press wall & ρ to drag forming, injection molding and transfer forming. When the sealing material 514 is applied, the encapsulating material 514 is hardened or solidified to form a seal, '= 526. For example, the encapsulating material 514 can be hardened or cured by lowering the temperature to the packaging material Μ $, below. In continuous
Ο 】製程中’為了使基板500能正確地被定位，可於封 、、、。構5 2 6中形成基準點’例如是使用雷射標印之方式 形成基準點。或者，基準點可單獨或同時形成於鄰近義 板50〇之周圍之處。 土 從封裝結構526之上表面516切割封裝結構526， 此稱為稱為正面（front-side)切割。請參照第5C圖及 第5D圖’可透過刀具518切割出數個切割狹縫，以完成 正面切割製程。切割狹缝包括切割狹縫520a及520b。具 體來說’切割狹縫520a及520b係向下延伸且完全穿透 封裳結構526及基板500並穿透部份的膠帶506,藉以將 封裳結構526及基板500分離為不連續之單元，此單元 包括封膠體114及基板單元102。由於位於不同位置之封 裝結構526及基板500係透過一次切割而分離，而非數 次切割。因此，此種切割製程可稱為全穿切（fuU_cut) I程。多次的切割製程例如是多次之半穿切（ha 1 f-cut) 的切割製程。切割製程較佳地為全穿切製程，而非半穿 切製程。如此一來，藉由減少切割製程之切割次數，可 加強製造產能並減少此些程序之時間。此外，增加基板 25 201101452 1 Τ* I \ 500之使用率亦降低了製造成本，且減少了由於切割錯誤 所造成之不良品之機率，進而增加整體之產率。如第⑽ 圖所示，於全穿切製程中，膠帶5〇6固定基板單元1〇2 及封膠體114與鄰近之基板單元及封膠體之間的相對位 置。 請繼續參照第5D圖，刀具518係橫向地配置且實質 上對齊於每—個接科孔，使得產生的切懸縫移除掉、 接地導孔之特定體積或重量百分比，例如是於體積或重 量上移除約為10%至90%、約為3〇%至7〇%，或約為4〇% 至60%。按照此方式可形成接地元件丨丨^及丨丨牝，且接 地元件1183及118b係分別包括連接表面S1及犯。連接 S1及S2係係於基板單元1〇2之周圍而暴露於周圍 環，中。於切割製程中，可藉由基準點來對齊刀具518， 使2刀具518可於形成切割狹縫5，及5施時正確地 被定位。在某些實施方式中，每一個切割狹縫52〇&及52牝 之寬度Ci (有時稱為全穿切寬度或全穿切切割道）可介 於約ΙΟΟμιη至600_，例如是介於約2〇〇_至4〇〇帥，或 介於約250jum至350_。 +、然後，如第5E圖所示，於鄰近於暴露表面之處形成 私磁干擾塗層522’且暴露表面包括封膠體114之外部表 面、接地tl件118a及11扑之連接表面S1及S2以及基 反單元102之側表面142及144。電磁干擾塗層522可使 ，數種塗佈技術中任—種形成，該些數種塗佈技術例如 是化學氣相沈積、無電電鑛、電解電鑛、印刷、喷塗、 ;賤鑛及真空沈積。舉例來說’電磁干擾塗層522可包括 26】 】 In the process, in order to enable the substrate 500 to be correctly positioned, it can be sealed, and. The reference point is formed in the structure 516, for example, by using a laser marking to form a reference point. Alternatively, the reference points may be formed separately or simultaneously around the adjacent slab 50'. The earth cuts the package structure 526 from the upper surface 516 of the package structure 526, which is referred to as a front-side cut. Please refer to the 5C and 5D drawings. Several cutting slits can be cut through the cutter 518 to complete the front cutting process. The cutting slit includes cutting slits 520a and 520b. Specifically, the cutting slits 520a and 520b extend downwardly and completely penetrate the sealing structure 526 and the substrate 500 and penetrate a portion of the tape 506, thereby separating the sealing structure 526 and the substrate 500 into discrete units. This unit includes a sealant 114 and a substrate unit 102. Since the package structure 526 and the substrate 500 at different positions are separated by one cut, instead of several cuts. Therefore, such a cutting process can be referred to as a full cut (fuU_cut) process. The multiple cutting process is, for example, a ha 1 f-cut cutting process. The cutting process is preferably a full-cut process rather than a half-cut process. In this way, by reducing the number of cuts in the cutting process, manufacturing capacity can be increased and the time for such procedures can be reduced. In addition, increasing the use rate of the substrate 25 201101452 1 Τ * I \ 500 also reduces the manufacturing cost and reduces the probability of defective products due to cutting errors, thereby increasing the overall yield. As shown in the figure (10), in the full-cutting process, the tape 5〇6 fixes the relative positions between the substrate unit 1〇2 and the encapsulant 114 and the adjacent substrate unit and the encapsulant. Continuing to refer to FIG. 5D, the cutters 518 are laterally disposed and substantially aligned with each of the access holes such that the resulting slits are removed, a particular volume or weight percentage of the ground vias, such as volume or The weight removal is about 10% to 90%, about 3% to 7%, or about 4% to 60%. In this manner, the grounding members 丨丨牝 and 丨丨牝 can be formed, and the grounding members 1183 and 118b respectively include the connecting surface S1 and the sin. The connections S1 and S2 are attached to the periphery of the substrate unit 1〇2 and exposed to the surrounding ring. In the cutting process, the tool 518 can be aligned by the reference point so that the 2 tool 518 can be properly positioned when the cutting slit 5 is formed and 5 is applied. In some embodiments, the width Ci of each of the cutting slits 52 amp & and 52 ( (sometimes referred to as full cut width or full cut cut scribe) may be between about ΙΟΟ μιη to 600 _, for example, About 2 〇〇 to 4 〇〇 handsome, or between about 250jum to 350 _. +, then, as shown in FIG. 5E, a private magnetic interference coating 522' is formed adjacent to the exposed surface and the exposed surface includes the outer surface of the encapsulant 114, the grounding tl pieces 118a and 11 are connected to the connecting surfaces S1 and S2 And side surfaces 142 and 144 of the base unit 102. The electromagnetic interference coating 522 can be formed by any of several coating techniques, such as chemical vapor deposition, electroless ore, electrolytic ore, printing, spraying, and antimony ore. Vacuum deposition. For example, the electromagnetic interference coating 522 can include 26
第6圖繪示依照本發明之另一實施例之半導體封裝 ，之形成方法。為了方便說明，下狀製造方法係參^ f 4A圖之半導體封裝件4〇〇而敘述。然而，可以了解的 製造方法亦可用以形成其它之半導體封裝件，例如 是第1圖至第3圖中繪示之半導體封裝件1〇〇、第牝圖 中繪示之半導體封裝件460以及第4C圖中繪示之半導體 201101452 猎由無電電鍍所形成 此膜層的厚度至少約、θ，且此膜層係由鎳所形成。 或約為5_至10_。杏、::如是約為5_至50μι„， 不同膜層可使用相^ 層522為多層結構時， 說，内層可使用之塗佈技術所形㈣ 電電鑛或電解電7而外層可由無 内層（作為基層之、科為鎳。另一例子中， 其材料為銅。内層之^ 4或無電電贿形成，且 至·，或^ Μ至少約為1⑽，例如是約為細 之材料可為不齡卿至·。外層（作為抗氧化層之用） 外層之犀声 一、，且外層係糟由濺鍍所形成。 之谷度約不大於〗_ ’例如 或約為0.01_m_。在 子卜:: 内經過特定之預先處理程序，藉以形成 曰二！ 先處理程序包括表面粗糙化及形成 =層/面婦化例如是藉由化學_或機械研磨所 由膠帶506 i分離基板單元102及相關之元件以 2包括電磁干擾防護罩124之半導體封裝件⑽。舉例 ^兄’由膠帶506 ±分離基板單元1〇2及相關之元件之 式可為取放技術（pick_and_place⑽以律）。 27 201101452 封裝件480。此外，部分之此製造方法係與第5A圖至第 5 E圖中纟會示之方法相似’在此不再贅述。 请參照第6圖，基板600及硬化之封裝材料614係 鄰近於膠帶606而配置，且膠帶6〇6可為單面或雙面之 黏著膠帶。切割製程係接著於硬化之封裝材料614之上 表面616上進行。如第6圖所示，切割製程係藉由刀具 618而完成。刀具形成之切割狹縫62〇a及620b係向下延 伸且完全貫穿硬化之封裝材料614及基板6〇〇，並穿透部 刀之膠π 6〇6’進而將硬化之封裝材料614及基板分 離為不連續之單元。此些單元包括封膠體114及基板單 元102具體來說，刀具gig係橫向放置且實質上對齊於 每一個接地導孔，使得形成之切割狹缝將接地導孔分離 為兩個接地元件。接地元件係彼此分離且鄰近於個別之 基板單元而配置。如此一來可形成接地元件418a及 418b，且接地元件418a及分別包括連接表面sj， 及犯，。連接表面si，及S2，係於基板單元1〇2之周圍 之處而暴露於周遭環境中。較佳地，第6圖所示之切割 製知之方式可增加製造產量，並進一步降低切割製程之 進行-人數，以及進行切割製程之時間，並藉由減少因切 J錯誤造成不良品之機率，進而增加整體之產率。在某 些實施方式中’每一個接地導孔之尺寸可介於約1〇〇_ 至7〇〇_’例如是介於約200μιη至6〇〇_，或介於約3〇〇_ 至50〇μιη。每一個接地導孔之導孔墊尺寸We可介於約 3〇〇μπι至11〇〇_，例如是介於約4〇〇_至1〇〇〇_，或介 於約5〇〇μιη至9〇〇μπι。切割狭縫62〇a及620b之寬度C2 28 201101452 - 1 VVJ^HUr/Λ 可實質上相等於上述之第5D圖中之寬度Cl，且寬度C2 可介於約ΙΟΟμπι至600μπι，例如是介於約200μπι至400μπι， 或介於約250μηι至350μπι。然而，可了解的是，在其它實 施方式中，寬度C2可為不同，且寬度C2可接近於接地導 孔之導孔尺寸W5或導孔墊尺寸W6，用以分割接地導孔為 數個接地元件。舉例來說，一般之寬度C2可表示為 C2<W5<W6 。 綜上所述，雖然本發明已以一較佳實施例揭露如 〇 上，然其並非用以限定本發明。本發明所屬技術領域中 具有通常知識者，在不脫離本發明之精神和範圍内，當 可作各種之更動與潤飾。因此，本發明之保護範圍當視 後附之申請專利範圍所界定者為準。此外，許多更動係 配合特定之情況、材料、物質組成、方法或程序。此些 更動係包含於後附之申請專利範圍。具體來說，當此處 揭露之方法係參照特定程序並以特定順序來敘述，可了 解的是，此些程序可被結合、分離或重新排序，用以在 Ο 不脫離本發明之精神下而形成等價之方法。除非文中特 別註明，否則本發明之程序之順序及群組並不以此為限。 【圖式簡單說明】 請參照下列詳細敘述及所附圖式以更了解本發明之 實施例之本質及目標。除非敘述中有特別說明，圖式中 之相似之元件係以相似之標號所標示。 第1圖繪示依照本發明之一實施例之半導體封裝件 之立體圖。 29FIG. 6 illustrates a method of forming a semiconductor package in accordance with another embodiment of the present invention. For convenience of explanation, the underlying manufacturing method is described in the semiconductor package of FIG. However, the manufacturing method that can be understood can also be used to form other semiconductor packages, such as the semiconductor package 1 第 shown in FIGS. 1 to 3 , the semiconductor package 460 illustrated in the first drawing, and the The semiconductor 201101452 shown in FIG. 4C is formed by electroless plating to have a thickness of at least about θ, and the film layer is formed of nickel. Or about 5_ to 10_. Apricot, :: If it is about 5_ to 50μι, when different layers can use the layer 522 as a multi-layer structure, it can be said that the inner layer can be used in the coating technology (4) electric ore or electrolytic 7 and the outer layer can be made without inner layer (As a base layer, the branch is nickel. In another example, the material is copper. The inner layer is formed by 4 or no electric bribe, and the distance to /, or ^ is at least about 1 (10), for example, the material is about fine. The outer layer (used as an antioxidant layer) The rhinoceros of the outer layer is one, and the outer layer is formed by sputtering. The valley is not more than __ 'for example or about 0.01_m_. Bu:: After a specific pre-processing procedure, the second processing is performed! The first processing procedure includes surface roughening and formation = layer/face mating, for example, by separating the substrate unit 102 by the tape 506 i by chemical or mechanical grinding. The related components are 2 including a semiconductor package (10) of the electromagnetic interference shield 124. For example, the method of separating the substrate unit 1〇2 and the related components by the tape 506± can be a pick-and-place technique (pick_and_place(10)). Package 480. In addition, part of The manufacturing method is similar to the method shown in FIGS. 5A to 5E, and will not be described herein. Referring to FIG. 6, the substrate 600 and the hardened packaging material 614 are disposed adjacent to the tape 606, and the tape is disposed. 6〇6 can be a single-sided or double-sided adhesive tape. The cutting process is then performed on the upper surface 616 of the hardened encapsulating material 614. As shown in Fig. 6, the cutting process is accomplished by the cutter 618. The cutting slits 62〇a and 620b extend downwardly and completely penetrate the hardened encapsulating material 614 and the substrate 6〇〇, and penetrate the rubber π 6〇6′ of the knives to separate the hardened encapsulating material 614 and the substrate into Discontinuous unit. The units include the encapsulant 114 and the substrate unit 102. Specifically, the cutter gig is placed laterally and substantially aligned with each of the ground vias such that the formed slit slit separates the ground via into two The grounding elements are disposed apart from each other and adjacent to the individual substrate units. Thus, the grounding elements 418a and 418b can be formed, and the grounding elements 418a and the connecting surfaces sj, respectively, and the connection surface si And S2 are exposed to the surrounding environment at the periphery of the substrate unit 1 。 2. Preferably, the cutting method shown in Fig. 6 can increase the manufacturing yield and further reduce the progress of the cutting process - the number of people And the time of the cutting process, and by reducing the probability of defective products caused by cutting J errors, thereby increasing the overall yield. In some embodiments, the size of each grounding via can be about 1〇〇. _ to 7〇〇_' is, for example, between about 200 μm to 6 〇〇 _, or between about 3 〇〇 to 50 〇 μη. The size of the via pad for each ground via can be between about 3 〇〇. Ππι to 11〇〇_, for example, is between about 4〇〇_ to 1〇〇〇_, or between about 5〇〇μιη to 9〇〇μπι. The width of the cutting slits 62〇a and 620b is C2 28 201101452 - 1 VVJ^HUr/Λ can be substantially equal to the width C1 in the 5Dth image described above, and the width C2 can be between about ΙΟΟμπι and 600μπι, for example, From about 200 μm to about 400 μm, or from about 250 μm to 350 μm. However, it can be understood that, in other embodiments, the width C2 can be different, and the width C2 can be close to the via hole size W5 of the ground via hole or the via pad size W6 for dividing the ground via hole into a plurality of ground elements. . For example, the general width C2 can be expressed as C2 < W5 < W6. In conclusion, the present invention has been described in terms of a preferred embodiment, and is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. In addition, many modifiers are tailored to specific situations, materials, material compositions, methods or procedures. These changes are included in the scope of the patent application attached. In particular, the methods disclosed herein are described in a particular order and are described in a particular order. It is understood that such procedures can be combined, separated, or re-sequenced without departing from the spirit of the invention. Form an equivalent method. The sequence and grouping of the procedures of the present invention are not limited thereto unless specifically noted herein. BRIEF DESCRIPTION OF THE DRAWINGS The nature and objects of the embodiments of the present invention will become more apparent from the detailed description and appended claims. Similar elements in the drawings are denoted by like reference numerals unless specifically stated in the description. 1 is a perspective view of a semiconductor package in accordance with an embodiment of the present invention. 29
圖之剖由綠A-A之剖面圖。 沿著第1 第3圖繪示第1圖之 圖。 半導體封裝件之部分放大剖 一實施例之半導體封 一實施例之半導體封 第4 A圖緣示依照本發明之另 裝件之剖面圖。 第4B圖繪示依照本發明之另 裝件之剖面圖。 第4C圖緣示依照本發明之另—實施例之半導 裝件之剖面圖。 第5A圖至第5E圖繪示依照本發明之一實施例之第 1圖之半導體封裝件之形成方法。 第6圖繪示依照本發明之另一實施例之第4A圖之 導體封裝件之形成方法。 【主要元件符號說明】 100、400、460、480 :半導體封裝件 102 ' 102 :基板單元 104、504 :上表面 106、524 :下表面 108a、1 〇8b、108c、408b :半導體元件 1 l〇a、11 〇b、110c :電性接點 112 :導線 Π4 :封膠體 118a、118b、418a、418b、462a、462b、482a、482b : 30 201101452 接地元件 120、122 :側表面 124 :電磁干擾防護罩 126 :上部 128 :側部 142、144 :側表面 150a、150b、450a、450b、470a、470b :通道餘留 部 〇 300 :内層 302 :外層 146a、146b、446a、446b、466a、466b、486a、486b : 上導孔墊餘留部 148a、148b、448a、448b、468a、468b、488a、488b : 下導孔墊餘留部 452、464、484a、484b :導電層 500、600 ··基板 O 502a、502b、502c、502d、502e :接地導孔 506、 606 ： 膠帶 514、 614 ： 封裝材料 516、 616 : 上表面 518、 618 : 刀具 520a、520b、620a、620b :切割狹缝 522:電磁干擾塗層 526 :封裝結構 546a、546b :上導孔墊 31 201101452 548a、548b :下導孔墊 550a、550b :電鑛通道 Cl、C2 :寬度 Hi、H2、Hb、He :高度 Li、L2 :間隔The cross section of the figure is taken from the green A-A section. The figure of Fig. 1 is shown along the first and third figures. A semiconductor package of a semiconductor package is partially enlarged. Fig. 4A is a cross-sectional view of an attachment according to the present invention. Figure 4B is a cross-sectional view of the attachment in accordance with the present invention. Figure 4C is a cross-sectional view showing a semiconductor package in accordance with another embodiment of the present invention. 5A to 5E are views showing a method of forming a semiconductor package according to Fig. 1 of an embodiment of the present invention. Fig. 6 is a view showing a method of forming a conductor package according to Fig. 4A of another embodiment of the present invention. [Description of main component symbols] 100, 400, 460, 480: semiconductor package 102' 102: substrate unit 104, 504: upper surface 106, 524: lower surface 108a, 1 〇 8b, 108c, 408b: semiconductor element 1 l〇 a, 11 〇b, 110c: electrical contact 112: wire Π 4: sealant 118a, 118b, 418a, 418b, 462a, 462b, 482a, 482b: 30 201101452 Grounding element 120, 122: side surface 124: electromagnetic interference protection Cover 126: upper portion 128: side portions 142, 144: side surfaces 150a, 150b, 450a, 450b, 470a, 470b: passage remaining portion 〇 300: inner layer 302: outer layers 146a, 146b, 446a, 446b, 466a, 466b, 486a 486b: upper via pad remaining portions 148a, 148b, 448a, 448b, 468a, 468b, 488a, 488b: lower via pad remaining portions 452, 464, 484a, 484b: conductive layers 500, 600 · · substrate O 502a, 502b, 502c, 502d, 502e: grounding vias 506, 606: tapes 514, 614: encapsulation material 516, 616: upper surface 518, 618: cutters 520a, 520b, 620a, 620b: cutting slit 522: electromagnetic interference Coating 526: package structure 546a, 546b: upper via pad 31 201101452 548a, 548b : Lower via pad 550a, 550b: Electron mine channel Cl, C2: Width Hi, H2, Hb, He: Height Li, L2: Interval
、SI S卜 S2、S1’ 、S2，、S1，，、S2，， S2’ ’ ’ ：連接表面, SI S Bu S2, S1', S2, S1,, S2,, S2' ’ ′: connecting surface
Wi、W2、Wb、We :寬度 W3、W4 :側向長度 W5、W6 :尺寸 32Wi, W2, Wb, We: Width W3, W4: Lateral length W5, W6: Size 32