TWI634640B - Electronic package and method of manufacture - Google Patents
Electronic package and method of manufacture Download PDFInfo
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- TWI634640B TWI634640B TW105138624A TW105138624A TWI634640B TW I634640 B TWI634640 B TW I634640B TW 105138624 A TW105138624 A TW 105138624A TW 105138624 A TW105138624 A TW 105138624A TW I634640 B TWI634640 B TW I634640B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims description 23
- 238000005253 cladding Methods 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 58
- 239000011247 coating layer Substances 0.000 abstract description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一種電子封裝件，係包括：埋設有屏蔽部之承載結構、設於該承載結構上之電子元件、形成於該承載結構上以包覆該電子元件之包覆層、設於該包覆層中並電性連接該屏蔽部之屏蔽構件、以及形成於該包覆層上且電性連接該屏蔽構件之導電部，使該導電部、屏蔽構件與屏蔽部構成屏蔽結構。本發明復提供該電子封裝件之製法。 An electronic package includes: a load-bearing structure embedded with a shield, an electronic component disposed on the load-bearing structure, a cladding layer formed on the load-bearing structure to cover the electronic component, and disposed in the cladding layer And electrically connecting the shielding member of the shielding portion and the conductive portion formed on the coating layer and electrically connecting the shielding member, so that the conductive portion, the shielding member and the shielding portion form a shielding structure. The invention provides a method of manufacturing the electronic package.
Description
本發明係關於一種電子封裝件，更詳而言之，係有關於一種防止電磁干擾之電子封裝件及其製法。 The present invention relates to an electronic package, and more particularly to an electronic package for preventing electromagnetic interference and a method of fabricating the same.
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為提升電性品質，多種半導體產品具有屏蔽之功能，以防止電磁干擾(Electromagnetic Interference，簡稱EMI)產生。 With the evolution of semiconductor technology, semiconductor products have developed different package product types, and in order to improve electrical quality, a variety of semiconductor products have a shielding function to prevent electromagnetic interference (Electromagnetic Interference, referred to as EMI).
請參閱第1A至1C圖，係為習知之避免EMI之射頻(Radio frequency,RF)模組之製法示意圖，該射頻模組1係將複數如射頻及非射頻式晶片之電子元件11電性連接在一基板10上，再以如環氧樹脂之封裝層13包覆各該電子元件11，之後進行切單製程(如第1B圖所示之切割路徑，其以虛線表示)，再於該封裝層13之頂面13a與側面13c及該基板10之側面10c上形成一金屬薄膜15，以藉由該金屬薄膜15保護該些電子元件11免受外界EMI影響。 Please refer to FIGS. 1A to 1C for a schematic diagram of a conventional radio frequency (RF) module for avoiding EMI. The RF module 1 is electrically connected to a plurality of electronic components 11 such as radio frequency and non-RF chips. On a substrate 10, each of the electronic components 11 is covered with an encapsulation layer 13 such as an epoxy resin, and then a singulation process (such as the cutting path shown in FIG. 1B, which is indicated by a broken line) is performed, and the package is further packaged. A metal film 15 is formed on the top surface 13a and the side surface 13c of the layer 13 and the side surface 10c of the substrate 10 to protect the electronic components 11 from external EMI by the metal film 15.
惟，習知射頻模組1中，係於切單製程後，再分別於單一射頻模組1上形成該金屬薄膜15，故需一一於各該射 頻模組1上形成該金屬薄膜15，因而無法一次形成該金屬薄膜15於所有之射頻模組1上，導致該射頻模組1之整體製作較為費時且生產成本較高。 However, in the conventional RF module 1, the metal film 15 is formed on the single RF module 1 after the singulation process, so that the metal film 15 is formed on each of the RF modules 1 . Therefore, the metal film 15 cannot be formed on all the RF modules 1 at one time, which results in the overall fabrication of the RF module 1 being time consuming and high in production cost.
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.
為解決上述習知技術之種種問題，本發明遂揭露一種電子封裝件，係包括：承載結構，係埋設有屏蔽部；電子元件，係設於該承載結構上；包覆層，係形成於該承載結構上以包覆該電子元件；屏蔽構件，係設於該包覆層中並電性連接該屏蔽部；以及導電部，係設於該包覆層上且電性連接該屏蔽構件。 In order to solve the above problems of the prior art, the present invention discloses an electronic package comprising: a load-bearing structure, a shield portion is embedded therein; an electronic component is disposed on the load-bearing structure; and a cladding layer is formed on the The supporting structure is configured to cover the electronic component; the shielding member is disposed in the cladding layer and electrically connected to the shielding portion; and the conductive portion is disposed on the cladding layer and electrically connected to the shielding member.
本發明復提供一種電子封裝件之製法，係包括：設置電子元件於一埋設有屏蔽部之承載結構上；形成包覆層於該承載結構上，以令該包覆層包覆該電子元件，並於該包覆層中設有電性連接該屏蔽部之屏蔽構件；以及設置導電部於該包覆層上，且令該導電部電性連接該屏蔽構件。 The invention provides a method for manufacturing an electronic package, comprising: disposing an electronic component on a load-bearing structure in which a shield portion is embedded; forming a cladding layer on the load-bearing structure, so that the cover layer covers the electronic component, And providing a shielding member electrically connected to the shielding portion; and providing a conductive portion on the covering layer, and electrically connecting the conductive portion to the shielding member.
前述之製法中，該屏蔽部之製程係包括：於該承載結構中形成凹部；以及於該凹部中形成導電材，以令該導電材作為該屏蔽部。 In the above manufacturing method, the process of the shielding portion includes: forming a concave portion in the supporting structure; and forming a conductive material in the concave portion to make the conductive material as the shielding portion.
前述之製法中，復包括於形成該導電部後，進行切單製程。 In the above manufacturing method, after the formation of the conductive portion, a singulation process is performed.
前述之電子封裝件及其製法中，該承載結構復埋設有接地層，以電性連接該屏蔽部。 In the above electronic package and the method of manufacturing the same, the bearing structure is buried with a grounding layer to electrically connect the shielding portion.
前述之電子封裝件及其製法中，該屏蔽部係為板體或柱體。 In the above electronic package and the method of manufacturing the same, the shielding portion is a plate body or a cylinder.
前述之電子封裝件及其製法中，該屏蔽部係為環狀。 In the above electronic package and the method of manufacturing the same, the shield portion is annular.
前述之電子封裝件及其製法中，該屏蔽部係未凸出該承載結構之側面，例如，該屏蔽部係位於該承載結構之側面內。 In the above electronic package and method of manufacturing the same, the shielding portion does not protrude from the side of the supporting structure, for example, the shielding portion is located in a side surface of the supporting structure.
前述之電子封裝件及其製法中，該屏蔽構件之部分表面係外露於該包覆層以接觸該導電部。 In the above electronic package and method of manufacturing the same, a part of the surface of the shielding member is exposed to the cladding layer to contact the conductive portion.
前述之電子封裝件及其製法中，該承載結構定義有置晶區以供接置該電子元件，且該屏蔽部對應位於該置晶區之周圍。 In the foregoing electronic package and method of manufacturing the same, the carrying structure defines a crystallizing region for receiving the electronic component, and the shielding portion is correspondingly located around the crystallizing region.
前述之電子封裝件及其製法中，該屏蔽構件位於該電子元件周圍。 In the aforementioned electronic package and method of manufacturing the same, the shielding member is located around the electronic component.
前述之電子封裝件及其製法中，該承載結構上設有複數該電子元件，且該屏蔽構件位於任二該電子元件之間。 In the foregoing electronic package and method of manufacturing the same, the carrier structure is provided with a plurality of the electronic components, and the shielding member is located between any two of the electronic components.
另外，前述之電子封裝件及其製法中，該導電部係為蓋體，以置放於該包覆層上。或者，該導電部係為金屬層，其以電鍍、塗佈、濺鍍、化鍍、無電鍍或蒸鍍方式形成者。 Further, in the above electronic package and the method of manufacturing the same, the conductive portion is a lid body to be placed on the cladding layer. Alternatively, the conductive portion is a metal layer formed by plating, coating, sputtering, plating, electroless plating or vapor deposition.
由上可知，本發明之電子封裝件及其製法，主要藉由先於該承載結構中形成屏蔽部，使該導電部只需形成於該包覆層之頂面上，而無需延伸至該承載結構之側面，故相較於習知技術，只需進行一次形成導電部製程，即可於複數個電子封裝件上形成屏蔽結構，而無需於複數電子封裝件上一一進行形成導電部之製程，因而能有效縮短該電子 封裝件之整體製作時間，且利於量產化而降低成本。 It can be seen that the electronic package of the present invention and the method for manufacturing the same are mainly formed by forming a shielding portion in the bearing structure, so that the conductive portion only needs to be formed on the top surface of the cladding layer without extending to the bearing. Compared with the prior art, it is only necessary to perform the process of forming the conductive portion once, so that the shielding structure can be formed on the plurality of electronic packages without performing the process of forming the conductive portions one by one on the plurality of electronic packages. Therefore, the overall manufacturing time of the electronic package can be effectively shortened, and the mass production can be reduced to reduce the cost.
1‧‧‧射頻模組 1‧‧‧RF Module
10‧‧‧基板 10‧‧‧Substrate
10c,13c,20c,23c‧‧‧側面 10c, 13c, 20c, 23c‧‧‧ side
11‧‧‧電子元件 11‧‧‧Electronic components
13‧‧‧封裝層 13‧‧‧Encapsulation layer
13a,23a‧‧‧頂面 13a, 23a‧‧‧ top
15‧‧‧金屬薄膜 15‧‧‧Metal film
2‧‧‧電子封裝件 2‧‧‧Electronic package
20‧‧‧承載結構 20‧‧‧bearing structure
20a‧‧‧第一側 20a‧‧‧ first side
20b‧‧‧第二側 20b‧‧‧ second side
200‧‧‧絕緣層 200‧‧‧Insulation
201‧‧‧線路層 201‧‧‧Line layer
202‧‧‧接地層 202‧‧‧ Grounding layer
21‧‧‧電子元件 21‧‧‧Electronic components
22‧‧‧屏蔽部 22‧‧ ‧Shielding Department
22a‧‧‧連接墊 22a‧‧‧Connecting mat
220‧‧‧凹部 220‧‧‧ recess
23‧‧‧包覆層 23‧‧‧Cladding
24‧‧‧屏蔽構件 24‧‧‧Shielding members
25‧‧‧導電部 25‧‧‧Electrical Department
26‧‧‧導電元件 26‧‧‧Conductive components
A‧‧‧置晶區 A‧‧‧ crystal zone
S‧‧‧切割路徑 S‧‧‧ cutting path
第1A至1C圖係為習知射頻模組之製法之剖面示意圖；第2A至2E圖係為本發明之電子封裝件之製法之剖面示意圖；第3A至3C圖係為對應第2B圖之不同實施例之上視示意圖；以及第4圖係為對應第2C圖之上視示意圖。 1A to 1C are schematic cross-sectional views showing a method of manufacturing a conventional radio frequency module; FIGS. 2A to 2E are schematic cross-sectional views showing a manufacturing method of the electronic package of the present invention; and FIGS. 3A to 3C are diagrams corresponding to the second FIG. The top view of the embodiment; and the fourth figure is a top view corresponding to the 2C figure.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“內”、“頂”、“側面”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "inside", "top", "side" and "one" are used in this specification for convenience of description and are not intended to limit the invention. The scope, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.
第2A至2E圖係為本發明之電子封裝件2之製法的剖面示意圖。 2A to 2E are schematic cross-sectional views showing the manufacturing method of the electronic package 2 of the present invention.
如第2A圖所示，提供一承載結構20，其具有相對之第一側20a與第二側20b，且於該承載結構20之第一側20a形成至少一凹部220。 As shown in FIG. 2A, a load-bearing structure 20 having opposite first and second sides 20a, 20b is provided, and at least one recess 220 is formed on the first side 20a of the load-bearing structure 20.
於本實施例中，該承載結構20之第一側20a係定義有至少一置晶區A，且令該凹部220位於該置晶區A之外圍。該承載結構20係為具有核心層之線路結構或無核心層(coreless)之線路結構，該線路結構具有絕緣層200與設於該絕緣層200上之線路層201，該線路層201係對應設於該置晶區A之範圍，例如為扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，且形成該線路層201之材質係為銅，而形成該絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該承載結構20亦可為其它承載晶片之承載件，如有機板材、晶圓(wafer)、或其他具有金屬佈線(routing)之載板，並不限於上述。 In this embodiment, the first side 20a of the load-bearing structure 20 defines at least one crystal-clear region A, and the recess portion 220 is located at the periphery of the crystal-crystalline region A. The load-bearing structure 20 is a circuit structure having a core layer or a coreless core structure. The circuit structure has an insulation layer 200 and a circuit layer 201 disposed on the insulation layer 200. The circuit layer 201 is correspondingly provided. The range of the crystallographic region A is, for example, a fan out type redistribution layer (RDL), and the material forming the circuit layer 201 is copper, and the material of the insulating layer 200 is formed. It is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), and prepreg (PP). It should be understood that the carrying structure 20 may also be other carrier supporting the wafer, such as an organic board, a wafer, or other carrier board having a metal routing, and is not limited to the above.
再者，該線路層201具有複數外露於該第一側20a之電性接觸墊(圖略)，且該線路結構中設有鄰近該第二側20b之接地層202，例如，該接地層202係位於該線路結構之最下層，以令該凹部220位於該線路層201與該接地層202之外圍。 Furthermore, the circuit layer 201 has a plurality of electrical contact pads (not shown) exposed on the first side 20a, and the ground structure 202 is disposed adjacent to the second side 20b, for example, the ground layer 202. It is located at the lowermost layer of the circuit structure such that the recess 220 is located at the periphery of the circuit layer 201 and the ground layer 202.
又，該凹部220係以雷射或切割刀具形成者，其可依 需求連通或未連通至該第二側20b。如第3A圖所示，該凹部220例如為一連續環狀溝槽，以圍繞置晶區A；或如第3B圖所示，該凹部220例如為複數之長形溝槽，且構成不連續環狀溝槽，以圍繞置晶區A；亦或如第3C圖所示，該凹部220例如為複數之柱狀溝槽，且圍繞置晶區A。 Further, the recess 220 is formed by a laser or cutting tool that can be connected or not connected to the second side 20b as desired. As shown in FIG. 3A, the recess 220 is, for example, a continuous annular groove to surround the crystallized area A; or as shown in FIG. 3B, the recess 220 is, for example, a plurality of elongated grooves and is discontinuous. The annular groove surrounds the crystallized region A; or as shown in FIG. 3C, the recess 220 is, for example, a plurality of columnar grooves and surrounds the crystal region A.
如第2B圖所示，形成導電材(如銅材)於該凹部220中，以作為屏蔽部22，使該屏蔽部22埋設於該承載結構20中並電性連接該接地層202。 As shown in FIG. 2B, a conductive material (such as a copper material) is formed in the recess 220 as a shield portion 22, and the shield portion 22 is buried in the load-bearing structure 20 and electrically connected to the ground layer 202.
於本實施例中，該屏蔽部22大致垂直該承載結構20之第一側20a，且該屏蔽部22於該承載結構20之第一側20a設有外露之連接墊22a。 In this embodiment, the shielding portion 22 is substantially perpendicular to the first side 20a of the supporting structure 20, and the shielding portion 22 is provided with an exposed connecting pad 22a on the first side 20a of the supporting structure 20.
再者，該屏蔽部22係為板體，且如第3A圖所示，其為連續環狀；該屏蔽部22亦可如第3B或3C圖所示之不連續環狀，其中，第3B圖所示之屏蔽部22係為板體，而第3C圖所示之屏蔽部22係為柱體。 Furthermore, the shielding portion 22 is a plate body, and as shown in FIG. 3A, it is a continuous ring shape; the shielding portion 22 may also be a discontinuous ring shape as shown in FIG. 3B or 3C, wherein the third portion The shield portion 22 shown in the figure is a plate body, and the shield portion 22 shown in Fig. 3C is a column.
如第2C圖所示，設置複數電子元件21於該承載結構20之第一側20a之置晶區A上，且該些電子元件21電性連接該承載結構20。接著，形成一包覆層23於該承載結構20之第一側20a上，以令該包覆層23包覆該些電子元件21，並於該包覆層23中形成有至少一屏蔽構件24。 As shown in FIG. 2C, a plurality of electronic components 21 are disposed on the crystallographic region A of the first side 20a of the carrier structure 20, and the electronic components 21 are electrically connected to the carrier structure 20. Then, a cladding layer 23 is formed on the first side 20a of the supporting structure 20, so that the cladding layer 23 covers the electronic components 21, and at least one shielding member 24 is formed in the cladding layer 23. .
於本實施例中，該電子元件21係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該電子元件21係為射頻晶片(例如：藍芽晶片或Wi-Fi晶片)，但 亦可為其它不受電磁波干擾之電子元件。具體地，該電子元件21係以覆晶方式或打線方式電性連接該線路層201之電性接觸墊(圖略)。然而，有關該電子元件電性連接該承載結構之方式不限於上述。 In this embodiment, the electronic component 21 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 is a radio frequency chip (e.g., a Bluetooth chip or a Wi-Fi chip), but may be other electronic components that are not interfered by electromagnetic waves. Specifically, the electronic component 21 is electrically connected to the electrical contact pad (not shown) of the circuit layer 201 in a flip chip manner or a wire bonding manner. However, the manner in which the electronic component is electrically connected to the load-bearing structure is not limited to the above.
再者，該包覆層23係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該承載結構20之第一側20a上。 Furthermore, the coating layer 23 is an insulating material such as polyimide (PI), dry film, epoxy or molding compound, which can be pressed. A lamination or molding is formed on the first side 20a of the carrier structure 20.
又，該屏蔽構件24係為導電材質(如銅、金、鎳或鋁等之金屬)之板體或柱體，其立設於該承載結構20上且位於各該電子元件21周圍(如第4圖所示，且該屏蔽構件24位於任二該電子元件21之間)並對應該屏蔽部22之連接墊22a之位置以電性連接該屏蔽部22。有關該屏蔽構件24之製作方式繁多，並無特別限制。例如，該屏蔽構件24之製程可先設置該屏蔽構件24於該承載結構20之第一側20a上，再形成該包覆層23於該承載結構20之第一側20a上，以令該包覆層23包覆該屏蔽構件24；或者，先形成該包覆層23於該承載結構20之第一側20a上，再於該包覆層23中形成穿孔，之後形成該屏蔽構件24於該穿孔中。 Moreover, the shielding member 24 is a plate or a cylinder of a conductive material (such as a metal such as copper, gold, nickel or aluminum), which is erected on the carrying structure 20 and located around each of the electronic components 21 (eg, 4, and the shield member 24 is located between any two of the electronic components 21) and electrically connected to the shield portion 22 at the position of the connection pad 22a of the shield portion 22. The shielding member 24 is produced in a wide variety of ways and is not particularly limited. For example, the shielding member 24 can be disposed on the first side 20a of the supporting structure 20, and then the covering layer 23 is formed on the first side 20a of the supporting structure 20 to make the package. The cover layer 23 covers the shield member 24; or, the cover layer 23 is formed on the first side 20a of the load-bearing structure 20, and a through hole is formed in the cover layer 23, and then the shield member 24 is formed thereon. Perforated.
另外，該屏蔽構件24之部分表面(頂面)係外露於該包覆層23之頂面23a。例如，形成孔洞於該包覆層23上，以令該屏蔽構件24之頂面外露於該孔洞；或者，如第2C圖所示，進行整平製程，使該屏蔽構件24之頂面齊平該包 覆層23之頂面23a。 In addition, a part of the surface (top surface) of the shield member 24 is exposed on the top surface 23a of the cladding layer 23. For example, a hole is formed in the cladding layer 23 to expose the top surface of the shielding member 24 to the hole; or, as shown in FIG. 2C, a leveling process is performed to make the top surface of the shielding member 24 flush The top surface 23a of the cladding layer 23.
據此，藉由該屏蔽構件24作為電磁波屏障以遮蔽該些電子元件21的側壁，而防止各該電子元件21之間相互電磁波(或訊號)干擾，使該些電子元件21得以保持應有的功效。 Accordingly, the shield member 24 serves as an electromagnetic wave barrier to shield the sidewalls of the electronic components 21, thereby preventing mutual electromagnetic waves (or signals) from interfering with each other, thereby keeping the electronic components 21 in a proper state. efficacy.
如第2D圖所示，形成一導電部25於該包覆層23之頂面23a上，且該導電部25接觸該屏蔽構件24以電性連接該屏蔽構件24，俾供作為電磁屏蔽隔間(EMI partition)。 As shown in FIG. 2D, a conductive portion 25 is formed on the top surface 23a of the cladding layer 23, and the conductive portion 25 contacts the shielding member 24 to electrically connect the shielding member 24, and serves as an electromagnetic shielding compartment. (EMI partition).
於本實施例中，形成該導電部25之材質係如金屬或導電膠，如金、銀、銅(Cu)、鎳(Ni)、鐵(Fe)、鋁(Al)、不銹鋼(Sus)等，但不以此為限。 In this embodiment, the material of the conductive portion 25 is formed of a metal or a conductive paste such as gold, silver, copper (Cu), nickel (Ni), iron (Fe), aluminum (Al), stainless steel (Sus), or the like. , but not limited to this.
再者，該導電部25可為蓋體，以置放於該包覆層23之頂面23a上；或者，該導電部25可為金屬層，係藉由電鍍、塗佈(coating)、濺鍍(sputtering)、化鍍、無電鍍或蒸鍍等方式形成該導電部25。 In addition, the conductive portion 25 may be a cover body to be placed on the top surface 23a of the cladding layer 23; or the conductive portion 25 may be a metal layer by plating, coating, splashing The conductive portion 25 is formed by sputtering, plating, electroless plating, or vapor deposition.
如第2E圖所示，形成複數如銲球之導電元件26於該承載結構20之第二側20b上，再沿如第2D圖所示之切割路徑S進行切單製程，以得到複數個本發明之電子封裝件2。 As shown in FIG. 2E, a plurality of conductive elements 26, such as solder balls, are formed on the second side 20b of the load-bearing structure 20, and then a singulation process is performed along the cutting path S as shown in FIG. 2D to obtain a plurality of copies. Inventive electronic package 2.
於本實施例中，該導電元件26係電性連接該線路層201及接地層202。 In this embodiment, the conductive element 26 is electrically connected to the circuit layer 201 and the ground layer 202.
再者，該屏蔽部22未凸出該承載結構20之側面20c，其可外露或不外露於該承載結構20之側面20c。具體地，如第2E圖所示，該屏蔽部22係位於該承載結構20之側面 20c內；或者，該屏蔽部22齊平該承載結構20之側面20c，以令該屏蔽部22外露於該承載結構20之側面20c。 Moreover, the shielding portion 22 does not protrude from the side surface 20c of the supporting structure 20, and may be exposed or not exposed to the side surface 20c of the supporting structure 20. Specifically, as shown in FIG. 2E, the shielding portion 22 is located in the side surface 20c of the supporting structure 20; or the shielding portion 22 is flush with the side surface 20c of the supporting structure 20 to expose the shielding portion 22 to the shielding portion 22. The side 20c of the load bearing structure 20.
本發明之電子封裝件2之製法，係先於該承載結構20中形成圍繞置晶區A之凹部220，再於該凹部220中形成該屏蔽部22，並使該屏蔽部22電性連接該接地層202，故於後續製程中，該導電部25藉由該屏蔽構件24電性連接該屏蔽部22，即可構成屏蔽結構，使該電子封裝件2於運作時，該些電子元件21不會遭受外界之電磁干擾(EMI)，且該屏蔽部22亦可避免該線路層201受外界之電磁干擾。 The electronic package 2 of the present invention is formed by forming a recess 220 surrounding the crystallographic region A in the load-bearing structure 20, and forming the shield portion 22 in the recess portion 220, and electrically connecting the shield portion 22 to the shield portion 22 The grounding layer 202, so that the conductive portion 25 is electrically connected to the shielding portion 22 by the shielding member 24 in a subsequent process, thereby forming a shielding structure. When the electronic package 2 is in operation, the electronic components 21 are not It will be subject to external electromagnetic interference (EMI), and the shielding portion 22 can also prevent the circuit layer 201 from being subjected to external electromagnetic interference.
因此，該導電部25只需形成於該包覆層23之頂面23a上，而無需延伸至該承載結構20之側面20c，故於切單製程前，只需進行一次形成該導電部25之製程(如第2D圖所示)，而無需於切單製程後，一一於各該電子封裝件2上形成導電部25，因而能有效縮短該電子封裝件2之整體製作時間，且利於量產化而降低成本。 Therefore, the conductive portion 25 only needs to be formed on the top surface 23a of the cladding layer 23 without extending to the side surface 20c of the supporting structure 20. Therefore, it is only necessary to form the conductive portion 25 once before the singulation process. The process (as shown in FIG. 2D) does not need to form the conductive portion 25 on each of the electronic packages 2 after the singulation process, so that the overall fabrication time of the electronic package 2 can be effectively shortened, and the amount is facilitated. Production and reduce costs.
本發明復提供一種電子封裝件2，係包括：一承載結構20、複數電子元件21、一包覆層23、一屏蔽構件24以及導電部25。 The present invention further provides an electronic package 2 comprising: a carrier structure 20, a plurality of electronic components 21, a cladding layer 23, a shielding member 24, and a conductive portion 25.
所述之承載結構20係埋設有一屏蔽部22。 The bearing structure 20 is embedded with a shielding portion 22 .
所述之電子元件21係設於該承載結構20上。 The electronic component 21 is disposed on the carrying structure 20 .
所述之包覆層23係形成於該承載結構20上並包覆該些電子元件21。 The covering layer 23 is formed on the carrying structure 20 and covers the electronic components 21 .
所述之屏蔽構件24係設於該包覆層23中並電性連接該屏蔽部22。 The shielding member 24 is disposed in the cladding layer 23 and electrically connected to the shielding portion 22 .
所述之導電部25係形成於該包覆層23上且電性連接該屏蔽構件24。 The conductive portion 25 is formed on the cladding layer 23 and electrically connected to the shielding member 24 .
於一實施例中，該承載結構20復埋設有接地層202，以電性連接該屏蔽部22。 In one embodiment, the load-bearing structure 20 is buried with a ground layer 202 to electrically connect the shield portion 22.
於一實施例中，該屏蔽部22係為板體或柱體。 In an embodiment, the shielding portion 22 is a plate or a cylinder.
於一實施例中，該屏蔽部22係為環狀。 In an embodiment, the shielding portion 22 is annular.
於一實施例中，該屏蔽部22未凸出該承載結構20之側面20c，例如，該屏蔽部22係埋設於該承載結構20之側面20c內。 In one embodiment, the shielding portion 22 does not protrude from the side surface 20c of the supporting structure 20. For example, the shielding portion 22 is embedded in the side surface 20c of the supporting structure 20.
於一實施例中，該屏蔽構件24之部分表面係外露於該包覆層23以接觸該導電部25。 In one embodiment, a portion of the surface of the shield member 24 is exposed to the cladding layer 23 to contact the conductive portion 25.
於一實施例中，該承載結構20定義有置晶區A以供接置該電子元件21，且該屏蔽部22對應位於該置晶區A之周圍。 In an embodiment, the carrying structure 20 defines a crystal area A for the electronic component 21 to be connected, and the shielding portion 22 is located around the crystal forming area A.
於一實施例中，該屏蔽構件24係位於該電子元件21周圍。 In an embodiment, the shielding member 24 is located around the electronic component 21.
於一實施例中，該屏蔽構件24係位於任二該電子元件21之間。 In one embodiment, the shield member 24 is located between any two of the electronic components 21.
於一實施例中，該導電部25係為金屬層或蓋體。 In an embodiment, the conductive portion 25 is a metal layer or a cover.
綜上所述，本發明之電子封裝件及其製法中，係藉由先於該承載結構中形成屏蔽部，使該導電部只需形成於該包覆層之頂面上，而無需延伸至該承載結構之側面，故只需進行一次形成導電部製程，即可於複數個電子封裝件上形成屏蔽結構，而無需於複數電子封裝件上一一進行形成 導電部之製程，因而能有效縮短該電子封裝件之整體製作時間，且利於量產化而降低成本。 In summary, in the electronic package of the present invention and the method of manufacturing the same, the conductive portion is formed on the top surface of the cladding layer by extending the shield portion before the shield portion is formed. The side of the supporting structure, so that the conductive portion process can be formed only once, the shielding structure can be formed on the plurality of electronic packages, and the process of forming the conductive portion is not required to be performed on the plurality of electronic packages, thereby effectively shortening The overall manufacturing time of the electronic package is advantageous for mass production and cost reduction.
上述該些實施樣態僅例示性說明本發明之功效，而非用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述該些實施態樣進行修飾與改變。此外，在上述該些實施態樣中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention, and those skilled in the art can practice the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
Claims (23)
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| TWI723414B (en) * | 2019-06-05 | 2021-04-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
| CN112103269B (en) * | 2020-08-07 | 2022-09-20 | 珠海越亚半导体股份有限公司 | Embedded packaging structure with shielding cavity and manufacturing method thereof |
| CN112103196B (en) * | 2020-11-03 | 2021-02-26 | 甬矽电子(宁波)股份有限公司 | Electromagnetic shielding module structure and preparation method thereof |
| CN112490218B (en) * | 2020-12-14 | 2024-04-16 | 甬矽电子(宁波)股份有限公司 | Packaging structure with electromagnetic shielding and manufacturing method of packaging structure |
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| TW201820582A (en) | 2018-06-01 |
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